1 /******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
34 #include <sys/param.h>
35 #include <sys/sysctl.h>
36 #include <net/if_var.h>
38 #include "e1000_api.h"
39 #include "e1000_dragonfly.h"
42 * NOTE: the following routines using the e1000
43 * naming style are provided to the shared
44 * code but are OS specific
48 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
50 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);
54 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
56 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);
60 e1000_pci_set_mwi(struct e1000_hw *hw)
62 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
63 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
67 e1000_pci_clear_mwi(struct e1000_hw *hw)
69 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
70 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
74 * Read the PCI Express capabilities
77 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
79 device_t dev = ((struct e1000_osdep *)hw->back)->dev;
82 pcie_ptr = pci_get_pciecap_ptr(dev);
84 return E1000_NOT_IMPLEMENTED;
86 *value = pci_read_config(dev, pcie_ptr + reg, 2);
91 e1000_write_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
93 device_t dev = ((struct e1000_osdep *)hw->back)->dev;
96 pcie_ptr = pci_get_pciecap_ptr(dev);
98 return E1000_NOT_IMPLEMENTED;
100 pci_write_config(dev, pcie_ptr + reg, *value, 2);
101 return E1000_SUCCESS;
105 e1000_str2fc(const char *str)
107 if (strcmp(str, E1000_FC_STR_NONE) == 0)
108 return e1000_fc_none;
109 else if (strcmp(str, E1000_FC_STR_RX_PAUSE) == 0)
110 return e1000_fc_rx_pause;
111 else if (strcmp(str, E1000_FC_STR_TX_PAUSE) == 0)
112 return e1000_fc_tx_pause;
114 return e1000_fc_full;
118 e1000_fc2str(enum e1000_fc_mode fc, char *str, int len)
120 const char *fc_str = E1000_FC_STR_FULL;
124 fc_str = E1000_FC_STR_NONE;
127 case e1000_fc_rx_pause:
128 fc_str = E1000_FC_STR_RX_PAUSE;
131 case e1000_fc_tx_pause:
132 fc_str = E1000_FC_STR_TX_PAUSE;
138 strlcpy(str, fc_str, len);
142 e1000_sysctl_flowctrl(struct ifnet *ifp, enum e1000_fc_mode *fc0,
143 struct e1000_hw *hw, struct sysctl_oid *oidp, struct sysctl_req *req)
145 char flowctrl[E1000_FC_STRLEN];
146 enum e1000_fc_mode fc;
149 e1000_fc2str(*fc0, flowctrl, sizeof(flowctrl));
150 error = sysctl_handle_string(oidp, flowctrl, sizeof(flowctrl), req);
151 if (error != 0 || req->newptr == NULL)
154 fc = e1000_str2fc(flowctrl);
156 ifnet_serialize_all(ifp);
161 hw->fc.requested_mode = fc;
162 hw->fc.current_mode = fc;
163 e1000_force_mac_fc(hw);
165 ifnet_deserialize_all(ifp);
171 static moduledata_t ig_hal_mod = { "ig_hal" };
172 DECLARE_MODULE(ig_hal, ig_hal_mod, SI_SUB_DRIVERS, SI_ORDER_MIDDLE);
173 MODULE_VERSION(ig_hal, 1);