2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.16 2007/10/21 09:50:33 sephe Exp $
37 #include <sys/param.h>
38 #include <sys/bitops.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
42 #include <sys/malloc.h>
45 #include <sys/serialize.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
50 #include <net/ethernet.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
58 #include <netproto/802_11/ieee80211_radiotap.h>
59 #include <netproto/802_11/ieee80211_var.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwimac.h>
68 #include <dev/netif/bwi/bwirf.h>
70 struct bwi_clock_freq {
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
93 static void bwi_next_scan(void *);
94 static void bwi_calibrate(void *);
96 static int bwi_stop(struct bwi_softc *);
97 static int bwi_newbuf(struct bwi_softc *, int, int);
98 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
99 struct ieee80211_node **, int);
101 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
102 bus_addr_t, int, int);
103 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
105 static int bwi_init_tx_ring32(struct bwi_softc *, int);
106 static int bwi_init_rx_ring32(struct bwi_softc *);
107 static int bwi_init_txstats32(struct bwi_softc *);
108 static void bwi_free_tx_ring32(struct bwi_softc *, int);
109 static void bwi_free_rx_ring32(struct bwi_softc *);
110 static void bwi_free_txstats32(struct bwi_softc *);
111 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
112 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
113 int, bus_addr_t, int);
114 static int bwi_rxeof32(struct bwi_softc *);
115 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
116 static void bwi_txeof_status32(struct bwi_softc *);
118 static int bwi_init_tx_ring64(struct bwi_softc *, int);
119 static int bwi_init_rx_ring64(struct bwi_softc *);
120 static int bwi_init_txstats64(struct bwi_softc *);
121 static void bwi_free_tx_ring64(struct bwi_softc *, int);
122 static void bwi_free_rx_ring64(struct bwi_softc *);
123 static void bwi_free_txstats64(struct bwi_softc *);
124 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
125 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
126 int, bus_addr_t, int);
127 static int bwi_rxeof64(struct bwi_softc *);
128 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
129 static void bwi_txeof_status64(struct bwi_softc *);
131 static void bwi_intr(void *);
132 static int bwi_rxeof(struct bwi_softc *, int);
133 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
134 static void bwi_txeof(struct bwi_softc *);
135 static void bwi_txeof_status(struct bwi_softc *, int);
136 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
137 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
138 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
139 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
140 struct bwi_rxbuf_hdr *, const void *, int, int);
142 static int bwi_dma_alloc(struct bwi_softc *);
143 static void bwi_dma_free(struct bwi_softc *);
144 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
145 struct bwi_ring_data *, bus_size_t,
147 static int bwi_dma_mbuf_create(struct bwi_softc *);
148 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
149 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
150 static void bwi_dma_txstats_free(struct bwi_softc *);
151 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
152 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
155 static void bwi_power_on(struct bwi_softc *, int);
156 static int bwi_power_off(struct bwi_softc *, int);
157 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
158 static int bwi_set_clock_delay(struct bwi_softc *);
159 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
160 static int bwi_get_pwron_delay(struct bwi_softc *sc);
161 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
163 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
164 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
166 static void bwi_get_card_flags(struct bwi_softc *);
167 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
169 static int bwi_bus_attach(struct bwi_softc *);
170 static int bwi_bbp_attach(struct bwi_softc *);
171 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
172 static void bwi_bbp_power_off(struct bwi_softc *);
174 static const char *bwi_regwin_name(const struct bwi_regwin *);
175 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
176 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
177 static int bwi_regwin_select(struct bwi_softc *, int);
179 static void bwi_led_attach(struct bwi_softc *);
180 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
181 static void bwi_led_event(struct bwi_softc *, int);
182 static void bwi_led_blink_start(struct bwi_softc *, int, int);
183 static void bwi_led_blink_next(void *);
184 static void bwi_led_blink_end(void *);
186 static const struct bwi_dev {
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
192 "Broadcom BCM4301 802.11 Wireless Lan" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
195 "Broadcom BCM4307 802.11 Wireless Lan" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
198 "Broadcom BCM4311 802.11 Wireless Lan" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
201 "Broadcom BCM4312 802.11 Wireless Lan" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
204 "Broadcom BCM4306 802.11 Wireless Lan" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
213 "Broadcom BCM4309 802.11 Wireless Lan" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
216 "Broadcom BCM4318 802.11 Wireless Lan" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
219 "Broadcom BCM4319 802.11 Wireless Lan" }
222 static device_method_t bwi_methods[] = {
223 DEVMETHOD(device_probe, bwi_probe),
224 DEVMETHOD(device_attach, bwi_attach),
225 DEVMETHOD(device_detach, bwi_detach),
226 DEVMETHOD(device_shutdown, bwi_shutdown),
228 DEVMETHOD(device_suspend, bwi_suspend),
229 DEVMETHOD(device_resume, bwi_resume),
234 static driver_t bwi_driver = {
237 sizeof(struct bwi_softc)
240 static devclass_t bwi_devclass;
242 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
243 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
245 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
246 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
248 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
250 MODULE_DEPEND(bwi, pci, 1, 1, 1);
251 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
253 static const struct {
257 } bwi_bbpid_map[] = {
258 { 0x4301, 0x4301, 0x4301 },
259 { 0x4305, 0x4307, 0x4307 },
260 { 0x4403, 0x4403, 0x4402 },
261 { 0x4610, 0x4615, 0x4610 },
262 { 0x4710, 0x4715, 0x4710 },
263 { 0x4720, 0x4725, 0x4309 }
266 static const struct {
269 } bwi_regwin_count[] = {
282 #define CLKSRC(src) \
283 [BWI_CLKSRC_ ## src] = { \
284 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
285 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
288 static const struct {
291 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
299 #define VENDOR_LED_ACT(vendor) \
301 .vid = PCI_VENDOR_##vendor, \
302 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
305 static const struct {
307 uint8_t led_act[BWI_LED_MAX];
308 } bwi_vendor_led_act[] = {
309 VENDOR_LED_ACT(COMPAQ),
310 VENDOR_LED_ACT(LINKSYS)
313 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
314 { BWI_VENDOR_LED_ACT_DEFAULT };
316 #undef VENDOR_LED_ACT
318 static const struct {
321 } bwi_led_duration[109] = {
338 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
339 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
342 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
344 static const struct ieee80211_rateset bwi_rateset_11b =
345 { 4, { 2, 4, 11, 22 } };
346 static const struct ieee80211_rateset bwi_rateset_11g =
347 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
350 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
352 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
356 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
357 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
360 struct bwi_desc32 *desc = &desc_array[desc_idx];
361 uint32_t ctrl, addr, addr_hi, addr_lo;
363 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
364 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
366 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
367 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
369 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
370 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
371 if (desc_idx == ndesc - 1)
372 ctrl |= BWI_DESC32_C_EOR;
375 ctrl |= BWI_DESC32_C_FRAME_START |
376 BWI_DESC32_C_FRAME_END |
380 desc->addr = htole32(addr);
381 desc->ctrl = htole32(ctrl);
384 /* XXX does not belong here */
386 bwi_rate2plcp(uint8_t rate)
388 rate &= IEEE80211_RATE_VAL;
393 case 11: return 0x37;
394 case 22: return 0x6e;
395 case 44: return 0xdc;
404 case 108: return 0xc;
407 panic("unsupported rate %u\n", rate);
411 /* XXX does not belong here */
412 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
413 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
416 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
420 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
421 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
422 *plcp0 = htole32(plcp);
425 /* XXX does not belong here */
426 struct ieee80211_ds_plcp_hdr {
433 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
434 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
435 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
436 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
437 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
440 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
443 int len, service, pkt_bitlen;
445 pkt_bitlen = pkt_len * NBBY;
446 len = howmany(pkt_bitlen * 2, rate);
448 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
449 if (rate == (11 * 2)) {
453 * PLCP service field needs to be adjusted,
454 * if TX rate is 11Mbytes/s
456 pkt_bitlen1 = len * 11;
457 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
458 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
461 plcp->i_signal = bwi_rate2plcp(rate);
462 plcp->i_service = service;
463 plcp->i_length = htole16(len);
464 /* NOTE: do NOT touch i_crc */
468 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
470 enum ieee80211_modtype modtype;
473 * Assume caller has zeroed 'plcp'
476 modtype = ieee80211_rate2modtype(rate);
477 if (modtype == IEEE80211_MODTYPE_OFDM)
478 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
479 else if (modtype == IEEE80211_MODTYPE_DS)
480 bwi_ds_plcp_header(plcp, pkt_len, rate);
482 panic("unsupport modulation type %u\n", modtype);
485 static __inline uint8_t
486 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
491 plcp = le32toh(*plcp0);
492 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
493 return ieee80211_plcp2rate(plcp_rate, 1);
496 static __inline uint8_t
497 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
499 return ieee80211_plcp2rate(hdr->i_signal, 0);
503 bwi_probe(device_t dev)
505 const struct bwi_dev *b;
508 did = pci_get_device(dev);
509 vid = pci_get_vendor(dev);
511 for (b = bwi_devices; b->desc != NULL; ++b) {
512 if (b->did == did && b->vid == vid) {
513 device_set_desc(dev, b->desc);
521 bwi_attach(device_t dev)
523 struct bwi_softc *sc = device_get_softc(dev);
524 struct ieee80211com *ic = &sc->sc_ic;
525 struct ifnet *ifp = &ic->ic_if;
530 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
534 * Initialize sysctl variables
536 sc->sc_fw_version = BWI_FW_VERSION3;
537 sc->sc_dwell_time = 200;
538 sc->sc_led_idle = (2350 * hz) / 1000;
539 sc->sc_led_blink = 1;
540 sc->sc_txpwr_calib = 1;
542 sc->sc_debug = bwi_debug;
545 callout_init(&sc->sc_scan_ch);
546 callout_init(&sc->sc_calib_ch);
549 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
552 /* XXX Save more PCIR */
553 irq = pci_read_config(dev, PCIR_INTLINE, 4);
554 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
556 device_printf(dev, "chip is in D%d power mode "
557 "-- setting to D0\n", pci_get_powerstate(dev));
559 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
561 pci_write_config(dev, PCIR_INTLINE, irq, 4);
562 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
564 #endif /* !BURN_BRIDGE */
566 pci_enable_busmaster(dev);
568 /* Get more PCI information */
569 sc->sc_pci_revid = pci_get_revid(dev);
570 sc->sc_pci_subvid = pci_get_subvendor(dev);
571 sc->sc_pci_subdid = pci_get_subdevice(dev);
576 sc->sc_mem_rid = BWI_PCIR_BAR;
577 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
578 &sc->sc_mem_rid, RF_ACTIVE);
579 if (sc->sc_mem_res == NULL) {
580 device_printf(dev, "can't allocate IO memory\n");
583 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
584 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
590 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
592 RF_SHAREABLE | RF_ACTIVE);
593 if (sc->sc_irq_res == NULL) {
594 device_printf(dev, "can't allocate irq\n");
602 sysctl_ctx_init(&sc->sc_sysctl_ctx);
603 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
604 SYSCTL_STATIC_CHILDREN(_hw),
606 device_get_nameunit(dev),
608 if (sc->sc_sysctl_tree == NULL) {
609 device_printf(dev, "can't add sysctl node\n");
614 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
615 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
616 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
617 "Channel dwell time during scan (msec)");
618 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
619 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
620 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
622 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
623 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
624 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
625 "# ticks before LED enters idle state");
626 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
627 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
628 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
629 "Allow LED to blink");
630 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
631 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
632 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
633 "Enable software TX power calibration");
635 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
636 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
637 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
642 error = bwi_bbp_attach(sc);
646 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
650 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
651 error = bwi_set_clock_delay(sc);
655 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
659 error = bwi_get_pwron_delay(sc);
664 error = bwi_bus_attach(sc);
668 bwi_get_card_flags(sc);
672 for (i = 0; i < sc->sc_nmac; ++i) {
673 struct bwi_regwin *old;
675 mac = &sc->sc_mac[i];
676 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
680 error = bwi_mac_lateattach(mac);
684 error = bwi_regwin_switch(sc, old, NULL);
690 * XXX First MAC is known to exist
693 mac = &sc->sc_mac[0];
696 bwi_bbp_power_off(sc);
698 error = bwi_dma_alloc(sc);
703 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
704 ifp->if_init = bwi_init;
705 ifp->if_ioctl = bwi_ioctl;
706 ifp->if_start = bwi_start;
707 ifp->if_watchdog = bwi_watchdog;
708 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
709 ifq_set_ready(&ifp->if_snd);
712 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
713 BWI_SPROM_CARD_INFO_LOCALE);
714 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
717 * Setup ratesets, phytype, channels and get MAC address
719 if (phy->phy_mode == IEEE80211_MODE_11B ||
720 phy->phy_mode == IEEE80211_MODE_11G) {
723 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
725 if (phy->phy_mode == IEEE80211_MODE_11B) {
726 chan_flags = IEEE80211_CHAN_B;
727 ic->ic_phytype = IEEE80211_T_DS;
729 chan_flags = IEEE80211_CHAN_CCK |
730 IEEE80211_CHAN_OFDM |
733 ic->ic_phytype = IEEE80211_T_OFDM;
734 ic->ic_sup_rates[IEEE80211_MODE_11G] =
738 /* XXX depend on locale */
739 for (i = 1; i <= 14; ++i) {
740 ic->ic_channels[i].ic_freq =
741 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
742 ic->ic_channels[i].ic_flags = chan_flags;
745 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
746 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
747 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
748 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
749 device_printf(dev, "invalid MAC address: "
750 "%6D\n", ic->ic_myaddr, ":");
753 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
758 panic("unknown phymode %d\n", phy->phy_mode);
761 ic->ic_caps = IEEE80211_C_SHSLOT |
762 IEEE80211_C_SHPREAMBLE |
765 ic->ic_state = IEEE80211_S_INIT;
766 ic->ic_opmode = IEEE80211_M_STA;
768 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
769 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
771 ic->ic_updateslot = bwi_updateslot;
773 ieee80211_ifattach(ic);
775 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
776 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
778 sc->sc_newstate = ic->ic_newstate;
779 ic->ic_newstate = bwi_newstate;
781 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
786 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
787 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
790 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
791 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
792 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
794 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
795 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
796 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
798 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
799 &sc->sc_irq_handle, ifp->if_serializer);
801 device_printf(dev, "can't setup intr\n");
803 ieee80211_ifdetach(ic);
808 ieee80211_announce(ic);
817 bwi_detach(device_t dev)
819 struct bwi_softc *sc = device_get_softc(dev);
821 if (device_is_attached(dev)) {
822 struct ifnet *ifp = &sc->sc_ic.ic_if;
825 lwkt_serialize_enter(ifp->if_serializer);
827 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
828 lwkt_serialize_exit(ifp->if_serializer);
831 ieee80211_ifdetach(&sc->sc_ic);
833 for (i = 0; i < sc->sc_nmac; ++i)
834 bwi_mac_detach(&sc->sc_mac[i]);
837 if (sc->sc_sysctl_tree != NULL)
838 sysctl_ctx_free(&sc->sc_sysctl_ctx);
840 if (sc->sc_irq_res != NULL) {
841 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
845 if (sc->sc_mem_res != NULL) {
846 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
856 bwi_shutdown(device_t dev)
858 struct bwi_softc *sc = device_get_softc(dev);
859 struct ifnet *ifp = &sc->sc_ic.ic_if;
861 lwkt_serialize_enter(ifp->if_serializer);
863 lwkt_serialize_exit(ifp->if_serializer);
868 bwi_power_on(struct bwi_softc *sc, int with_pll)
870 uint32_t gpio_in, gpio_out, gpio_en;
873 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
874 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
877 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
878 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
880 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
881 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
883 /* Turn off PLL first */
884 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
885 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
888 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
889 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
894 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
895 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
900 /* Clear "Signaled Target Abort" */
901 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
902 status &= ~PCIM_STATUS_STABORT;
903 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
907 bwi_power_off(struct bwi_softc *sc, int with_pll)
909 uint32_t gpio_out, gpio_en;
911 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
912 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
913 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
915 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
916 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
918 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
919 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
922 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
923 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
928 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
929 struct bwi_regwin **old_rw)
936 if (!BWI_REGWIN_EXIST(rw))
939 if (sc->sc_cur_regwin != rw) {
940 error = bwi_regwin_select(sc, rw->rw_id);
942 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
949 *old_rw = sc->sc_cur_regwin;
950 sc->sc_cur_regwin = rw;
955 bwi_regwin_select(struct bwi_softc *sc, int id)
957 uint32_t win = BWI_PCIM_REGWIN(id);
961 for (i = 0; i < RETRY_MAX; ++i) {
962 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
963 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
973 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
977 val = CSR_READ_4(sc, BWI_ID_HI);
978 *type = BWI_ID_HI_REGWIN_TYPE(val);
979 *rev = BWI_ID_HI_REGWIN_REV(val);
981 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
982 "vendor 0x%04x\n", *type, *rev,
983 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
987 bwi_bbp_attach(struct bwi_softc *sc)
989 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
990 uint16_t bbp_id, rw_type;
993 int error, nregwin, i;
996 * Get 0th regwin information
997 * NOTE: 0th regwin should exist
999 error = bwi_regwin_select(sc, 0);
1001 device_printf(sc->sc_dev, "can't select regwin 0\n");
1004 bwi_regwin_info(sc, &rw_type, &rw_rev);
1011 if (rw_type == BWI_REGWIN_T_COM) {
1012 info = CSR_READ_4(sc, BWI_INFO);
1013 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1015 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1017 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1019 uint16_t did = pci_get_device(sc->sc_dev);
1020 uint8_t revid = pci_get_revid(sc->sc_dev);
1022 for (i = 0; i < N(bwi_bbpid_map); ++i) {
1023 if (did >= bwi_bbpid_map[i].did_min &&
1024 did <= bwi_bbpid_map[i].did_max) {
1025 bbp_id = bwi_bbpid_map[i].bbp_id;
1030 device_printf(sc->sc_dev, "no BBP id for device id "
1035 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1036 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1040 * Find out number of regwins
1043 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1044 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1046 for (i = 0; i < N(bwi_regwin_count); ++i) {
1047 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1048 nregwin = bwi_regwin_count[i].nregwin;
1053 device_printf(sc->sc_dev, "no number of win for "
1054 "BBP id 0x%04x\n", bbp_id);
1059 /* Record BBP id/rev for later using */
1060 sc->sc_bbp_id = bbp_id;
1061 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1062 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1063 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1064 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1066 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1067 nregwin, sc->sc_cap);
1070 * Create rest of the regwins
1073 /* Don't re-create common regwin, if it is already created */
1074 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1076 for (; i < nregwin; ++i) {
1078 * Get regwin information
1080 error = bwi_regwin_select(sc, i);
1082 device_printf(sc->sc_dev,
1083 "can't select regwin %d\n", i);
1086 bwi_regwin_info(sc, &rw_type, &rw_rev);
1090 * 1) Bus (PCI/PCIE) regwin
1092 * Ignore rest types of regwin
1094 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1095 rw_type == BWI_REGWIN_T_BUSPCIE) {
1096 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1097 device_printf(sc->sc_dev,
1098 "bus regwin already exists\n");
1100 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1103 } else if (rw_type == BWI_REGWIN_T_MAC) {
1104 /* XXX ignore return value */
1105 bwi_mac_attach(sc, i, rw_rev);
1109 /* At least one MAC shold exist */
1110 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1111 device_printf(sc->sc_dev, "no MAC was found\n");
1114 KKASSERT(sc->sc_nmac > 0);
1116 /* Bus regwin must exist */
1117 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1118 device_printf(sc->sc_dev, "no bus regwin was found\n");
1122 /* Start with first MAC */
1123 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1132 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1134 struct bwi_regwin *old, *bus;
1138 bus = &sc->sc_bus_regwin;
1139 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1142 * Tell bus to generate requested interrupts
1144 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1146 * NOTE: Read BWI_FLAGS from MAC regwin
1148 val = CSR_READ_4(sc, BWI_FLAGS);
1150 error = bwi_regwin_switch(sc, bus, &old);
1154 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1158 mac_mask = 1 << mac->mac_id;
1160 error = bwi_regwin_switch(sc, bus, &old);
1164 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1165 val |= mac_mask << 8;
1166 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1169 if (sc->sc_flags & BWI_F_BUS_INITED)
1172 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1174 * Enable prefetch and burst
1176 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1177 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1179 if (bus->rw_rev < 5) {
1180 struct bwi_regwin *com = &sc->sc_com_regwin;
1183 * Configure timeouts for bus operation
1187 * Set service timeout and request timeout
1189 CSR_SETBITS_4(sc, BWI_CONF_LO,
1190 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1191 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1194 * If there is common regwin, we switch to that regwin
1195 * and switch back to bus regwin once we have done.
1197 if (BWI_REGWIN_EXIST(com)) {
1198 error = bwi_regwin_switch(sc, com, NULL);
1203 /* Let bus know what we have changed */
1204 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1205 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1206 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1207 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1209 if (BWI_REGWIN_EXIST(com)) {
1210 error = bwi_regwin_switch(sc, bus, NULL);
1214 } else if (bus->rw_rev >= 11) {
1216 * Enable memory read multiple
1218 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1224 sc->sc_flags |= BWI_F_BUS_INITED;
1226 return bwi_regwin_switch(sc, old, NULL);
1230 bwi_get_card_flags(struct bwi_softc *sc)
1232 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1233 if (sc->sc_card_flags == 0xffff)
1234 sc->sc_card_flags = 0;
1236 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1237 sc->sc_pci_subdid == 0x4e && /* XXX */
1238 sc->sc_pci_revid > 0x40)
1239 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1241 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1245 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1249 for (i = 0; i < 3; ++i) {
1250 *((uint16_t *)eaddr + i) =
1251 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1256 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1258 struct bwi_regwin *com;
1263 bzero(freq, sizeof(*freq));
1264 com = &sc->sc_com_regwin;
1266 KKASSERT(BWI_REGWIN_EXIST(com));
1267 KKASSERT(sc->sc_cur_regwin == com);
1268 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1271 * Calculate clock frequency
1275 if (com->rw_rev < 6) {
1276 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1277 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1278 src = BWI_CLKSRC_PCI;
1281 src = BWI_CLKSRC_CS_OSC;
1284 } else if (com->rw_rev < 10) {
1285 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1287 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1288 if (src == BWI_CLKSRC_LP_OSC) {
1291 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1293 /* Unknown source */
1294 if (src >= BWI_CLKSRC_MAX)
1295 src = BWI_CLKSRC_CS_OSC;
1298 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1300 src = BWI_CLKSRC_CS_OSC;
1301 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1304 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1307 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1308 src == BWI_CLKSRC_PCI ? "PCI" :
1309 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1311 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1312 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1314 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1315 freq->clkfreq_min, freq->clkfreq_max);
1319 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1321 struct bwi_regwin *old, *com;
1322 uint32_t clk_ctrl, clk_src;
1323 int error, pwr_off = 0;
1325 com = &sc->sc_com_regwin;
1326 if (!BWI_REGWIN_EXIST(com))
1329 if (com->rw_rev >= 10 || com->rw_rev < 6)
1333 * For common regwin whose rev is [6, 10), the chip
1334 * must be capable to change clock mode.
1336 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1339 error = bwi_regwin_switch(sc, com, &old);
1343 if (clk_mode == BWI_CLOCK_MODE_FAST)
1344 bwi_power_on(sc, 0); /* Don't turn on PLL */
1346 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1347 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1350 case BWI_CLOCK_MODE_FAST:
1351 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1352 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1354 case BWI_CLOCK_MODE_SLOW:
1355 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1357 case BWI_CLOCK_MODE_DYN:
1358 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1359 BWI_CLOCK_CTRL_IGNPLL |
1360 BWI_CLOCK_CTRL_NODYN);
1361 if (clk_src != BWI_CLKSRC_CS_OSC) {
1362 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1367 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1370 bwi_power_off(sc, 0); /* Leave PLL as it is */
1372 return bwi_regwin_switch(sc, old, NULL);
1376 bwi_set_clock_delay(struct bwi_softc *sc)
1378 struct bwi_regwin *old, *com;
1381 com = &sc->sc_com_regwin;
1382 if (!BWI_REGWIN_EXIST(com))
1385 error = bwi_regwin_switch(sc, com, &old);
1389 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1390 if (sc->sc_bbp_rev == 0)
1391 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1392 else if (sc->sc_bbp_rev == 1)
1393 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1396 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1397 if (com->rw_rev >= 10) {
1398 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1400 struct bwi_clock_freq freq;
1402 bwi_get_clock_freq(sc, &freq);
1403 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1404 howmany(freq.clkfreq_max * 150, 1000000));
1405 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1406 howmany(freq.clkfreq_max * 15, 1000000));
1410 return bwi_regwin_switch(sc, old, NULL);
1416 struct bwi_softc *sc = xsc;
1417 struct ieee80211com *ic = &sc->sc_ic;
1418 struct ifnet *ifp = &ic->ic_if;
1419 struct bwi_mac *mac;
1422 ASSERT_SERIALIZED(ifp->if_serializer);
1424 error = bwi_stop(sc);
1426 if_printf(ifp, "can't stop\n");
1430 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1434 mac = &sc->sc_mac[0];
1435 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1439 error = bwi_mac_init(mac);
1443 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1445 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1447 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1448 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1450 bwi_mac_reset_hwkeys(mac);
1452 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1457 * Drain any possible pending TX status
1459 for (i = 0; i < NRETRY; ++i) {
1460 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1461 BWI_TXSTATUS0_VALID) == 0)
1463 CSR_READ_4(sc, BWI_TXSTATUS1);
1466 if_printf(ifp, "can't drain TX status\n");
1470 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1471 bwi_mac_updateslot(mac, 1);
1474 error = bwi_mac_start(mac);
1479 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1481 ifp->if_flags |= IFF_RUNNING;
1482 ifp->if_flags &= ~IFF_OACTIVE;
1484 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1485 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1486 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1488 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1496 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1498 struct bwi_softc *sc = ifp->if_softc;
1501 ASSERT_SERIALIZED(ifp->if_serializer);
1505 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1506 (IFF_UP | IFF_RUNNING)) {
1507 struct bwi_mac *mac;
1510 KKASSERT(sc->sc_cur_regwin->rw_type ==
1512 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1514 if ((ifp->if_flags & IFF_PROMISC) &&
1515 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1517 sc->sc_flags |= BWI_F_PROMISC;
1518 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1519 (sc->sc_flags & BWI_F_PROMISC)) {
1521 sc->sc_flags &= ~BWI_F_PROMISC;
1525 bwi_mac_set_promisc(mac, promisc);
1528 if (ifp->if_flags & IFF_UP) {
1529 if ((ifp->if_flags & IFF_RUNNING) == 0)
1532 if (ifp->if_flags & IFF_RUNNING)
1537 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1541 if (error == ENETRESET) {
1542 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1543 (IFF_UP | IFF_RUNNING))
1551 bwi_start(struct ifnet *ifp)
1553 struct bwi_softc *sc = ifp->if_softc;
1554 struct ieee80211com *ic = &sc->sc_ic;
1555 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1558 ASSERT_SERIALIZED(ifp->if_serializer);
1560 if ((ifp->if_flags & IFF_OACTIVE) ||
1561 (ifp->if_flags & IFF_RUNNING) == 0)
1567 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1568 struct ieee80211_frame *wh;
1569 struct ieee80211_node *ni;
1573 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1574 IF_DEQUEUE(&ic->ic_mgtq, m);
1576 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1577 m->m_pkthdr.rcvif = NULL;
1580 } else if (!ifq_is_empty(&ifp->if_snd)) {
1581 struct ether_header *eh;
1583 if (ic->ic_state != IEEE80211_S_RUN)
1586 m = ifq_dequeue(&ifp->if_snd, NULL);
1590 if (m->m_len < sizeof(*eh)) {
1591 m = m_pullup(m, sizeof(*eh));
1597 eh = mtod(m, struct ether_header *);
1599 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1610 m = ieee80211_encap(ic, m, ni);
1612 ieee80211_free_node(ni);
1620 if (ic->ic_rawbpf != NULL)
1621 bpf_mtap(ic->ic_rawbpf, m);
1623 wh = mtod(m, struct ieee80211_frame *);
1624 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1625 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1626 ieee80211_free_node(ni);
1632 wh = NULL; /* Catch any invalid use */
1634 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1635 /* 'm' is freed in bwi_encap() if we reach here */
1637 ieee80211_free_node(ni);
1644 idx = (idx + 1) % BWI_TX_NDESC;
1646 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1647 ifp->if_flags |= IFF_OACTIVE;
1654 sc->sc_tx_timer = 5;
1659 bwi_watchdog(struct ifnet *ifp)
1661 struct bwi_softc *sc = ifp->if_softc;
1663 ASSERT_SERIALIZED(ifp->if_serializer);
1667 if ((ifp->if_flags & IFF_RUNNING) == 0)
1670 if (sc->sc_tx_timer) {
1671 if (--sc->sc_tx_timer == 0) {
1672 if_printf(ifp, "watchdog timeout\n");
1679 ieee80211_watchdog(&sc->sc_ic);
1683 bwi_stop(struct bwi_softc *sc)
1685 struct ieee80211com *ic = &sc->sc_ic;
1686 struct ifnet *ifp = &ic->ic_if;
1687 struct bwi_mac *mac;
1688 int i, error, pwr_off = 0;
1690 ASSERT_SERIALIZED(ifp->if_serializer);
1692 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1694 if (ifp->if_flags & IFF_RUNNING) {
1695 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1696 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1698 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1699 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1703 for (i = 0; i < sc->sc_nmac; ++i) {
1704 struct bwi_regwin *old_rw;
1706 mac = &sc->sc_mac[i];
1707 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1710 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1714 bwi_mac_shutdown(mac);
1717 bwi_regwin_switch(sc, old_rw, NULL);
1721 bwi_bbp_power_off(sc);
1723 sc->sc_tx_timer = 0;
1725 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1732 struct bwi_softc *sc = xsc;
1733 struct ifnet *ifp = &sc->sc_ic.ic_if;
1734 uint32_t intr_status;
1735 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1736 int i, txrx_error, tx = 0, rx_data = -1;
1738 ASSERT_SERIALIZED(ifp->if_serializer);
1740 if ((ifp->if_flags & IFF_RUNNING) == 0)
1744 * Get interrupt status
1746 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1747 if (intr_status == 0xffffffff) /* Not for us */
1750 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1752 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1753 if (intr_status == 0) /* Nothing is interesting */
1757 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1758 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1761 if (BWI_TXRX_IS_RX(i))
1762 mask = BWI_TXRX_RX_INTRS;
1764 mask = BWI_TXRX_TX_INTRS;
1766 txrx_intr_status[i] =
1767 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1769 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1770 i, txrx_intr_status[i]);
1772 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1773 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1774 i, txrx_intr_status[i]);
1778 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1781 * Acknowledge interrupt
1783 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1785 for (i = 0; i < BWI_TXRX_NRING; ++i)
1786 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1788 /* Disable all interrupts */
1789 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1791 if (intr_status & BWI_INTR_PHY_TXERR)
1792 if_printf(ifp, "intr PHY TX error\n");
1795 /* TODO: reset device */
1798 if (intr_status & BWI_INTR_TBTT) {
1799 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1800 bwi_mac_config_ps((struct bwi_mac *)sc->sc_cur_regwin);
1803 if (intr_status & BWI_INTR_EO_ATIM)
1804 if_printf(ifp, "EO_ATIM\n");
1806 if (intr_status & BWI_INTR_PMQ) {
1808 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1811 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1814 if (intr_status & BWI_INTR_NOISE)
1815 if_printf(ifp, "intr noise\n");
1817 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1818 rx_data = sc->sc_rxeof(sc);
1820 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1821 sc->sc_txeof_status(sc);
1825 if (intr_status & BWI_INTR_TX_DONE) {
1830 /* Re-enable interrupts */
1831 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1833 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1834 int evt = BWI_LED_EVENT_NONE;
1836 if (tx && rx_data > 0) {
1837 if (sc->sc_rx_rate > sc->sc_tx_rate)
1838 evt = BWI_LED_EVENT_RX;
1840 evt = BWI_LED_EVENT_TX;
1842 evt = BWI_LED_EVENT_TX;
1843 } else if (rx_data > 0) {
1844 evt = BWI_LED_EVENT_RX;
1845 } else if (rx_data == 0) {
1846 evt = BWI_LED_EVENT_POLL;
1849 if (evt != BWI_LED_EVENT_NONE)
1850 bwi_led_event(sc, evt);
1855 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1857 struct bwi_softc *sc = ic->ic_if.if_softc;
1858 struct ifnet *ifp = &ic->ic_if;
1861 ASSERT_SERIALIZED(ifp->if_serializer);
1863 callout_stop(&sc->sc_scan_ch);
1864 callout_stop(&sc->sc_calib_ch);
1866 ieee80211_ratectl_newstate(ic, nstate);
1867 bwi_led_newstate(sc, nstate);
1869 if (nstate == IEEE80211_S_INIT)
1872 error = bwi_set_chan(sc, ic->ic_curchan);
1874 if_printf(ifp, "can't set channel to %u\n",
1875 ieee80211_chan2ieee(ic, ic->ic_curchan));
1879 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1881 } else if (nstate == IEEE80211_S_RUN) {
1882 struct bwi_mac *mac;
1884 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1886 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1887 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1889 /* Initial TX power calibration */
1890 bwi_mac_calibrate_txpower(mac);
1892 bwi_set_bssid(sc, bwi_zero_addr);
1896 error = sc->sc_newstate(ic, nstate, arg);
1898 if (nstate == IEEE80211_S_SCAN) {
1899 callout_reset(&sc->sc_scan_ch,
1900 (sc->sc_dwell_time * hz) / 1000,
1902 } else if (nstate == IEEE80211_S_RUN) {
1903 /* XXX 15 seconds */
1904 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
1910 bwi_media_change(struct ifnet *ifp)
1914 ASSERT_SERIALIZED(ifp->if_serializer);
1916 error = ieee80211_media_change(ifp);
1917 if (error != ENETRESET)
1920 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1921 bwi_init(ifp->if_softc);
1926 bwi_dma_alloc(struct bwi_softc *sc)
1928 int error, i, has_txstats;
1929 bus_addr_t lowaddr = 0;
1930 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1931 uint32_t txrx_ctrl_step = 0;
1934 for (i = 0; i < sc->sc_nmac; ++i) {
1935 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1941 switch (sc->sc_bus_space) {
1942 case BWI_BUS_SPACE_30BIT:
1943 case BWI_BUS_SPACE_32BIT:
1944 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1945 lowaddr = BWI_BUS_SPACE_MAXADDR;
1947 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1948 desc_sz = sizeof(struct bwi_desc32);
1949 txrx_ctrl_step = 0x20;
1951 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1952 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1953 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1954 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1955 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1956 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1957 sc->sc_rxeof = bwi_rxeof32;
1958 sc->sc_start_tx = bwi_start_tx32;
1960 sc->sc_init_txstats = bwi_init_txstats32;
1961 sc->sc_free_txstats = bwi_free_txstats32;
1962 sc->sc_txeof_status = bwi_txeof_status32;
1966 case BWI_BUS_SPACE_64BIT:
1967 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1968 desc_sz = sizeof(struct bwi_desc64);
1969 txrx_ctrl_step = 0x40;
1971 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1972 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1973 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1974 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1975 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1976 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1977 sc->sc_rxeof = bwi_rxeof64;
1978 sc->sc_start_tx = bwi_start_tx64;
1980 sc->sc_init_txstats = bwi_init_txstats64;
1981 sc->sc_free_txstats = bwi_free_txstats64;
1982 sc->sc_txeof_status = bwi_txeof_status64;
1987 KKASSERT(lowaddr != 0);
1988 KKASSERT(desc_sz != 0);
1989 KKASSERT(txrx_ctrl_step != 0);
1991 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1992 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1995 * Create top level DMA tag
1997 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
1998 lowaddr, BUS_SPACE_MAXADDR,
2001 BUS_SPACE_UNRESTRICTED,
2002 BUS_SPACE_MAXSIZE_32BIT,
2003 0, &sc->sc_parent_dtag);
2005 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2009 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2012 * Create TX ring DMA stuffs
2014 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2015 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2017 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2018 0, &sc->sc_txring_dtag);
2020 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2024 for (i = 0; i < BWI_TX_NRING; ++i) {
2025 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2026 &sc->sc_tx_rdata[i], tx_ring_sz,
2029 device_printf(sc->sc_dev, "%dth TX ring "
2030 "DMA alloc failed\n", i);
2036 * Create RX ring DMA stuffs
2038 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2039 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2041 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2042 0, &sc->sc_rxring_dtag);
2044 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2048 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2049 rx_ring_sz, TXRX_CTRL(0));
2051 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2056 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2058 device_printf(sc->sc_dev,
2059 "TX stats DMA alloc failed\n");
2066 return bwi_dma_mbuf_create(sc);
2070 bwi_dma_free(struct bwi_softc *sc)
2072 if (sc->sc_txring_dtag != NULL) {
2075 for (i = 0; i < BWI_TX_NRING; ++i) {
2076 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2078 if (rd->rdata_desc != NULL) {
2079 bus_dmamap_unload(sc->sc_txring_dtag,
2081 bus_dmamem_free(sc->sc_txring_dtag,
2086 bus_dma_tag_destroy(sc->sc_txring_dtag);
2089 if (sc->sc_rxring_dtag != NULL) {
2090 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2092 if (rd->rdata_desc != NULL) {
2093 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2094 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2097 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2100 bwi_dma_txstats_free(sc);
2101 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2103 if (sc->sc_parent_dtag != NULL)
2104 bus_dma_tag_destroy(sc->sc_parent_dtag);
2108 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2109 struct bwi_ring_data *rd, bus_size_t size,
2114 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2115 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2118 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2122 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2123 bwi_dma_ring_addr, &rd->rdata_paddr,
2126 device_printf(sc->sc_dev, "can't load DMA mem\n");
2127 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2128 rd->rdata_desc = NULL;
2132 rd->rdata_txrx_ctrl = txrx_ctrl;
2137 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2140 struct bwi_txstats_data *st;
2141 bus_size_t dma_size;
2144 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2145 sc->sc_txstats = st;
2148 * Create TX stats descriptor DMA stuffs
2150 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2152 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2153 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2155 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2156 0, &st->stats_ring_dtag);
2158 device_printf(sc->sc_dev, "can't create txstats ring "
2163 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2164 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2165 &st->stats_ring_dmap);
2167 device_printf(sc->sc_dev, "can't allocate txstats ring "
2169 bus_dma_tag_destroy(st->stats_ring_dtag);
2170 st->stats_ring_dtag = NULL;
2174 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2175 st->stats_ring, dma_size,
2176 bwi_dma_ring_addr, &st->stats_ring_paddr,
2179 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2180 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2181 st->stats_ring_dmap);
2182 bus_dma_tag_destroy(st->stats_ring_dtag);
2183 st->stats_ring_dtag = NULL;
2188 * Create TX stats DMA stuffs
2190 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2193 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2194 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2196 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2197 0, &st->stats_dtag);
2199 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2203 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2204 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2207 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2208 bus_dma_tag_destroy(st->stats_dtag);
2209 st->stats_dtag = NULL;
2213 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2214 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2217 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2218 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2219 bus_dma_tag_destroy(st->stats_dtag);
2220 st->stats_dtag = NULL;
2224 st->stats_ctrl_base = ctrl_base;
2229 bwi_dma_txstats_free(struct bwi_softc *sc)
2231 struct bwi_txstats_data *st;
2233 if (sc->sc_txstats == NULL)
2235 st = sc->sc_txstats;
2237 if (st->stats_ring_dtag != NULL) {
2238 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2239 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2240 st->stats_ring_dmap);
2241 bus_dma_tag_destroy(st->stats_ring_dtag);
2244 if (st->stats_dtag != NULL) {
2245 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2246 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2247 bus_dma_tag_destroy(st->stats_dtag);
2250 kfree(st, M_DEVBUF);
2254 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2256 KASSERT(nseg == 1, ("too many segments\n"));
2257 *((bus_addr_t *)arg) = seg->ds_addr;
2261 bwi_dma_mbuf_create(struct bwi_softc *sc)
2263 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2264 int i, j, k, ntx, error;
2267 * Create TX/RX mbuf DMA tag
2269 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2270 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2271 NULL, NULL, MCLBYTES, 1,
2272 BUS_SPACE_MAXSIZE_32BIT,
2273 0, &sc->sc_buf_dtag);
2275 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2282 * Create TX mbuf DMA map
2284 for (i = 0; i < BWI_TX_NRING; ++i) {
2285 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2287 for (j = 0; j < BWI_TX_NDESC; ++j) {
2288 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2289 &tbd->tbd_buf[j].tb_dmap);
2291 device_printf(sc->sc_dev, "can't create "
2292 "%dth tbd, %dth DMA map\n", i, j);
2295 for (k = 0; k < j; ++k) {
2296 bus_dmamap_destroy(sc->sc_buf_dtag,
2297 tbd->tbd_buf[k].tb_dmap);
2306 * Create RX mbuf DMA map and a spare DMA map
2308 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2309 &rbd->rbd_tmp_dmap);
2311 device_printf(sc->sc_dev,
2312 "can't create spare RX buf DMA map\n");
2316 for (j = 0; j < BWI_RX_NDESC; ++j) {
2317 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2318 &rbd->rbd_buf[j].rb_dmap);
2320 device_printf(sc->sc_dev, "can't create %dth "
2321 "RX buf DMA map\n", j);
2323 for (k = 0; k < j; ++k) {
2324 bus_dmamap_destroy(sc->sc_buf_dtag,
2325 rbd->rbd_buf[j].rb_dmap);
2327 bus_dmamap_destroy(sc->sc_buf_dtag,
2335 bwi_dma_mbuf_destroy(sc, ntx, 0);
2340 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2344 if (sc->sc_buf_dtag == NULL)
2347 for (i = 0; i < ntx; ++i) {
2348 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2350 for (j = 0; j < BWI_TX_NDESC; ++j) {
2351 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2353 if (tb->tb_mbuf != NULL) {
2354 bus_dmamap_unload(sc->sc_buf_dtag,
2356 m_freem(tb->tb_mbuf);
2358 if (tb->tb_ni != NULL)
2359 ieee80211_free_node(tb->tb_ni);
2360 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2365 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2367 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2368 for (j = 0; j < BWI_RX_NDESC; ++j) {
2369 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2371 if (rb->rb_mbuf != NULL) {
2372 bus_dmamap_unload(sc->sc_buf_dtag,
2374 m_freem(rb->rb_mbuf);
2376 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2380 bus_dma_tag_destroy(sc->sc_buf_dtag);
2381 sc->sc_buf_dtag = NULL;
2385 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2387 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2391 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2393 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2397 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2399 struct bwi_ring_data *rd;
2400 struct bwi_txbuf_data *tbd;
2401 uint32_t val, addr_hi, addr_lo;
2403 KKASSERT(ring_idx < BWI_TX_NRING);
2404 rd = &sc->sc_tx_rdata[ring_idx];
2405 tbd = &sc->sc_tx_bdata[ring_idx];
2410 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2411 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2412 BUS_DMASYNC_PREWRITE);
2414 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2415 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2417 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2418 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2419 BWI_TXRX32_RINGINFO_FUNC_MASK);
2420 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2422 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2423 BWI_TXRX32_CTRL_ENABLE;
2424 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2430 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2431 bus_addr_t paddr, int hdr_size, int ndesc)
2433 uint32_t val, addr_hi, addr_lo;
2435 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2436 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2438 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2439 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2440 BWI_TXRX32_RINGINFO_FUNC_MASK);
2441 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2443 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2444 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2445 BWI_TXRX32_CTRL_ENABLE;
2446 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2448 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2449 (ndesc - 1) * sizeof(struct bwi_desc32));
2453 bwi_init_rx_ring32(struct bwi_softc *sc)
2455 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2458 sc->sc_rx_bdata.rbd_idx = 0;
2460 for (i = 0; i < BWI_RX_NDESC; ++i) {
2461 error = bwi_newbuf(sc, i, 1);
2463 if_printf(&sc->sc_ic.ic_if,
2464 "can't allocate %dth RX buffer\n", i);
2468 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2469 BUS_DMASYNC_PREWRITE);
2471 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2472 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2477 bwi_init_txstats32(struct bwi_softc *sc)
2479 struct bwi_txstats_data *st = sc->sc_txstats;
2480 bus_addr_t stats_paddr;
2483 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2484 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2488 stats_paddr = st->stats_paddr;
2489 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2490 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2491 stats_paddr, sizeof(struct bwi_txstats), 0);
2492 stats_paddr += sizeof(struct bwi_txstats);
2494 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2495 BUS_DMASYNC_PREWRITE);
2497 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2498 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2503 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2506 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2508 KKASSERT(buf_idx < BWI_RX_NDESC);
2509 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2514 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2515 int buf_idx, bus_addr_t paddr, int buf_len)
2517 KKASSERT(buf_idx < BWI_TX_NDESC);
2518 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2523 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2530 bwi_init_rx_ring64(struct bwi_softc *sc)
2537 bwi_init_txstats64(struct bwi_softc *sc)
2544 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2551 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2552 int buf_idx, bus_addr_t paddr, int buf_len)
2558 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2559 bus_size_t mapsz __unused, int error)
2562 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2563 *((bus_addr_t *)arg) = seg->ds_addr;
2568 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2570 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2571 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2572 struct bwi_rxbuf_hdr *hdr;
2578 KKASSERT(buf_idx < BWI_RX_NDESC);
2580 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2585 * If the NIC is up and running, we need to:
2586 * - Clear RX buffer's header.
2587 * - Restore RX descriptor settings.
2594 m->m_len = m->m_pkthdr.len = MCLBYTES;
2597 * Try to load RX buf into temporary DMA map
2599 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2600 bwi_dma_buf_addr, &paddr,
2601 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2606 * See the comment above
2615 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2617 rxbuf->rb_paddr = paddr;
2620 * Swap RX buf's DMA map with the loaded temporary one
2622 map = rxbuf->rb_dmap;
2623 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2624 rbd->rbd_tmp_dmap = map;
2628 * Clear RX buf header
2630 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2631 bzero(hdr, sizeof(*hdr));
2632 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2635 * Setup RX buf descriptor
2637 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2638 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2643 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2644 const uint8_t *addr)
2648 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2649 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2651 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2654 addr_val = (uint16_t)addr[i * 2] |
2655 (((uint16_t)addr[(i * 2) + 1]) << 8);
2656 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2661 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2663 struct ieee80211com *ic = &sc->sc_ic;
2664 struct ifnet *ifp = &ic->ic_if;
2665 struct bwi_mac *mac;
2669 ASSERT_SERIALIZED(ifp->if_serializer);
2671 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2672 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2674 chan = ieee80211_chan2ieee(ic, c);
2676 bwi_rf_set_chan(mac, chan, 0);
2679 * Setup radio tap channel freq and flags
2681 if (IEEE80211_IS_CHAN_G(c))
2682 flags = IEEE80211_CHAN_G;
2684 flags = IEEE80211_CHAN_B;
2686 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2687 htole16(c->ic_freq);
2688 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2695 bwi_next_scan(void *xsc)
2697 struct bwi_softc *sc = xsc;
2698 struct ieee80211com *ic = &sc->sc_ic;
2699 struct ifnet *ifp = &ic->ic_if;
2701 lwkt_serialize_enter(ifp->if_serializer);
2703 if (ic->ic_state == IEEE80211_S_SCAN)
2704 ieee80211_next_scan(ic);
2706 lwkt_serialize_exit(ifp->if_serializer);
2710 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2712 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2713 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2714 struct ieee80211com *ic = &sc->sc_ic;
2715 struct ifnet *ifp = &ic->ic_if;
2716 int idx, rx_data = 0;
2719 while (idx != end_idx) {
2720 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2721 struct bwi_rxbuf_hdr *hdr;
2722 struct ieee80211_frame_min *wh;
2723 struct ieee80211_node *ni;
2727 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2730 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2731 BUS_DMASYNC_POSTREAD);
2733 if (bwi_newbuf(sc, idx, 0)) {
2738 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2739 flags2 = le16toh(hdr->rxh_flags2);
2742 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2744 wh_ofs = hdr_extra + 6; /* XXX magic number */
2746 buflen = le16toh(hdr->rxh_buflen);
2747 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2748 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2755 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2756 rssi = bwi_calc_rssi(sc, hdr);
2758 m->m_pkthdr.rcvif = ifp;
2759 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2760 m_adj(m, sizeof(*hdr) + wh_ofs);
2762 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2763 rate = bwi_ofdm_plcp2rate(plcp);
2765 rate = bwi_ds_plcp2rate(plcp);
2768 if (sc->sc_drvbpf != NULL)
2769 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2771 m_adj(m, -IEEE80211_CRC_LEN);
2773 wh = mtod(m, struct ieee80211_frame_min *);
2774 ni = ieee80211_find_rxnode(ic, wh);
2776 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2777 le16toh(hdr->rxh_tsf));
2778 ieee80211_free_node(ni);
2780 if (type == IEEE80211_FC0_TYPE_DATA) {
2782 sc->sc_rx_rate = rate;
2785 idx = (idx + 1) % BWI_RX_NDESC;
2789 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2790 BUS_DMASYNC_PREWRITE);
2795 bwi_rxeof32(struct bwi_softc *sc)
2797 uint32_t val, rx_ctrl;
2798 int end_idx, rx_data;
2800 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2802 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2803 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2804 sizeof(struct bwi_desc32);
2806 rx_data = bwi_rxeof(sc, end_idx);
2808 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2809 end_idx * sizeof(struct bwi_desc32));
2815 bwi_rxeof64(struct bwi_softc *sc)
2822 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2826 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2830 for (i = 0; i < NRETRY; ++i) {
2833 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2834 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2835 BWI_RX32_STATUS_STATE_DISABLED)
2841 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2845 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2849 bwi_free_txstats32(struct bwi_softc *sc)
2851 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2855 bwi_free_rx_ring32(struct bwi_softc *sc)
2857 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2858 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2861 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2863 for (i = 0; i < BWI_RX_NDESC; ++i) {
2864 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2866 if (rb->rb_mbuf != NULL) {
2867 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2868 m_freem(rb->rb_mbuf);
2875 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2877 struct bwi_ring_data *rd;
2878 struct bwi_txbuf_data *tbd;
2879 struct ifnet *ifp = &sc->sc_ic.ic_if;
2880 uint32_t state, val;
2883 KKASSERT(ring_idx < BWI_TX_NRING);
2884 rd = &sc->sc_tx_rdata[ring_idx];
2885 tbd = &sc->sc_tx_bdata[ring_idx];
2889 for (i = 0; i < NRETRY; ++i) {
2890 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2891 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2892 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2893 state == BWI_TX32_STATUS_STATE_IDLE ||
2894 state == BWI_TX32_STATUS_STATE_STOPPED)
2900 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2904 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2905 for (i = 0; i < NRETRY; ++i) {
2906 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2907 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2908 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2914 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2920 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2922 for (i = 0; i < BWI_TX_NDESC; ++i) {
2923 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2925 if (tb->tb_mbuf != NULL) {
2926 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2927 m_freem(tb->tb_mbuf);
2930 if (tb->tb_ni != NULL) {
2931 ieee80211_free_node(tb->tb_ni);
2938 bwi_free_txstats64(struct bwi_softc *sc)
2944 bwi_free_rx_ring64(struct bwi_softc *sc)
2950 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2956 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2957 struct ieee80211_node **ni0, int mgt_pkt)
2959 struct ieee80211com *ic = &sc->sc_ic;
2960 struct ieee80211_node *ni = *ni0;
2961 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2962 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2963 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2964 struct bwi_mac *mac;
2965 struct bwi_txbuf_hdr *hdr;
2966 struct ieee80211_frame *wh;
2967 uint8_t rate, rate_fb;
2971 int pkt_len, error, mcast_pkt = 0;
2977 KKASSERT(ni != NULL);
2978 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2979 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2981 wh = mtod(m, struct ieee80211_frame *);
2983 /* Get 802.11 frame len before prepending TX header */
2984 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2989 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
2991 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
2994 rate = IEEE80211_RS_RATE(&ni->ni_rates,
2997 if (ic->ic_fixed_rate >= 1)
2998 idx = ic->ic_fixed_rate - 1;
3001 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3003 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3004 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3006 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3008 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3009 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3014 tb->tb_buflen = m->m_pkthdr.len;
3017 /* Fixed at 1Mbits/s for mgt frames */
3018 rate = rate_fb = (1 * 2);
3021 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3022 rate = rate_fb = ic->ic_mcast_rate;
3026 if (rate == 0 || rate_fb == 0) {
3027 /* XXX this should not happen */
3028 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3030 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3032 sc->sc_tx_rate = rate;
3037 if (sc->sc_drvbpf != NULL) {
3038 sc->sc_tx_th.wt_flags = 0;
3039 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3040 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3041 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3042 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3044 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3046 sc->sc_tx_th.wt_rate = rate;
3048 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3052 * Setup the embedded TX header
3054 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3056 if_printf(&ic->ic_if, "prepend TX header failed\n");
3059 hdr = mtod(m, struct bwi_txbuf_hdr *);
3061 bzero(hdr, sizeof(*hdr));
3063 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3064 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3070 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3071 dur = ieee80211_txtime(ni,
3072 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3073 ack_rate, ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3075 hdr->txh_fb_duration = htole16(dur);
3078 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3079 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3081 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3082 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3084 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3085 BWI_TXH_PHY_C_ANTMODE_MASK);
3086 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3087 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3088 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3089 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3091 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3092 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3093 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3094 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3095 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3097 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3098 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3100 /* Catch any further usage */
3105 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3106 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3107 if (error && error != EFBIG) {
3108 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3112 if (error) { /* error == EFBIG */
3115 m_new = m_defrag(m, MB_DONTWAIT);
3116 if (m_new == NULL) {
3117 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3124 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3125 bwi_dma_buf_addr, &paddr,
3128 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3135 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3137 if (mgt_pkt || mcast_pkt) {
3138 /* Don't involve mcast/mgt packets into TX rate control */
3139 ieee80211_free_node(ni);
3146 p = mtod(m, const uint8_t *);
3147 for (i = 0; i < m->m_pkthdr.len; ++i) {
3148 if (i != 0 && i % 8 == 0)
3150 kprintf("%02x ", p[i]);
3155 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3156 idx, pkt_len, m->m_pkthdr.len);
3158 /* Setup TX descriptor */
3159 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3160 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3161 BUS_DMASYNC_PREWRITE);
3164 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3173 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3175 idx = (idx + 1) % BWI_TX_NDESC;
3176 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3177 idx * sizeof(struct bwi_desc32));
3181 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3187 bwi_txeof_status32(struct bwi_softc *sc)
3189 struct ifnet *ifp = &sc->sc_ic.ic_if;
3190 uint32_t val, ctrl_base;
3193 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3195 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3196 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3197 sizeof(struct bwi_desc32);
3199 bwi_txeof_status(sc, end_idx);
3201 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3202 end_idx * sizeof(struct bwi_desc32));
3204 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3209 bwi_txeof_status64(struct bwi_softc *sc)
3215 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3217 struct ifnet *ifp = &sc->sc_ic.ic_if;
3218 struct bwi_txbuf_data *tbd;
3219 struct bwi_txbuf *tb;
3220 int ring_idx, buf_idx;
3223 if_printf(ifp, "zero tx id\n");
3227 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3228 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3230 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3231 KKASSERT(buf_idx < BWI_TX_NDESC);
3233 tbd = &sc->sc_tx_bdata[ring_idx];
3234 KKASSERT(tbd->tbd_used > 0);
3237 tb = &tbd->tbd_buf[buf_idx];
3239 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3240 "acked %d, data_txcnt %d, ni %p\n",
3241 buf_idx, acked, data_txcnt, tb->tb_ni);
3243 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3244 m_freem(tb->tb_mbuf);
3247 if (tb->tb_ni != NULL) {
3248 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3251 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3253 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3254 res[0].rc_res_tries = data_txcnt;
3256 res_len = BWI_NTXRATE;
3257 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3258 res[0].rc_res_tries = BWI_SHRETRY_FB;
3259 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3260 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3264 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3268 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3269 res, res_len, retry, 0, !acked);
3271 ieee80211_free_node(tb->tb_ni);
3275 if (tbd->tbd_used == 0)
3276 sc->sc_tx_timer = 0;
3278 ifp->if_flags &= ~IFF_OACTIVE;
3282 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3284 struct bwi_txstats_data *st = sc->sc_txstats;
3287 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3289 idx = st->stats_idx;
3290 while (idx != end_idx) {
3291 const struct bwi_txstats *stats = &st->stats[idx];
3293 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3296 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3297 BWI_TXS_TXCNT_DATA);
3298 _bwi_txeof(sc, le16toh(stats->txs_id),
3299 stats->txs_flags & BWI_TXS_F_ACKED,
3302 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3304 st->stats_idx = idx;
3308 bwi_txeof(struct bwi_softc *sc)
3310 struct ifnet *ifp = &sc->sc_ic.ic_if;
3313 uint32_t tx_status0, tx_status1;
3317 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3318 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3320 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3322 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3323 data_txcnt = __SHIFTOUT(tx_status0,
3324 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3326 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3329 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3333 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3338 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3340 bwi_power_on(sc, 1);
3341 return bwi_set_clock_mode(sc, clk_mode);
3345 bwi_bbp_power_off(struct bwi_softc *sc)
3347 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3348 bwi_power_off(sc, 1);
3352 bwi_get_pwron_delay(struct bwi_softc *sc)
3354 struct bwi_regwin *com, *old;
3355 struct bwi_clock_freq freq;
3359 com = &sc->sc_com_regwin;
3360 KKASSERT(BWI_REGWIN_EXIST(com));
3362 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3365 error = bwi_regwin_switch(sc, com, &old);
3369 bwi_get_clock_freq(sc, &freq);
3371 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3372 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3373 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3375 return bwi_regwin_switch(sc, old, NULL);
3379 bwi_bus_attach(struct bwi_softc *sc)
3381 struct bwi_regwin *bus, *old;
3384 bus = &sc->sc_bus_regwin;
3386 error = bwi_regwin_switch(sc, bus, &old);
3390 if (!bwi_regwin_is_enabled(sc, bus))
3391 bwi_regwin_enable(sc, bus, 0);
3393 /* Disable interripts */
3394 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3396 return bwi_regwin_switch(sc, old, NULL);
3400 bwi_regwin_name(const struct bwi_regwin *rw)
3402 switch (rw->rw_type) {
3403 case BWI_REGWIN_T_COM:
3405 case BWI_REGWIN_T_BUSPCI:
3407 case BWI_REGWIN_T_MAC:
3409 case BWI_REGWIN_T_BUSPCIE:
3412 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3417 bwi_regwin_disable_bits(struct bwi_softc *sc)
3421 /* XXX cache this */
3422 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3423 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3424 "bus rev %u\n", busrev);
3426 if (busrev == BWI_BUSREV_0)
3427 return BWI_STATE_LO_DISABLE1;
3428 else if (busrev == BWI_BUSREV_1)
3429 return BWI_STATE_LO_DISABLE2;
3431 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3435 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3437 uint32_t val, disable_bits;
3439 disable_bits = bwi_regwin_disable_bits(sc);
3440 val = CSR_READ_4(sc, BWI_STATE_LO);
3442 if ((val & (BWI_STATE_LO_CLOCK |
3443 BWI_STATE_LO_RESET |
3444 disable_bits)) == BWI_STATE_LO_CLOCK) {
3445 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3446 bwi_regwin_name(rw));
3449 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3450 bwi_regwin_name(rw));
3456 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3458 uint32_t state_lo, disable_bits;
3461 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3464 * If current regwin is in 'reset' state, it was already disabled.
3466 if (state_lo & BWI_STATE_LO_RESET) {
3467 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3468 "%s was already disabled\n", bwi_regwin_name(rw));
3472 disable_bits = bwi_regwin_disable_bits(sc);
3475 * Disable normal clock
3477 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3478 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3481 * Wait until normal clock is disabled
3484 for (i = 0; i < NRETRY; ++i) {
3485 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3486 if (state_lo & disable_bits)
3491 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3492 bwi_regwin_name(rw));
3495 for (i = 0; i < NRETRY; ++i) {
3498 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3499 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3504 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3505 bwi_regwin_name(rw));
3510 * Reset and disable regwin with gated clock
3512 state_lo = BWI_STATE_LO_RESET | disable_bits |
3513 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3514 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3515 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3517 /* Flush pending bus write */
3518 CSR_READ_4(sc, BWI_STATE_LO);
3521 /* Reset and disable regwin */
3522 state_lo = BWI_STATE_LO_RESET | disable_bits |
3523 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3524 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3526 /* Flush pending bus write */
3527 CSR_READ_4(sc, BWI_STATE_LO);
3532 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3534 uint32_t state_lo, state_hi, imstate;
3536 bwi_regwin_disable(sc, rw, flags);
3538 /* Reset regwin with gated clock */
3539 state_lo = BWI_STATE_LO_RESET |
3540 BWI_STATE_LO_CLOCK |
3541 BWI_STATE_LO_GATED_CLOCK |
3542 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3543 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3545 /* Flush pending bus write */
3546 CSR_READ_4(sc, BWI_STATE_LO);
3549 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3550 if (state_hi & BWI_STATE_HI_SERROR)
3551 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3553 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3554 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3555 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3556 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3559 /* Enable regwin with gated clock */
3560 state_lo = BWI_STATE_LO_CLOCK |
3561 BWI_STATE_LO_GATED_CLOCK |
3562 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3563 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3565 /* Flush pending bus write */
3566 CSR_READ_4(sc, BWI_STATE_LO);
3569 /* Enable regwin with normal clock */
3570 state_lo = BWI_STATE_LO_CLOCK |
3571 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3572 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3574 /* Flush pending bus write */
3575 CSR_READ_4(sc, BWI_STATE_LO);
3580 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3582 struct ieee80211com *ic = &sc->sc_ic;
3583 struct bwi_mac *mac;
3584 struct bwi_myaddr_bssid buf;
3589 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3590 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3592 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3594 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3595 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3597 n = sizeof(buf) / sizeof(val);
3598 p = (const uint8_t *)&buf;
3599 for (i = 0; i < n; ++i) {
3603 for (j = 0; j < sizeof(val); ++j)
3604 val |= ((uint32_t)(*p++)) << (j * 8);
3606 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3611 bwi_updateslot(struct ifnet *ifp)
3613 struct bwi_softc *sc = ifp->if_softc;
3614 struct ieee80211com *ic = &sc->sc_ic;
3615 struct bwi_mac *mac;
3617 if ((ifp->if_flags & IFF_RUNNING) == 0)
3620 ASSERT_SERIALIZED(ifp->if_serializer);
3622 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3624 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3625 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3627 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3631 bwi_calibrate(void *xsc)
3633 struct bwi_softc *sc = xsc;
3634 struct ieee80211com *ic = &sc->sc_ic;
3635 struct ifnet *ifp = &ic->ic_if;
3637 lwkt_serialize_enter(ifp->if_serializer);
3639 if (ic->ic_state == IEEE80211_S_RUN) {
3640 struct bwi_mac *mac;
3642 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3643 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3645 if (ic->ic_opmode != IEEE80211_M_MONITOR)
3646 bwi_mac_calibrate_txpower(mac);
3648 /* XXX 15 seconds */
3649 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3652 lwkt_serialize_exit(ifp->if_serializer);
3656 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3658 struct bwi_mac *mac;
3660 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3661 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3663 return bwi_rf_calc_rssi(mac, hdr);
3667 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3668 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3671 const struct ieee80211_frame_min *wh;
3673 KKASSERT(sc->sc_drvbpf != NULL);
3675 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3676 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3677 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3679 wh = mtod(m, const struct ieee80211_frame_min *);
3680 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3681 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3683 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3684 sc->sc_rx_th.wr_rate = rate;
3685 sc->sc_rx_th.wr_antsignal = rssi;
3686 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3688 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3692 bwi_led_attach(struct bwi_softc *sc)
3694 const uint8_t *led_act = NULL;
3695 uint16_t gpio, val[BWI_LED_MAX];
3698 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3700 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3701 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3702 led_act = bwi_vendor_led_act[i].led_act;
3706 if (led_act == NULL)
3707 led_act = bwi_default_led_act;
3711 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3712 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3713 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3715 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3716 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3717 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3719 for (i = 0; i < BWI_LED_MAX; ++i) {
3720 struct bwi_led *led = &sc->sc_leds[i];
3722 if (val[i] == 0xff) {
3723 led->l_act = led_act[i];
3725 if (val[i] & BWI_LED_ACT_LOW)
3726 led->l_flags |= BWI_LED_F_ACTLOW;
3727 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3729 led->l_mask = (1 << i);
3731 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3732 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3733 led->l_act == BWI_LED_ACT_BLINK) {
3734 led->l_flags |= BWI_LED_F_BLINK;
3735 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3736 led->l_flags |= BWI_LED_F_POLLABLE;
3737 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3738 led->l_flags |= BWI_LED_F_SLOW;
3740 if (sc->sc_blink_led == NULL) {
3741 sc->sc_blink_led = led;
3742 if (led->l_flags & BWI_LED_F_SLOW)
3743 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3747 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3748 "%dth led, act %d, lowact %d\n", i,
3749 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3751 callout_init(&sc->sc_led_blink_ch);
3754 static __inline uint16_t
3755 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3757 if (led->l_flags & BWI_LED_F_ACTLOW)
3762 val &= ~led->l_mask;
3767 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3769 struct ieee80211com *ic = &sc->sc_ic;
3773 if (nstate == IEEE80211_S_INIT) {
3774 callout_stop(&sc->sc_led_blink_ch);
3775 sc->sc_led_blinking = 0;
3778 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3781 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3782 for (i = 0; i < BWI_LED_MAX; ++i) {
3783 struct bwi_led *led = &sc->sc_leds[i];
3786 if (led->l_act == BWI_LED_ACT_UNKN ||
3787 led->l_act == BWI_LED_ACT_NULL)
3790 if ((led->l_flags & BWI_LED_F_BLINK) &&
3791 nstate != IEEE80211_S_INIT)
3794 switch (led->l_act) {
3795 case BWI_LED_ACT_ON: /* Always on */
3798 case BWI_LED_ACT_OFF: /* Always off */
3799 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3805 case IEEE80211_S_INIT:
3808 case IEEE80211_S_RUN:
3809 if (led->l_act == BWI_LED_ACT_11G &&
3810 ic->ic_curmode != IEEE80211_MODE_11G)
3814 if (led->l_act == BWI_LED_ACT_ASSOC)
3821 val = bwi_led_onoff(led, val, on);
3823 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3827 bwi_led_event(struct bwi_softc *sc, int event)
3829 struct bwi_led *led = sc->sc_blink_led;
3832 if (event == BWI_LED_EVENT_POLL) {
3833 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3835 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3839 sc->sc_led_ticks = ticks;
3840 if (sc->sc_led_blinking)
3844 case BWI_LED_EVENT_RX:
3845 rate = sc->sc_rx_rate;
3847 case BWI_LED_EVENT_TX:
3848 rate = sc->sc_tx_rate;
3850 case BWI_LED_EVENT_POLL:
3854 panic("unknown LED event %d\n", event);
3857 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3858 bwi_led_duration[rate].off_dur);
3862 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3864 struct bwi_led *led = sc->sc_blink_led;
3867 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3868 val = bwi_led_onoff(led, val, 1);
3869 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3871 if (led->l_flags & BWI_LED_F_SLOW) {
3872 BWI_LED_SLOWDOWN(on_dur);
3873 BWI_LED_SLOWDOWN(off_dur);
3876 sc->sc_led_blinking = 1;
3877 sc->sc_led_blink_offdur = off_dur;
3879 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3883 bwi_led_blink_next(void *xsc)
3885 struct bwi_softc *sc = xsc;
3888 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3889 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3890 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3892 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3893 bwi_led_blink_end, sc);
3897 bwi_led_blink_end(void *xsc)
3899 struct bwi_softc *sc = xsc;
3901 sc->sc_led_blinking = 0;