sys/dev/netif/ig_hal/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
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  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD: $*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #ifndef NO_82542_SUPPORT
  45 #define E1000_DEV_ID_82542                    0x1000
  46 #endif
  47 #define E1000_DEV_ID_82543GC_FIBER            0x1001
  48 #define E1000_DEV_ID_82543GC_COPPER           0x1004
  49 #define E1000_DEV_ID_82544EI_COPPER           0x1008
  50 #define E1000_DEV_ID_82544EI_FIBER            0x1009
  51 #define E1000_DEV_ID_82544GC_COPPER           0x100C
  52 #define E1000_DEV_ID_82544GC_LOM              0x100D
  53 #define E1000_DEV_ID_82540EM                  0x100E
  54 #define E1000_DEV_ID_82540EM_LOM              0x1015
  55 #define E1000_DEV_ID_82540EP_LOM              0x1016
  56 #define E1000_DEV_ID_82540EP                  0x1017
  57 #define E1000_DEV_ID_82540EP_LP               0x101E
  58 #define E1000_DEV_ID_82545EM_COPPER           0x100F
  59 #define E1000_DEV_ID_82545EM_FIBER            0x1011
  60 #define E1000_DEV_ID_82545GM_COPPER           0x1026
  61 #define E1000_DEV_ID_82545GM_FIBER            0x1027
  62 #define E1000_DEV_ID_82545GM_SERDES           0x1028
  63 #define E1000_DEV_ID_82546EB_COPPER           0x1010
  64 #define E1000_DEV_ID_82546EB_FIBER            0x1012
  65 #define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
  66 #define E1000_DEV_ID_82546GB_COPPER           0x1079
  67 #define E1000_DEV_ID_82546GB_FIBER            0x107A
  68 #define E1000_DEV_ID_82546GB_SERDES           0x107B
  69 #define E1000_DEV_ID_82546GB_PCIE             0x108A
  70 #define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
  71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
  72 #define E1000_DEV_ID_82541EI                  0x1013
  73 #define E1000_DEV_ID_82541EI_MOBILE           0x1018
  74 #define E1000_DEV_ID_82541ER_LOM              0x1014
  75 #define E1000_DEV_ID_82541ER                  0x1078
  76 #define E1000_DEV_ID_82541GI                  0x1076
  77 #define E1000_DEV_ID_82541GI_LF               0x107C
  78 #define E1000_DEV_ID_82541GI_MOBILE           0x1077
  79 #define E1000_DEV_ID_82547EI                  0x1019
  80 #define E1000_DEV_ID_82547EI_MOBILE           0x101A
  81 #define E1000_DEV_ID_82547GI                  0x1075
  82 #define E1000_DEV_ID_82571EB_COPPER           0x105E
  83 #define E1000_DEV_ID_82571EB_FIBER            0x105F
  84 #define E1000_DEV_ID_82571EB_SERDES           0x1060
  85 #define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
  86 #define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
  88 #define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
  89 #define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
  90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
  91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP   0x10A0
  92 #define E1000_DEV_ID_82572EI_COPPER           0x107D
  93 #define E1000_DEV_ID_82572EI_FIBER            0x107E
  94 #define E1000_DEV_ID_82572EI_SERDES           0x107F
  95 #define E1000_DEV_ID_82572EI                  0x10B9
  96 #define E1000_DEV_ID_82573E                   0x108B
  97 #define E1000_DEV_ID_82573E_IAMT              0x108C
  98 #define E1000_DEV_ID_82573L                   0x109A
  99 #define E1000_DEV_ID_82574L                   0x10D3
 100 #define E1000_DEV_ID_82574LA                  0x10F6
 101 #define E1000_DEV_ID_82583V                   0x150C
 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
 106 #define E1000_DEV_ID_ICH8_82567V_3            0x1501
 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
 108 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
 109 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
 110 #define E1000_DEV_ID_ICH8_IFE                 0x104C
 111 #define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
 112 #define E1000_DEV_ID_ICH8_IFE_G               0x10C5
 113 #define E1000_DEV_ID_ICH8_IGP_M               0x104D
 114 #define E1000_DEV_ID_ICH9_IGP_M               0x10BF
 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
 116 #define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
 117 #define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
 118 #define E1000_DEV_ID_ICH9_BM                  0x10E5
 119 #define E1000_DEV_ID_ICH9_IGP_C               0x294C
 120 #define E1000_DEV_ID_ICH9_IFE                 0x10C0
 121 #define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
 122 #define E1000_DEV_ID_ICH9_IFE_G               0x10C2
 123 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
 124 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
 125 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
 126 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
 127 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
 128 #define E1000_DEV_ID_ICH10_D_BM_V             0x1525
 129
 130 #define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
 131 #define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
 132 #define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
 133 #define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
 134 #define E1000_DEV_ID_PCH2_LV_LM               0x1502
 135 #define E1000_DEV_ID_PCH2_LV_V                0x1503
 136 #define E1000_DEV_ID_82580_COPPER             0x150E
 137 #define E1000_DEV_ID_82580_FIBER              0x150F
 138 #define E1000_DEV_ID_82580_SERDES             0x1510
 139 #define E1000_DEV_ID_82580_SGMII              0x1511
 140 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
 141 #define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
 142 #define E1000_REVISION_0 0
 143 #define E1000_REVISION_1 1
 144 #define E1000_REVISION_2 2
 145 #define E1000_REVISION_3 3
 146 #define E1000_REVISION_4 4
 147
 148 #define E1000_FUNC_0     0
 149 #define E1000_FUNC_1     1
 150 #define E1000_FUNC_2     2
 151 #define E1000_FUNC_3     3
 152
 153 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
 154 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
 155 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
 156 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
 157
 158 enum e1000_mac_type {
 159         e1000_undefined = 0,
 160 #ifndef NO_82542_SUPPORT
 161         e1000_82542,
 162 #endif
 163         e1000_82543,
 164         e1000_82544,
 165         e1000_82540,
 166         e1000_82545,
 167         e1000_82545_rev_3,
 168         e1000_82546,
 169         e1000_82546_rev_3,
 170         e1000_82541,
 171         e1000_82541_rev_2,
 172         e1000_82547,
 173         e1000_82547_rev_2,
 174         e1000_82571,
 175         e1000_82572,
 176         e1000_82573,
 177         e1000_82574,
 178         e1000_82583,
 179         e1000_80003es2lan,
 180         e1000_ich8lan,
 181         e1000_ich9lan,
 182         e1000_ich10lan,
 183         e1000_pchlan,
 184         e1000_pch2lan,
 185         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 186 };
 187
 188 enum e1000_media_type {
 189         e1000_media_type_unknown = 0,
 190         e1000_media_type_copper = 1,
 191         e1000_media_type_fiber = 2,
 192         e1000_media_type_internal_serdes = 3,
 193         e1000_num_media_types
 194 };
 195
 196 enum e1000_nvm_type {
 197         e1000_nvm_unknown = 0,
 198         e1000_nvm_none,
 199         e1000_nvm_eeprom_spi,
 200         e1000_nvm_eeprom_microwire,
 201         e1000_nvm_flash_hw,
 202         e1000_nvm_flash_sw
 203 };
 204
 205 enum e1000_nvm_override {
 206         e1000_nvm_override_none = 0,
 207         e1000_nvm_override_spi_small,
 208         e1000_nvm_override_spi_large,
 209         e1000_nvm_override_microwire_small,
 210         e1000_nvm_override_microwire_large
 211 };
 212
 213 enum e1000_phy_type {
 214         e1000_phy_unknown = 0,
 215         e1000_phy_none,
 216         e1000_phy_m88,
 217         e1000_phy_igp,
 218         e1000_phy_igp_2,
 219         e1000_phy_gg82563,
 220         e1000_phy_igp_3,
 221         e1000_phy_ife,
 222         e1000_phy_bm,
 223         e1000_phy_82578,
 224         e1000_phy_82577,
 225         e1000_phy_82579,
 226         e1000_phy_82580,
 227 };
 228
 229 enum e1000_bus_type {
 230         e1000_bus_type_unknown = 0,
 231         e1000_bus_type_pci,
 232         e1000_bus_type_pcix,
 233         e1000_bus_type_pci_express,
 234         e1000_bus_type_reserved
 235 };
 236
 237 enum e1000_bus_speed {
 238         e1000_bus_speed_unknown = 0,
 239         e1000_bus_speed_33,
 240         e1000_bus_speed_66,
 241         e1000_bus_speed_100,
 242         e1000_bus_speed_120,
 243         e1000_bus_speed_133,
 244         e1000_bus_speed_2500,
 245         e1000_bus_speed_5000,
 246         e1000_bus_speed_reserved
 247 };
 248
 249 enum e1000_bus_width {
 250         e1000_bus_width_unknown = 0,
 251         e1000_bus_width_pcie_x1,
 252         e1000_bus_width_pcie_x2,
 253         e1000_bus_width_pcie_x4 = 4,
 254         e1000_bus_width_pcie_x8 = 8,
 255         e1000_bus_width_32,
 256         e1000_bus_width_64,
 257         e1000_bus_width_reserved
 258 };
 259
 260 enum e1000_1000t_rx_status {
 261         e1000_1000t_rx_status_not_ok = 0,
 262         e1000_1000t_rx_status_ok,
 263         e1000_1000t_rx_status_undefined = 0xFF
 264 };
 265
 266 enum e1000_rev_polarity {
 267         e1000_rev_polarity_normal = 0,
 268         e1000_rev_polarity_reversed,
 269         e1000_rev_polarity_undefined = 0xFF
 270 };
 271
 272 enum e1000_fc_mode {
 273         e1000_fc_none = 0,
 274         e1000_fc_rx_pause,
 275         e1000_fc_tx_pause,
 276         e1000_fc_full,
 277         e1000_fc_default = 0xFF
 278 };
 279
 280 enum e1000_ffe_config {
 281         e1000_ffe_config_enabled = 0,
 282         e1000_ffe_config_active,
 283         e1000_ffe_config_blocked
 284 };
 285
 286 enum e1000_dsp_config {
 287         e1000_dsp_config_disabled = 0,
 288         e1000_dsp_config_enabled,
 289         e1000_dsp_config_activated,
 290         e1000_dsp_config_undefined = 0xFF
 291 };
 292
 293 enum e1000_ms_type {
 294         e1000_ms_hw_default = 0,
 295         e1000_ms_force_master,
 296         e1000_ms_force_slave,
 297         e1000_ms_auto
 298 };
 299
 300 enum e1000_smart_speed {
 301         e1000_smart_speed_default = 0,
 302         e1000_smart_speed_on,
 303         e1000_smart_speed_off
 304 };
 305
 306 enum e1000_serdes_link_state {
 307         e1000_serdes_link_down = 0,
 308         e1000_serdes_link_autoneg_progress,
 309         e1000_serdes_link_autoneg_complete,
 310         e1000_serdes_link_forced_up
 311 };
 312
 313 #define __le16 u16
 314 #define __le32 u32
 315 #define __le64 u64
 316 /* Receive Descriptor */
 317 struct e1000_rx_desc {
 318         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 319         __le16 length;      /* Length of data DMAed into data buffer */
 320         __le16 csum;        /* Packet checksum */
 321         u8  status;         /* Descriptor status */
 322         u8  errors;         /* Descriptor Errors */
 323         __le16 special;
 324 };
 325
 326 /* Receive Descriptor - Extended */
 327 union e1000_rx_desc_extended {
 328         struct {
 329                 __le64 buffer_addr;
 330                 __le64 reserved;
 331         } read;
 332         struct {
 333                 struct {
 334                         __le32 mrq;           /* Multiple Rx Queues */
 335                         union {
 336                                 __le32 rss;         /* RSS Hash */
 337                                 struct {
 338                                         __le16 ip_id;  /* IP id */
 339                                         __le16 csum;   /* Packet Checksum */
 340                                 } csum_ip;
 341                         } hi_dword;
 342                 } lower;
 343                 struct {
 344                         __le32 status_error;  /* ext status/error */
 345                         __le16 length;
 346                         __le16 vlan;          /* VLAN tag */
 347                 } upper;
 348         } wb;  /* writeback */
 349 };
 350
 351 #define MAX_PS_BUFFERS 4
 352 /* Receive Descriptor - Packet Split */
 353 union e1000_rx_desc_packet_split {
 354         struct {
 355                 /* one buffer for protocol header(s), three data buffers */
 356                 __le64 buffer_addr[MAX_PS_BUFFERS];
 357         } read;
 358         struct {
 359                 struct {
 360                         __le32 mrq;           /* Multiple Rx Queues */
 361                         union {
 362                                 __le32 rss;           /* RSS Hash */
 363                                 struct {
 364                                         __le16 ip_id;    /* IP id */
 365                                         __le16 csum;     /* Packet Checksum */
 366                                 } csum_ip;
 367                         } hi_dword;
 368                 } lower;
 369                 struct {
 370                         __le32 status_error;  /* ext status/error */
 371                         __le16 length0;       /* length of buffer 0 */
 372                         __le16 vlan;          /* VLAN tag */
 373                 } middle;
 374                 struct {
 375                         __le16 header_status;
 376                         __le16 length[3];     /* length of buffers 1-3 */
 377                 } upper;
 378                 __le64 reserved;
 379         } wb; /* writeback */
 380 };
 381
 382 /* Transmit Descriptor */
 383 struct e1000_tx_desc {
 384         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 385         union {
 386                 __le32 data;
 387                 struct {
 388                         __le16 length;    /* Data buffer length */
 389                         u8 cso;           /* Checksum offset */
 390                         u8 cmd;           /* Descriptor control */
 391                 } flags;
 392         } lower;
 393         union {
 394                 __le32 data;
 395                 struct {
 396                         u8 status;        /* Descriptor status */
 397                         u8 css;           /* Checksum start */
 398                         __le16 special;
 399                 } fields;
 400         } upper;
 401 };
 402
 403 /* Offload Context Descriptor */
 404 struct e1000_context_desc {
 405         union {
 406                 __le32 ip_config;
 407                 struct {
 408                         u8 ipcss;         /* IP checksum start */
 409                         u8 ipcso;         /* IP checksum offset */
 410                         __le16 ipcse;     /* IP checksum end */
 411                 } ip_fields;
 412         } lower_setup;
 413         union {
 414                 __le32 tcp_config;
 415                 struct {
 416                         u8 tucss;         /* TCP checksum start */
 417                         u8 tucso;         /* TCP checksum offset */
 418                         __le16 tucse;     /* TCP checksum end */
 419                 } tcp_fields;
 420         } upper_setup;
 421         __le32 cmd_and_length;
 422         union {
 423                 __le32 data;
 424                 struct {
 425                         u8 status;        /* Descriptor status */
 426                         u8 hdr_len;       /* Header length */
 427                         __le16 mss;       /* Maximum segment size */
 428                 } fields;
 429         } tcp_seg_setup;
 430 };
 431
 432 /* Offload data descriptor */
 433 struct e1000_data_desc {
 434         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 435         union {
 436                 __le32 data;
 437                 struct {
 438                         __le16 length;    /* Data buffer length */
 439                         u8 typ_len_ext;
 440                         u8 cmd;
 441                 } flags;
 442         } lower;
 443         union {
 444                 __le32 data;
 445                 struct {
 446                         u8 status;        /* Descriptor status */
 447                         u8 popts;         /* Packet Options */
 448                         __le16 special;
 449                 } fields;
 450         } upper;
 451 };
 452
 453 /* Statistics counters collected by the MAC */
 454 struct e1000_hw_stats {
 455         u64 crcerrs;
 456         u64 algnerrc;
 457         u64 symerrs;
 458         u64 rxerrc;
 459         u64 mpc;
 460         u64 scc;
 461         u64 ecol;
 462         u64 mcc;
 463         u64 latecol;
 464         u64 colc;
 465         u64 dc;
 466         u64 tncrs;
 467         u64 sec;
 468         u64 cexterr;
 469         u64 rlec;
 470         u64 xonrxc;
 471         u64 xontxc;
 472         u64 xoffrxc;
 473         u64 xofftxc;
 474         u64 fcruc;
 475         u64 prc64;
 476         u64 prc127;
 477         u64 prc255;
 478         u64 prc511;
 479         u64 prc1023;
 480         u64 prc1522;
 481         u64 gprc;
 482         u64 bprc;
 483         u64 mprc;
 484         u64 gptc;
 485         u64 gorc;
 486         u64 gotc;
 487         u64 rnbc;
 488         u64 ruc;
 489         u64 rfc;
 490         u64 roc;
 491         u64 rjc;
 492         u64 mgprc;
 493         u64 mgpdc;
 494         u64 mgptc;
 495         u64 tor;
 496         u64 tot;
 497         u64 tpr;
 498         u64 tpt;
 499         u64 ptc64;
 500         u64 ptc127;
 501         u64 ptc255;
 502         u64 ptc511;
 503         u64 ptc1023;
 504         u64 ptc1522;
 505         u64 mptc;
 506         u64 bptc;
 507         u64 tsctc;
 508         u64 tsctfc;
 509         u64 iac;
 510         u64 icrxptc;
 511         u64 icrxatc;
 512         u64 ictxptc;
 513         u64 ictxatc;
 514         u64 ictxqec;
 515         u64 ictxqmtc;
 516         u64 icrxdmtc;
 517         u64 icrxoc;
 518         u64 cbtmpc;
 519         u64 htdpmc;
 520         u64 cbrdpc;
 521         u64 cbrmpc;
 522         u64 rpthc;
 523         u64 hgptc;
 524         u64 htcbdpc;
 525         u64 hgorc;
 526         u64 hgotc;
 527         u64 lenerrs;
 528         u64 scvpc;
 529         u64 hrmpc;
 530         u64 doosync;
 531 };
 532
 533
 534 struct e1000_phy_stats {
 535         u32 idle_errors;
 536         u32 receive_errors;
 537 };
 538
 539 struct e1000_host_mng_dhcp_cookie {
 540         u32 signature;
 541         u8  status;
 542         u8  reserved0;
 543         u16 vlan_id;
 544         u32 reserved1;
 545         u16 reserved2;
 546         u8  reserved3;
 547         u8  checksum;
 548 };
 549
 550 /* Host Interface "Rev 1" */
 551 struct e1000_host_command_header {
 552         u8 command_id;
 553         u8 command_length;
 554         u8 command_options;
 555         u8 checksum;
 556 };
 557
 558 #define E1000_HI_MAX_DATA_LENGTH     252
 559 struct e1000_host_command_info {
 560         struct e1000_host_command_header command_header;
 561         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 562 };
 563
 564 /* Host Interface "Rev 2" */
 565 struct e1000_host_mng_command_header {
 566         u8  command_id;
 567         u8  checksum;
 568         u16 reserved1;
 569         u16 reserved2;
 570         u16 command_length;
 571 };
 572
 573 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 574 struct e1000_host_mng_command_info {
 575         struct e1000_host_mng_command_header command_header;
 576         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 577 };
 578
 579 #include "e1000_mac.h"
 580 #include "e1000_phy.h"
 581 #include "e1000_nvm.h"
 582 #include "e1000_manage.h"
 583
 584 struct e1000_mac_operations {
 585         /* Function pointers for the MAC. */
 586         s32  (*init_params)(struct e1000_hw *);
 587         s32  (*id_led_init)(struct e1000_hw *);
 588         s32  (*blink_led)(struct e1000_hw *);
 589         s32  (*check_for_link)(struct e1000_hw *);
 590         bool (*check_mng_mode)(struct e1000_hw *hw);
 591         s32  (*cleanup_led)(struct e1000_hw *);
 592         void (*clear_hw_cntrs)(struct e1000_hw *);
 593         void (*clear_vfta)(struct e1000_hw *);
 594         s32  (*get_bus_info)(struct e1000_hw *);
 595         void (*set_lan_id)(struct e1000_hw *);
 596         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 597         s32  (*led_on)(struct e1000_hw *);
 598         s32  (*led_off)(struct e1000_hw *);
 599         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 600         s32  (*reset_hw)(struct e1000_hw *);
 601         s32  (*init_hw)(struct e1000_hw *);
 602         s32  (*setup_link)(struct e1000_hw *);
 603         s32  (*setup_physical_interface)(struct e1000_hw *);
 604         s32  (*setup_led)(struct e1000_hw *);
 605         void (*write_vfta)(struct e1000_hw *, u32, u32);
 606         void (*config_collision_dist)(struct e1000_hw *);
 607         void (*rar_set)(struct e1000_hw *, u8*, u32);
 608         s32  (*read_mac_addr)(struct e1000_hw *);
 609         s32  (*validate_mdi_setting)(struct e1000_hw *);
 610         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 611         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 612                       struct e1000_host_mng_command_header*);
 613         s32  (*mng_enable_host_if)(struct e1000_hw *);
 614         s32  (*wait_autoneg)(struct e1000_hw *);
 615 };
 616
 617 /*
 618  * When to use various PHY register access functions:
 619  *
 620  *                 Func   Caller
 621  *   Function      Does   Does    When to use
 622  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 623  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 624  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 625  *                                on different pages
 626  *   X_reg_page    A      L,P     for multiple accesses of different regs
 627  *                                on the same page
 628  *
 629  * Where X=[read|write], L=locking, P=sets page, A=register access
 630  *
 631  */
 632 struct e1000_phy_operations {
 633         s32  (*init_params)(struct e1000_hw *);
 634         s32  (*acquire)(struct e1000_hw *);
 635         s32  (*cfg_on_link_up)(struct e1000_hw *);
 636         s32  (*check_polarity)(struct e1000_hw *);
 637         s32  (*check_reset_block)(struct e1000_hw *);
 638         s32  (*commit)(struct e1000_hw *);
 639         s32  (*force_speed_duplex)(struct e1000_hw *);
 640         s32  (*get_cfg_done)(struct e1000_hw *hw);
 641         s32  (*get_cable_length)(struct e1000_hw *);
 642         s32  (*get_info)(struct e1000_hw *);
 643         s32  (*set_page)(struct e1000_hw *, u16);
 644         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 645         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 646         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 647         void (*release)(struct e1000_hw *);
 648         s32  (*reset)(struct e1000_hw *);
 649         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 650         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 651         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 652         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 653         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 654         void (*power_up)(struct e1000_hw *);
 655         void (*power_down)(struct e1000_hw *);
 656 };
 657
 658 struct e1000_nvm_operations {
 659         s32  (*init_params)(struct e1000_hw *);
 660         s32  (*acquire)(struct e1000_hw *);
 661         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 662         void (*release)(struct e1000_hw *);
 663         void (*reload)(struct e1000_hw *);
 664         s32  (*update)(struct e1000_hw *);
 665         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 666         s32  (*validate)(struct e1000_hw *);
 667         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 668 };
 669
 670 struct e1000_mac_info {
 671         struct e1000_mac_operations ops;
 672         u8 addr[ETH_ADDR_LEN];
 673         u8 perm_addr[ETH_ADDR_LEN];
 674
 675         enum e1000_mac_type type;
 676
 677         u32 collision_delta;
 678         u32 ledctl_default;
 679         u32 ledctl_mode1;
 680         u32 ledctl_mode2;
 681         u32 mc_filter_type;
 682         u32 tx_packet_delta;
 683         u32 txcw;
 684
 685         u16 current_ifs_val;
 686         u16 ifs_max_val;
 687         u16 ifs_min_val;
 688         u16 ifs_ratio;
 689         u16 ifs_step_size;
 690         u16 mta_reg_count;
 691
 692         /* Maximum size of the MTA register table in all supported adapters */
 693         #define MAX_MTA_REG 128
 694         u32 mta_shadow[MAX_MTA_REG];
 695         u16 rar_entry_count;
 696
 697         u8  forced_speed_duplex;
 698
 699         bool adaptive_ifs;
 700         bool has_fwsm;
 701         bool arc_subsystem_valid;
 702         bool asf_firmware_present;
 703         bool autoneg;
 704         bool autoneg_failed;
 705         bool get_link_status;
 706         bool in_ifs_mode;
 707 #ifndef NO_82542_SUPPORT
 708         bool report_tx_early;
 709 #endif
 710         enum e1000_serdes_link_state serdes_link_state;
 711         bool serdes_has_link;
 712         bool tx_pkt_filtering;
 713 };
 714
 715 struct e1000_phy_info {
 716         struct e1000_phy_operations ops;
 717         enum e1000_phy_type type;
 718
 719         enum e1000_1000t_rx_status local_rx;
 720         enum e1000_1000t_rx_status remote_rx;
 721         enum e1000_ms_type ms_type;
 722         enum e1000_ms_type original_ms_type;
 723         enum e1000_rev_polarity cable_polarity;
 724         enum e1000_smart_speed smart_speed;
 725
 726         u32 addr;
 727         u32 id;
 728         u32 reset_delay_us; /* in usec */
 729         u32 revision;
 730
 731         enum e1000_media_type media_type;
 732
 733         u16 autoneg_advertised;
 734         u16 autoneg_mask;
 735         u16 cable_length;
 736         u16 max_cable_length;
 737         u16 min_cable_length;
 738
 739         u8 mdix;
 740
 741         bool disable_polarity_correction;
 742         bool is_mdix;
 743         bool polarity_correction;
 744         bool reset_disable;
 745         bool speed_downgraded;
 746         bool autoneg_wait_to_complete;
 747 };
 748
 749 struct e1000_nvm_info {
 750         struct e1000_nvm_operations ops;
 751         enum e1000_nvm_type type;
 752         enum e1000_nvm_override override;
 753
 754         u32 flash_bank_size;
 755         u32 flash_base_addr;
 756
 757         u16 word_size;
 758         u16 delay_usec;
 759         u16 address_bits;
 760         u16 opcode_bits;
 761         u16 page_size;
 762 };
 763
 764 struct e1000_bus_info {
 765         enum e1000_bus_type type;
 766         enum e1000_bus_speed speed;
 767         enum e1000_bus_width width;
 768
 769         u16 func;
 770         u16 pci_cmd_word;
 771 };
 772
 773 struct e1000_fc_info {
 774         u32 high_water;          /* Flow control high-water mark */
 775         u32 low_water;           /* Flow control low-water mark */
 776         u16 pause_time;          /* Flow control pause timer */
 777         u16 refresh_time;        /* Flow control refresh timer */
 778         bool send_xon;           /* Flow control send XON */
 779         bool strict_ieee;        /* Strict IEEE mode */
 780         enum e1000_fc_mode current_mode; /* FC mode in effect */
 781         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 782 };
 783
 784 struct e1000_dev_spec_82541 {
 785         enum e1000_dsp_config dsp_config;
 786         enum e1000_ffe_config ffe_config;
 787         u16 spd_default;
 788         bool phy_init_script;
 789 };
 790
 791 #ifndef NO_82542_SUPPORT
 792 struct e1000_dev_spec_82542 {
 793         bool dma_fairness;
 794 };
 795
 796 #endif /* NO_82542_SUPPORT */
 797 struct e1000_dev_spec_82543 {
 798         u32  tbi_compatibility;
 799         bool dma_fairness;
 800         bool init_phy_disabled;
 801 };
 802
 803 struct e1000_dev_spec_82571 {
 804         bool laa_is_present;
 805         u32 smb_counter;
 806 };
 807
 808 struct e1000_dev_spec_80003es2lan {
 809         bool  mdic_wa_enable;
 810 };
 811
 812 struct e1000_shadow_ram {
 813         u16  value;
 814         bool modified;
 815 };
 816
 817 #define E1000_SHADOW_RAM_WORDS  2048
 818
 819 struct e1000_dev_spec_ich8lan {
 820         bool kmrn_lock_loss_workaround_enabled;
 821         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 822         bool nvm_k1_enabled;
 823         bool eee_disable;
 824 };
 825
 826 struct e1000_hw {
 827         void *back;
 828
 829         u8 *hw_addr;
 830         u8 *flash_address;
 831         unsigned long io_base;
 832
 833         struct e1000_mac_info  mac;
 834         struct e1000_fc_info   fc;
 835         struct e1000_phy_info  phy;
 836         struct e1000_nvm_info  nvm;
 837         struct e1000_bus_info  bus;
 838         struct e1000_host_mng_dhcp_cookie mng_cookie;
 839
 840         union {
 841                 struct e1000_dev_spec_82541 _82541;
 842 #ifndef NO_82542_SUPPORT
 843                 struct e1000_dev_spec_82542 _82542;
 844 #endif
 845                 struct e1000_dev_spec_82543 _82543;
 846                 struct e1000_dev_spec_82571 _82571;
 847                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 848                 struct e1000_dev_spec_ich8lan ich8lan;
 849         } dev_spec;
 850
 851         u16 device_id;
 852         u16 subsystem_vendor_id;
 853         u16 subsystem_device_id;
 854         u16 vendor_id;
 855
 856         u8  revision_id;
 857 };
 858
 859 #include "e1000_82541.h"
 860 #include "e1000_82543.h"
 861 #include "e1000_82571.h"
 862 #include "e1000_80003es2lan.h"
 863 #include "e1000_ich8lan.h"
 864
 865 /* These functions must be implemented by drivers */
 866 #ifndef NO_82542_SUPPORT
 867 void e1000_pci_clear_mwi(struct e1000_hw *hw);
 868 void e1000_pci_set_mwi(struct e1000_hw *hw);
 869 #endif
 870 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 871 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 872 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 873 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
 874
 875 #endif