2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.38 2008/08/17 04:32:34 sephe Exp $
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
87 #include "opt_polling.h"
89 #include <sys/param.h>
90 #include <sys/endian.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/module.h>
97 #include <sys/socket.h>
98 #include <sys/serialize.h>
100 #include <sys/rman.h>
101 #include <sys/thread2.h>
102 #include <sys/interrupt.h>
105 #include <net/ifq_var.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
113 #include <dev/netif/mii_layer/mii.h>
114 #include <dev/netif/mii_layer/miivar.h>
116 #include <bus/pci/pcidevs.h>
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
131 #define RL_USEIOSPACE
133 #include <dev/netif/rl/if_rlreg.h>
136 * Various supported device vendors/types and their names.
138 static struct rl_type {
143 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129,
144 "RealTek 8129 10/100BaseTX" },
145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
146 "RealTek 8139 10/100BaseTX" },
147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030,
150 "Accton MPX 5030/5038 10/100BaseTX" },
151 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139,
152 "Delta Electronics 8139 10/100BaseTX" },
153 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139,
154 "Addtron Technology 8139 10/100BaseTX" },
155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS,
156 "D-Link DFE-530TX+ 10/100BaseTX" },
157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD,
158 "D-Link DFE-690TX 10/100BaseTX" },
159 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21,
160 "Nortel Networks 10/100BaseTX" },
161 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF,
162 "Peppercon AG ROL/F" },
163 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD,
164 "Corega FEther CB-TXD" },
165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD,
166 "Corega FEtherII CB-TXD" },
167 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX,
168 "Planex FNW-3800-TX" },
172 static int rl_probe(device_t);
173 static int rl_attach(device_t);
174 static int rl_detach(device_t);
176 static int rl_encap(struct rl_softc *, struct mbuf * );
178 static void rl_rxeof(struct rl_softc *);
179 static void rl_txeof(struct rl_softc *);
180 static void rl_intr(void *);
181 static void rl_tick(void *);
182 static void rl_start(struct ifnet *);
183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
184 static void rl_init(void *);
185 static void rl_stop (struct rl_softc *);
186 static void rl_watchdog(struct ifnet *);
187 static int rl_suspend(device_t);
188 static int rl_resume(device_t);
189 static void rl_shutdown(device_t);
190 static int rl_ifmedia_upd(struct ifnet *);
191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
193 static void rl_eeprom_putbyte(struct rl_softc *, int);
194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
196 static void rl_mii_sync(struct rl_softc *);
197 static void rl_mii_send(struct rl_softc *, uint32_t, int);
198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
201 static int rl_miibus_readreg(device_t, int, int);
202 static int rl_miibus_writereg(device_t, int, int, int);
203 static void rl_miibus_statchg(device_t);
205 static void rl_setmulti(struct rl_softc *);
206 static void rl_reset(struct rl_softc *);
207 static void rl_list_tx_init(struct rl_softc *);
209 #ifdef DEVICE_POLLING
210 static poll_handler_t rl_poll;
213 static int rl_dma_alloc(struct rl_softc *);
214 static void rl_dma_free(struct rl_softc *);
217 #define RL_RES SYS_RES_IOPORT
218 #define RL_RID RL_PCI_LOIO
220 #define RL_RES SYS_RES_MEMORY
221 #define RL_RID RL_PCI_LOMEM
224 static device_method_t rl_methods[] = {
225 /* Device interface */
226 DEVMETHOD(device_probe, rl_probe),
227 DEVMETHOD(device_attach, rl_attach),
228 DEVMETHOD(device_detach, rl_detach),
229 DEVMETHOD(device_suspend, rl_suspend),
230 DEVMETHOD(device_resume, rl_resume),
231 DEVMETHOD(device_shutdown, rl_shutdown),
234 DEVMETHOD(bus_print_child, bus_generic_print_child),
235 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
238 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
239 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
240 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
245 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
246 static devclass_t rl_devclass;
248 DECLARE_DUMMY_MODULE(if_rl);
249 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
250 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
251 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
252 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
255 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
258 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
261 * Send a read command and address to the EEPROM, check for ACK.
264 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
268 d = addr | sc->rl_eecmd_read;
271 * Feed in each bit and strobe the clock.
273 for (i = 0x400; i; i >>= 1) {
275 EE_SET(RL_EE_DATAIN);
277 EE_CLR(RL_EE_DATAIN);
287 * Read a word of data stored in the EEPROM at address 'addr.'
290 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
295 /* Enter EEPROM access mode. */
296 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
299 * Send address of word we want to read.
301 rl_eeprom_putbyte(sc, addr);
303 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
306 * Start reading bits from EEPROM.
308 for (i = 0x8000; i; i >>= 1) {
311 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
317 /* Turn off EEPROM access mode. */
318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
324 * Read a sequence of words from the EEPROM.
327 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
330 u_int16_t word = 0, *ptr;
332 for (i = 0; i < cnt; i++) {
333 rl_eeprom_getword(sc, off + i, &word);
334 ptr = (u_int16_t *)(dest + (i * 2));
344 * MII access routines are provided for the 8129, which
345 * doesn't have a built-in PHY. For the 8139, we fake things
346 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
347 * direct access PHY registers.
350 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
353 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
356 * Sync the PHYs by setting data bit and strobing the clock 32 times.
359 rl_mii_sync(struct rl_softc *sc)
363 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
365 for (i = 0; i < 32; i++) {
374 * Clock a series of bits through the MII.
377 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
383 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
385 MII_SET(RL_MII_DATAOUT);
387 MII_CLR(RL_MII_DATAOUT);
396 * Read an PHY register through the MII.
399 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
404 * Set up frame for RX.
406 frame->mii_stdelim = RL_MII_STARTDELIM;
407 frame->mii_opcode = RL_MII_READOP;
408 frame->mii_turnaround = 0;
411 CSR_WRITE_2(sc, RL_MII, 0);
421 * Send command/address info.
423 rl_mii_send(sc, frame->mii_stdelim, 2);
424 rl_mii_send(sc, frame->mii_opcode, 2);
425 rl_mii_send(sc, frame->mii_phyaddr, 5);
426 rl_mii_send(sc, frame->mii_regaddr, 5);
429 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
440 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
445 * Now try reading data bits. If the ack failed, we still
446 * need to clock through 16 cycles to keep the PHY(s) in sync.
449 for(i = 0; i < 16; i++) {
456 for (i = 0x8000; i; i >>= 1) {
460 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
461 frame->mii_data |= i;
478 * Write to a PHY register through the MII.
481 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
484 * Set up frame for TX.
486 frame->mii_stdelim = RL_MII_STARTDELIM;
487 frame->mii_opcode = RL_MII_WRITEOP;
488 frame->mii_turnaround = RL_MII_TURNAROUND;
491 * Turn on data output.
497 rl_mii_send(sc, frame->mii_stdelim, 2);
498 rl_mii_send(sc, frame->mii_opcode, 2);
499 rl_mii_send(sc, frame->mii_phyaddr, 5);
500 rl_mii_send(sc, frame->mii_regaddr, 5);
501 rl_mii_send(sc, frame->mii_turnaround, 2);
502 rl_mii_send(sc, frame->mii_data, 16);
519 rl_miibus_readreg(device_t dev, int phy, int reg)
522 struct rl_mii_frame frame;
524 uint16_t rl8139_reg = 0;
526 sc = device_get_softc(dev);
528 if (sc->rl_type == RL_8139) {
529 /* Pretend the internal PHY is only at address 0 */
534 rl8139_reg = RL_BMCR;
537 rl8139_reg = RL_BMSR;
540 rl8139_reg = RL_ANAR;
543 rl8139_reg = RL_ANER;
546 rl8139_reg = RL_LPAR;
553 * Allow the rlphy driver to read the media status
554 * register. If we have a link partner which does not
555 * support NWAY, this is the register which will tell
556 * us the results of parallel detection.
559 rval = CSR_READ_1(sc, RL_MEDIASTAT);
562 device_printf(dev, "bad phy register\n");
565 rval = CSR_READ_2(sc, rl8139_reg);
569 bzero(&frame, sizeof(frame));
571 frame.mii_phyaddr = phy;
572 frame.mii_regaddr = reg;
573 rl_mii_readreg(sc, &frame);
575 return(frame.mii_data);
579 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
582 struct rl_mii_frame frame;
583 u_int16_t rl8139_reg = 0;
585 sc = device_get_softc(dev);
587 if (sc->rl_type == RL_8139) {
588 /* Pretend the internal PHY is only at address 0 */
593 rl8139_reg = RL_BMCR;
596 rl8139_reg = RL_BMSR;
599 rl8139_reg = RL_ANAR;
602 rl8139_reg = RL_ANER;
605 rl8139_reg = RL_LPAR;
611 device_printf(dev, "bad phy register\n");
614 CSR_WRITE_2(sc, rl8139_reg, data);
618 bzero(&frame, sizeof(frame));
620 frame.mii_phyaddr = phy;
621 frame.mii_regaddr = reg;
622 frame.mii_data = data;
624 rl_mii_writereg(sc, &frame);
630 rl_miibus_statchg(device_t dev)
635 * Program the 64-bit multicast hash filter.
638 rl_setmulti(struct rl_softc *sc)
642 uint32_t hashes[2] = { 0, 0 };
643 struct ifmultiaddr *ifma;
647 ifp = &sc->arpcom.ac_if;
649 rxfilt = CSR_READ_4(sc, RL_RXCFG);
651 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
652 rxfilt |= RL_RXCFG_RX_MULTI;
653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
659 /* first, zot all the existing hash bits */
660 CSR_WRITE_4(sc, RL_MAR0, 0);
661 CSR_WRITE_4(sc, RL_MAR4, 0);
663 /* now program new ones */
664 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
665 if (ifma->ifma_addr->sa_family != AF_LINK)
668 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
669 ETHER_ADDR_LEN) >> 26;
671 hashes[0] |= (1 << h);
673 hashes[1] |= (1 << (h - 32));
678 rxfilt |= RL_RXCFG_RX_MULTI;
680 rxfilt &= ~RL_RXCFG_RX_MULTI;
682 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
683 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
684 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
688 rl_reset(struct rl_softc *sc)
692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
694 for (i = 0; i < RL_TIMEOUT; i++) {
696 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
700 device_printf(sc->rl_dev, "reset never completed!\n");
704 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
705 * IDs against our list and return a device name if we find a match.
707 * Return with a value < 0 to give re(4) a change to attach.
710 rl_probe(device_t dev)
713 uint16_t product = pci_get_device(dev);
714 uint16_t vendor = pci_get_vendor(dev);
716 for (t = rl_devs; t->rl_name != NULL; t++) {
717 if (vendor == t->rl_vid && product == t->rl_did) {
718 device_set_desc(dev, t->rl_name);
727 * Attach the interface. Allocate softc structures, do ifmedia
728 * setup and ethernet/BPF attach.
731 rl_attach(device_t dev)
733 uint8_t eaddr[ETHER_ADDR_LEN];
738 int error = 0, rid, i;
740 sc = device_get_softc(dev);
744 * Handle power management nonsense.
747 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
748 uint32_t iobase, membase, irq;
750 /* Save important PCI config data. */
751 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
752 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
753 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
755 /* Reset the power state. */
756 device_printf(dev, "chip is in D%d power mode "
757 "-- setting to D0\n", pci_get_powerstate(dev));
758 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
760 /* Restore PCI config data. */
761 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
762 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
763 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
766 pci_enable_busmaster(dev);
769 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
771 if (sc->rl_res == NULL) {
772 device_printf(dev, "couldn't map ports/memory\n");
777 sc->rl_btag = rman_get_bustag(sc->rl_res);
778 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
781 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
782 RF_SHAREABLE | RF_ACTIVE);
784 if (sc->rl_irq == NULL) {
785 device_printf(dev, "couldn't map interrupt\n");
790 callout_init(&sc->rl_stat_timer);
792 /* Reset the adapter. */
795 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
796 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
797 if (rl_did != 0x8129)
798 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
801 * Get station address from the EEPROM.
803 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
804 for (i = 0; i < 3; i++) {
805 eaddr[(i * 2) + 0] = as[i] & 0xff;
806 eaddr[(i * 2) + 1] = as[i] >> 8;
810 * Now read the exact device type from the EEPROM to find
811 * out if it's an 8129 or 8139.
813 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
815 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 ||
816 rl_did == PCI_PRODUCT_ACCTON_MPX5030 ||
817 rl_did == PCI_PRODUCT_DELTA_8139 ||
818 rl_did == PCI_PRODUCT_ADDTRON_8139 ||
819 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS ||
820 rl_did == PCI_PRODUCT_REALTEK_RT8139B ||
821 rl_did == PCI_PRODUCT_DLINK_DFE690TXD ||
822 rl_did == PCI_PRODUCT_COREGA_CB_TXD ||
823 rl_did == PCI_PRODUCT_COREGA_2CB_TXD ||
824 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX)
825 sc->rl_type = RL_8139;
826 else if (rl_did == PCI_PRODUCT_REALTEK_RT8129)
827 sc->rl_type = RL_8129;
829 device_printf(dev, "unknown device ID: %x\n", rl_did);
834 error = rl_dma_alloc(sc);
839 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
841 device_printf(dev, "MII without any phy!\n");
846 ifp = &sc->arpcom.ac_if;
848 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
849 ifp->if_mtu = ETHERMTU;
850 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
851 ifp->if_ioctl = rl_ioctl;
852 ifp->if_start = rl_start;
853 ifp->if_watchdog = rl_watchdog;
854 ifp->if_init = rl_init;
855 ifp->if_baudrate = 10000000;
856 ifp->if_capabilities = IFCAP_VLAN_MTU;
857 #ifdef DEVICE_POLLING
858 ifp->if_poll = rl_poll;
860 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
861 ifq_set_ready(&ifp->if_snd);
864 * Call MI attach routine.
866 ether_ifattach(ifp, eaddr, NULL);
868 error = bus_setup_intr(dev, sc->rl_irq, INTR_MPSAFE, rl_intr,
869 sc, &sc->rl_intrhand, ifp->if_serializer);
872 device_printf(dev, "couldn't set up irq\n");
877 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->rl_irq));
878 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
888 rl_detach(device_t dev)
893 sc = device_get_softc(dev);
894 ifp = &sc->arpcom.ac_if;
896 if (device_is_attached(dev)) {
897 lwkt_serialize_enter(ifp->if_serializer);
899 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
900 lwkt_serialize_exit(ifp->if_serializer);
906 device_delete_child(dev, sc->rl_miibus);
907 bus_generic_detach(dev);
910 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
912 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
920 * Initialize the transmit descriptors.
923 rl_list_tx_init(struct rl_softc *sc)
925 struct rl_chain_data *cd;
929 for (i = 0; i < RL_TX_LIST_CNT; i++) {
930 cd->rl_tx_chain[i] = NULL;
931 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
935 sc->rl_cdata.cur_tx = 0;
936 sc->rl_cdata.last_tx = 0;
940 * A frame has been uploaded: pass the resulting mbuf chain up to
941 * the higher level protocols.
943 * You know there's something wrong with a PCI bus-master chip design
944 * when you have to use m_devget().
946 * The receive operation is badly documented in the datasheet, so I'll
947 * attempt to document it here. The driver provides a buffer area and
948 * places its base address in the RX buffer start address register.
949 * The chip then begins copying frames into the RX buffer. Each frame
950 * is preceded by a 32-bit RX status word which specifies the length
951 * of the frame and certain other status bits. Each frame (starting with
952 * the status word) is also 32-bit aligned. The frame length is in the
953 * first 16 bits of the status word; the lower 15 bits correspond with
954 * the 'rx status register' mentioned in the datasheet.
956 * Note: to make the Alpha happy, the frame payload needs to be aligned
957 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
958 * the ring buffer starting at an address two bytes before the actual
959 * data location. We can then shave off the first two bytes using m_adj().
960 * The reason we do this is because m_devget() doesn't let us specify an
961 * offset into the mbuf storage space, so we have to artificially create
962 * one. The ring is allocated in such a way that there are a few unused
963 * bytes of space preceecing it so that it will be safe for us to do the
964 * 2-byte backstep even if reading from the ring at offset 0.
967 rl_rxeof(struct rl_softc *sc)
975 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
977 ifp = &sc->arpcom.ac_if;
979 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
981 /* Do not try to read past this point. */
982 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
985 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
987 max_bytes = limit - cur_rx;
989 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
990 #ifdef DEVICE_POLLING
991 if (ifp->if_flags & IFF_POLLING) {
992 if (sc->rxcycles <= 0)
996 #endif /* DEVICE_POLLING */
997 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
998 rxstat = le32toh(*(uint32_t *)rxbufpos);
1001 * Here's a totally undocumented fact for you. When the
1002 * RealTek chip is in the process of copying a packet into
1003 * RAM for you, the length will be 0xfff0. If you spot a
1004 * packet header with this value, you need to stop. The
1005 * datasheet makes absolutely no mention of this and
1006 * RealTek should be shot for this.
1008 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1011 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1017 /* No errors; receive the packet. */
1018 total_len = rxstat >> 16;
1019 rx_bytes += total_len + 4;
1022 * XXX The RealTek chip includes the CRC with every
1023 * received frame, and there's no way to turn this
1024 * behavior off (at least, I can't find anything in
1025 * the manual that explains how to do it) so we have
1026 * to trim off the CRC manually.
1028 total_len -= ETHER_CRC_LEN;
1031 * Avoid trying to read more bytes than we know
1032 * the chip has prepared for us.
1034 if (rx_bytes > max_bytes)
1037 rxbufpos = sc->rl_cdata.rl_rx_buf +
1038 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1040 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1041 rxbufpos = sc->rl_cdata.rl_rx_buf;
1043 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1045 if (total_len > wrap) {
1047 * Fool m_devget() into thinking we want to copy
1048 * the whole buffer so we don't end up fragmenting
1051 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1052 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1056 m_adj(m, RL_ETHER_ALIGN);
1057 m_copyback(m, wrap, total_len - wrap,
1058 sc->rl_cdata.rl_rx_buf);
1060 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1062 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1063 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1067 m_adj(m, RL_ETHER_ALIGN);
1068 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1072 * Round up to 32-bit boundary.
1074 cur_rx = (cur_rx + 3) & ~3;
1075 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1082 ifp->if_input(ifp, m);
1087 * A frame was downloaded to the chip. It's safe for us to clean up
1091 rl_txeof(struct rl_softc *sc)
1096 ifp = &sc->arpcom.ac_if;
1099 * Go through our tx list and free mbufs for those
1100 * frames that have been uploaded.
1103 if (RL_LAST_TXMBUF(sc) == NULL)
1105 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1106 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1107 RL_TXSTAT_TXABRT)) == 0)
1110 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1112 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1113 m_freem(RL_LAST_TXMBUF(sc));
1114 RL_LAST_TXMBUF(sc) = NULL;
1115 RL_INC(sc->rl_cdata.last_tx);
1117 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1118 sc->rl_txthresh += 32;
1119 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1120 sc->rl_txthresh = RL_TX_THRESH_MAX;
1123 if (txstat & RL_TXSTAT_TX_OK) {
1127 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
1128 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1130 ifp->if_flags &= ~IFF_OACTIVE;
1131 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1133 if (RL_LAST_TXMBUF(sc) == NULL)
1135 else if (ifp->if_timer == 0)
1142 struct rl_softc *sc = xsc;
1143 struct mii_data *mii;
1145 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1147 mii = device_get_softc(sc->rl_miibus);
1150 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1152 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1155 #ifdef DEVICE_POLLING
1158 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1160 struct rl_softc *sc = ifp->if_softc;
1164 /* disable interrupts */
1165 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1167 case POLL_DEREGISTER:
1168 /* enable interrupts */
1169 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1172 sc->rxcycles = count;
1175 if (!ifq_is_empty(&ifp->if_snd))
1178 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1181 status = CSR_READ_2(sc, RL_ISR);
1182 if (status == 0xffff)
1185 CSR_WRITE_2(sc, RL_ISR, status);
1188 * XXX check behaviour on receiver stalls.
1191 if (status & RL_ISR_SYSTEM_ERR) {
1199 #endif /* DEVICE_POLLING */
1204 struct rl_softc *sc;
1213 ifp = &sc->arpcom.ac_if;
1216 status = CSR_READ_2(sc, RL_ISR);
1217 /* If the card has gone away, the read returns 0xffff. */
1218 if (status == 0xffff)
1222 CSR_WRITE_2(sc, RL_ISR, status);
1224 if ((status & RL_INTRS) == 0)
1227 if (status & RL_ISR_RX_OK)
1230 if (status & RL_ISR_RX_ERR)
1233 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1236 if (status & RL_ISR_SYSTEM_ERR) {
1243 if (!ifq_is_empty(&ifp->if_snd))
1248 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1249 * pointers to the fragment pointers.
1252 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1254 struct mbuf *m_new = NULL;
1255 bus_dma_segment_t seg;
1259 * The RealTek is brain damaged and wants longword-aligned
1260 * TX buffers, plus we can only have one fragment buffer
1261 * per packet. We have to copy pretty much all the time.
1263 m_new = m_defrag(m_head, MB_DONTWAIT);
1264 if (m_new == NULL) {
1270 /* Pad frames to at least 60 bytes. */
1271 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1272 error = m_devpad(m_head, RL_MIN_FRAMELEN);
1279 /* Extract physical address. */
1280 error = bus_dmamap_load_mbuf_segment(sc->rl_cdata.rl_tx_tag,
1281 RL_CUR_DMAMAP(sc), m_head,
1282 &seg, 1, &nseg, BUS_DMA_NOWAIT);
1288 /* Sync the loaded TX buffer. */
1289 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1290 BUS_DMASYNC_PREWRITE);
1293 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), seg.ds_addr);
1294 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1295 RL_TXTHRESH(sc->rl_txthresh) | seg.ds_len);
1297 RL_CUR_TXMBUF(sc) = m_head;
1302 * Main transmit routine.
1306 rl_start(struct ifnet *ifp)
1308 struct rl_softc *sc = ifp->if_softc;
1309 struct mbuf *m_head = NULL;
1311 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1314 while (RL_CUR_TXMBUF(sc) == NULL) {
1315 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1319 if (rl_encap(sc, m_head))
1323 * If there's a BPF listener, bounce a copy of this frame
1326 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1328 RL_INC(sc->rl_cdata.cur_tx);
1331 * Set a timeout in case the chip goes out to lunch.
1337 * We broke out of the loop because all our TX slots are
1338 * full. Mark the NIC as busy until it drains some of the
1339 * packets from the queue.
1341 if (RL_CUR_TXMBUF(sc) != NULL)
1342 ifp->if_flags |= IFF_OACTIVE;
1348 struct rl_softc *sc = xsc;
1349 struct ifnet *ifp = &sc->arpcom.ac_if;
1350 struct mii_data *mii;
1353 mii = device_get_softc(sc->rl_miibus);
1356 * Cancel pending I/O and free all RX/TX buffers.
1361 * Init our MAC address. Even though the chipset documentation
1362 * doesn't mention it, we need to enter "Config register write enable"
1363 * mode to modify the ID registers.
1365 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1366 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1367 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1368 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1369 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1370 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1372 /* Init the RX buffer pointer register. */
1373 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr);
1375 /* Init TX descriptors. */
1376 rl_list_tx_init(sc);
1379 * Enable transmit and receive.
1381 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1384 * Set the initial TX and RX configuration.
1386 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1387 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1389 /* Set the individual bit to receive frames for this host only. */
1390 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1391 rxcfg |= RL_RXCFG_RX_INDIV;
1393 /* If we want promiscuous mode, set the allframes bit. */
1394 if (ifp->if_flags & IFF_PROMISC) {
1395 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1396 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1398 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1399 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1403 * Set capture broadcast bit to capture broadcast frames.
1405 if (ifp->if_flags & IFF_BROADCAST) {
1406 rxcfg |= RL_RXCFG_RX_BROAD;
1407 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1409 rxcfg &= ~RL_RXCFG_RX_BROAD;
1410 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1414 * Program the multicast filter, if necessary.
1418 #ifdef DEVICE_POLLING
1420 * Only enable interrupts if we are polling, keep them off otherwise.
1422 if (ifp->if_flags & IFF_POLLING)
1423 CSR_WRITE_2(sc, RL_IMR, 0);
1425 #endif /* DEVICE_POLLING */
1427 * Enable interrupts.
1429 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1431 /* Set initial TX threshold */
1432 sc->rl_txthresh = RL_TX_THRESH_INIT;
1434 /* Start RX/TX process. */
1435 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1437 /* Enable receiver and transmitter. */
1438 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1442 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1444 ifp->if_flags |= IFF_RUNNING;
1445 ifp->if_flags &= ~IFF_OACTIVE;
1447 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1451 * Set media options.
1454 rl_ifmedia_upd(struct ifnet *ifp)
1456 struct rl_softc *sc;
1457 struct mii_data *mii;
1460 mii = device_get_softc(sc->rl_miibus);
1467 * Report current media status.
1470 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1472 struct rl_softc *sc = ifp->if_softc;
1473 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1476 ifmr->ifm_active = mii->mii_media_active;
1477 ifmr->ifm_status = mii->mii_media_status;
1481 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1483 struct rl_softc *sc = ifp->if_softc;
1484 struct ifreq *ifr = (struct ifreq *) data;
1485 struct mii_data *mii;
1490 if (ifp->if_flags & IFF_UP) {
1493 if (ifp->if_flags & IFF_RUNNING)
1505 mii = device_get_softc(sc->rl_miibus);
1506 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1511 error = ether_ioctl(ifp, command, data);
1519 rl_watchdog(struct ifnet *ifp)
1521 struct rl_softc *sc = ifp->if_softc;
1523 device_printf(sc->rl_dev, "watchdog timeout\n");
1533 * Stop the adapter and free any mbufs allocated to the
1537 rl_stop(struct rl_softc *sc)
1539 struct ifnet *ifp = &sc->arpcom.ac_if;
1544 callout_stop(&sc->rl_stat_timer);
1545 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1547 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1548 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1551 * Free the TX list buffers.
1553 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1554 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1555 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1556 sc->rl_cdata.rl_tx_dmamap[i]);
1557 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1558 sc->rl_cdata.rl_tx_chain[i] = NULL;
1559 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1566 * Stop all chip I/O so that the kernel's probe routines don't
1567 * get confused by errant DMAs when rebooting.
1570 rl_shutdown(device_t dev)
1572 struct rl_softc *sc;
1574 sc = device_get_softc(dev);
1575 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1577 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1581 * Device suspend routine. Stop the interface and save some PCI
1582 * settings in case the BIOS doesn't restore them properly on
1586 rl_suspend(device_t dev)
1588 struct rl_softc *sc = device_get_softc(dev);
1591 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1594 for (i = 0; i < 5; i++)
1595 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1596 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1597 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1598 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1599 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1603 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1608 * Device resume routine. Restore some PCI settings in case the BIOS
1609 * doesn't, re-enable busmastering, and restart the interface if
1613 rl_resume(device_t dev)
1615 struct rl_softc *sc = device_get_softc(dev);
1616 struct ifnet *ifp = &sc->arpcom.ac_if;
1619 lwkt_serialize_enter(ifp->if_serializer);
1621 /* better way to do this? */
1622 for (i = 0; i < 5; i++)
1623 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1624 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1625 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1626 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1627 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1629 /* reenable busmastering */
1630 pci_enable_busmaster(dev);
1631 pci_enable_io(dev, RL_RES);
1633 /* reinitialize interface if necessary */
1634 if (ifp->if_flags & IFF_UP)
1638 lwkt_serialize_exit(ifp->if_serializer);
1643 rl_dma_alloc(struct rl_softc *sc)
1648 error = bus_dma_tag_create(NULL, /* parent */
1649 1, 0, /* alignment, boundary */
1650 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1651 BUS_SPACE_MAXADDR, /* highaddr */
1652 NULL, NULL, /* filter, filterarg */
1653 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1655 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1657 &sc->rl_parent_tag);
1659 device_printf(sc->rl_dev, "can't create parent tag\n");
1663 /* Allocate a chunk of coherent memory for RX */
1664 error = bus_dmamem_coherent(sc->rl_parent_tag, 1, 0,
1665 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1666 RL_RXBUFLEN + 1518, BUS_DMA_WAITOK, &dmem);
1670 sc->rl_cdata.rl_rx_tag = dmem.dmem_tag;
1671 sc->rl_cdata.rl_rx_dmamap = dmem.dmem_map;
1672 sc->rl_cdata.rl_rx_buf_ptr = dmem.dmem_addr;
1674 /* NOTE: Apply same adjustment to vaddr and paddr */
1675 sc->rl_cdata.rl_rx_buf = sc->rl_cdata.rl_rx_buf_ptr + sizeof(uint64_t);
1676 sc->rl_cdata.rl_rx_buf_paddr = dmem.dmem_busaddr + sizeof(uint64_t);
1679 * Allocate TX mbuf's DMA tag and maps
1681 error = bus_dma_tag_create(sc->rl_parent_tag,/* parent */
1682 4, 0, /* alignment, boundary */
1683 BUS_SPACE_MAXADDR, /* lowaddr */
1684 BUS_SPACE_MAXADDR, /* highaddr */
1685 NULL, NULL, /* filter, filterarg */
1686 MCLBYTES, /* maxsize */
1688 MCLBYTES, /* maxsegsize */
1689 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
1690 BUS_DMA_ALIGNED, /* flags */
1691 &sc->rl_cdata.rl_tx_tag);
1693 device_printf(sc->rl_dev, "can't create TX mbuf tag\n");
1697 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1698 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag,
1699 BUS_DMA_WAITOK, &sc->rl_cdata.rl_tx_dmamap[i]);
1703 for (j = 0; j < i; ++j) {
1704 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1705 sc->rl_cdata.rl_tx_dmamap[j]);
1707 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1708 sc->rl_cdata.rl_tx_tag = NULL;
1710 device_printf(sc->rl_dev, "can't create TX mbuf map\n");
1718 rl_dma_free(struct rl_softc *sc)
1720 if (sc->rl_cdata.rl_tx_tag != NULL) {
1723 for (i = 0; i < RL_TX_LIST_CNT; ++i) {
1724 bus_dmamap_destroy(sc->rl_cdata.rl_tx_tag,
1725 sc->rl_cdata.rl_tx_dmamap[i]);
1727 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1730 if (sc->rl_cdata.rl_rx_tag != NULL) {
1731 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1732 sc->rl_cdata.rl_rx_dmamap);
1733 /* NOTE: Use rl_rx_buf_ptr here */
1734 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1735 sc->rl_cdata.rl_rx_buf_ptr,
1736 sc->rl_cdata.rl_rx_dmamap);
1737 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1740 if (sc->rl_parent_tag)
1741 bus_dma_tag_destroy(sc->rl_parent_tag);