2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.12 2008/11/26 11:55:18 sephe Exp $
31 #include "opt_polling.h"
35 #include <sys/param.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/interrupt.h>
40 #include <sys/malloc.h>
43 #include <sys/serialize.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/sysctl.h>
48 #include <net/ethernet.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/ifq_var.h>
56 #include <net/toeplitz.h>
58 #include <net/vlan/if_vlan_var.h>
59 #include <net/vlan/if_vlan_ether.h>
61 #include <dev/netif/mii_layer/miivar.h>
62 #include <dev/netif/mii_layer/jmphyreg.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/jme/if_jmereg.h>
69 #include <dev/netif/jme/if_jmevar.h>
71 #include "miibus_if.h"
73 /* Define the following to disable printing Rx errors. */
74 #undef JME_SHOW_ERRORS
76 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
81 if ((sc)->jme_rss_debug > (lvl)) \
82 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
84 #else /* !JME_RSS_DEBUG */
85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
86 #endif /* JME_RSS_DEBUG */
88 static int jme_probe(device_t);
89 static int jme_attach(device_t);
90 static int jme_detach(device_t);
91 static int jme_shutdown(device_t);
92 static int jme_suspend(device_t);
93 static int jme_resume(device_t);
95 static int jme_miibus_readreg(device_t, int, int);
96 static int jme_miibus_writereg(device_t, int, int, int);
97 static void jme_miibus_statchg(device_t);
99 static void jme_init(void *);
100 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
101 static void jme_start(struct ifnet *);
102 static void jme_watchdog(struct ifnet *);
103 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
104 static int jme_mediachange(struct ifnet *);
105 #ifdef DEVICE_POLLING
106 static void jme_poll(struct ifnet *, enum poll_cmd, int);
109 static void jme_intr(void *);
110 static void jme_txeof(struct jme_softc *);
111 static void jme_rxeof(struct jme_softc *, int);
112 static int jme_rxeof_chain(struct jme_softc *, int,
113 struct mbuf_chain *, int);
114 static void jme_rx_intr(struct jme_softc *, uint32_t);
116 static int jme_dma_alloc(struct jme_softc *);
117 static void jme_dma_free(struct jme_softc *);
118 static int jme_init_rx_ring(struct jme_softc *, int);
119 static void jme_init_tx_ring(struct jme_softc *);
120 static void jme_init_ssb(struct jme_softc *);
121 static int jme_newbuf(struct jme_softc *, int, struct jme_rxdesc *, int);
122 static int jme_encap(struct jme_softc *, struct mbuf **);
123 static void jme_rxpkt(struct jme_softc *, int, struct mbuf_chain *);
124 static int jme_rxring_dma_alloc(struct jme_softc *, int);
125 static int jme_rxbuf_dma_alloc(struct jme_softc *, int);
127 static void jme_tick(void *);
128 static void jme_stop(struct jme_softc *);
129 static void jme_reset(struct jme_softc *);
130 static void jme_set_vlan(struct jme_softc *);
131 static void jme_set_filter(struct jme_softc *);
132 static void jme_stop_tx(struct jme_softc *);
133 static void jme_stop_rx(struct jme_softc *);
134 static void jme_mac_config(struct jme_softc *);
135 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
136 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
137 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
139 static void jme_setwol(struct jme_softc *);
140 static void jme_setlinkspeed(struct jme_softc *);
142 static void jme_set_tx_coal(struct jme_softc *);
143 static void jme_set_rx_coal(struct jme_softc *);
145 static void jme_enable_rss(struct jme_softc *);
147 static void jme_disable_rss(struct jme_softc *);
149 static void jme_sysctl_node(struct jme_softc *);
150 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
151 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
152 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
153 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
156 * Devices supported by this driver.
158 static const struct jme_dev {
159 uint16_t jme_vendorid;
160 uint16_t jme_deviceid;
162 const char *jme_name;
164 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
166 "JMicron Inc, JMC250 Gigabit Ethernet" },
167 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
169 "JMicron Inc, JMC260 Fast Ethernet" },
173 static device_method_t jme_methods[] = {
174 /* Device interface. */
175 DEVMETHOD(device_probe, jme_probe),
176 DEVMETHOD(device_attach, jme_attach),
177 DEVMETHOD(device_detach, jme_detach),
178 DEVMETHOD(device_shutdown, jme_shutdown),
179 DEVMETHOD(device_suspend, jme_suspend),
180 DEVMETHOD(device_resume, jme_resume),
183 DEVMETHOD(bus_print_child, bus_generic_print_child),
184 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
187 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
188 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
189 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
194 static driver_t jme_driver = {
197 sizeof(struct jme_softc)
200 static devclass_t jme_devclass;
202 DECLARE_DUMMY_MODULE(if_jme);
203 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
204 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
205 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
207 static const struct {
210 } jme_rx_status[JME_NRXRING_MAX] = {
211 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP },
212 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP },
213 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP },
214 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP }
217 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
218 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
219 static int jme_rx_ring_count = JME_NRXRING_DEF;
221 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
222 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
223 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
226 * Read a PHY register on the MII of the JMC250.
229 jme_miibus_readreg(device_t dev, int phy, int reg)
231 struct jme_softc *sc = device_get_softc(dev);
235 /* For FPGA version, PHY address 0 should be ignored. */
236 if (sc->jme_caps & JME_CAP_FPGA) {
240 if (sc->jme_phyaddr != phy)
244 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
245 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
247 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
249 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
253 device_printf(sc->jme_dev, "phy read timeout: "
254 "phy %d, reg %d\n", phy, reg);
258 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
262 * Write a PHY register on the MII of the JMC250.
265 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
267 struct jme_softc *sc = device_get_softc(dev);
270 /* For FPGA version, PHY address 0 should be ignored. */
271 if (sc->jme_caps & JME_CAP_FPGA) {
275 if (sc->jme_phyaddr != phy)
279 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
280 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
281 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
283 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
285 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
289 device_printf(sc->jme_dev, "phy write timeout: "
290 "phy %d, reg %d\n", phy, reg);
297 * Callback from MII layer when media changes.
300 jme_miibus_statchg(device_t dev)
302 struct jme_softc *sc = device_get_softc(dev);
303 struct ifnet *ifp = &sc->arpcom.ac_if;
304 struct mii_data *mii;
305 struct jme_txdesc *txd;
309 ASSERT_SERIALIZED(ifp->if_serializer);
311 if ((ifp->if_flags & IFF_RUNNING) == 0)
314 mii = device_get_softc(sc->jme_miibus);
316 sc->jme_flags &= ~JME_FLAG_LINK;
317 if ((mii->mii_media_status & IFM_AVALID) != 0) {
318 switch (IFM_SUBTYPE(mii->mii_media_active)) {
321 sc->jme_flags |= JME_FLAG_LINK;
324 if (sc->jme_caps & JME_CAP_FASTETH)
326 sc->jme_flags |= JME_FLAG_LINK;
334 * Disabling Rx/Tx MACs have a side-effect of resetting
335 * JME_TXNDA/JME_RXNDA register to the first address of
336 * Tx/Rx descriptor address. So driver should reset its
337 * internal procucer/consumer pointer and reclaim any
338 * allocated resources. Note, just saving the value of
339 * JME_TXNDA and JME_RXNDA registers before stopping MAC
340 * and restoring JME_TXNDA/JME_RXNDA register is not
341 * sufficient to make sure correct MAC state because
342 * stopping MAC operation can take a while and hardware
343 * might have updated JME_TXNDA/JME_RXNDA registers
344 * during the stop operation.
347 /* Disable interrupts */
348 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
351 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
353 callout_stop(&sc->jme_tick_ch);
355 /* Stop receiver/transmitter. */
359 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
360 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
363 if (rdata->jme_rxhead != NULL)
364 m_freem(rdata->jme_rxhead);
365 JME_RXCHAIN_RESET(sc, r);
368 * Reuse configured Rx descriptors and reset
369 * procuder/consumer index.
371 rdata->jme_rx_cons = 0;
375 if (sc->jme_cdata.jme_tx_cnt != 0) {
376 /* Remove queued packets for transmit. */
377 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
378 txd = &sc->jme_cdata.jme_txdesc[i];
379 if (txd->tx_m != NULL) {
381 sc->jme_cdata.jme_tx_tag,
390 jme_init_tx_ring(sc);
392 /* Initialize shadow status block. */
395 /* Program MAC with resolved speed/duplex/flow-control. */
396 if (sc->jme_flags & JME_FLAG_LINK) {
399 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
401 /* Set Tx ring address to the hardware. */
402 paddr = sc->jme_cdata.jme_tx_ring_paddr;
403 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
404 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
406 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
407 CSR_WRITE_4(sc, JME_RXCSR,
408 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
410 /* Set Rx ring address to the hardware. */
411 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
412 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
413 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
416 /* Restart receiver/transmitter. */
417 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
419 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
422 ifp->if_flags |= IFF_RUNNING;
423 ifp->if_flags &= ~IFF_OACTIVE;
424 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
426 #ifdef DEVICE_POLLING
427 if (!(ifp->if_flags & IFF_POLLING))
429 /* Reenable interrupts. */
430 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
434 * Get the current interface media status.
437 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
439 struct jme_softc *sc = ifp->if_softc;
440 struct mii_data *mii = device_get_softc(sc->jme_miibus);
442 ASSERT_SERIALIZED(ifp->if_serializer);
445 ifmr->ifm_status = mii->mii_media_status;
446 ifmr->ifm_active = mii->mii_media_active;
450 * Set hardware to newly-selected media.
453 jme_mediachange(struct ifnet *ifp)
455 struct jme_softc *sc = ifp->if_softc;
456 struct mii_data *mii = device_get_softc(sc->jme_miibus);
459 ASSERT_SERIALIZED(ifp->if_serializer);
461 if (mii->mii_instance != 0) {
462 struct mii_softc *miisc;
464 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
465 mii_phy_reset(miisc);
467 error = mii_mediachg(mii);
473 jme_probe(device_t dev)
475 const struct jme_dev *sp;
478 vid = pci_get_vendor(dev);
479 did = pci_get_device(dev);
480 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
481 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
482 struct jme_softc *sc = device_get_softc(dev);
484 sc->jme_caps = sp->jme_caps;
485 device_set_desc(dev, sp->jme_name);
493 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
499 for (i = JME_TIMEOUT; i > 0; i--) {
500 reg = CSR_READ_4(sc, JME_SMBCSR);
501 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
507 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
511 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
512 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
513 for (i = JME_TIMEOUT; i > 0; i--) {
515 reg = CSR_READ_4(sc, JME_SMBINTF);
516 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
521 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
525 reg = CSR_READ_4(sc, JME_SMBINTF);
526 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
532 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
534 uint8_t fup, reg, val;
539 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
540 fup != JME_EEPROM_SIG0)
542 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
543 fup != JME_EEPROM_SIG1)
547 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
549 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
550 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
551 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
553 if (reg >= JME_PAR0 &&
554 reg < JME_PAR0 + ETHER_ADDR_LEN) {
555 if (jme_eeprom_read_byte(sc, offset + 2,
558 eaddr[reg - JME_PAR0] = val;
562 /* Check for the end of EEPROM descriptor. */
563 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
565 /* Try next eeprom descriptor. */
566 offset += JME_EEPROM_DESC_BYTES;
567 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
569 if (match == ETHER_ADDR_LEN)
576 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
580 /* Read station address. */
581 par0 = CSR_READ_4(sc, JME_PAR0);
582 par1 = CSR_READ_4(sc, JME_PAR1);
584 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
585 device_printf(sc->jme_dev,
586 "generating fake ethernet address.\n");
587 par0 = karc4random();
588 /* Set OUI to JMicron. */
592 eaddr[3] = (par0 >> 16) & 0xff;
593 eaddr[4] = (par0 >> 8) & 0xff;
594 eaddr[5] = par0 & 0xff;
596 eaddr[0] = (par0 >> 0) & 0xFF;
597 eaddr[1] = (par0 >> 8) & 0xFF;
598 eaddr[2] = (par0 >> 16) & 0xFF;
599 eaddr[3] = (par0 >> 24) & 0xFF;
600 eaddr[4] = (par1 >> 0) & 0xFF;
601 eaddr[5] = (par1 >> 8) & 0xFF;
606 jme_attach(device_t dev)
608 struct jme_softc *sc = device_get_softc(dev);
609 struct ifnet *ifp = &sc->arpcom.ac_if;
612 uint8_t pcie_ptr, rev;
614 uint8_t eaddr[ETHER_ADDR_LEN];
616 sc->jme_rx_desc_cnt = roundup(jme_rx_desc_count, JME_NDESC_ALIGN);
617 if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
618 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
620 sc->jme_tx_desc_cnt = roundup(jme_tx_desc_count, JME_NDESC_ALIGN);
621 if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
622 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
625 sc->jme_rx_ring_cnt = jme_rx_ring_count;
626 if (sc->jme_rx_ring_cnt <= 0)
627 sc->jme_rx_ring_cnt = JME_NRXRING_1;
628 if (sc->jme_rx_ring_cnt > ncpus2)
629 sc->jme_rx_ring_cnt = ncpus2;
631 if (sc->jme_rx_ring_cnt >= JME_NRXRING_4)
632 sc->jme_rx_ring_cnt = JME_NRXRING_4;
633 else if (sc->jme_rx_ring_cnt >= JME_NRXRING_2)
634 sc->jme_rx_ring_cnt = JME_NRXRING_2;
636 sc->jme_rx_ring_cnt = JME_NRXRING_MIN;
638 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
641 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
643 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
645 callout_init(&sc->jme_tick_ch);
648 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
651 irq = pci_read_config(dev, PCIR_INTLINE, 4);
652 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
654 device_printf(dev, "chip is in D%d power mode "
655 "-- setting to D0\n", pci_get_powerstate(dev));
657 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
659 pci_write_config(dev, PCIR_INTLINE, irq, 4);
660 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
662 #endif /* !BURN_BRIDGE */
664 /* Enable bus mastering */
665 pci_enable_busmaster(dev);
670 * JMC250 supports both memory mapped and I/O register space
671 * access. Because I/O register access should use different
672 * BARs to access registers it's waste of time to use I/O
673 * register spce access. JMC250 uses 16K to map entire memory
676 sc->jme_mem_rid = JME_PCIR_BAR;
677 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
678 &sc->jme_mem_rid, RF_ACTIVE);
679 if (sc->jme_mem_res == NULL) {
680 device_printf(dev, "can't allocate IO memory\n");
683 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
684 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
690 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
692 RF_SHAREABLE | RF_ACTIVE);
693 if (sc->jme_irq_res == NULL) {
694 device_printf(dev, "can't allocate irq\n");
702 reg = CSR_READ_4(sc, JME_CHIPMODE);
703 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
705 sc->jme_caps |= JME_CAP_FPGA;
707 device_printf(dev, "FPGA revision: 0x%04x\n",
708 (reg & CHIPMODE_FPGA_REV_MASK) >>
709 CHIPMODE_FPGA_REV_SHIFT);
713 /* NOTE: FM revision is put in the upper 4 bits */
714 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
715 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
717 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
719 did = pci_get_device(dev);
721 case PCI_PRODUCT_JMICRON_JMC250:
722 if (rev == JME_REV1_A2)
723 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
726 case PCI_PRODUCT_JMICRON_JMC260:
728 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
732 panic("unknown device id 0x%04x\n", did);
734 if (rev >= JME_REV2) {
735 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
736 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
737 GHC_TXMAC_CLKSRC_1000;
740 /* Reset the ethernet controller. */
743 /* Get station address. */
744 reg = CSR_READ_4(sc, JME_SMBCSR);
745 if (reg & SMBCSR_EEPROM_PRESENT)
746 error = jme_eeprom_macaddr(sc, eaddr);
747 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
748 if (error != 0 && (bootverbose)) {
749 device_printf(dev, "ethernet hardware address "
750 "not found in EEPROM.\n");
752 jme_reg_macaddr(sc, eaddr);
757 * Integrated JR0211 has fixed PHY address whereas FPGA version
758 * requires PHY probing to get correct PHY address.
760 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
761 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
762 GPREG0_PHY_ADDR_MASK;
764 device_printf(dev, "PHY is at address %d.\n",
771 /* Set max allowable DMA size. */
772 pcie_ptr = pci_get_pciecap_ptr(dev);
776 sc->jme_caps |= JME_CAP_PCIE;
777 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
779 device_printf(dev, "Read request size : %d bytes.\n",
780 128 << ((ctrl >> 12) & 0x07));
781 device_printf(dev, "TLP payload size : %d bytes.\n",
782 128 << ((ctrl >> 5) & 0x07));
784 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
785 case PCIEM_DEVCTL_MAX_READRQ_128:
786 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
788 case PCIEM_DEVCTL_MAX_READRQ_256:
789 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
792 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
795 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
797 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
798 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
802 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
803 sc->jme_caps |= JME_CAP_PMCAP;
811 /* Allocate DMA stuffs */
812 error = jme_dma_alloc(sc);
817 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
818 ifp->if_init = jme_init;
819 ifp->if_ioctl = jme_ioctl;
820 ifp->if_start = jme_start;
821 #ifdef DEVICE_POLLING
822 ifp->if_poll = jme_poll;
824 ifp->if_watchdog = jme_watchdog;
825 ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
826 ifq_set_ready(&ifp->if_snd);
828 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
829 ifp->if_capabilities = IFCAP_HWCSUM |
831 IFCAP_VLAN_HWTAGGING;
832 if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
833 ifp->if_capabilities |= IFCAP_RSS;
834 ifp->if_hwassist = JME_CSUM_FEATURES;
835 ifp->if_capenable = ifp->if_capabilities;
837 /* Set up MII bus. */
838 error = mii_phy_probe(dev, &sc->jme_miibus,
839 jme_mediachange, jme_mediastatus);
841 device_printf(dev, "no PHY found!\n");
846 * Save PHYADDR for FPGA mode PHY.
848 if (sc->jme_caps & JME_CAP_FPGA) {
849 struct mii_data *mii = device_get_softc(sc->jme_miibus);
851 if (mii->mii_instance != 0) {
852 struct mii_softc *miisc;
854 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
855 if (miisc->mii_phy != 0) {
856 sc->jme_phyaddr = miisc->mii_phy;
860 if (sc->jme_phyaddr != 0) {
861 device_printf(sc->jme_dev,
862 "FPGA PHY is at %d\n", sc->jme_phyaddr);
864 jme_miibus_writereg(dev, sc->jme_phyaddr,
865 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
867 /* XXX should we clear JME_WA_EXTFIFO */
872 ether_ifattach(ifp, eaddr, NULL);
874 /* Tell the upper layer(s) we support long frames. */
875 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
877 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
878 &sc->jme_irq_handle, ifp->if_serializer);
880 device_printf(dev, "could not set up interrupt handler.\n");
885 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
886 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
894 jme_detach(device_t dev)
896 struct jme_softc *sc = device_get_softc(dev);
898 if (device_is_attached(dev)) {
899 struct ifnet *ifp = &sc->arpcom.ac_if;
901 lwkt_serialize_enter(ifp->if_serializer);
903 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
904 lwkt_serialize_exit(ifp->if_serializer);
909 if (sc->jme_sysctl_tree != NULL)
910 sysctl_ctx_free(&sc->jme_sysctl_ctx);
912 if (sc->jme_miibus != NULL)
913 device_delete_child(dev, sc->jme_miibus);
914 bus_generic_detach(dev);
916 if (sc->jme_irq_res != NULL) {
917 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
921 if (sc->jme_mem_res != NULL) {
922 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
932 jme_sysctl_node(struct jme_softc *sc)
936 char rx_ring_pkt[32];
940 sysctl_ctx_init(&sc->jme_sysctl_ctx);
941 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
942 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
943 device_get_nameunit(sc->jme_dev),
945 if (sc->jme_sysctl_tree == NULL) {
946 device_printf(sc->jme_dev, "can't add sysctl node\n");
950 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
951 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
952 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
953 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
955 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
956 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
957 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
958 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
960 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
961 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
962 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
963 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
965 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
966 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
967 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
968 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
970 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
971 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
972 "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
974 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
975 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
976 "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
978 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
979 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
980 "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
982 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
983 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
984 "rx_ring_inuse", CTLFLAG_RD, &sc->jme_rx_ring_inuse,
985 0, "RX ring in use");
987 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
988 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
989 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
990 0, "RSS debug level");
991 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
992 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
993 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
994 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
995 rx_ring_pkt, CTLFLAG_RD,
996 &sc->jme_rx_ring_pkt[r],
1002 * Set default coalesce valves
1004 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1005 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1006 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1007 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1010 * Adjust coalesce valves, in case that the number of TX/RX
1011 * descs are set to small values by users.
1013 * NOTE: coal_max will not be zero, since number of descs
1014 * must aligned by JME_NDESC_ALIGN (16 currently)
1016 coal_max = sc->jme_tx_desc_cnt / 6;
1017 if (coal_max < sc->jme_tx_coal_pkt)
1018 sc->jme_tx_coal_pkt = coal_max;
1020 coal_max = sc->jme_rx_desc_cnt / 4;
1021 if (coal_max < sc->jme_rx_coal_pkt)
1022 sc->jme_rx_coal_pkt = coal_max;
1026 jme_dma_alloc(struct jme_softc *sc)
1028 struct jme_txdesc *txd;
1032 sc->jme_cdata.jme_txdesc =
1033 kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1034 M_DEVBUF, M_WAITOK | M_ZERO);
1035 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1036 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1037 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1038 M_DEVBUF, M_WAITOK | M_ZERO);
1041 /* Create parent ring tag. */
1042 error = bus_dma_tag_create(NULL,/* parent */
1043 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1044 sc->jme_lowaddr, /* lowaddr */
1045 BUS_SPACE_MAXADDR, /* highaddr */
1046 NULL, NULL, /* filter, filterarg */
1047 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1049 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1051 &sc->jme_cdata.jme_ring_tag);
1053 device_printf(sc->jme_dev,
1054 "could not create parent ring DMA tag.\n");
1059 * Create DMA stuffs for TX ring
1061 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1062 JME_TX_RING_ALIGN, 0,
1063 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1064 JME_TX_RING_SIZE(sc),
1065 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1067 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1070 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1071 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1072 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1073 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1076 * Create DMA stuffs for RX rings
1078 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1079 error = jme_rxring_dma_alloc(sc, i);
1084 /* Create parent buffer tag. */
1085 error = bus_dma_tag_create(NULL,/* parent */
1086 1, 0, /* algnmnt, boundary */
1087 sc->jme_lowaddr, /* lowaddr */
1088 BUS_SPACE_MAXADDR, /* highaddr */
1089 NULL, NULL, /* filter, filterarg */
1090 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1092 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1094 &sc->jme_cdata.jme_buffer_tag);
1096 device_printf(sc->jme_dev,
1097 "could not create parent buffer DMA tag.\n");
1102 * Create DMA stuffs for shadow status block
1104 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1105 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1106 JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1108 device_printf(sc->jme_dev,
1109 "could not create shadow status block.\n");
1112 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1113 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1114 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1115 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1118 * Create DMA stuffs for TX buffers
1121 /* Create tag for Tx buffers. */
1122 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1123 1, 0, /* algnmnt, boundary */
1124 BUS_SPACE_MAXADDR, /* lowaddr */
1125 BUS_SPACE_MAXADDR, /* highaddr */
1126 NULL, NULL, /* filter, filterarg */
1127 JME_JUMBO_FRAMELEN, /* maxsize */
1128 JME_MAXTXSEGS, /* nsegments */
1129 JME_MAXSEGSIZE, /* maxsegsize */
1130 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1131 &sc->jme_cdata.jme_tx_tag);
1133 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1137 /* Create DMA maps for Tx buffers. */
1138 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1139 txd = &sc->jme_cdata.jme_txdesc[i];
1140 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1141 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1146 device_printf(sc->jme_dev,
1147 "could not create %dth Tx dmamap.\n", i);
1149 for (j = 0; j < i; ++j) {
1150 txd = &sc->jme_cdata.jme_txdesc[j];
1151 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1154 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1155 sc->jme_cdata.jme_tx_tag = NULL;
1161 * Create DMA stuffs for RX buffers
1163 for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1164 error = jme_rxbuf_dma_alloc(sc, i);
1172 jme_dma_free(struct jme_softc *sc)
1174 struct jme_txdesc *txd;
1175 struct jme_rxdesc *rxd;
1176 struct jme_rxdata *rdata;
1180 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1181 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1182 sc->jme_cdata.jme_tx_ring_map);
1183 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1184 sc->jme_cdata.jme_tx_ring,
1185 sc->jme_cdata.jme_tx_ring_map);
1186 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1187 sc->jme_cdata.jme_tx_ring_tag = NULL;
1191 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1192 rdata = &sc->jme_cdata.jme_rx_data[r];
1193 if (rdata->jme_rx_ring_tag != NULL) {
1194 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1195 rdata->jme_rx_ring_map);
1196 bus_dmamem_free(rdata->jme_rx_ring_tag,
1198 rdata->jme_rx_ring_map);
1199 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1200 rdata->jme_rx_ring_tag = NULL;
1205 if (sc->jme_cdata.jme_tx_tag != NULL) {
1206 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1207 txd = &sc->jme_cdata.jme_txdesc[i];
1208 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1211 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1212 sc->jme_cdata.jme_tx_tag = NULL;
1216 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1217 rdata = &sc->jme_cdata.jme_rx_data[r];
1218 if (rdata->jme_rx_tag != NULL) {
1219 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1220 rxd = &rdata->jme_rxdesc[i];
1221 bus_dmamap_destroy(rdata->jme_rx_tag,
1224 bus_dmamap_destroy(rdata->jme_rx_tag,
1225 rdata->jme_rx_sparemap);
1226 bus_dma_tag_destroy(rdata->jme_rx_tag);
1227 rdata->jme_rx_tag = NULL;
1231 /* Shadow status block. */
1232 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1233 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1234 sc->jme_cdata.jme_ssb_map);
1235 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1236 sc->jme_cdata.jme_ssb_block,
1237 sc->jme_cdata.jme_ssb_map);
1238 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1239 sc->jme_cdata.jme_ssb_tag = NULL;
1242 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1243 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1244 sc->jme_cdata.jme_buffer_tag = NULL;
1246 if (sc->jme_cdata.jme_ring_tag != NULL) {
1247 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1248 sc->jme_cdata.jme_ring_tag = NULL;
1251 if (sc->jme_cdata.jme_txdesc != NULL) {
1252 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1253 sc->jme_cdata.jme_txdesc = NULL;
1255 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1256 rdata = &sc->jme_cdata.jme_rx_data[r];
1257 if (rdata->jme_rxdesc != NULL) {
1258 kfree(rdata->jme_rxdesc, M_DEVBUF);
1259 rdata->jme_rxdesc = NULL;
1265 * Make sure the interface is stopped at reboot time.
1268 jme_shutdown(device_t dev)
1270 return jme_suspend(dev);
1275 * Unlike other ethernet controllers, JMC250 requires
1276 * explicit resetting link speed to 10/100Mbps as gigabit
1277 * link will cunsume more power than 375mA.
1278 * Note, we reset the link speed to 10/100Mbps with
1279 * auto-negotiation but we don't know whether that operation
1280 * would succeed or not as we have no control after powering
1281 * off. If the renegotiation fail WOL may not work. Running
1282 * at 1Gbps draws more power than 375mA at 3.3V which is
1283 * specified in PCI specification and that would result in
1284 * complete shutdowning power to ethernet controller.
1287 * Save current negotiated media speed/duplex/flow-control
1288 * to softc and restore the same link again after resuming.
1289 * PHY handling such as power down/resetting to 100Mbps
1290 * may be better handled in suspend method in phy driver.
1293 jme_setlinkspeed(struct jme_softc *sc)
1295 struct mii_data *mii;
1298 JME_LOCK_ASSERT(sc);
1300 mii = device_get_softc(sc->jme_miibus);
1303 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1304 switch IFM_SUBTYPE(mii->mii_media_active) {
1314 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1315 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1316 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1317 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1318 BMCR_AUTOEN | BMCR_STARTNEG);
1321 /* Poll link state until jme(4) get a 10/100 link. */
1322 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1324 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1325 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1335 pause("jmelnk", hz);
1338 if (i == MII_ANEGTICKS_GIGE)
1339 device_printf(sc->jme_dev, "establishing link failed, "
1340 "WOL may not work!");
1343 * No link, force MAC to have 100Mbps, full-duplex link.
1344 * This is the last resort and may/may not work.
1346 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1347 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1352 jme_setwol(struct jme_softc *sc)
1354 struct ifnet *ifp = &sc->arpcom.ac_if;
1359 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1360 /* No PME capability, PHY power down. */
1361 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1362 MII_BMCR, BMCR_PDOWN);
1366 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1367 pmcs = CSR_READ_4(sc, JME_PMCS);
1368 pmcs &= ~PMCS_WOL_ENB_MASK;
1369 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1370 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1371 /* Enable PME message. */
1372 gpr |= GPREG0_PME_ENB;
1373 /* For gigabit controllers, reset link speed to 10/100. */
1374 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1375 jme_setlinkspeed(sc);
1378 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1379 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1382 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1383 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1384 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1385 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1386 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1387 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1388 /* No WOL, PHY power down. */
1389 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1390 MII_BMCR, BMCR_PDOWN);
1396 jme_suspend(device_t dev)
1398 struct jme_softc *sc = device_get_softc(dev);
1399 struct ifnet *ifp = &sc->arpcom.ac_if;
1401 lwkt_serialize_enter(ifp->if_serializer);
1406 lwkt_serialize_exit(ifp->if_serializer);
1412 jme_resume(device_t dev)
1414 struct jme_softc *sc = device_get_softc(dev);
1415 struct ifnet *ifp = &sc->arpcom.ac_if;
1420 lwkt_serialize_enter(ifp->if_serializer);
1423 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1426 pmstat = pci_read_config(sc->jme_dev,
1427 pmc + PCIR_POWER_STATUS, 2);
1428 /* Disable PME clear PME status. */
1429 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1430 pci_write_config(sc->jme_dev,
1431 pmc + PCIR_POWER_STATUS, pmstat, 2);
1435 if (ifp->if_flags & IFF_UP)
1438 lwkt_serialize_exit(ifp->if_serializer);
1444 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1446 struct jme_txdesc *txd;
1447 struct jme_desc *desc;
1449 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1451 int error, i, prod, symbol_desc;
1452 uint32_t cflags, flag64;
1454 M_ASSERTPKTHDR((*m_head));
1456 prod = sc->jme_cdata.jme_tx_prod;
1457 txd = &sc->jme_cdata.jme_txdesc[prod];
1459 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1464 maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1465 (JME_TXD_RSVD + symbol_desc);
1466 if (maxsegs > JME_MAXTXSEGS)
1467 maxsegs = JME_MAXTXSEGS;
1468 KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1469 ("not enough segments %d\n", maxsegs));
1471 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1472 txd->tx_dmamap, m_head,
1473 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1477 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1478 BUS_DMASYNC_PREWRITE);
1483 /* Configure checksum offload. */
1484 if (m->m_pkthdr.csum_flags & CSUM_IP)
1485 cflags |= JME_TD_IPCSUM;
1486 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1487 cflags |= JME_TD_TCPCSUM;
1488 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1489 cflags |= JME_TD_UDPCSUM;
1491 /* Configure VLAN. */
1492 if (m->m_flags & M_VLANTAG) {
1493 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1494 cflags |= JME_TD_VLAN_TAG;
1497 desc = &sc->jme_cdata.jme_tx_ring[prod];
1498 desc->flags = htole32(cflags);
1499 desc->addr_hi = htole32(m->m_pkthdr.len);
1500 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1502 * Use 64bits TX desc chain format.
1504 * The first TX desc of the chain, which is setup here,
1505 * is just a symbol TX desc carrying no payload.
1507 flag64 = JME_TD_64BIT;
1511 /* No effective TX desc is consumed */
1515 * Use 32bits TX desc chain format.
1517 * The first TX desc of the chain, which is setup here,
1518 * is an effective TX desc carrying the first segment of
1522 desc->buflen = htole32(txsegs[0].ds_len);
1523 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1525 /* One effective TX desc is consumed */
1528 sc->jme_cdata.jme_tx_cnt++;
1529 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1530 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1531 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1533 txd->tx_ndesc = 1 - i;
1534 for (; i < nsegs; i++) {
1535 desc = &sc->jme_cdata.jme_tx_ring[prod];
1536 desc->flags = htole32(JME_TD_OWN | flag64);
1537 desc->buflen = htole32(txsegs[i].ds_len);
1538 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1539 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1541 sc->jme_cdata.jme_tx_cnt++;
1542 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1543 sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1544 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1547 /* Update producer index. */
1548 sc->jme_cdata.jme_tx_prod = prod;
1550 * Finally request interrupt and give the first descriptor
1551 * owenership to hardware.
1553 desc = txd->tx_desc;
1554 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1557 txd->tx_ndesc += nsegs;
1567 jme_start(struct ifnet *ifp)
1569 struct jme_softc *sc = ifp->if_softc;
1570 struct mbuf *m_head;
1573 ASSERT_SERIALIZED(ifp->if_serializer);
1575 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1576 ifq_purge(&ifp->if_snd);
1580 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1583 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1586 while (!ifq_is_empty(&ifp->if_snd)) {
1588 * Check number of available TX descs, always
1589 * leave JME_TXD_RSVD free TX descs.
1591 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1592 sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1593 ifp->if_flags |= IFF_OACTIVE;
1597 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1602 * Pack the data into the transmit ring. If we
1603 * don't have room, set the OACTIVE flag and wait
1604 * for the NIC to drain the ring.
1606 if (jme_encap(sc, &m_head)) {
1607 KKASSERT(m_head == NULL);
1609 ifp->if_flags |= IFF_OACTIVE;
1615 * If there's a BPF listener, bounce a copy of this frame
1618 ETHER_BPF_MTAP(ifp, m_head);
1623 * Reading TXCSR takes very long time under heavy load
1624 * so cache TXCSR value and writes the ORed value with
1625 * the kick command to the TXCSR. This saves one register
1628 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1629 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1630 /* Set a timeout in case the chip goes out to lunch. */
1631 ifp->if_timer = JME_TX_TIMEOUT;
1636 jme_watchdog(struct ifnet *ifp)
1638 struct jme_softc *sc = ifp->if_softc;
1640 ASSERT_SERIALIZED(ifp->if_serializer);
1642 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1643 if_printf(ifp, "watchdog timeout (missed link)\n");
1650 if (sc->jme_cdata.jme_tx_cnt == 0) {
1651 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1653 if (!ifq_is_empty(&ifp->if_snd))
1658 if_printf(ifp, "watchdog timeout\n");
1661 if (!ifq_is_empty(&ifp->if_snd))
1666 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1668 struct jme_softc *sc = ifp->if_softc;
1669 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1670 struct ifreq *ifr = (struct ifreq *)data;
1671 int error = 0, mask;
1673 ASSERT_SERIALIZED(ifp->if_serializer);
1677 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1678 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1679 ifr->ifr_mtu > JME_MAX_MTU)) {
1684 if (ifp->if_mtu != ifr->ifr_mtu) {
1686 * No special configuration is required when interface
1687 * MTU is changed but availability of Tx checksum
1688 * offload should be chcked against new MTU size as
1689 * FIFO size is just 2K.
1691 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1692 ifp->if_capenable &= ~IFCAP_TXCSUM;
1693 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1695 ifp->if_mtu = ifr->ifr_mtu;
1696 if (ifp->if_flags & IFF_RUNNING)
1702 if (ifp->if_flags & IFF_UP) {
1703 if (ifp->if_flags & IFF_RUNNING) {
1704 if ((ifp->if_flags ^ sc->jme_if_flags) &
1705 (IFF_PROMISC | IFF_ALLMULTI))
1711 if (ifp->if_flags & IFF_RUNNING)
1714 sc->jme_if_flags = ifp->if_flags;
1719 if (ifp->if_flags & IFF_RUNNING)
1725 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1729 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1731 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1732 ifp->if_capenable ^= IFCAP_TXCSUM;
1733 if (IFCAP_TXCSUM & ifp->if_capenable)
1734 ifp->if_hwassist |= JME_CSUM_FEATURES;
1736 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1738 if (mask & IFCAP_RXCSUM) {
1741 ifp->if_capenable ^= IFCAP_RXCSUM;
1742 reg = CSR_READ_4(sc, JME_RXMAC);
1743 reg &= ~RXMAC_CSUM_ENB;
1744 if (ifp->if_capenable & IFCAP_RXCSUM)
1745 reg |= RXMAC_CSUM_ENB;
1746 CSR_WRITE_4(sc, JME_RXMAC, reg);
1749 if (mask & IFCAP_VLAN_HWTAGGING) {
1750 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1754 if (mask & IFCAP_RSS) {
1755 ifp->if_capenable ^= IFCAP_RSS;
1756 if (ifp->if_flags & IFF_RUNNING)
1762 error = ether_ioctl(ifp, cmd, data);
1769 jme_mac_config(struct jme_softc *sc)
1771 struct mii_data *mii;
1772 uint32_t ghc, rxmac, txmac, txpause, gp1;
1773 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1775 mii = device_get_softc(sc->jme_miibus);
1777 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1779 CSR_WRITE_4(sc, JME_GHC, 0);
1781 rxmac = CSR_READ_4(sc, JME_RXMAC);
1782 rxmac &= ~RXMAC_FC_ENB;
1783 txmac = CSR_READ_4(sc, JME_TXMAC);
1784 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1785 txpause = CSR_READ_4(sc, JME_TXPFC);
1786 txpause &= ~TXPFC_PAUSE_ENB;
1787 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1788 ghc |= GHC_FULL_DUPLEX;
1789 rxmac &= ~RXMAC_COLL_DET_ENB;
1790 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1791 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1794 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1795 txpause |= TXPFC_PAUSE_ENB;
1796 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1797 rxmac |= RXMAC_FC_ENB;
1799 /* Disable retry transmit timer/retry limit. */
1800 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1801 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1803 rxmac |= RXMAC_COLL_DET_ENB;
1804 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1805 /* Enable retry transmit timer/retry limit. */
1806 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1807 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1811 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1813 gp1 = CSR_READ_4(sc, JME_GPREG1);
1814 gp1 &= ~GPREG1_WA_HDX;
1816 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1819 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1821 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1823 gp1 |= GPREG1_WA_HDX;
1827 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1829 gp1 |= GPREG1_WA_HDX;
1832 * Use extended FIFO depth to workaround CRC errors
1833 * emitted by chips before JMC250B
1835 phyconf = JMPHY_CONF_EXTFIFO;
1839 if (sc->jme_caps & JME_CAP_FASTETH)
1842 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1844 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1850 CSR_WRITE_4(sc, JME_GHC, ghc);
1851 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1852 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1853 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1855 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1856 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1857 JMPHY_CONF, phyconf);
1859 if (sc->jme_workaround & JME_WA_HDX)
1860 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1866 struct jme_softc *sc = xsc;
1867 struct ifnet *ifp = &sc->arpcom.ac_if;
1871 ASSERT_SERIALIZED(ifp->if_serializer);
1873 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1874 if (status == 0 || status == 0xFFFFFFFF)
1877 /* Disable interrupts. */
1878 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1880 status = CSR_READ_4(sc, JME_INTR_STATUS);
1881 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1884 /* Reset PCC counter/timer and Ack interrupts. */
1885 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1887 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1888 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1890 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
1891 if (status & jme_rx_status[r].jme_coal) {
1892 status |= jme_rx_status[r].jme_coal |
1893 jme_rx_status[r].jme_comp;
1897 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1899 if (ifp->if_flags & IFF_RUNNING) {
1900 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1901 jme_rx_intr(sc, status);
1903 if (status & INTR_RXQ_DESC_EMPTY) {
1905 * Notify hardware availability of new Rx buffers.
1906 * Reading RXCSR takes very long time under heavy
1907 * load so cache RXCSR value and writes the ORed
1908 * value with the kick command to the RXCSR. This
1909 * saves one register access cycle.
1911 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1912 RXCSR_RX_ENB | RXCSR_RXQ_START);
1915 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1917 if (!ifq_is_empty(&ifp->if_snd))
1922 /* Reenable interrupts. */
1923 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1927 jme_txeof(struct jme_softc *sc)
1929 struct ifnet *ifp = &sc->arpcom.ac_if;
1930 struct jme_txdesc *txd;
1934 cons = sc->jme_cdata.jme_tx_cons;
1935 if (cons == sc->jme_cdata.jme_tx_prod)
1939 * Go through our Tx list and free mbufs for those
1940 * frames which have been transmitted.
1942 while (cons != sc->jme_cdata.jme_tx_prod) {
1943 txd = &sc->jme_cdata.jme_txdesc[cons];
1944 KASSERT(txd->tx_m != NULL,
1945 ("%s: freeing NULL mbuf!\n", __func__));
1947 status = le32toh(txd->tx_desc->flags);
1948 if ((status & JME_TD_OWN) == JME_TD_OWN)
1951 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1955 if (status & JME_TD_COLLISION) {
1956 ifp->if_collisions +=
1957 le32toh(txd->tx_desc->buflen) &
1958 JME_TD_BUF_LEN_MASK;
1963 * Only the first descriptor of multi-descriptor
1964 * transmission is updated so driver have to skip entire
1965 * chained buffers for the transmiited frame. In other
1966 * words, JME_TD_OWN bit is valid only at the first
1967 * descriptor of a multi-descriptor transmission.
1969 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
1970 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
1971 JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
1974 /* Reclaim transferred mbufs. */
1975 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1978 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
1979 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
1980 ("%s: Active Tx desc counter was garbled\n", __func__));
1983 sc->jme_cdata.jme_tx_cons = cons;
1985 if (sc->jme_cdata.jme_tx_cnt == 0)
1988 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
1989 sc->jme_tx_desc_cnt - JME_TXD_RSVD)
1990 ifp->if_flags &= ~IFF_OACTIVE;
1993 static __inline void
1994 jme_discard_rxbufs(struct jme_softc *sc, int ring, int cons, int count)
1996 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
1999 for (i = 0; i < count; ++i) {
2000 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2002 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2003 desc->buflen = htole32(MCLBYTES);
2004 JME_DESC_INC(cons, sc->jme_rx_desc_cnt);
2008 /* Receive a frame. */
2010 jme_rxpkt(struct jme_softc *sc, int ring, struct mbuf_chain *chain)
2012 struct ifnet *ifp = &sc->arpcom.ac_if;
2013 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2014 struct jme_desc *desc;
2015 struct jme_rxdesc *rxd;
2016 struct mbuf *mp, *m;
2017 uint32_t flags, status;
2018 int cons, count, nsegs;
2020 cons = rdata->jme_rx_cons;
2021 desc = &rdata->jme_rx_ring[cons];
2022 flags = le32toh(desc->flags);
2023 status = le32toh(desc->buflen);
2024 nsegs = JME_RX_NSEGS(status);
2026 JME_RSS_DPRINTF(sc, 10, "ring%d, flags 0x%08x, "
2027 "hash 0x%08x, hash type 0x%08x\n",
2028 ring, flags, desc->addr_hi, desc->addr_lo);
2030 if (status & JME_RX_ERR_STAT) {
2032 jme_discard_rxbufs(sc, ring, cons, nsegs);
2033 #ifdef JME_SHOW_ERRORS
2034 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2035 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2037 rdata->jme_rx_cons += nsegs;
2038 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2042 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2043 for (count = 0; count < nsegs; count++,
2044 JME_DESC_INC(cons, sc->jme_rx_desc_cnt)) {
2045 rxd = &rdata->jme_rxdesc[cons];
2048 /* Add a new receive buffer to the ring. */
2049 if (jme_newbuf(sc, ring, rxd, 0) != 0) {
2052 jme_discard_rxbufs(sc, ring, cons, nsegs - count);
2053 if (rdata->jme_rxhead != NULL) {
2054 m_freem(rdata->jme_rxhead);
2055 JME_RXCHAIN_RESET(sc, ring);
2061 * Assume we've received a full sized frame.
2062 * Actual size is fixed when we encounter the end of
2063 * multi-segmented frame.
2065 mp->m_len = MCLBYTES;
2067 /* Chain received mbufs. */
2068 if (rdata->jme_rxhead == NULL) {
2069 rdata->jme_rxhead = mp;
2070 rdata->jme_rxtail = mp;
2073 * Receive processor can receive a maximum frame
2074 * size of 65535 bytes.
2076 mp->m_flags &= ~M_PKTHDR;
2077 rdata->jme_rxtail->m_next = mp;
2078 rdata->jme_rxtail = mp;
2081 if (count == nsegs - 1) {
2082 /* Last desc. for this frame. */
2083 m = rdata->jme_rxhead;
2084 /* XXX assert PKTHDR? */
2085 m->m_flags |= M_PKTHDR;
2086 m->m_pkthdr.len = rdata->jme_rxlen;
2088 /* Set first mbuf size. */
2089 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2090 /* Set last mbuf size. */
2091 mp->m_len = rdata->jme_rxlen -
2092 ((MCLBYTES - JME_RX_PAD_BYTES) +
2093 (MCLBYTES * (nsegs - 2)));
2095 m->m_len = rdata->jme_rxlen;
2097 m->m_pkthdr.rcvif = ifp;
2100 * Account for 10bytes auto padding which is used
2101 * to align IP header on 32bit boundary. Also note,
2102 * CRC bytes is automatically removed by the
2105 m->m_data += JME_RX_PAD_BYTES;
2107 /* Set checksum information. */
2108 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2109 (flags & JME_RD_IPV4)) {
2110 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2111 if (flags & JME_RD_IPCSUM)
2112 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2113 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2114 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2115 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2116 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2117 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2118 m->m_pkthdr.csum_flags |=
2119 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2120 m->m_pkthdr.csum_data = 0xffff;
2124 /* Check for VLAN tagged packets. */
2125 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2126 (flags & JME_RD_VLAN_TAG)) {
2127 m->m_pkthdr.ether_vlantag =
2128 flags & JME_RD_VLAN_MASK;
2129 m->m_flags |= M_VLANTAG;
2134 ether_input_chain(ifp, m, chain);
2136 /* Reset mbuf chains. */
2137 JME_RXCHAIN_RESET(sc, ring);
2138 #ifdef JME_RSS_DEBUG
2139 sc->jme_rx_ring_pkt[ring]++;
2144 rdata->jme_rx_cons += nsegs;
2145 rdata->jme_rx_cons %= sc->jme_rx_desc_cnt;
2149 jme_rxeof_chain(struct jme_softc *sc, int ring, struct mbuf_chain *chain,
2152 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2153 struct jme_desc *desc;
2154 int nsegs, prog, pktlen;
2158 #ifdef DEVICE_POLLING
2159 if (count >= 0 && count-- == 0)
2162 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2163 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2165 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2169 * Check number of segments against received bytes.
2170 * Non-matching value would indicate that hardware
2171 * is still trying to update Rx descriptors. I'm not
2172 * sure whether this check is needed.
2174 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2175 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2176 if (nsegs != howmany(pktlen, MCLBYTES)) {
2177 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2178 "and packet size(%d) mismach\n",
2183 /* Received a frame. */
2184 jme_rxpkt(sc, ring, chain);
2191 jme_rxeof(struct jme_softc *sc, int ring)
2193 struct mbuf_chain chain[MAXCPU];
2195 ether_input_chain_init(chain);
2196 if (jme_rxeof_chain(sc, ring, chain, -1))
2197 ether_input_dispatch(chain);
2203 struct jme_softc *sc = xsc;
2204 struct ifnet *ifp = &sc->arpcom.ac_if;
2205 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2207 lwkt_serialize_enter(ifp->if_serializer);
2210 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2212 lwkt_serialize_exit(ifp->if_serializer);
2216 jme_reset(struct jme_softc *sc)
2219 /* Stop receiver, transmitter. */
2223 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2225 CSR_WRITE_4(sc, JME_GHC, 0);
2231 struct jme_softc *sc = xsc;
2232 struct ifnet *ifp = &sc->arpcom.ac_if;
2233 struct mii_data *mii;
2234 uint8_t eaddr[ETHER_ADDR_LEN];
2239 ASSERT_SERIALIZED(ifp->if_serializer);
2242 * Cancel any pending I/O.
2247 * Reset the chip to a known state.
2252 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2253 KKASSERT(sc->jme_txd_spare >= 1);
2256 * If we use 64bit address mode for transmitting, each Tx request
2257 * needs one more symbol descriptor.
2259 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2260 sc->jme_txd_spare += 1;
2263 if (ifp->if_capenable & IFCAP_RSS)
2267 jme_disable_rss(sc);
2269 /* Init RX descriptors */
2270 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2271 error = jme_init_rx_ring(sc, r);
2273 if_printf(ifp, "initialization failed: "
2274 "no memory for %dth RX ring.\n", r);
2280 /* Init TX descriptors */
2281 jme_init_tx_ring(sc);
2283 /* Initialize shadow status block. */
2286 /* Reprogram the station address. */
2287 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2288 CSR_WRITE_4(sc, JME_PAR0,
2289 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2290 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2293 * Configure Tx queue.
2294 * Tx priority queue weight value : 0
2295 * Tx FIFO threshold for processing next packet : 16QW
2296 * Maximum Tx DMA length : 512
2297 * Allow Tx DMA burst.
2299 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2300 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2301 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2302 sc->jme_txcsr |= sc->jme_tx_dma_size;
2303 sc->jme_txcsr |= TXCSR_DMA_BURST;
2304 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2306 /* Set Tx descriptor counter. */
2307 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2309 /* Set Tx ring address to the hardware. */
2310 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2311 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2312 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2314 /* Configure TxMAC parameters. */
2315 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2316 reg |= TXMAC_THRESH_1_PKT;
2317 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2318 CSR_WRITE_4(sc, JME_TXMAC, reg);
2321 * Configure Rx queue.
2322 * FIFO full threshold for transmitting Tx pause packet : 128T
2323 * FIFO threshold for processing next packet : 128QW
2325 * Max Rx DMA length : 128
2326 * Rx descriptor retry : 32
2327 * Rx descriptor retry time gap : 256ns
2328 * Don't receive runt/bad frame.
2330 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2333 * Since Rx FIFO size is 4K bytes, receiving frames larger
2334 * than 4K bytes will suffer from Rx FIFO overruns. So
2335 * decrease FIFO threshold to reduce the FIFO overruns for
2336 * frames larger than 4000 bytes.
2337 * For best performance of standard MTU sized frames use
2338 * maximum allowable FIFO threshold, 128QW.
2340 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2342 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2344 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2346 /* Improve PCI Express compatibility */
2347 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2349 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2350 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2351 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2352 /* XXX TODO DROP_BAD */
2354 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2355 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2357 /* Set Rx descriptor counter. */
2358 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2360 /* Set Rx ring address to the hardware. */
2361 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2362 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2363 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2366 /* Clear receive filter. */
2367 CSR_WRITE_4(sc, JME_RXMAC, 0);
2369 /* Set up the receive filter. */
2374 * Disable all WOL bits as WOL can interfere normal Rx
2375 * operation. Also clear WOL detection status bits.
2377 reg = CSR_READ_4(sc, JME_PMCS);
2378 reg &= ~PMCS_WOL_ENB_MASK;
2379 CSR_WRITE_4(sc, JME_PMCS, reg);
2382 * Pad 10bytes right before received frame. This will greatly
2383 * help Rx performance on strict-alignment architectures as
2384 * it does not need to copy the frame to align the payload.
2386 reg = CSR_READ_4(sc, JME_RXMAC);
2387 reg |= RXMAC_PAD_10BYTES;
2389 if (ifp->if_capenable & IFCAP_RXCSUM)
2390 reg |= RXMAC_CSUM_ENB;
2391 CSR_WRITE_4(sc, JME_RXMAC, reg);
2393 /* Configure general purpose reg0 */
2394 reg = CSR_READ_4(sc, JME_GPREG0);
2395 reg &= ~GPREG0_PCC_UNIT_MASK;
2396 /* Set PCC timer resolution to micro-seconds unit. */
2397 reg |= GPREG0_PCC_UNIT_US;
2399 * Disable all shadow register posting as we have to read
2400 * JME_INTR_STATUS register in jme_intr. Also it seems
2401 * that it's hard to synchronize interrupt status between
2402 * hardware and software with shadow posting due to
2403 * requirements of bus_dmamap_sync(9).
2405 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2406 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2407 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2408 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2409 /* Disable posting of DW0. */
2410 reg &= ~GPREG0_POST_DW0_ENB;
2411 /* Clear PME message. */
2412 reg &= ~GPREG0_PME_ENB;
2413 /* Set PHY address. */
2414 reg &= ~GPREG0_PHY_ADDR_MASK;
2415 reg |= sc->jme_phyaddr;
2416 CSR_WRITE_4(sc, JME_GPREG0, reg);
2418 /* Configure Tx queue 0 packet completion coalescing. */
2419 jme_set_tx_coal(sc);
2421 /* Configure Rx queue 0 packet completion coalescing. */
2422 jme_set_rx_coal(sc);
2424 /* Configure shadow status block but don't enable posting. */
2425 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2426 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2427 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2429 /* Disable Timer 1 and Timer 2. */
2430 CSR_WRITE_4(sc, JME_TIMER1, 0);
2431 CSR_WRITE_4(sc, JME_TIMER2, 0);
2433 /* Configure retry transmit period, retry limit value. */
2434 CSR_WRITE_4(sc, JME_TXTRHD,
2435 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2436 TXTRHD_RT_PERIOD_MASK) |
2437 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2438 TXTRHD_RT_LIMIT_SHIFT));
2440 #ifdef DEVICE_POLLING
2441 if (!(ifp->if_flags & IFF_POLLING))
2443 /* Initialize the interrupt mask. */
2444 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2445 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2448 * Enabling Tx/Rx DMA engines and Rx queue processing is
2449 * done after detection of valid link in jme_miibus_statchg.
2451 sc->jme_flags &= ~JME_FLAG_LINK;
2453 /* Set the current media. */
2454 mii = device_get_softc(sc->jme_miibus);
2457 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2459 ifp->if_flags |= IFF_RUNNING;
2460 ifp->if_flags &= ~IFF_OACTIVE;
2464 jme_stop(struct jme_softc *sc)
2466 struct ifnet *ifp = &sc->arpcom.ac_if;
2467 struct jme_txdesc *txd;
2468 struct jme_rxdesc *rxd;
2469 struct jme_rxdata *rdata;
2472 ASSERT_SERIALIZED(ifp->if_serializer);
2475 * Mark the interface down and cancel the watchdog timer.
2477 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2480 callout_stop(&sc->jme_tick_ch);
2481 sc->jme_flags &= ~JME_FLAG_LINK;
2484 * Disable interrupts.
2486 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2487 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2489 /* Disable updating shadow status block. */
2490 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2491 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2493 /* Stop receiver, transmitter. */
2498 * Free partial finished RX segments
2500 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2501 rdata = &sc->jme_cdata.jme_rx_data[r];
2502 if (rdata->jme_rxhead != NULL)
2503 m_freem(rdata->jme_rxhead);
2504 JME_RXCHAIN_RESET(sc, r);
2508 * Free RX and TX mbufs still in the queues.
2510 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
2511 rdata = &sc->jme_cdata.jme_rx_data[r];
2512 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2513 rxd = &rdata->jme_rxdesc[i];
2514 if (rxd->rx_m != NULL) {
2515 bus_dmamap_unload(rdata->jme_rx_tag,
2522 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2523 txd = &sc->jme_cdata.jme_txdesc[i];
2524 if (txd->tx_m != NULL) {
2525 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2535 jme_stop_tx(struct jme_softc *sc)
2540 reg = CSR_READ_4(sc, JME_TXCSR);
2541 if ((reg & TXCSR_TX_ENB) == 0)
2543 reg &= ~TXCSR_TX_ENB;
2544 CSR_WRITE_4(sc, JME_TXCSR, reg);
2545 for (i = JME_TIMEOUT; i > 0; i--) {
2547 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2551 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2555 jme_stop_rx(struct jme_softc *sc)
2560 reg = CSR_READ_4(sc, JME_RXCSR);
2561 if ((reg & RXCSR_RX_ENB) == 0)
2563 reg &= ~RXCSR_RX_ENB;
2564 CSR_WRITE_4(sc, JME_RXCSR, reg);
2565 for (i = JME_TIMEOUT; i > 0; i--) {
2567 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2571 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2575 jme_init_tx_ring(struct jme_softc *sc)
2577 struct jme_chain_data *cd;
2578 struct jme_txdesc *txd;
2581 sc->jme_cdata.jme_tx_prod = 0;
2582 sc->jme_cdata.jme_tx_cons = 0;
2583 sc->jme_cdata.jme_tx_cnt = 0;
2585 cd = &sc->jme_cdata;
2586 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2587 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2588 txd = &sc->jme_cdata.jme_txdesc[i];
2590 txd->tx_desc = &cd->jme_tx_ring[i];
2596 jme_init_ssb(struct jme_softc *sc)
2598 struct jme_chain_data *cd;
2600 cd = &sc->jme_cdata;
2601 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2605 jme_init_rx_ring(struct jme_softc *sc, int ring)
2607 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2608 struct jme_rxdesc *rxd;
2611 KKASSERT(rdata->jme_rxhead == NULL &&
2612 rdata->jme_rxtail == NULL &&
2613 rdata->jme_rxlen == 0);
2614 rdata->jme_rx_cons = 0;
2616 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(sc));
2617 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2620 rxd = &rdata->jme_rxdesc[i];
2622 rxd->rx_desc = &rdata->jme_rx_ring[i];
2623 error = jme_newbuf(sc, ring, rxd, 1);
2631 jme_newbuf(struct jme_softc *sc, int ring, struct jme_rxdesc *rxd, int init)
2633 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2634 struct jme_desc *desc;
2636 bus_dma_segment_t segs;
2640 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2644 * JMC250 has 64bit boundary alignment limitation so jme(4)
2645 * takes advantage of 10 bytes padding feature of hardware
2646 * in order not to copy entire frame to align IP header on
2649 m->m_len = m->m_pkthdr.len = MCLBYTES;
2651 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2652 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2657 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2661 if (rxd->rx_m != NULL) {
2662 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2663 BUS_DMASYNC_POSTREAD);
2664 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2666 map = rxd->rx_dmamap;
2667 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2668 rdata->jme_rx_sparemap = map;
2671 desc = rxd->rx_desc;
2672 desc->buflen = htole32(segs.ds_len);
2673 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2674 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2675 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2681 jme_set_vlan(struct jme_softc *sc)
2683 struct ifnet *ifp = &sc->arpcom.ac_if;
2686 ASSERT_SERIALIZED(ifp->if_serializer);
2688 reg = CSR_READ_4(sc, JME_RXMAC);
2689 reg &= ~RXMAC_VLAN_ENB;
2690 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2691 reg |= RXMAC_VLAN_ENB;
2692 CSR_WRITE_4(sc, JME_RXMAC, reg);
2696 jme_set_filter(struct jme_softc *sc)
2698 struct ifnet *ifp = &sc->arpcom.ac_if;
2699 struct ifmultiaddr *ifma;
2704 ASSERT_SERIALIZED(ifp->if_serializer);
2706 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2707 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2711 * Always accept frames destined to our station address.
2712 * Always accept broadcast frames.
2714 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2716 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2717 if (ifp->if_flags & IFF_PROMISC)
2718 rxcfg |= RXMAC_PROMISC;
2719 if (ifp->if_flags & IFF_ALLMULTI)
2720 rxcfg |= RXMAC_ALLMULTI;
2721 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2722 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2723 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2728 * Set up the multicast address filter by passing all multicast
2729 * addresses through a CRC generator, and then using the low-order
2730 * 6 bits as an index into the 64 bit multicast hash table. The
2731 * high order bits select the register, while the rest of the bits
2732 * select the bit within the register.
2734 rxcfg |= RXMAC_MULTICAST;
2735 bzero(mchash, sizeof(mchash));
2737 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2738 if (ifma->ifma_addr->sa_family != AF_LINK)
2740 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2741 ifma->ifma_addr), ETHER_ADDR_LEN);
2743 /* Just want the 6 least significant bits. */
2746 /* Set the corresponding bit in the hash table. */
2747 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2750 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2751 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2752 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2756 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2758 struct jme_softc *sc = arg1;
2759 struct ifnet *ifp = &sc->arpcom.ac_if;
2762 lwkt_serialize_enter(ifp->if_serializer);
2764 v = sc->jme_tx_coal_to;
2765 error = sysctl_handle_int(oidp, &v, 0, req);
2766 if (error || req->newptr == NULL)
2769 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2774 if (v != sc->jme_tx_coal_to) {
2775 sc->jme_tx_coal_to = v;
2776 if (ifp->if_flags & IFF_RUNNING)
2777 jme_set_tx_coal(sc);
2780 lwkt_serialize_exit(ifp->if_serializer);
2785 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2787 struct jme_softc *sc = arg1;
2788 struct ifnet *ifp = &sc->arpcom.ac_if;
2791 lwkt_serialize_enter(ifp->if_serializer);
2793 v = sc->jme_tx_coal_pkt;
2794 error = sysctl_handle_int(oidp, &v, 0, req);
2795 if (error || req->newptr == NULL)
2798 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2803 if (v != sc->jme_tx_coal_pkt) {
2804 sc->jme_tx_coal_pkt = v;
2805 if (ifp->if_flags & IFF_RUNNING)
2806 jme_set_tx_coal(sc);
2809 lwkt_serialize_exit(ifp->if_serializer);
2814 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2816 struct jme_softc *sc = arg1;
2817 struct ifnet *ifp = &sc->arpcom.ac_if;
2820 lwkt_serialize_enter(ifp->if_serializer);
2822 v = sc->jme_rx_coal_to;
2823 error = sysctl_handle_int(oidp, &v, 0, req);
2824 if (error || req->newptr == NULL)
2827 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2832 if (v != sc->jme_rx_coal_to) {
2833 sc->jme_rx_coal_to = v;
2834 if (ifp->if_flags & IFF_RUNNING)
2835 jme_set_rx_coal(sc);
2838 lwkt_serialize_exit(ifp->if_serializer);
2843 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2845 struct jme_softc *sc = arg1;
2846 struct ifnet *ifp = &sc->arpcom.ac_if;
2849 lwkt_serialize_enter(ifp->if_serializer);
2851 v = sc->jme_rx_coal_pkt;
2852 error = sysctl_handle_int(oidp, &v, 0, req);
2853 if (error || req->newptr == NULL)
2856 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2861 if (v != sc->jme_rx_coal_pkt) {
2862 sc->jme_rx_coal_pkt = v;
2863 if (ifp->if_flags & IFF_RUNNING)
2864 jme_set_rx_coal(sc);
2867 lwkt_serialize_exit(ifp->if_serializer);
2872 jme_set_tx_coal(struct jme_softc *sc)
2876 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2878 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2879 PCCTX_COAL_PKT_MASK;
2880 reg |= PCCTX_COAL_TXQ0;
2881 CSR_WRITE_4(sc, JME_PCCTX, reg);
2885 jme_set_rx_coal(struct jme_softc *sc)
2890 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2892 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2893 PCCRX_COAL_PKT_MASK;
2894 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2895 if (r < sc->jme_rx_ring_inuse)
2896 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
2898 CSR_WRITE_4(sc, JME_PCCRX(r), 0);
2902 #ifdef DEVICE_POLLING
2905 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2907 struct jme_softc *sc = ifp->if_softc;
2908 struct mbuf_chain chain[MAXCPU];
2912 ASSERT_SERIALIZED(ifp->if_serializer);
2916 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2919 case POLL_DEREGISTER:
2920 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2923 case POLL_AND_CHECK_STATUS:
2925 status = CSR_READ_4(sc, JME_INTR_STATUS);
2927 ether_input_chain_init(chain);
2928 for (r = 0; r < sc->jme_rx_ring_inuse; ++r)
2929 prog += jme_rxeof_chain(sc, r, chain, count);
2931 ether_input_dispatch(chain);
2933 if (status & INTR_RXQ_DESC_EMPTY) {
2934 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2935 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2936 RXCSR_RX_ENB | RXCSR_RXQ_START);
2940 if (!ifq_is_empty(&ifp->if_snd))
2946 #endif /* DEVICE_POLLING */
2949 jme_rxring_dma_alloc(struct jme_softc *sc, int ring)
2951 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2955 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
2956 JME_RX_RING_ALIGN, 0,
2957 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2958 JME_RX_RING_SIZE(sc),
2959 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
2961 device_printf(sc->jme_dev,
2962 "could not allocate %dth Rx ring.\n", ring);
2965 rdata->jme_rx_ring_tag = dmem.dmem_tag;
2966 rdata->jme_rx_ring_map = dmem.dmem_map;
2967 rdata->jme_rx_ring = dmem.dmem_addr;
2968 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
2974 jme_rxbuf_dma_alloc(struct jme_softc *sc, int ring)
2976 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[ring];
2979 /* Create tag for Rx buffers. */
2980 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
2981 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
2982 BUS_SPACE_MAXADDR, /* lowaddr */
2983 BUS_SPACE_MAXADDR, /* highaddr */
2984 NULL, NULL, /* filter, filterarg */
2985 MCLBYTES, /* maxsize */
2987 MCLBYTES, /* maxsegsize */
2988 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
2989 &rdata->jme_rx_tag);
2991 device_printf(sc->jme_dev,
2992 "could not create %dth Rx DMA tag.\n", ring);
2996 /* Create DMA maps for Rx buffers. */
2997 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
2998 &rdata->jme_rx_sparemap);
3000 device_printf(sc->jme_dev,
3001 "could not create %dth spare Rx dmamap.\n", ring);
3002 bus_dma_tag_destroy(rdata->jme_rx_tag);
3003 rdata->jme_rx_tag = NULL;
3006 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
3007 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3009 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3014 device_printf(sc->jme_dev,
3015 "could not create %dth Rx dmamap "
3016 "for %dth RX ring.\n", i, ring);
3018 for (j = 0; j < i; ++j) {
3019 rxd = &rdata->jme_rxdesc[j];
3020 bus_dmamap_destroy(rdata->jme_rx_tag,
3023 bus_dmamap_destroy(rdata->jme_rx_tag,
3024 rdata->jme_rx_sparemap);
3025 bus_dma_tag_destroy(rdata->jme_rx_tag);
3026 rdata->jme_rx_tag = NULL;
3034 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3036 struct mbuf_chain chain[MAXCPU];
3039 ether_input_chain_init(chain);
3040 for (r = 0; r < sc->jme_rx_ring_inuse; ++r) {
3041 if (status & jme_rx_status[r].jme_coal)
3042 prog += jme_rxeof_chain(sc, r, chain, -1);
3045 ether_input_dispatch(chain);
3051 jme_enable_rss(struct jme_softc *sc)
3054 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3057 sc->jme_rx_ring_inuse = sc->jme_rx_ring_cnt;
3059 rssc = RSSC_HASH_64_ENTRY;
3060 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3061 rssc |= sc->jme_rx_ring_inuse >> 1;
3062 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3063 CSR_WRITE_4(sc, JME_RSSC, rssc);
3065 toeplitz_get_key(key, sizeof(key));
3066 for (i = 0; i < RSSKEY_NREGS; ++i) {
3069 keyreg = RSSKEY_REGVAL(key, i);
3070 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3072 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3076 if (sc->jme_rx_ring_inuse == JME_NRXRING_2) {
3078 } else if (sc->jme_rx_ring_inuse == JME_NRXRING_4) {
3081 panic("%s: invalid # of RX rings (%d)\n",
3082 sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_inuse);
3084 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3085 for (i = 0; i < RSSTBL_NREGS; ++i)
3086 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3092 jme_disable_rss(struct jme_softc *sc)
3094 sc->jme_rx_ring_inuse = JME_NRXRING_1;
3095 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);