2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
62 #include <dev/netif/mii_layer/miivar.h>
63 #include <dev/netif/mii_layer/jmphyreg.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/jme/if_jmereg.h>
70 #include <dev/netif/jme/if_jmevar.h>
72 #include "miibus_if.h"
74 #define JME_TX_SERIALIZE 1
75 #define JME_RX_SERIALIZE 2
77 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82 if ((sc)->jme_rss_debug >= (lvl)) \
83 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85 #else /* !JME_RSS_DEBUG */
86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
87 #endif /* JME_RSS_DEBUG */
89 static int jme_probe(device_t);
90 static int jme_attach(device_t);
91 static int jme_detach(device_t);
92 static int jme_shutdown(device_t);
93 static int jme_suspend(device_t);
94 static int jme_resume(device_t);
96 static int jme_miibus_readreg(device_t, int, int);
97 static int jme_miibus_writereg(device_t, int, int, int);
98 static void jme_miibus_statchg(device_t);
100 static void jme_init(void *);
101 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void jme_start(struct ifnet *);
103 static void jme_watchdog(struct ifnet *);
104 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
105 static int jme_mediachange(struct ifnet *);
106 #ifdef DEVICE_POLLING
107 static void jme_poll(struct ifnet *, enum poll_cmd, int);
109 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
110 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
111 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
113 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
117 static void jme_intr(void *);
118 static void jme_msix_tx(void *);
119 static void jme_msix_rx(void *);
120 static void jme_txeof(struct jme_softc *);
121 static void jme_rxeof(struct jme_rxdata *, int);
122 static void jme_rx_intr(struct jme_softc *, uint32_t);
124 static int jme_msix_setup(device_t);
125 static void jme_msix_teardown(device_t, int);
126 static int jme_intr_setup(device_t);
127 static void jme_intr_teardown(device_t);
128 static void jme_msix_try_alloc(device_t);
129 static void jme_msix_free(device_t);
130 static int jme_intr_alloc(device_t);
131 static void jme_intr_free(device_t);
132 static int jme_dma_alloc(struct jme_softc *);
133 static void jme_dma_free(struct jme_softc *);
134 static int jme_init_rx_ring(struct jme_rxdata *);
135 static void jme_init_tx_ring(struct jme_softc *);
136 static void jme_init_ssb(struct jme_softc *);
137 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
138 static int jme_encap(struct jme_softc *, struct mbuf **);
139 static void jme_rxpkt(struct jme_rxdata *);
140 static int jme_rxring_dma_alloc(struct jme_rxdata *);
141 static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
142 static int jme_rxbuf_dma_filter(void *, bus_addr_t);
144 static void jme_tick(void *);
145 static void jme_stop(struct jme_softc *);
146 static void jme_reset(struct jme_softc *);
147 static void jme_set_msinum(struct jme_softc *);
148 static void jme_set_vlan(struct jme_softc *);
149 static void jme_set_filter(struct jme_softc *);
150 static void jme_stop_tx(struct jme_softc *);
151 static void jme_stop_rx(struct jme_softc *);
152 static void jme_mac_config(struct jme_softc *);
153 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
154 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
155 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
157 static void jme_setwol(struct jme_softc *);
158 static void jme_setlinkspeed(struct jme_softc *);
160 static void jme_set_tx_coal(struct jme_softc *);
161 static void jme_set_rx_coal(struct jme_softc *);
162 static void jme_enable_rss(struct jme_softc *);
163 static void jme_disable_rss(struct jme_softc *);
164 static void jme_serialize_skipmain(struct jme_softc *);
165 static void jme_deserialize_skipmain(struct jme_softc *);
167 static void jme_sysctl_node(struct jme_softc *);
168 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
169 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
170 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
171 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
174 * Devices supported by this driver.
176 static const struct jme_dev {
177 uint16_t jme_vendorid;
178 uint16_t jme_deviceid;
180 const char *jme_name;
182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
184 "JMicron Inc, JMC250 Gigabit Ethernet" },
185 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
187 "JMicron Inc, JMC260 Fast Ethernet" },
191 static device_method_t jme_methods[] = {
192 /* Device interface. */
193 DEVMETHOD(device_probe, jme_probe),
194 DEVMETHOD(device_attach, jme_attach),
195 DEVMETHOD(device_detach, jme_detach),
196 DEVMETHOD(device_shutdown, jme_shutdown),
197 DEVMETHOD(device_suspend, jme_suspend),
198 DEVMETHOD(device_resume, jme_resume),
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
206 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
207 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
212 static driver_t jme_driver = {
215 sizeof(struct jme_softc)
218 static devclass_t jme_devclass;
220 DECLARE_DUMMY_MODULE(if_jme);
221 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
222 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
223 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
225 static const struct {
229 } jme_rx_status[JME_NRXRING_MAX] = {
230 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
231 INTR_RXQ0_DESC_EMPTY },
232 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
233 INTR_RXQ1_DESC_EMPTY },
234 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
235 INTR_RXQ2_DESC_EMPTY },
236 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
237 INTR_RXQ3_DESC_EMPTY }
240 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
241 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
242 static int jme_rx_ring_count = 0;
243 static int jme_msi_enable = 1;
244 static int jme_msix_enable = 1;
246 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
247 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
248 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
249 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
250 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
253 jme_setup_rxdesc(struct jme_rxdesc *rxd)
255 struct jme_desc *desc;
258 desc->buflen = htole32(MCLBYTES);
259 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
260 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
261 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
265 * Read a PHY register on the MII of the JMC250.
268 jme_miibus_readreg(device_t dev, int phy, int reg)
270 struct jme_softc *sc = device_get_softc(dev);
274 /* For FPGA version, PHY address 0 should be ignored. */
275 if (sc->jme_caps & JME_CAP_FPGA) {
279 if (sc->jme_phyaddr != phy)
283 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
284 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
286 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
288 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
292 device_printf(sc->jme_dev, "phy read timeout: "
293 "phy %d, reg %d\n", phy, reg);
297 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
301 * Write a PHY register on the MII of the JMC250.
304 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
306 struct jme_softc *sc = device_get_softc(dev);
309 /* For FPGA version, PHY address 0 should be ignored. */
310 if (sc->jme_caps & JME_CAP_FPGA) {
314 if (sc->jme_phyaddr != phy)
318 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
319 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
320 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
322 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
324 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
328 device_printf(sc->jme_dev, "phy write timeout: "
329 "phy %d, reg %d\n", phy, reg);
336 * Callback from MII layer when media changes.
339 jme_miibus_statchg(device_t dev)
341 struct jme_softc *sc = device_get_softc(dev);
342 struct ifnet *ifp = &sc->arpcom.ac_if;
343 struct mii_data *mii;
344 struct jme_txdesc *txd;
349 jme_serialize_skipmain(sc);
350 ASSERT_IFNET_SERIALIZED_ALL(ifp);
352 if ((ifp->if_flags & IFF_RUNNING) == 0)
355 mii = device_get_softc(sc->jme_miibus);
357 sc->jme_has_link = FALSE;
358 if ((mii->mii_media_status & IFM_AVALID) != 0) {
359 switch (IFM_SUBTYPE(mii->mii_media_active)) {
362 sc->jme_has_link = TRUE;
365 if (sc->jme_caps & JME_CAP_FASTETH)
367 sc->jme_has_link = TRUE;
375 * Disabling Rx/Tx MACs have a side-effect of resetting
376 * JME_TXNDA/JME_RXNDA register to the first address of
377 * Tx/Rx descriptor address. So driver should reset its
378 * internal procucer/consumer pointer and reclaim any
379 * allocated resources. Note, just saving the value of
380 * JME_TXNDA and JME_RXNDA registers before stopping MAC
381 * and restoring JME_TXNDA/JME_RXNDA register is not
382 * sufficient to make sure correct MAC state because
383 * stopping MAC operation can take a while and hardware
384 * might have updated JME_TXNDA/JME_RXNDA registers
385 * during the stop operation.
388 /* Disable interrupts */
389 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
392 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
394 callout_stop(&sc->jme_tick_ch);
396 /* Stop receiver/transmitter. */
400 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
401 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
403 jme_rxeof(rdata, -1);
404 if (rdata->jme_rxhead != NULL)
405 m_freem(rdata->jme_rxhead);
406 JME_RXCHAIN_RESET(rdata);
409 * Reuse configured Rx descriptors and reset
410 * procuder/consumer index.
412 rdata->jme_rx_cons = 0;
414 if (JME_ENABLE_HWRSS(sc))
420 if (sc->jme_cdata.jme_tx_cnt != 0) {
421 /* Remove queued packets for transmit. */
422 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
423 txd = &sc->jme_cdata.jme_txdesc[i];
424 if (txd->tx_m != NULL) {
426 sc->jme_cdata.jme_tx_tag,
435 jme_init_tx_ring(sc);
437 /* Initialize shadow status block. */
440 /* Program MAC with resolved speed/duplex/flow-control. */
441 if (sc->jme_has_link) {
444 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
446 /* Set Tx ring address to the hardware. */
447 paddr = sc->jme_cdata.jme_tx_ring_paddr;
448 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
449 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
451 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
452 CSR_WRITE_4(sc, JME_RXCSR,
453 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
455 /* Set Rx ring address to the hardware. */
456 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
457 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
458 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
461 /* Restart receiver/transmitter. */
462 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
464 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
467 ifp->if_flags |= IFF_RUNNING;
468 ifp->if_flags &= ~IFF_OACTIVE;
469 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
471 #ifdef DEVICE_POLLING
472 if (!(ifp->if_flags & IFF_POLLING))
474 /* Reenable interrupts. */
475 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
479 jme_deserialize_skipmain(sc);
483 * Get the current interface media status.
486 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
488 struct jme_softc *sc = ifp->if_softc;
489 struct mii_data *mii = device_get_softc(sc->jme_miibus);
491 ASSERT_IFNET_SERIALIZED_ALL(ifp);
494 ifmr->ifm_status = mii->mii_media_status;
495 ifmr->ifm_active = mii->mii_media_active;
499 * Set hardware to newly-selected media.
502 jme_mediachange(struct ifnet *ifp)
504 struct jme_softc *sc = ifp->if_softc;
505 struct mii_data *mii = device_get_softc(sc->jme_miibus);
508 ASSERT_IFNET_SERIALIZED_ALL(ifp);
510 if (mii->mii_instance != 0) {
511 struct mii_softc *miisc;
513 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
514 mii_phy_reset(miisc);
516 error = mii_mediachg(mii);
522 jme_probe(device_t dev)
524 const struct jme_dev *sp;
527 vid = pci_get_vendor(dev);
528 did = pci_get_device(dev);
529 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
530 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
531 struct jme_softc *sc = device_get_softc(dev);
533 sc->jme_caps = sp->jme_caps;
534 device_set_desc(dev, sp->jme_name);
542 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
548 for (i = JME_TIMEOUT; i > 0; i--) {
549 reg = CSR_READ_4(sc, JME_SMBCSR);
550 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
556 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
560 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
561 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
562 for (i = JME_TIMEOUT; i > 0; i--) {
564 reg = CSR_READ_4(sc, JME_SMBINTF);
565 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
570 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
574 reg = CSR_READ_4(sc, JME_SMBINTF);
575 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
581 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
583 uint8_t fup, reg, val;
588 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
589 fup != JME_EEPROM_SIG0)
591 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
592 fup != JME_EEPROM_SIG1)
596 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
598 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
599 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
600 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
602 if (reg >= JME_PAR0 &&
603 reg < JME_PAR0 + ETHER_ADDR_LEN) {
604 if (jme_eeprom_read_byte(sc, offset + 2,
607 eaddr[reg - JME_PAR0] = val;
611 /* Check for the end of EEPROM descriptor. */
612 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
614 /* Try next eeprom descriptor. */
615 offset += JME_EEPROM_DESC_BYTES;
616 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
618 if (match == ETHER_ADDR_LEN)
625 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
629 /* Read station address. */
630 par0 = CSR_READ_4(sc, JME_PAR0);
631 par1 = CSR_READ_4(sc, JME_PAR1);
633 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
634 device_printf(sc->jme_dev,
635 "generating fake ethernet address.\n");
636 par0 = karc4random();
637 /* Set OUI to JMicron. */
641 eaddr[3] = (par0 >> 16) & 0xff;
642 eaddr[4] = (par0 >> 8) & 0xff;
643 eaddr[5] = par0 & 0xff;
645 eaddr[0] = (par0 >> 0) & 0xFF;
646 eaddr[1] = (par0 >> 8) & 0xFF;
647 eaddr[2] = (par0 >> 16) & 0xFF;
648 eaddr[3] = (par0 >> 24) & 0xFF;
649 eaddr[4] = (par1 >> 0) & 0xFF;
650 eaddr[5] = (par1 >> 8) & 0xFF;
655 jme_attach(device_t dev)
657 struct jme_softc *sc = device_get_softc(dev);
658 struct ifnet *ifp = &sc->arpcom.ac_if;
661 uint8_t pcie_ptr, rev;
662 int error = 0, i, j, rx_desc_cnt;
663 uint8_t eaddr[ETHER_ADDR_LEN];
665 lwkt_serialize_init(&sc->jme_serialize);
666 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
667 for (i = 0; i < JME_NRXRING_MAX; ++i) {
669 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
672 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
674 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
675 if (rx_desc_cnt > JME_NDESC_MAX)
676 rx_desc_cnt = JME_NDESC_MAX;
678 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
680 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
682 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
683 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
688 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
690 sc->jme_cdata.jme_rx_ring_cnt =
691 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
694 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
696 KKASSERT(i == JME_TX_SERIALIZE);
697 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
699 KKASSERT(i == JME_RX_SERIALIZE);
700 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
701 sc->jme_serialize_arr[i++] =
702 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
704 KKASSERT(i <= JME_NSERIALIZE);
705 sc->jme_serialize_cnt = i;
707 sc->jme_cdata.jme_sc = sc;
708 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
709 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
712 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
713 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
714 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
715 rdata->jme_rx_idx = i;
716 rdata->jme_rx_desc_cnt = rx_desc_cnt;
720 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
722 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
724 callout_init(&sc->jme_tick_ch);
727 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
730 irq = pci_read_config(dev, PCIR_INTLINE, 4);
731 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
733 device_printf(dev, "chip is in D%d power mode "
734 "-- setting to D0\n", pci_get_powerstate(dev));
736 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
738 pci_write_config(dev, PCIR_INTLINE, irq, 4);
739 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
741 #endif /* !BURN_BRIDGE */
743 /* Enable bus mastering */
744 pci_enable_busmaster(dev);
749 * JMC250 supports both memory mapped and I/O register space
750 * access. Because I/O register access should use different
751 * BARs to access registers it's waste of time to use I/O
752 * register spce access. JMC250 uses 16K to map entire memory
755 sc->jme_mem_rid = JME_PCIR_BAR;
756 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
757 &sc->jme_mem_rid, RF_ACTIVE);
758 if (sc->jme_mem_res == NULL) {
759 device_printf(dev, "can't allocate IO memory\n");
762 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
763 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
768 error = jme_intr_alloc(dev);
775 reg = CSR_READ_4(sc, JME_CHIPMODE);
776 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
778 sc->jme_caps |= JME_CAP_FPGA;
780 device_printf(dev, "FPGA revision: 0x%04x\n",
781 (reg & CHIPMODE_FPGA_REV_MASK) >>
782 CHIPMODE_FPGA_REV_SHIFT);
786 /* NOTE: FM revision is put in the upper 4 bits */
787 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
788 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
790 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
792 did = pci_get_device(dev);
794 case PCI_PRODUCT_JMICRON_JMC250:
795 if (rev == JME_REV1_A2)
796 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
799 case PCI_PRODUCT_JMICRON_JMC260:
801 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
805 panic("unknown device id 0x%04x", did);
807 if (rev >= JME_REV2) {
808 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
809 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
810 GHC_TXMAC_CLKSRC_1000;
813 /* Reset the ethernet controller. */
816 /* Map MSI/MSI-X vectors */
819 /* Get station address. */
820 reg = CSR_READ_4(sc, JME_SMBCSR);
821 if (reg & SMBCSR_EEPROM_PRESENT)
822 error = jme_eeprom_macaddr(sc, eaddr);
823 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
824 if (error != 0 && (bootverbose)) {
825 device_printf(dev, "ethernet hardware address "
826 "not found in EEPROM.\n");
828 jme_reg_macaddr(sc, eaddr);
833 * Integrated JR0211 has fixed PHY address whereas FPGA version
834 * requires PHY probing to get correct PHY address.
836 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
837 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
838 GPREG0_PHY_ADDR_MASK;
840 device_printf(dev, "PHY is at address %d.\n",
847 /* Set max allowable DMA size. */
848 pcie_ptr = pci_get_pciecap_ptr(dev);
852 sc->jme_caps |= JME_CAP_PCIE;
853 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
855 device_printf(dev, "Read request size : %d bytes.\n",
856 128 << ((ctrl >> 12) & 0x07));
857 device_printf(dev, "TLP payload size : %d bytes.\n",
858 128 << ((ctrl >> 5) & 0x07));
860 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
861 case PCIEM_DEVCTL_MAX_READRQ_128:
862 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
864 case PCIEM_DEVCTL_MAX_READRQ_256:
865 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
868 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
871 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
873 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
874 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
878 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
879 sc->jme_caps |= JME_CAP_PMCAP;
887 /* Allocate DMA stuffs */
888 error = jme_dma_alloc(sc);
893 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
894 ifp->if_init = jme_init;
895 ifp->if_ioctl = jme_ioctl;
896 ifp->if_start = jme_start;
897 #ifdef DEVICE_POLLING
898 ifp->if_poll = jme_poll;
900 ifp->if_watchdog = jme_watchdog;
901 ifp->if_serialize = jme_serialize;
902 ifp->if_deserialize = jme_deserialize;
903 ifp->if_tryserialize = jme_tryserialize;
905 ifp->if_serialize_assert = jme_serialize_assert;
907 ifq_set_maxlen(&ifp->if_snd,
908 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
909 ifq_set_ready(&ifp->if_snd);
911 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
912 ifp->if_capabilities = IFCAP_HWCSUM |
915 IFCAP_VLAN_HWTAGGING;
916 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
917 ifp->if_capabilities |= IFCAP_RSS;
918 ifp->if_capenable = ifp->if_capabilities;
921 * Disable TXCSUM by default to improve bulk data
922 * transmit performance (+20Mbps improvement).
924 ifp->if_capenable &= ~IFCAP_TXCSUM;
926 if (ifp->if_capenable & IFCAP_TXCSUM)
927 ifp->if_hwassist |= JME_CSUM_FEATURES;
928 ifp->if_hwassist |= CSUM_TSO;
930 /* Set up MII bus. */
931 error = mii_phy_probe(dev, &sc->jme_miibus,
932 jme_mediachange, jme_mediastatus);
934 device_printf(dev, "no PHY found!\n");
939 * Save PHYADDR for FPGA mode PHY.
941 if (sc->jme_caps & JME_CAP_FPGA) {
942 struct mii_data *mii = device_get_softc(sc->jme_miibus);
944 if (mii->mii_instance != 0) {
945 struct mii_softc *miisc;
947 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948 if (miisc->mii_phy != 0) {
949 sc->jme_phyaddr = miisc->mii_phy;
953 if (sc->jme_phyaddr != 0) {
954 device_printf(sc->jme_dev,
955 "FPGA PHY is at %d\n", sc->jme_phyaddr);
957 jme_miibus_writereg(dev, sc->jme_phyaddr,
958 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
960 /* XXX should we clear JME_WA_EXTFIFO */
965 ether_ifattach(ifp, eaddr, NULL);
967 /* Tell the upper layer(s) we support long frames. */
968 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
970 error = jme_intr_setup(dev);
983 jme_detach(device_t dev)
985 struct jme_softc *sc = device_get_softc(dev);
987 if (device_is_attached(dev)) {
988 struct ifnet *ifp = &sc->arpcom.ac_if;
990 ifnet_serialize_all(ifp);
992 jme_intr_teardown(dev);
993 ifnet_deserialize_all(ifp);
998 if (sc->jme_sysctl_tree != NULL)
999 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1001 if (sc->jme_miibus != NULL)
1002 device_delete_child(dev, sc->jme_miibus);
1003 bus_generic_detach(dev);
1007 if (sc->jme_mem_res != NULL) {
1008 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1018 jme_sysctl_node(struct jme_softc *sc)
1021 #ifdef JME_RSS_DEBUG
1025 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028 device_get_nameunit(sc->jme_dev),
1030 if (sc->jme_sysctl_tree == NULL) {
1031 device_printf(sc->jme_dev, "can't add sysctl node\n");
1035 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1040 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1045 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1047 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1050 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1052 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1055 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057 "rx_desc_count", CTLFLAG_RD,
1058 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1059 0, "RX desc count");
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062 "tx_desc_count", CTLFLAG_RD,
1063 &sc->jme_cdata.jme_tx_desc_cnt,
1064 0, "TX desc count");
1065 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1067 "rx_ring_count", CTLFLAG_RD,
1068 &sc->jme_cdata.jme_rx_ring_cnt,
1069 0, "RX ring count");
1070 #ifdef JME_RSS_DEBUG
1071 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1073 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1074 0, "RSS debug level");
1075 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076 char rx_ring_pkt[32];
1078 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1079 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1080 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1081 rx_ring_pkt, CTLFLAG_RW,
1082 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1087 * Set default coalesce valves
1089 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1090 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1091 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1092 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1095 * Adjust coalesce valves, in case that the number of TX/RX
1096 * descs are set to small values by users.
1098 * NOTE: coal_max will not be zero, since number of descs
1099 * must aligned by JME_NDESC_ALIGN (16 currently)
1101 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1102 if (coal_max < sc->jme_tx_coal_pkt)
1103 sc->jme_tx_coal_pkt = coal_max;
1105 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1106 if (coal_max < sc->jme_rx_coal_pkt)
1107 sc->jme_rx_coal_pkt = coal_max;
1111 jme_dma_alloc(struct jme_softc *sc)
1113 struct jme_txdesc *txd;
1115 int error, i, asize;
1117 sc->jme_cdata.jme_txdesc =
1118 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1119 M_DEVBUF, M_WAITOK | M_ZERO);
1120 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1121 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1124 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1125 M_DEVBUF, M_WAITOK | M_ZERO);
1128 /* Create parent ring tag. */
1129 error = bus_dma_tag_create(NULL,/* parent */
1130 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1131 sc->jme_lowaddr, /* lowaddr */
1132 BUS_SPACE_MAXADDR, /* highaddr */
1133 NULL, NULL, /* filter, filterarg */
1134 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1136 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1138 &sc->jme_cdata.jme_ring_tag);
1140 device_printf(sc->jme_dev,
1141 "could not create parent ring DMA tag.\n");
1146 * Create DMA stuffs for TX ring
1148 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1149 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1150 JME_TX_RING_ALIGN, 0,
1151 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1152 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1154 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1157 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1158 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1159 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1160 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1163 * Create DMA stuffs for RX rings
1165 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1166 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1171 /* Create parent buffer tag. */
1172 error = bus_dma_tag_create(NULL,/* parent */
1173 1, 0, /* algnmnt, boundary */
1174 sc->jme_lowaddr, /* lowaddr */
1175 BUS_SPACE_MAXADDR, /* highaddr */
1176 NULL, NULL, /* filter, filterarg */
1177 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1179 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1181 &sc->jme_cdata.jme_buffer_tag);
1183 device_printf(sc->jme_dev,
1184 "could not create parent buffer DMA tag.\n");
1189 * Create DMA stuffs for shadow status block
1191 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1192 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1193 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1194 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1196 device_printf(sc->jme_dev,
1197 "could not create shadow status block.\n");
1200 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1201 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1202 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1203 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1206 * Create DMA stuffs for TX buffers
1209 /* Create tag for Tx buffers. */
1210 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211 1, 0, /* algnmnt, boundary */
1212 BUS_SPACE_MAXADDR, /* lowaddr */
1213 BUS_SPACE_MAXADDR, /* highaddr */
1214 NULL, NULL, /* filter, filterarg */
1215 JME_TSO_MAXSIZE, /* maxsize */
1216 JME_MAXTXSEGS, /* nsegments */
1217 JME_MAXSEGSIZE, /* maxsegsize */
1218 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1219 &sc->jme_cdata.jme_tx_tag);
1221 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1225 /* Create DMA maps for Tx buffers. */
1226 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1227 txd = &sc->jme_cdata.jme_txdesc[i];
1228 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1229 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1234 device_printf(sc->jme_dev,
1235 "could not create %dth Tx dmamap.\n", i);
1237 for (j = 0; j < i; ++j) {
1238 txd = &sc->jme_cdata.jme_txdesc[j];
1239 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1242 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1243 sc->jme_cdata.jme_tx_tag = NULL;
1249 * Create DMA stuffs for RX buffers
1251 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1252 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1260 jme_dma_free(struct jme_softc *sc)
1262 struct jme_txdesc *txd;
1263 struct jme_rxdesc *rxd;
1264 struct jme_rxdata *rdata;
1268 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1269 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1270 sc->jme_cdata.jme_tx_ring_map);
1271 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1272 sc->jme_cdata.jme_tx_ring,
1273 sc->jme_cdata.jme_tx_ring_map);
1274 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1275 sc->jme_cdata.jme_tx_ring_tag = NULL;
1279 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1280 rdata = &sc->jme_cdata.jme_rx_data[r];
1281 if (rdata->jme_rx_ring_tag != NULL) {
1282 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1283 rdata->jme_rx_ring_map);
1284 bus_dmamem_free(rdata->jme_rx_ring_tag,
1286 rdata->jme_rx_ring_map);
1287 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1288 rdata->jme_rx_ring_tag = NULL;
1293 if (sc->jme_cdata.jme_tx_tag != NULL) {
1294 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1295 txd = &sc->jme_cdata.jme_txdesc[i];
1296 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1300 sc->jme_cdata.jme_tx_tag = NULL;
1304 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1305 rdata = &sc->jme_cdata.jme_rx_data[r];
1306 if (rdata->jme_rx_tag != NULL) {
1307 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1308 rxd = &rdata->jme_rxdesc[i];
1309 bus_dmamap_destroy(rdata->jme_rx_tag,
1312 bus_dmamap_destroy(rdata->jme_rx_tag,
1313 rdata->jme_rx_sparemap);
1314 bus_dma_tag_destroy(rdata->jme_rx_tag);
1315 rdata->jme_rx_tag = NULL;
1319 /* Shadow status block. */
1320 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1321 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1322 sc->jme_cdata.jme_ssb_map);
1323 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1324 sc->jme_cdata.jme_ssb_block,
1325 sc->jme_cdata.jme_ssb_map);
1326 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1327 sc->jme_cdata.jme_ssb_tag = NULL;
1330 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1331 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1332 sc->jme_cdata.jme_buffer_tag = NULL;
1334 if (sc->jme_cdata.jme_ring_tag != NULL) {
1335 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1336 sc->jme_cdata.jme_ring_tag = NULL;
1339 if (sc->jme_cdata.jme_txdesc != NULL) {
1340 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1341 sc->jme_cdata.jme_txdesc = NULL;
1343 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1344 rdata = &sc->jme_cdata.jme_rx_data[r];
1345 if (rdata->jme_rxdesc != NULL) {
1346 kfree(rdata->jme_rxdesc, M_DEVBUF);
1347 rdata->jme_rxdesc = NULL;
1353 * Make sure the interface is stopped at reboot time.
1356 jme_shutdown(device_t dev)
1358 return jme_suspend(dev);
1363 * Unlike other ethernet controllers, JMC250 requires
1364 * explicit resetting link speed to 10/100Mbps as gigabit
1365 * link will cunsume more power than 375mA.
1366 * Note, we reset the link speed to 10/100Mbps with
1367 * auto-negotiation but we don't know whether that operation
1368 * would succeed or not as we have no control after powering
1369 * off. If the renegotiation fail WOL may not work. Running
1370 * at 1Gbps draws more power than 375mA at 3.3V which is
1371 * specified in PCI specification and that would result in
1372 * complete shutdowning power to ethernet controller.
1375 * Save current negotiated media speed/duplex/flow-control
1376 * to softc and restore the same link again after resuming.
1377 * PHY handling such as power down/resetting to 100Mbps
1378 * may be better handled in suspend method in phy driver.
1381 jme_setlinkspeed(struct jme_softc *sc)
1383 struct mii_data *mii;
1386 JME_LOCK_ASSERT(sc);
1388 mii = device_get_softc(sc->jme_miibus);
1391 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1392 switch IFM_SUBTYPE(mii->mii_media_active) {
1402 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1403 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1404 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1405 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1406 BMCR_AUTOEN | BMCR_STARTNEG);
1409 /* Poll link state until jme(4) get a 10/100 link. */
1410 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1412 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1413 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1423 pause("jmelnk", hz);
1426 if (i == MII_ANEGTICKS_GIGE)
1427 device_printf(sc->jme_dev, "establishing link failed, "
1428 "WOL may not work!");
1431 * No link, force MAC to have 100Mbps, full-duplex link.
1432 * This is the last resort and may/may not work.
1434 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1435 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1440 jme_setwol(struct jme_softc *sc)
1442 struct ifnet *ifp = &sc->arpcom.ac_if;
1447 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1448 /* No PME capability, PHY power down. */
1449 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1450 MII_BMCR, BMCR_PDOWN);
1454 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1455 pmcs = CSR_READ_4(sc, JME_PMCS);
1456 pmcs &= ~PMCS_WOL_ENB_MASK;
1457 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1458 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1459 /* Enable PME message. */
1460 gpr |= GPREG0_PME_ENB;
1461 /* For gigabit controllers, reset link speed to 10/100. */
1462 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1463 jme_setlinkspeed(sc);
1466 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1467 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1470 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1471 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1472 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1473 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1474 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1475 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1476 /* No WOL, PHY power down. */
1477 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1478 MII_BMCR, BMCR_PDOWN);
1484 jme_suspend(device_t dev)
1486 struct jme_softc *sc = device_get_softc(dev);
1487 struct ifnet *ifp = &sc->arpcom.ac_if;
1489 ifnet_serialize_all(ifp);
1494 ifnet_deserialize_all(ifp);
1500 jme_resume(device_t dev)
1502 struct jme_softc *sc = device_get_softc(dev);
1503 struct ifnet *ifp = &sc->arpcom.ac_if;
1508 ifnet_serialize_all(ifp);
1511 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1514 pmstat = pci_read_config(sc->jme_dev,
1515 pmc + PCIR_POWER_STATUS, 2);
1516 /* Disable PME clear PME status. */
1517 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1518 pci_write_config(sc->jme_dev,
1519 pmc + PCIR_POWER_STATUS, pmstat, 2);
1523 if (ifp->if_flags & IFF_UP)
1526 ifnet_deserialize_all(ifp);
1532 jme_tso_pullup(struct mbuf **mp)
1534 int hoff, iphlen, thoff;
1538 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1540 iphlen = m->m_pkthdr.csum_iphlen;
1541 thoff = m->m_pkthdr.csum_thlen;
1542 hoff = m->m_pkthdr.csum_lhlen;
1544 KASSERT(iphlen > 0, ("invalid ip hlen"));
1545 KASSERT(thoff > 0, ("invalid tcp hlen"));
1546 KASSERT(hoff > 0, ("invalid ether hlen"));
1548 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1549 m = m_pullup(m, hoff + iphlen + thoff);
1560 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1562 struct jme_txdesc *txd;
1563 struct jme_desc *desc;
1565 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1567 int error, i, prod, symbol_desc;
1568 uint32_t cflags, flag64, mss;
1570 M_ASSERTPKTHDR((*m_head));
1572 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1573 /* XXX Is this necessary? */
1574 error = jme_tso_pullup(m_head);
1579 prod = sc->jme_cdata.jme_tx_prod;
1580 txd = &sc->jme_cdata.jme_txdesc[prod];
1582 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1587 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1588 (JME_TXD_RSVD + symbol_desc);
1589 if (maxsegs > JME_MAXTXSEGS)
1590 maxsegs = JME_MAXTXSEGS;
1591 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
1592 ("not enough segments %d", maxsegs));
1594 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1595 txd->tx_dmamap, m_head,
1596 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1600 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1601 BUS_DMASYNC_PREWRITE);
1607 /* Configure checksum offload. */
1608 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1609 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1610 cflags |= JME_TD_TSO;
1611 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1612 if (m->m_pkthdr.csum_flags & CSUM_IP)
1613 cflags |= JME_TD_IPCSUM;
1614 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1615 cflags |= JME_TD_TCPCSUM;
1616 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1617 cflags |= JME_TD_UDPCSUM;
1620 /* Configure VLAN. */
1621 if (m->m_flags & M_VLANTAG) {
1622 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1623 cflags |= JME_TD_VLAN_TAG;
1626 desc = &sc->jme_cdata.jme_tx_ring[prod];
1627 desc->flags = htole32(cflags);
1628 desc->addr_hi = htole32(m->m_pkthdr.len);
1629 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1631 * Use 64bits TX desc chain format.
1633 * The first TX desc of the chain, which is setup here,
1634 * is just a symbol TX desc carrying no payload.
1636 flag64 = JME_TD_64BIT;
1637 desc->buflen = htole32(mss);
1640 /* No effective TX desc is consumed */
1644 * Use 32bits TX desc chain format.
1646 * The first TX desc of the chain, which is setup here,
1647 * is an effective TX desc carrying the first segment of
1651 desc->buflen = htole32(mss | txsegs[0].ds_len);
1652 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1654 /* One effective TX desc is consumed */
1657 sc->jme_cdata.jme_tx_cnt++;
1658 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1659 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1660 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1662 txd->tx_ndesc = 1 - i;
1663 for (; i < nsegs; i++) {
1664 desc = &sc->jme_cdata.jme_tx_ring[prod];
1665 desc->buflen = htole32(txsegs[i].ds_len);
1666 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1667 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1668 desc->flags = htole32(JME_TD_OWN | flag64);
1670 sc->jme_cdata.jme_tx_cnt++;
1671 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1672 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1673 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1676 /* Update producer index. */
1677 sc->jme_cdata.jme_tx_prod = prod;
1679 * Finally request interrupt and give the first descriptor
1680 * owenership to hardware.
1682 desc = txd->tx_desc;
1683 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1686 txd->tx_ndesc += nsegs;
1696 jme_start(struct ifnet *ifp)
1698 struct jme_softc *sc = ifp->if_softc;
1699 struct mbuf *m_head;
1702 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1704 if (!sc->jme_has_link) {
1705 ifq_purge(&ifp->if_snd);
1709 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1712 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1715 while (!ifq_is_empty(&ifp->if_snd)) {
1717 * Check number of available TX descs, always
1718 * leave JME_TXD_RSVD free TX descs.
1720 if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE >
1721 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1722 ifp->if_flags |= IFF_OACTIVE;
1726 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1731 * Pack the data into the transmit ring. If we
1732 * don't have room, set the OACTIVE flag and wait
1733 * for the NIC to drain the ring.
1735 if (jme_encap(sc, &m_head)) {
1736 KKASSERT(m_head == NULL);
1738 ifp->if_flags |= IFF_OACTIVE;
1744 * If there's a BPF listener, bounce a copy of this frame
1747 ETHER_BPF_MTAP(ifp, m_head);
1752 * Reading TXCSR takes very long time under heavy load
1753 * so cache TXCSR value and writes the ORed value with
1754 * the kick command to the TXCSR. This saves one register
1757 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1758 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1759 /* Set a timeout in case the chip goes out to lunch. */
1760 ifp->if_timer = JME_TX_TIMEOUT;
1765 jme_watchdog(struct ifnet *ifp)
1767 struct jme_softc *sc = ifp->if_softc;
1769 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1771 if (!sc->jme_has_link) {
1772 if_printf(ifp, "watchdog timeout (missed link)\n");
1779 if (sc->jme_cdata.jme_tx_cnt == 0) {
1780 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1782 if (!ifq_is_empty(&ifp->if_snd))
1787 if_printf(ifp, "watchdog timeout\n");
1790 if (!ifq_is_empty(&ifp->if_snd))
1795 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1797 struct jme_softc *sc = ifp->if_softc;
1798 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1799 struct ifreq *ifr = (struct ifreq *)data;
1800 int error = 0, mask;
1802 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1806 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1807 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1808 ifr->ifr_mtu > JME_MAX_MTU)) {
1813 if (ifp->if_mtu != ifr->ifr_mtu) {
1815 * No special configuration is required when interface
1816 * MTU is changed but availability of Tx checksum
1817 * offload should be chcked against new MTU size as
1818 * FIFO size is just 2K.
1820 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1821 ifp->if_capenable &=
1822 ~(IFCAP_TXCSUM | IFCAP_TSO);
1824 ~(JME_CSUM_FEATURES | CSUM_TSO);
1826 ifp->if_mtu = ifr->ifr_mtu;
1827 if (ifp->if_flags & IFF_RUNNING)
1833 if (ifp->if_flags & IFF_UP) {
1834 if (ifp->if_flags & IFF_RUNNING) {
1835 if ((ifp->if_flags ^ sc->jme_if_flags) &
1836 (IFF_PROMISC | IFF_ALLMULTI))
1842 if (ifp->if_flags & IFF_RUNNING)
1845 sc->jme_if_flags = ifp->if_flags;
1850 if (ifp->if_flags & IFF_RUNNING)
1856 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1860 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1862 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1863 ifp->if_capenable ^= IFCAP_TXCSUM;
1864 if (ifp->if_capenable & IFCAP_TXCSUM)
1865 ifp->if_hwassist |= JME_CSUM_FEATURES;
1867 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1869 if (mask & IFCAP_RXCSUM) {
1872 ifp->if_capenable ^= IFCAP_RXCSUM;
1873 reg = CSR_READ_4(sc, JME_RXMAC);
1874 reg &= ~RXMAC_CSUM_ENB;
1875 if (ifp->if_capenable & IFCAP_RXCSUM)
1876 reg |= RXMAC_CSUM_ENB;
1877 CSR_WRITE_4(sc, JME_RXMAC, reg);
1880 if (mask & IFCAP_VLAN_HWTAGGING) {
1881 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1885 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1886 ifp->if_capenable ^= IFCAP_TSO;
1887 if (ifp->if_capenable & IFCAP_TSO)
1888 ifp->if_hwassist |= CSUM_TSO;
1890 ifp->if_hwassist &= ~CSUM_TSO;
1893 if (mask & IFCAP_RSS)
1894 ifp->if_capenable ^= IFCAP_RSS;
1898 error = ether_ioctl(ifp, cmd, data);
1905 jme_mac_config(struct jme_softc *sc)
1907 struct mii_data *mii;
1908 uint32_t ghc, rxmac, txmac, txpause, gp1;
1909 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1911 mii = device_get_softc(sc->jme_miibus);
1913 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1915 CSR_WRITE_4(sc, JME_GHC, 0);
1917 rxmac = CSR_READ_4(sc, JME_RXMAC);
1918 rxmac &= ~RXMAC_FC_ENB;
1919 txmac = CSR_READ_4(sc, JME_TXMAC);
1920 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1921 txpause = CSR_READ_4(sc, JME_TXPFC);
1922 txpause &= ~TXPFC_PAUSE_ENB;
1923 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1924 ghc |= GHC_FULL_DUPLEX;
1925 rxmac &= ~RXMAC_COLL_DET_ENB;
1926 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1927 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1930 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1931 txpause |= TXPFC_PAUSE_ENB;
1932 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1933 rxmac |= RXMAC_FC_ENB;
1935 /* Disable retry transmit timer/retry limit. */
1936 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1937 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1939 rxmac |= RXMAC_COLL_DET_ENB;
1940 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1941 /* Enable retry transmit timer/retry limit. */
1942 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1943 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1947 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1949 gp1 = CSR_READ_4(sc, JME_GPREG1);
1950 gp1 &= ~GPREG1_WA_HDX;
1952 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1955 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1957 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1959 gp1 |= GPREG1_WA_HDX;
1963 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1965 gp1 |= GPREG1_WA_HDX;
1968 * Use extended FIFO depth to workaround CRC errors
1969 * emitted by chips before JMC250B
1971 phyconf = JMPHY_CONF_EXTFIFO;
1975 if (sc->jme_caps & JME_CAP_FASTETH)
1978 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1980 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1986 CSR_WRITE_4(sc, JME_GHC, ghc);
1987 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1988 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1989 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1991 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1992 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1993 JMPHY_CONF, phyconf);
1995 if (sc->jme_workaround & JME_WA_HDX)
1996 CSR_WRITE_4(sc, JME_GPREG1, gp1);
2002 struct jme_softc *sc = xsc;
2003 struct ifnet *ifp = &sc->arpcom.ac_if;
2007 ASSERT_SERIALIZED(&sc->jme_serialize);
2009 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2010 if (status == 0 || status == 0xFFFFFFFF)
2013 /* Disable interrupts. */
2014 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2016 status = CSR_READ_4(sc, JME_INTR_STATUS);
2017 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2020 /* Reset PCC counter/timer and Ack interrupts. */
2021 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2023 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2024 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2026 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2027 if (status & jme_rx_status[r].jme_coal) {
2028 status |= jme_rx_status[r].jme_coal |
2029 jme_rx_status[r].jme_comp;
2033 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2035 if (ifp->if_flags & IFF_RUNNING) {
2036 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2037 jme_rx_intr(sc, status);
2039 if (status & INTR_RXQ_DESC_EMPTY) {
2041 * Notify hardware availability of new Rx buffers.
2042 * Reading RXCSR takes very long time under heavy
2043 * load so cache RXCSR value and writes the ORed
2044 * value with the kick command to the RXCSR. This
2045 * saves one register access cycle.
2047 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2048 RXCSR_RX_ENB | RXCSR_RXQ_START);
2051 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2052 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
2054 if (!ifq_is_empty(&ifp->if_snd))
2056 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
2060 /* Reenable interrupts. */
2061 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2065 jme_txeof(struct jme_softc *sc)
2067 struct ifnet *ifp = &sc->arpcom.ac_if;
2070 cons = sc->jme_cdata.jme_tx_cons;
2071 if (cons == sc->jme_cdata.jme_tx_prod)
2075 * Go through our Tx list and free mbufs for those
2076 * frames which have been transmitted.
2078 while (cons != sc->jme_cdata.jme_tx_prod) {
2079 struct jme_txdesc *txd, *next_txd;
2080 uint32_t status, next_status;
2081 int next_cons, nsegs;
2083 txd = &sc->jme_cdata.jme_txdesc[cons];
2084 KASSERT(txd->tx_m != NULL,
2085 ("%s: freeing NULL mbuf!", __func__));
2087 status = le32toh(txd->tx_desc->flags);
2088 if ((status & JME_TD_OWN) == JME_TD_OWN)
2093 * This chip will always update the TX descriptor's
2094 * buflen field and this updating always happens
2095 * after clearing the OWN bit, so even if the OWN
2096 * bit is cleared by the chip, we still don't sure
2097 * about whether the buflen field has been updated
2098 * by the chip or not. To avoid this race, we wait
2099 * for the next TX descriptor's OWN bit to be cleared
2100 * by the chip before reusing this TX descriptor.
2103 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2104 sc->jme_cdata.jme_tx_desc_cnt);
2105 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2106 if (next_txd->tx_m == NULL)
2108 next_status = le32toh(next_txd->tx_desc->flags);
2109 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2112 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2116 if (status & JME_TD_COLLISION) {
2117 ifp->if_collisions +=
2118 le32toh(txd->tx_desc->buflen) &
2119 JME_TD_BUF_LEN_MASK;
2124 * Only the first descriptor of multi-descriptor
2125 * transmission is updated so driver have to skip entire
2126 * chained buffers for the transmiited frame. In other
2127 * words, JME_TD_OWN bit is valid only at the first
2128 * descriptor of a multi-descriptor transmission.
2130 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2131 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2132 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2135 /* Reclaim transferred mbufs. */
2136 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2139 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2140 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2141 ("%s: Active Tx desc counter was garbled", __func__));
2144 sc->jme_cdata.jme_tx_cons = cons;
2146 /* 1 for symbol TX descriptor */
2147 if (sc->jme_cdata.jme_tx_cnt <= JME_MAXTXSEGS + 1)
2150 if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE <=
2151 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2152 ifp->if_flags &= ~IFF_OACTIVE;
2155 static __inline void
2156 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2160 for (i = 0; i < count; ++i) {
2161 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2162 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2166 static __inline struct pktinfo *
2167 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2169 if (flags & JME_RD_IPV4)
2170 pi->pi_netisr = NETISR_IP;
2171 else if (flags & JME_RD_IPV6)
2172 pi->pi_netisr = NETISR_IPV6;
2177 pi->pi_l3proto = IPPROTO_UNKNOWN;
2179 if (flags & JME_RD_MORE_FRAG)
2180 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2181 else if (flags & JME_RD_TCP)
2182 pi->pi_l3proto = IPPROTO_TCP;
2183 else if (flags & JME_RD_UDP)
2184 pi->pi_l3proto = IPPROTO_UDP;
2190 /* Receive a frame. */
2192 jme_rxpkt(struct jme_rxdata *rdata)
2194 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2195 struct jme_desc *desc;
2196 struct jme_rxdesc *rxd;
2197 struct mbuf *mp, *m;
2198 uint32_t flags, status, hash, hashinfo;
2199 int cons, count, nsegs;
2201 cons = rdata->jme_rx_cons;
2202 desc = &rdata->jme_rx_ring[cons];
2204 flags = le32toh(desc->flags);
2205 status = le32toh(desc->buflen);
2206 hash = le32toh(desc->addr_hi);
2207 hashinfo = le32toh(desc->addr_lo);
2208 nsegs = JME_RX_NSEGS(status);
2211 /* Skip the first descriptor. */
2212 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2215 * Clear the OWN bit of the following RX descriptors;
2216 * hardware will not clear the OWN bit except the first
2219 * Since the first RX descriptor is setup, i.e. OWN bit
2220 * on, before its followins RX descriptors, leaving the
2221 * OWN bit on the following RX descriptors will trick
2222 * the hardware into thinking that the following RX
2223 * descriptors are ready to be used too.
2225 for (count = 1; count < nsegs; count++,
2226 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2227 rdata->jme_rx_ring[cons].flags = 0;
2229 cons = rdata->jme_rx_cons;
2232 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2233 "hash 0x%08x, hash info 0x%08x\n",
2234 rdata->jme_rx_idx, flags, hash, hashinfo);
2236 if (status & JME_RX_ERR_STAT) {
2238 jme_discard_rxbufs(rdata, cons, nsegs);
2239 #ifdef JME_SHOW_ERRORS
2240 if_printf(ifp, "%s : receive error = 0x%b\n",
2241 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2243 rdata->jme_rx_cons += nsegs;
2244 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2248 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2249 for (count = 0; count < nsegs; count++,
2250 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2251 rxd = &rdata->jme_rxdesc[cons];
2254 /* Add a new receive buffer to the ring. */
2255 if (jme_newbuf(rdata, rxd, 0) != 0) {
2258 jme_discard_rxbufs(rdata, cons, nsegs - count);
2259 if (rdata->jme_rxhead != NULL) {
2260 m_freem(rdata->jme_rxhead);
2261 JME_RXCHAIN_RESET(rdata);
2267 * Assume we've received a full sized frame.
2268 * Actual size is fixed when we encounter the end of
2269 * multi-segmented frame.
2271 mp->m_len = MCLBYTES;
2273 /* Chain received mbufs. */
2274 if (rdata->jme_rxhead == NULL) {
2275 rdata->jme_rxhead = mp;
2276 rdata->jme_rxtail = mp;
2279 * Receive processor can receive a maximum frame
2280 * size of 65535 bytes.
2282 rdata->jme_rxtail->m_next = mp;
2283 rdata->jme_rxtail = mp;
2286 if (count == nsegs - 1) {
2287 struct pktinfo pi0, *pi;
2289 /* Last desc. for this frame. */
2290 m = rdata->jme_rxhead;
2291 m->m_pkthdr.len = rdata->jme_rxlen;
2293 /* Set first mbuf size. */
2294 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2295 /* Set last mbuf size. */
2296 mp->m_len = rdata->jme_rxlen -
2297 ((MCLBYTES - JME_RX_PAD_BYTES) +
2298 (MCLBYTES * (nsegs - 2)));
2300 m->m_len = rdata->jme_rxlen;
2302 m->m_pkthdr.rcvif = ifp;
2305 * Account for 10bytes auto padding which is used
2306 * to align IP header on 32bit boundary. Also note,
2307 * CRC bytes is automatically removed by the
2310 m->m_data += JME_RX_PAD_BYTES;
2312 /* Set checksum information. */
2313 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2314 (flags & JME_RD_IPV4)) {
2315 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2316 if (flags & JME_RD_IPCSUM)
2317 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2318 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2319 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2320 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2321 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2322 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2323 m->m_pkthdr.csum_flags |=
2324 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2325 m->m_pkthdr.csum_data = 0xffff;
2329 /* Check for VLAN tagged packets. */
2330 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2331 (flags & JME_RD_VLAN_TAG)) {
2332 m->m_pkthdr.ether_vlantag =
2333 flags & JME_RD_VLAN_MASK;
2334 m->m_flags |= M_VLANTAG;
2339 if (ifp->if_capenable & IFCAP_RSS)
2340 pi = jme_pktinfo(&pi0, flags);
2345 (hashinfo & JME_RD_HASH_FN_MASK) ==
2346 JME_RD_HASH_FN_TOEPLITZ) {
2347 m->m_flags |= (M_HASH | M_CKHASH);
2348 m->m_pkthdr.hash = toeplitz_hash(hash);
2351 #ifdef JME_RSS_DEBUG
2353 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2354 "isr %d flags %08x, l3 %d %s\n",
2355 pi->pi_netisr, pi->pi_flags,
2357 (m->m_flags & M_HASH) ? "hash" : "");
2362 ether_input_pkt(ifp, m, pi);
2364 /* Reset mbuf chains. */
2365 JME_RXCHAIN_RESET(rdata);
2366 #ifdef JME_RSS_DEBUG
2367 rdata->jme_rx_pkt++;
2372 rdata->jme_rx_cons += nsegs;
2373 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2377 jme_rxeof(struct jme_rxdata *rdata, int count)
2379 struct jme_desc *desc;
2383 #ifdef DEVICE_POLLING
2384 if (count >= 0 && count-- == 0)
2387 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2388 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2390 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2394 * Check number of segments against received bytes.
2395 * Non-matching value would indicate that hardware
2396 * is still trying to update Rx descriptors. I'm not
2397 * sure whether this check is needed.
2399 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2400 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2401 if (nsegs != howmany(pktlen, MCLBYTES)) {
2402 if_printf(&rdata->jme_sc->arpcom.ac_if,
2403 "RX fragment count(%d) and "
2404 "packet size(%d) mismach\n", nsegs, pktlen);
2410 * RSS hash and hash information may _not_ be set by the
2411 * hardware even if the OWN bit is cleared and VALID bit
2414 * If the RSS information is not delivered by the hardware
2415 * yet, we MUST NOT accept this packet, let alone reusing
2416 * its RX descriptor. If this packet was accepted and its
2417 * RX descriptor was reused before hardware delivering the
2418 * RSS information, the RX buffer's address would be trashed
2419 * by the RSS information delivered by the hardware.
2421 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2422 struct jme_rxdesc *rxd;
2425 hashinfo = le32toh(desc->addr_lo);
2426 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2429 * This test should be enough to detect the pending
2430 * RSS information delivery, given:
2431 * - If RSS hash is not calculated, the hashinfo
2432 * will be 0. Howvever, the lower 32bits of RX
2433 * buffers' physical address will never be 0.
2434 * (see jme_rxbuf_dma_filter)
2435 * - If RSS hash is calculated, the lowest 4 bits
2436 * of hashinfo will be set, while the RX buffers
2437 * are at least 2K aligned.
2439 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2440 #ifdef JME_SHOW_RSSWB
2441 if_printf(&rdata->jme_sc->arpcom.ac_if,
2442 "RSS is not written back yet\n");
2448 /* Received a frame. */
2456 struct jme_softc *sc = xsc;
2457 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2459 lwkt_serialize_enter(&sc->jme_serialize);
2461 sc->jme_in_tick = TRUE;
2463 sc->jme_in_tick = FALSE;
2465 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2467 lwkt_serialize_exit(&sc->jme_serialize);
2471 jme_reset(struct jme_softc *sc)
2475 /* Make sure that TX and RX are stopped */
2480 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2484 * Hold reset bit before stop reset
2487 /* Disable TXMAC and TXOFL clock sources */
2488 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2489 /* Disable RXMAC clock source */
2490 val = CSR_READ_4(sc, JME_GPREG1);
2491 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2493 CSR_READ_4(sc, JME_GHC);
2496 CSR_WRITE_4(sc, JME_GHC, 0);
2498 CSR_READ_4(sc, JME_GHC);
2501 * Clear reset bit after stop reset
2504 /* Enable TXMAC and TXOFL clock sources */
2505 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2506 /* Enable RXMAC clock source */
2507 val = CSR_READ_4(sc, JME_GPREG1);
2508 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2510 CSR_READ_4(sc, JME_GHC);
2512 /* Disable TXMAC and TXOFL clock sources */
2513 CSR_WRITE_4(sc, JME_GHC, 0);
2514 /* Disable RXMAC clock source */
2515 val = CSR_READ_4(sc, JME_GPREG1);
2516 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2518 CSR_READ_4(sc, JME_GHC);
2520 /* Enable TX and RX */
2521 val = CSR_READ_4(sc, JME_TXCSR);
2522 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2523 val = CSR_READ_4(sc, JME_RXCSR);
2524 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2526 CSR_READ_4(sc, JME_TXCSR);
2527 CSR_READ_4(sc, JME_RXCSR);
2529 /* Enable TXMAC and TXOFL clock sources */
2530 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2531 /* Eisable RXMAC clock source */
2532 val = CSR_READ_4(sc, JME_GPREG1);
2533 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2535 CSR_READ_4(sc, JME_GHC);
2537 /* Stop TX and RX */
2545 struct jme_softc *sc = xsc;
2546 struct ifnet *ifp = &sc->arpcom.ac_if;
2547 struct mii_data *mii;
2548 uint8_t eaddr[ETHER_ADDR_LEN];
2553 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2556 * Cancel any pending I/O.
2561 * Reset the chip to a known state.
2566 * Setup MSI/MSI-X vectors to interrupts mapping
2570 if (JME_ENABLE_HWRSS(sc))
2573 jme_disable_rss(sc);
2575 /* Init RX descriptors */
2576 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2577 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2579 if_printf(ifp, "initialization failed: "
2580 "no memory for %dth RX ring.\n", r);
2586 /* Init TX descriptors */
2587 jme_init_tx_ring(sc);
2589 /* Initialize shadow status block. */
2592 /* Reprogram the station address. */
2593 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2594 CSR_WRITE_4(sc, JME_PAR0,
2595 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2596 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2599 * Configure Tx queue.
2600 * Tx priority queue weight value : 0
2601 * Tx FIFO threshold for processing next packet : 16QW
2602 * Maximum Tx DMA length : 512
2603 * Allow Tx DMA burst.
2605 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2606 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2607 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2608 sc->jme_txcsr |= sc->jme_tx_dma_size;
2609 sc->jme_txcsr |= TXCSR_DMA_BURST;
2610 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2612 /* Set Tx descriptor counter. */
2613 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2615 /* Set Tx ring address to the hardware. */
2616 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2617 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2618 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2620 /* Configure TxMAC parameters. */
2621 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2622 reg |= TXMAC_THRESH_1_PKT;
2623 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2624 CSR_WRITE_4(sc, JME_TXMAC, reg);
2627 * Configure Rx queue.
2628 * FIFO full threshold for transmitting Tx pause packet : 128T
2629 * FIFO threshold for processing next packet : 128QW
2631 * Max Rx DMA length : 128
2632 * Rx descriptor retry : 32
2633 * Rx descriptor retry time gap : 256ns
2634 * Don't receive runt/bad frame.
2636 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2639 * Since Rx FIFO size is 4K bytes, receiving frames larger
2640 * than 4K bytes will suffer from Rx FIFO overruns. So
2641 * decrease FIFO threshold to reduce the FIFO overruns for
2642 * frames larger than 4000 bytes.
2643 * For best performance of standard MTU sized frames use
2644 * maximum allowable FIFO threshold, 128QW.
2646 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2648 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2650 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2652 /* Improve PCI Express compatibility */
2653 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2655 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2656 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2657 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2658 /* XXX TODO DROP_BAD */
2660 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2661 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2663 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2665 /* Set Rx descriptor counter. */
2666 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2668 /* Set Rx ring address to the hardware. */
2669 paddr = rdata->jme_rx_ring_paddr;
2670 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2671 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2674 /* Clear receive filter. */
2675 CSR_WRITE_4(sc, JME_RXMAC, 0);
2677 /* Set up the receive filter. */
2682 * Disable all WOL bits as WOL can interfere normal Rx
2683 * operation. Also clear WOL detection status bits.
2685 reg = CSR_READ_4(sc, JME_PMCS);
2686 reg &= ~PMCS_WOL_ENB_MASK;
2687 CSR_WRITE_4(sc, JME_PMCS, reg);
2690 * Pad 10bytes right before received frame. This will greatly
2691 * help Rx performance on strict-alignment architectures as
2692 * it does not need to copy the frame to align the payload.
2694 reg = CSR_READ_4(sc, JME_RXMAC);
2695 reg |= RXMAC_PAD_10BYTES;
2697 if (ifp->if_capenable & IFCAP_RXCSUM)
2698 reg |= RXMAC_CSUM_ENB;
2699 CSR_WRITE_4(sc, JME_RXMAC, reg);
2701 /* Configure general purpose reg0 */
2702 reg = CSR_READ_4(sc, JME_GPREG0);
2703 reg &= ~GPREG0_PCC_UNIT_MASK;
2704 /* Set PCC timer resolution to micro-seconds unit. */
2705 reg |= GPREG0_PCC_UNIT_US;
2707 * Disable all shadow register posting as we have to read
2708 * JME_INTR_STATUS register in jme_intr. Also it seems
2709 * that it's hard to synchronize interrupt status between
2710 * hardware and software with shadow posting due to
2711 * requirements of bus_dmamap_sync(9).
2713 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2714 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2715 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2716 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2717 /* Disable posting of DW0. */
2718 reg &= ~GPREG0_POST_DW0_ENB;
2719 /* Clear PME message. */
2720 reg &= ~GPREG0_PME_ENB;
2721 /* Set PHY address. */
2722 reg &= ~GPREG0_PHY_ADDR_MASK;
2723 reg |= sc->jme_phyaddr;
2724 CSR_WRITE_4(sc, JME_GPREG0, reg);
2726 /* Configure Tx queue 0 packet completion coalescing. */
2727 jme_set_tx_coal(sc);
2729 /* Configure Rx queues packet completion coalescing. */
2730 jme_set_rx_coal(sc);
2732 /* Configure shadow status block but don't enable posting. */
2733 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2734 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2735 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2737 /* Disable Timer 1 and Timer 2. */
2738 CSR_WRITE_4(sc, JME_TIMER1, 0);
2739 CSR_WRITE_4(sc, JME_TIMER2, 0);
2741 /* Configure retry transmit period, retry limit value. */
2742 CSR_WRITE_4(sc, JME_TXTRHD,
2743 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2744 TXTRHD_RT_PERIOD_MASK) |
2745 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2746 TXTRHD_RT_LIMIT_SHIFT));
2748 #ifdef DEVICE_POLLING
2749 if (!(ifp->if_flags & IFF_POLLING))
2751 /* Initialize the interrupt mask. */
2752 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2753 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2756 * Enabling Tx/Rx DMA engines and Rx queue processing is
2757 * done after detection of valid link in jme_miibus_statchg.
2759 sc->jme_has_link = FALSE;
2761 /* Set the current media. */
2762 mii = device_get_softc(sc->jme_miibus);
2765 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2767 ifp->if_flags |= IFF_RUNNING;
2768 ifp->if_flags &= ~IFF_OACTIVE;
2772 jme_stop(struct jme_softc *sc)
2774 struct ifnet *ifp = &sc->arpcom.ac_if;
2775 struct jme_txdesc *txd;
2776 struct jme_rxdesc *rxd;
2777 struct jme_rxdata *rdata;
2780 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2783 * Mark the interface down and cancel the watchdog timer.
2785 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2788 callout_stop(&sc->jme_tick_ch);
2789 sc->jme_has_link = FALSE;
2792 * Disable interrupts.
2794 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2795 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2797 /* Disable updating shadow status block. */
2798 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2799 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2801 /* Stop receiver, transmitter. */
2806 * Free partial finished RX segments
2808 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2809 rdata = &sc->jme_cdata.jme_rx_data[r];
2810 if (rdata->jme_rxhead != NULL)
2811 m_freem(rdata->jme_rxhead);
2812 JME_RXCHAIN_RESET(rdata);
2816 * Free RX and TX mbufs still in the queues.
2818 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2819 rdata = &sc->jme_cdata.jme_rx_data[r];
2820 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2821 rxd = &rdata->jme_rxdesc[i];
2822 if (rxd->rx_m != NULL) {
2823 bus_dmamap_unload(rdata->jme_rx_tag,
2830 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2831 txd = &sc->jme_cdata.jme_txdesc[i];
2832 if (txd->tx_m != NULL) {
2833 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2843 jme_stop_tx(struct jme_softc *sc)
2848 reg = CSR_READ_4(sc, JME_TXCSR);
2849 if ((reg & TXCSR_TX_ENB) == 0)
2851 reg &= ~TXCSR_TX_ENB;
2852 CSR_WRITE_4(sc, JME_TXCSR, reg);
2853 for (i = JME_TIMEOUT; i > 0; i--) {
2855 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2859 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2863 jme_stop_rx(struct jme_softc *sc)
2868 reg = CSR_READ_4(sc, JME_RXCSR);
2869 if ((reg & RXCSR_RX_ENB) == 0)
2871 reg &= ~RXCSR_RX_ENB;
2872 CSR_WRITE_4(sc, JME_RXCSR, reg);
2873 for (i = JME_TIMEOUT; i > 0; i--) {
2875 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2879 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2883 jme_init_tx_ring(struct jme_softc *sc)
2885 struct jme_chain_data *cd;
2886 struct jme_txdesc *txd;
2889 sc->jme_cdata.jme_tx_prod = 0;
2890 sc->jme_cdata.jme_tx_cons = 0;
2891 sc->jme_cdata.jme_tx_cnt = 0;
2893 cd = &sc->jme_cdata;
2894 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2895 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2896 txd = &sc->jme_cdata.jme_txdesc[i];
2898 txd->tx_desc = &cd->jme_tx_ring[i];
2904 jme_init_ssb(struct jme_softc *sc)
2906 struct jme_chain_data *cd;
2908 cd = &sc->jme_cdata;
2909 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2913 jme_init_rx_ring(struct jme_rxdata *rdata)
2915 struct jme_rxdesc *rxd;
2918 KKASSERT(rdata->jme_rxhead == NULL &&
2919 rdata->jme_rxtail == NULL &&
2920 rdata->jme_rxlen == 0);
2921 rdata->jme_rx_cons = 0;
2923 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2924 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2927 rxd = &rdata->jme_rxdesc[i];
2929 rxd->rx_desc = &rdata->jme_rx_ring[i];
2930 error = jme_newbuf(rdata, rxd, 1);
2938 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2941 bus_dma_segment_t segs;
2945 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2949 * JMC250 has 64bit boundary alignment limitation so jme(4)
2950 * takes advantage of 10 bytes padding feature of hardware
2951 * in order not to copy entire frame to align IP header on
2954 m->m_len = m->m_pkthdr.len = MCLBYTES;
2956 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2957 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2962 if_printf(&rdata->jme_sc->arpcom.ac_if,
2963 "can't load RX mbuf\n");
2968 if (rxd->rx_m != NULL) {
2969 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2970 BUS_DMASYNC_POSTREAD);
2971 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2973 map = rxd->rx_dmamap;
2974 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2975 rdata->jme_rx_sparemap = map;
2977 rxd->rx_paddr = segs.ds_addr;
2979 jme_setup_rxdesc(rxd);
2984 jme_set_vlan(struct jme_softc *sc)
2986 struct ifnet *ifp = &sc->arpcom.ac_if;
2989 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2991 reg = CSR_READ_4(sc, JME_RXMAC);
2992 reg &= ~RXMAC_VLAN_ENB;
2993 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2994 reg |= RXMAC_VLAN_ENB;
2995 CSR_WRITE_4(sc, JME_RXMAC, reg);
2999 jme_set_filter(struct jme_softc *sc)
3001 struct ifnet *ifp = &sc->arpcom.ac_if;
3002 struct ifmultiaddr *ifma;
3007 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3009 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3010 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3014 * Always accept frames destined to our station address.
3015 * Always accept broadcast frames.
3017 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3019 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3020 if (ifp->if_flags & IFF_PROMISC)
3021 rxcfg |= RXMAC_PROMISC;
3022 if (ifp->if_flags & IFF_ALLMULTI)
3023 rxcfg |= RXMAC_ALLMULTI;
3024 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3025 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3026 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3031 * Set up the multicast address filter by passing all multicast
3032 * addresses through a CRC generator, and then using the low-order
3033 * 6 bits as an index into the 64 bit multicast hash table. The
3034 * high order bits select the register, while the rest of the bits
3035 * select the bit within the register.
3037 rxcfg |= RXMAC_MULTICAST;
3038 bzero(mchash, sizeof(mchash));
3040 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3041 if (ifma->ifma_addr->sa_family != AF_LINK)
3043 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3044 ifma->ifma_addr), ETHER_ADDR_LEN);
3046 /* Just want the 6 least significant bits. */
3049 /* Set the corresponding bit in the hash table. */
3050 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3053 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3054 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3055 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3059 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3061 struct jme_softc *sc = arg1;
3062 struct ifnet *ifp = &sc->arpcom.ac_if;
3065 ifnet_serialize_all(ifp);
3067 v = sc->jme_tx_coal_to;
3068 error = sysctl_handle_int(oidp, &v, 0, req);
3069 if (error || req->newptr == NULL)
3072 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3077 if (v != sc->jme_tx_coal_to) {
3078 sc->jme_tx_coal_to = v;
3079 if (ifp->if_flags & IFF_RUNNING)
3080 jme_set_tx_coal(sc);
3083 ifnet_deserialize_all(ifp);
3088 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3090 struct jme_softc *sc = arg1;
3091 struct ifnet *ifp = &sc->arpcom.ac_if;
3094 ifnet_serialize_all(ifp);
3096 v = sc->jme_tx_coal_pkt;
3097 error = sysctl_handle_int(oidp, &v, 0, req);
3098 if (error || req->newptr == NULL)
3101 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3106 if (v != sc->jme_tx_coal_pkt) {
3107 sc->jme_tx_coal_pkt = v;
3108 if (ifp->if_flags & IFF_RUNNING)
3109 jme_set_tx_coal(sc);
3112 ifnet_deserialize_all(ifp);
3117 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3119 struct jme_softc *sc = arg1;
3120 struct ifnet *ifp = &sc->arpcom.ac_if;
3123 ifnet_serialize_all(ifp);
3125 v = sc->jme_rx_coal_to;
3126 error = sysctl_handle_int(oidp, &v, 0, req);
3127 if (error || req->newptr == NULL)
3130 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3135 if (v != sc->jme_rx_coal_to) {
3136 sc->jme_rx_coal_to = v;
3137 if (ifp->if_flags & IFF_RUNNING)
3138 jme_set_rx_coal(sc);
3141 ifnet_deserialize_all(ifp);
3146 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3148 struct jme_softc *sc = arg1;
3149 struct ifnet *ifp = &sc->arpcom.ac_if;
3152 ifnet_serialize_all(ifp);
3154 v = sc->jme_rx_coal_pkt;
3155 error = sysctl_handle_int(oidp, &v, 0, req);
3156 if (error || req->newptr == NULL)
3159 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3164 if (v != sc->jme_rx_coal_pkt) {
3165 sc->jme_rx_coal_pkt = v;
3166 if (ifp->if_flags & IFF_RUNNING)
3167 jme_set_rx_coal(sc);
3170 ifnet_deserialize_all(ifp);
3175 jme_set_tx_coal(struct jme_softc *sc)
3179 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3181 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3182 PCCTX_COAL_PKT_MASK;
3183 reg |= PCCTX_COAL_TXQ0;
3184 CSR_WRITE_4(sc, JME_PCCTX, reg);
3188 jme_set_rx_coal(struct jme_softc *sc)
3193 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3195 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3196 PCCRX_COAL_PKT_MASK;
3197 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3198 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3201 #ifdef DEVICE_POLLING
3204 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3206 struct jme_softc *sc = ifp->if_softc;
3210 ASSERT_SERIALIZED(&sc->jme_serialize);
3214 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3217 case POLL_DEREGISTER:
3218 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3221 case POLL_AND_CHECK_STATUS:
3223 status = CSR_READ_4(sc, JME_INTR_STATUS);
3225 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3226 struct jme_rxdata *rdata =
3227 &sc->jme_cdata.jme_rx_data[r];
3229 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3230 jme_rxeof(rdata, count);
3231 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3234 if (status & INTR_RXQ_DESC_EMPTY) {
3235 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3236 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3237 RXCSR_RX_ENB | RXCSR_RXQ_START);
3240 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3242 if (!ifq_is_empty(&ifp->if_snd))
3244 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3249 #endif /* DEVICE_POLLING */
3252 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3257 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3258 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3259 JME_RX_RING_ALIGN, 0,
3260 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3261 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3263 device_printf(rdata->jme_sc->jme_dev,
3264 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3267 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3268 rdata->jme_rx_ring_map = dmem.dmem_map;
3269 rdata->jme_rx_ring = dmem.dmem_addr;
3270 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3276 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3278 if ((paddr & 0xffffffff) == 0) {
3280 * Don't allow lower 32bits of the RX buffer's
3281 * physical address to be 0, else it will break
3282 * hardware pending RSS information delivery
3283 * detection on RX path.
3291 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3296 lowaddr = BUS_SPACE_MAXADDR;
3297 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3298 /* jme_rxbuf_dma_filter will be called */
3299 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3302 /* Create tag for Rx buffers. */
3303 error = bus_dma_tag_create(
3304 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3305 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3306 lowaddr, /* lowaddr */
3307 BUS_SPACE_MAXADDR, /* highaddr */
3308 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3309 MCLBYTES, /* maxsize */
3311 MCLBYTES, /* maxsegsize */
3312 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3313 &rdata->jme_rx_tag);
3315 device_printf(rdata->jme_sc->jme_dev,
3316 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3320 /* Create DMA maps for Rx buffers. */
3321 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3322 &rdata->jme_rx_sparemap);
3324 device_printf(rdata->jme_sc->jme_dev,
3325 "could not create %dth spare Rx dmamap.\n",
3327 bus_dma_tag_destroy(rdata->jme_rx_tag);
3328 rdata->jme_rx_tag = NULL;
3331 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3332 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3334 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3339 device_printf(rdata->jme_sc->jme_dev,
3340 "could not create %dth Rx dmamap "
3341 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3343 for (j = 0; j < i; ++j) {
3344 rxd = &rdata->jme_rxdesc[j];
3345 bus_dmamap_destroy(rdata->jme_rx_tag,
3348 bus_dmamap_destroy(rdata->jme_rx_tag,
3349 rdata->jme_rx_sparemap);
3350 bus_dma_tag_destroy(rdata->jme_rx_tag);
3351 rdata->jme_rx_tag = NULL;
3359 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3363 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3364 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3366 if (status & rdata->jme_rx_coal) {
3367 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3368 jme_rxeof(rdata, -1);
3369 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3375 jme_enable_rss(struct jme_softc *sc)
3378 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3381 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3382 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3383 ("%s: invalid # of RX rings (%d)",
3384 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3386 rssc = RSSC_HASH_64_ENTRY;
3387 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3388 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3389 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3390 CSR_WRITE_4(sc, JME_RSSC, rssc);
3392 toeplitz_get_key(key, sizeof(key));
3393 for (i = 0; i < RSSKEY_NREGS; ++i) {
3396 keyreg = RSSKEY_REGVAL(key, i);
3397 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3399 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3403 * Create redirect table in following fashion:
3404 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3407 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3410 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3411 ind |= q << (i * 8);
3413 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3415 for (i = 0; i < RSSTBL_NREGS; ++i)
3416 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3420 jme_disable_rss(struct jme_softc *sc)
3422 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3426 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3428 struct jme_softc *sc = ifp->if_softc;
3430 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3431 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3435 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3437 struct jme_softc *sc = ifp->if_softc;
3439 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3440 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3444 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3446 struct jme_softc *sc = ifp->if_softc;
3448 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3449 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3455 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3456 boolean_t serialized)
3458 struct jme_softc *sc = ifp->if_softc;
3460 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3461 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3465 #endif /* INVARIANTS */
3468 jme_msix_try_alloc(device_t dev)
3470 struct jme_softc *sc = device_get_softc(dev);
3471 struct jme_msix_data *msix;
3472 int error, i, r, msix_enable, msix_count;
3473 int offset, offset_def;
3475 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3476 KKASSERT(msix_count <= JME_NMSIX);
3478 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3481 * We leave the 1st MSI-X vector unused, so we
3482 * actually need msix_count + 1 MSI-X vectors.
3484 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3487 for (i = 0; i < msix_count; ++i)
3488 sc->jme_msix[i].jme_msix_rid = -1;
3496 offset_def = device_get_unit(dev) % ncpus2;
3497 offset = device_getenv_int(dev, "msix.txoff", offset_def);
3498 if (offset >= ncpus2) {
3499 device_printf(dev, "invalid msix.txoff %d, use %d\n",
3500 offset, offset_def);
3501 offset = offset_def;
3504 msix = &sc->jme_msix[i++];
3505 msix->jme_msix_cpuid = offset;
3506 sc->jme_tx_cpuid = msix->jme_msix_cpuid;
3507 msix->jme_msix_arg = &sc->jme_cdata;
3508 msix->jme_msix_func = jme_msix_tx;
3509 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3510 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3511 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3512 device_get_nameunit(dev));
3518 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
3521 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
3522 device_get_unit(dev)) % ncpus2;
3524 offset = device_getenv_int(dev, "msix.rxoff", offset_def);
3525 if (offset >= ncpus2 ||
3526 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3527 device_printf(dev, "invalid msix.rxoff %d, use %d\n",
3528 offset, offset_def);
3529 offset = offset_def;
3533 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3534 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3536 msix = &sc->jme_msix[i++];
3537 msix->jme_msix_cpuid = r + offset;
3538 KKASSERT(msix->jme_msix_cpuid < ncpus2);
3539 msix->jme_msix_arg = rdata;
3540 msix->jme_msix_func = jme_msix_rx;
3541 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3542 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3543 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3544 "%s rx%d", device_get_nameunit(dev), r);
3547 KKASSERT(i == msix_count);
3549 error = pci_setup_msix(dev);
3553 /* Setup jme_msix_cnt early, so we could cleanup */
3554 sc->jme_msix_cnt = msix_count;
3556 for (i = 0; i < msix_count; ++i) {
3557 msix = &sc->jme_msix[i];
3559 msix->jme_msix_vector = i + 1;
3560 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3561 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3565 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3566 &msix->jme_msix_rid, RF_ACTIVE);
3567 if (msix->jme_msix_res == NULL) {
3573 for (i = 0; i < JME_INTR_CNT; ++i) {
3574 uint32_t intr_mask = (1 << i);
3577 if ((JME_INTRS & intr_mask) == 0)
3580 for (x = 0; x < msix_count; ++x) {
3581 msix = &sc->jme_msix[x];
3582 if (msix->jme_msix_intrs & intr_mask) {
3585 reg = i / JME_MSINUM_FACTOR;
3586 KKASSERT(reg < JME_MSINUM_CNT);
3588 shift = (i % JME_MSINUM_FACTOR) * 4;
3590 sc->jme_msinum[reg] |=
3591 (msix->jme_msix_vector << shift);
3599 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3600 device_printf(dev, "MSINUM%d: %#x\n", i,
3605 pci_enable_msix(dev);
3606 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3614 jme_intr_alloc(device_t dev)
3616 struct jme_softc *sc = device_get_softc(dev);
3619 jme_msix_try_alloc(dev);
3621 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3622 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3623 &sc->jme_irq_rid, &irq_flags);
3625 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3626 &sc->jme_irq_rid, irq_flags);
3627 if (sc->jme_irq_res == NULL) {
3628 device_printf(dev, "can't allocate irq\n");
3636 jme_msix_free(device_t dev)
3638 struct jme_softc *sc = device_get_softc(dev);
3641 KKASSERT(sc->jme_msix_cnt > 1);
3643 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3644 struct jme_msix_data *msix = &sc->jme_msix[i];
3646 if (msix->jme_msix_res != NULL) {
3647 bus_release_resource(dev, SYS_RES_IRQ,
3648 msix->jme_msix_rid, msix->jme_msix_res);
3649 msix->jme_msix_res = NULL;
3651 if (msix->jme_msix_rid >= 0) {
3652 pci_release_msix_vector(dev, msix->jme_msix_rid);
3653 msix->jme_msix_rid = -1;
3656 pci_teardown_msix(dev);
3660 jme_intr_free(device_t dev)
3662 struct jme_softc *sc = device_get_softc(dev);
3664 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3665 if (sc->jme_irq_res != NULL) {
3666 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3669 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3670 pci_release_msi(dev);
3677 jme_msix_tx(void *xcd)
3679 struct jme_chain_data *cd = xcd;
3680 struct jme_softc *sc = cd->jme_sc;
3681 struct ifnet *ifp = &sc->arpcom.ac_if;
3683 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3685 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3687 CSR_WRITE_4(sc, JME_INTR_STATUS,
3688 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3690 if (ifp->if_flags & IFF_RUNNING) {
3692 if (!ifq_is_empty(&ifp->if_snd))
3696 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3700 jme_msix_rx(void *xrdata)
3702 struct jme_rxdata *rdata = xrdata;
3703 struct jme_softc *sc = rdata->jme_sc;
3704 struct ifnet *ifp = &sc->arpcom.ac_if;
3707 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3709 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3710 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3712 status = CSR_READ_4(sc, JME_INTR_STATUS);
3713 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3715 if (status & rdata->jme_rx_coal)
3716 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3717 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3719 if (ifp->if_flags & IFF_RUNNING) {
3720 if (status & rdata->jme_rx_coal)
3721 jme_rxeof(rdata, -1);
3723 if (status & rdata->jme_rx_empty) {
3724 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3725 RXCSR_RX_ENB | RXCSR_RXQ_START);
3729 CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3730 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3734 jme_set_msinum(struct jme_softc *sc)
3738 for (i = 0; i < JME_MSINUM_CNT; ++i)
3739 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3743 jme_intr_setup(device_t dev)
3745 struct jme_softc *sc = device_get_softc(dev);
3746 struct ifnet *ifp = &sc->arpcom.ac_if;
3749 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3750 return jme_msix_setup(dev);
3752 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3753 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3755 device_printf(dev, "could not set up interrupt handler.\n");
3759 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3760 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3765 jme_intr_teardown(device_t dev)
3767 struct jme_softc *sc = device_get_softc(dev);
3769 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3770 jme_msix_teardown(dev, sc->jme_msix_cnt);
3772 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3776 jme_msix_setup(device_t dev)
3778 struct jme_softc *sc = device_get_softc(dev);
3779 struct ifnet *ifp = &sc->arpcom.ac_if;
3782 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3783 struct jme_msix_data *msix = &sc->jme_msix[x];
3786 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3787 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3788 &msix->jme_msix_handle, msix->jme_msix_serialize,
3789 msix->jme_msix_desc);
3791 device_printf(dev, "could not set up %s "
3792 "interrupt handler.\n", msix->jme_msix_desc);
3793 jme_msix_teardown(dev, x);
3797 ifp->if_cpuid = sc->jme_tx_cpuid;
3802 jme_msix_teardown(device_t dev, int msix_count)
3804 struct jme_softc *sc = device_get_softc(dev);
3807 for (x = 0; x < msix_count; ++x) {
3808 struct jme_msix_data *msix = &sc->jme_msix[x];
3810 bus_teardown_intr(dev, msix->jme_msix_res,
3811 msix->jme_msix_handle);
3816 jme_serialize_skipmain(struct jme_softc *sc)
3818 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3819 sc->jme_serialize_cnt, 1);
3823 jme_deserialize_skipmain(struct jme_softc *sc)
3825 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3826 sc->jme_serialize_cnt, 1);