jme: Allow MSI-X be evenly spreaded across CPUs
[dragonfly.git] / sys / dev / netif / jme / if_jme.c
1 /*-
2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice unmodified, this list of conditions, and the following
10  *    disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28  */
29
30 #include "opt_polling.h"
31 #include "opt_jme.h"
32
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
39 #include <sys/proc.h>
40 #include <sys/rman.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46
47 #include <net/ethernet.h>
48 #include <net/if.h>
49 #include <net/bpf.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
58
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61
62 #include <dev/netif/mii_layer/miivar.h>
63 #include <dev/netif/mii_layer/jmphyreg.h>
64
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
68
69 #include <dev/netif/jme/if_jmereg.h>
70 #include <dev/netif/jme/if_jmevar.h>
71
72 #include "miibus_if.h"
73
74 #define JME_TX_SERIALIZE        1
75 #define JME_RX_SERIALIZE        2
76
77 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
78
79 #ifdef JME_RSS_DEBUG
80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
81 do { \
82         if ((sc)->jme_rss_debug >= (lvl)) \
83                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
84 } while (0)
85 #else   /* !JME_RSS_DEBUG */
86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
87 #endif  /* JME_RSS_DEBUG */
88
89 static int      jme_probe(device_t);
90 static int      jme_attach(device_t);
91 static int      jme_detach(device_t);
92 static int      jme_shutdown(device_t);
93 static int      jme_suspend(device_t);
94 static int      jme_resume(device_t);
95
96 static int      jme_miibus_readreg(device_t, int, int);
97 static int      jme_miibus_writereg(device_t, int, int, int);
98 static void     jme_miibus_statchg(device_t);
99
100 static void     jme_init(void *);
101 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void     jme_start(struct ifnet *);
103 static void     jme_watchdog(struct ifnet *);
104 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
105 static int      jme_mediachange(struct ifnet *);
106 #ifdef DEVICE_POLLING
107 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
108 #endif
109 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
110 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
111 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
112 #ifdef INVARIANTS
113 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
114                     boolean_t);
115 #endif
116
117 static void     jme_intr(void *);
118 static void     jme_msix_tx(void *);
119 static void     jme_msix_rx(void *);
120 static void     jme_txeof(struct jme_softc *);
121 static void     jme_rxeof(struct jme_rxdata *, int);
122 static void     jme_rx_intr(struct jme_softc *, uint32_t);
123
124 static int      jme_msix_setup(device_t);
125 static void     jme_msix_teardown(device_t, int);
126 static int      jme_intr_setup(device_t);
127 static void     jme_intr_teardown(device_t);
128 static void     jme_msix_try_alloc(device_t);
129 static void     jme_msix_free(device_t);
130 static int      jme_intr_alloc(device_t);
131 static void     jme_intr_free(device_t);
132 static int      jme_dma_alloc(struct jme_softc *);
133 static void     jme_dma_free(struct jme_softc *);
134 static int      jme_init_rx_ring(struct jme_rxdata *);
135 static void     jme_init_tx_ring(struct jme_softc *);
136 static void     jme_init_ssb(struct jme_softc *);
137 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
138 static int      jme_encap(struct jme_softc *, struct mbuf **);
139 static void     jme_rxpkt(struct jme_rxdata *);
140 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
141 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
142 static int      jme_rxbuf_dma_filter(void *, bus_addr_t);
143
144 static void     jme_tick(void *);
145 static void     jme_stop(struct jme_softc *);
146 static void     jme_reset(struct jme_softc *);
147 static void     jme_set_msinum(struct jme_softc *);
148 static void     jme_set_vlan(struct jme_softc *);
149 static void     jme_set_filter(struct jme_softc *);
150 static void     jme_stop_tx(struct jme_softc *);
151 static void     jme_stop_rx(struct jme_softc *);
152 static void     jme_mac_config(struct jme_softc *);
153 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
154 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
155 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
156 #ifdef notyet
157 static void     jme_setwol(struct jme_softc *);
158 static void     jme_setlinkspeed(struct jme_softc *);
159 #endif
160 static void     jme_set_tx_coal(struct jme_softc *);
161 static void     jme_set_rx_coal(struct jme_softc *);
162 static void     jme_enable_rss(struct jme_softc *);
163 static void     jme_disable_rss(struct jme_softc *);
164 static void     jme_serialize_skipmain(struct jme_softc *);
165 static void     jme_deserialize_skipmain(struct jme_softc *);
166
167 static void     jme_sysctl_node(struct jme_softc *);
168 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
169 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
170 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
171 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
172
173 /*
174  * Devices supported by this driver.
175  */
176 static const struct jme_dev {
177         uint16_t        jme_vendorid;
178         uint16_t        jme_deviceid;
179         uint32_t        jme_caps;
180         const char      *jme_name;
181 } jme_devs[] = {
182         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
183             JME_CAP_JUMBO,
184             "JMicron Inc, JMC250 Gigabit Ethernet" },
185         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
186             JME_CAP_FASTETH,
187             "JMicron Inc, JMC260 Fast Ethernet" },
188         { 0, 0, 0, NULL }
189 };
190
191 static device_method_t jme_methods[] = {
192         /* Device interface. */
193         DEVMETHOD(device_probe,         jme_probe),
194         DEVMETHOD(device_attach,        jme_attach),
195         DEVMETHOD(device_detach,        jme_detach),
196         DEVMETHOD(device_shutdown,      jme_shutdown),
197         DEVMETHOD(device_suspend,       jme_suspend),
198         DEVMETHOD(device_resume,        jme_resume),
199
200         /* Bus interface. */
201         DEVMETHOD(bus_print_child,      bus_generic_print_child),
202         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
203
204         /* MII interface. */
205         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
206         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
207         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
208
209         { NULL, NULL }
210 };
211
212 static driver_t jme_driver = {
213         "jme",
214         jme_methods,
215         sizeof(struct jme_softc)
216 };
217
218 static devclass_t jme_devclass;
219
220 DECLARE_DUMMY_MODULE(if_jme);
221 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
222 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
223 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
224
225 static const struct {
226         uint32_t        jme_coal;
227         uint32_t        jme_comp;
228         uint32_t        jme_empty;
229 } jme_rx_status[JME_NRXRING_MAX] = {
230         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
231           INTR_RXQ0_DESC_EMPTY },
232         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
233           INTR_RXQ1_DESC_EMPTY },
234         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
235           INTR_RXQ2_DESC_EMPTY },
236         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
237           INTR_RXQ3_DESC_EMPTY }
238 };
239
240 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
241 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
242 static int      jme_rx_ring_count = 0;
243 static int      jme_msi_enable = 1;
244 static int      jme_msix_enable = 1;
245
246 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
247 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
248 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
249 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
250 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
251
252 static __inline void
253 jme_setup_rxdesc(struct jme_rxdesc *rxd)
254 {
255         struct jme_desc *desc;
256
257         desc = rxd->rx_desc;
258         desc->buflen = htole32(MCLBYTES);
259         desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
260         desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
261         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
262 }
263
264 /*
265  *      Read a PHY register on the MII of the JMC250.
266  */
267 static int
268 jme_miibus_readreg(device_t dev, int phy, int reg)
269 {
270         struct jme_softc *sc = device_get_softc(dev);
271         uint32_t val;
272         int i;
273
274         /* For FPGA version, PHY address 0 should be ignored. */
275         if (sc->jme_caps & JME_CAP_FPGA) {
276                 if (phy == 0)
277                         return (0);
278         } else {
279                 if (sc->jme_phyaddr != phy)
280                         return (0);
281         }
282
283         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
284             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
285
286         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
287                 DELAY(1);
288                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
289                         break;
290         }
291         if (i == 0) {
292                 device_printf(sc->jme_dev, "phy read timeout: "
293                               "phy %d, reg %d\n", phy, reg);
294                 return (0);
295         }
296
297         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
298 }
299
300 /*
301  *      Write a PHY register on the MII of the JMC250.
302  */
303 static int
304 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
305 {
306         struct jme_softc *sc = device_get_softc(dev);
307         int i;
308
309         /* For FPGA version, PHY address 0 should be ignored. */
310         if (sc->jme_caps & JME_CAP_FPGA) {
311                 if (phy == 0)
312                         return (0);
313         } else {
314                 if (sc->jme_phyaddr != phy)
315                         return (0);
316         }
317
318         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
319             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
320             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
321
322         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
323                 DELAY(1);
324                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
325                         break;
326         }
327         if (i == 0) {
328                 device_printf(sc->jme_dev, "phy write timeout: "
329                               "phy %d, reg %d\n", phy, reg);
330         }
331
332         return (0);
333 }
334
335 /*
336  *      Callback from MII layer when media changes.
337  */
338 static void
339 jme_miibus_statchg(device_t dev)
340 {
341         struct jme_softc *sc = device_get_softc(dev);
342         struct ifnet *ifp = &sc->arpcom.ac_if;
343         struct mii_data *mii;
344         struct jme_txdesc *txd;
345         bus_addr_t paddr;
346         int i, r;
347
348         if (sc->jme_in_tick)
349                 jme_serialize_skipmain(sc);
350         ASSERT_IFNET_SERIALIZED_ALL(ifp);
351
352         if ((ifp->if_flags & IFF_RUNNING) == 0)
353                 goto done;
354
355         mii = device_get_softc(sc->jme_miibus);
356
357         sc->jme_has_link = FALSE;
358         if ((mii->mii_media_status & IFM_AVALID) != 0) {
359                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
360                 case IFM_10_T:
361                 case IFM_100_TX:
362                         sc->jme_has_link = TRUE;
363                         break;
364                 case IFM_1000_T:
365                         if (sc->jme_caps & JME_CAP_FASTETH)
366                                 break;
367                         sc->jme_has_link = TRUE;
368                         break;
369                 default:
370                         break;
371                 }
372         }
373
374         /*
375          * Disabling Rx/Tx MACs have a side-effect of resetting
376          * JME_TXNDA/JME_RXNDA register to the first address of
377          * Tx/Rx descriptor address. So driver should reset its
378          * internal procucer/consumer pointer and reclaim any
379          * allocated resources.  Note, just saving the value of
380          * JME_TXNDA and JME_RXNDA registers before stopping MAC
381          * and restoring JME_TXNDA/JME_RXNDA register is not
382          * sufficient to make sure correct MAC state because
383          * stopping MAC operation can take a while and hardware
384          * might have updated JME_TXNDA/JME_RXNDA registers
385          * during the stop operation.
386          */
387
388         /* Disable interrupts */
389         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
390
391         /* Stop driver */
392         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
393         ifp->if_timer = 0;
394         callout_stop(&sc->jme_tick_ch);
395
396         /* Stop receiver/transmitter. */
397         jme_stop_rx(sc);
398         jme_stop_tx(sc);
399
400         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
401                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
402
403                 jme_rxeof(rdata, -1);
404                 if (rdata->jme_rxhead != NULL)
405                         m_freem(rdata->jme_rxhead);
406                 JME_RXCHAIN_RESET(rdata);
407
408                 /*
409                  * Reuse configured Rx descriptors and reset
410                  * procuder/consumer index.
411                  */
412                 rdata->jme_rx_cons = 0;
413         }
414         if (JME_ENABLE_HWRSS(sc))
415                 jme_enable_rss(sc);
416         else
417                 jme_disable_rss(sc);
418
419         jme_txeof(sc);
420         if (sc->jme_cdata.jme_tx_cnt != 0) {
421                 /* Remove queued packets for transmit. */
422                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
423                         txd = &sc->jme_cdata.jme_txdesc[i];
424                         if (txd->tx_m != NULL) {
425                                 bus_dmamap_unload(
426                                     sc->jme_cdata.jme_tx_tag,
427                                     txd->tx_dmamap);
428                                 m_freem(txd->tx_m);
429                                 txd->tx_m = NULL;
430                                 txd->tx_ndesc = 0;
431                                 ifp->if_oerrors++;
432                         }
433                 }
434         }
435         jme_init_tx_ring(sc);
436
437         /* Initialize shadow status block. */
438         jme_init_ssb(sc);
439
440         /* Program MAC with resolved speed/duplex/flow-control. */
441         if (sc->jme_has_link) {
442                 jme_mac_config(sc);
443
444                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
445
446                 /* Set Tx ring address to the hardware. */
447                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
448                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
449                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
450
451                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
452                         CSR_WRITE_4(sc, JME_RXCSR,
453                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
454
455                         /* Set Rx ring address to the hardware. */
456                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
457                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
458                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
459                 }
460
461                 /* Restart receiver/transmitter. */
462                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
463                     RXCSR_RXQ_START);
464                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
465         }
466
467         ifp->if_flags |= IFF_RUNNING;
468         ifp->if_flags &= ~IFF_OACTIVE;
469         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
470
471 #ifdef DEVICE_POLLING
472         if (!(ifp->if_flags & IFF_POLLING))
473 #endif
474         /* Reenable interrupts. */
475         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
476
477 done:
478         if (sc->jme_in_tick)
479                 jme_deserialize_skipmain(sc);
480 }
481
482 /*
483  *      Get the current interface media status.
484  */
485 static void
486 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
487 {
488         struct jme_softc *sc = ifp->if_softc;
489         struct mii_data *mii = device_get_softc(sc->jme_miibus);
490
491         ASSERT_IFNET_SERIALIZED_ALL(ifp);
492
493         mii_pollstat(mii);
494         ifmr->ifm_status = mii->mii_media_status;
495         ifmr->ifm_active = mii->mii_media_active;
496 }
497
498 /*
499  *      Set hardware to newly-selected media.
500  */
501 static int
502 jme_mediachange(struct ifnet *ifp)
503 {
504         struct jme_softc *sc = ifp->if_softc;
505         struct mii_data *mii = device_get_softc(sc->jme_miibus);
506         int error;
507
508         ASSERT_IFNET_SERIALIZED_ALL(ifp);
509
510         if (mii->mii_instance != 0) {
511                 struct mii_softc *miisc;
512
513                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
514                         mii_phy_reset(miisc);
515         }
516         error = mii_mediachg(mii);
517
518         return (error);
519 }
520
521 static int
522 jme_probe(device_t dev)
523 {
524         const struct jme_dev *sp;
525         uint16_t vid, did;
526
527         vid = pci_get_vendor(dev);
528         did = pci_get_device(dev);
529         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
530                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
531                         struct jme_softc *sc = device_get_softc(dev);
532
533                         sc->jme_caps = sp->jme_caps;
534                         device_set_desc(dev, sp->jme_name);
535                         return (0);
536                 }
537         }
538         return (ENXIO);
539 }
540
541 static int
542 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
543 {
544         uint32_t reg;
545         int i;
546
547         *val = 0;
548         for (i = JME_TIMEOUT; i > 0; i--) {
549                 reg = CSR_READ_4(sc, JME_SMBCSR);
550                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
551                         break;
552                 DELAY(1);
553         }
554
555         if (i == 0) {
556                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
557                 return (ETIMEDOUT);
558         }
559
560         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
561         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
562         for (i = JME_TIMEOUT; i > 0; i--) {
563                 DELAY(1);
564                 reg = CSR_READ_4(sc, JME_SMBINTF);
565                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
566                         break;
567         }
568
569         if (i == 0) {
570                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
571                 return (ETIMEDOUT);
572         }
573
574         reg = CSR_READ_4(sc, JME_SMBINTF);
575         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
576
577         return (0);
578 }
579
580 static int
581 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
582 {
583         uint8_t fup, reg, val;
584         uint32_t offset;
585         int match;
586
587         offset = 0;
588         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
589             fup != JME_EEPROM_SIG0)
590                 return (ENOENT);
591         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
592             fup != JME_EEPROM_SIG1)
593                 return (ENOENT);
594         match = 0;
595         do {
596                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
597                         break;
598                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
599                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
600                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
601                                 break;
602                         if (reg >= JME_PAR0 &&
603                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
604                                 if (jme_eeprom_read_byte(sc, offset + 2,
605                                     &val) != 0)
606                                         break;
607                                 eaddr[reg - JME_PAR0] = val;
608                                 match++;
609                         }
610                 }
611                 /* Check for the end of EEPROM descriptor. */
612                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
613                         break;
614                 /* Try next eeprom descriptor. */
615                 offset += JME_EEPROM_DESC_BYTES;
616         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
617
618         if (match == ETHER_ADDR_LEN)
619                 return (0);
620
621         return (ENOENT);
622 }
623
624 static void
625 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
626 {
627         uint32_t par0, par1;
628
629         /* Read station address. */
630         par0 = CSR_READ_4(sc, JME_PAR0);
631         par1 = CSR_READ_4(sc, JME_PAR1);
632         par1 &= 0xFFFF;
633         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
634                 device_printf(sc->jme_dev,
635                     "generating fake ethernet address.\n");
636                 par0 = karc4random();
637                 /* Set OUI to JMicron. */
638                 eaddr[0] = 0x00;
639                 eaddr[1] = 0x1B;
640                 eaddr[2] = 0x8C;
641                 eaddr[3] = (par0 >> 16) & 0xff;
642                 eaddr[4] = (par0 >> 8) & 0xff;
643                 eaddr[5] = par0 & 0xff;
644         } else {
645                 eaddr[0] = (par0 >> 0) & 0xFF;
646                 eaddr[1] = (par0 >> 8) & 0xFF;
647                 eaddr[2] = (par0 >> 16) & 0xFF;
648                 eaddr[3] = (par0 >> 24) & 0xFF;
649                 eaddr[4] = (par1 >> 0) & 0xFF;
650                 eaddr[5] = (par1 >> 8) & 0xFF;
651         }
652 }
653
654 static int
655 jme_attach(device_t dev)
656 {
657         struct jme_softc *sc = device_get_softc(dev);
658         struct ifnet *ifp = &sc->arpcom.ac_if;
659         uint32_t reg;
660         uint16_t did;
661         uint8_t pcie_ptr, rev;
662         int error = 0, i, j, rx_desc_cnt;
663         uint8_t eaddr[ETHER_ADDR_LEN];
664
665         lwkt_serialize_init(&sc->jme_serialize);
666         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
667         for (i = 0; i < JME_NRXRING_MAX; ++i) {
668                 lwkt_serialize_init(
669                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
670         }
671
672         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
673             jme_rx_desc_count);
674         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
675         if (rx_desc_cnt > JME_NDESC_MAX)
676                 rx_desc_cnt = JME_NDESC_MAX;
677
678         sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
679             jme_tx_desc_count);
680         sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
681             JME_NDESC_ALIGN);
682         if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
683                 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
684
685         /*
686          * Calculate rx rings
687          */
688         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
689             jme_rx_ring_count);
690         sc->jme_cdata.jme_rx_ring_cnt =
691             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
692
693         i = 0;
694         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
695
696         KKASSERT(i == JME_TX_SERIALIZE);
697         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
698
699         KKASSERT(i == JME_RX_SERIALIZE);
700         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
701                 sc->jme_serialize_arr[i++] =
702                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
703         }
704         KKASSERT(i <= JME_NSERIALIZE);
705         sc->jme_serialize_cnt = i;
706
707         sc->jme_cdata.jme_sc = sc;
708         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
709                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
710
711                 rdata->jme_sc = sc;
712                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
713                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
714                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
715                 rdata->jme_rx_idx = i;
716                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
717         }
718
719         sc->jme_dev = dev;
720         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
721
722         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
723
724         callout_init(&sc->jme_tick_ch);
725
726 #ifndef BURN_BRIDGES
727         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
728                 uint32_t irq, mem;
729
730                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
731                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
732
733                 device_printf(dev, "chip is in D%d power mode "
734                     "-- setting to D0\n", pci_get_powerstate(dev));
735
736                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
737
738                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
739                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
740         }
741 #endif  /* !BURN_BRIDGE */
742
743         /* Enable bus mastering */
744         pci_enable_busmaster(dev);
745
746         /*
747          * Allocate IO memory
748          *
749          * JMC250 supports both memory mapped and I/O register space
750          * access.  Because I/O register access should use different
751          * BARs to access registers it's waste of time to use I/O
752          * register spce access.  JMC250 uses 16K to map entire memory
753          * space.
754          */
755         sc->jme_mem_rid = JME_PCIR_BAR;
756         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
757                                                  &sc->jme_mem_rid, RF_ACTIVE);
758         if (sc->jme_mem_res == NULL) {
759                 device_printf(dev, "can't allocate IO memory\n");
760                 return ENXIO;
761         }
762         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
763         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
764
765         /*
766          * Allocate IRQ
767          */
768         error = jme_intr_alloc(dev);
769         if (error)
770                 goto fail;
771
772         /*
773          * Extract revisions
774          */
775         reg = CSR_READ_4(sc, JME_CHIPMODE);
776         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
777             CHIPMODE_NOT_FPGA) {
778                 sc->jme_caps |= JME_CAP_FPGA;
779                 if (bootverbose) {
780                         device_printf(dev, "FPGA revision: 0x%04x\n",
781                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
782                                       CHIPMODE_FPGA_REV_SHIFT);
783                 }
784         }
785
786         /* NOTE: FM revision is put in the upper 4 bits */
787         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
788         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
789         if (bootverbose)
790                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
791
792         did = pci_get_device(dev);
793         switch (did) {
794         case PCI_PRODUCT_JMICRON_JMC250:
795                 if (rev == JME_REV1_A2)
796                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
797                 break;
798
799         case PCI_PRODUCT_JMICRON_JMC260:
800                 if (rev == JME_REV2)
801                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
802                 break;
803
804         default:
805                 panic("unknown device id 0x%04x", did);
806         }
807         if (rev >= JME_REV2) {
808                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
809                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
810                                       GHC_TXMAC_CLKSRC_1000;
811         }
812
813         /* Reset the ethernet controller. */
814         jme_reset(sc);
815
816         /* Map MSI/MSI-X vectors */
817         jme_set_msinum(sc);
818
819         /* Get station address. */
820         reg = CSR_READ_4(sc, JME_SMBCSR);
821         if (reg & SMBCSR_EEPROM_PRESENT)
822                 error = jme_eeprom_macaddr(sc, eaddr);
823         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
824                 if (error != 0 && (bootverbose)) {
825                         device_printf(dev, "ethernet hardware address "
826                                       "not found in EEPROM.\n");
827                 }
828                 jme_reg_macaddr(sc, eaddr);
829         }
830
831         /*
832          * Save PHY address.
833          * Integrated JR0211 has fixed PHY address whereas FPGA version
834          * requires PHY probing to get correct PHY address.
835          */
836         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
837                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
838                     GPREG0_PHY_ADDR_MASK;
839                 if (bootverbose) {
840                         device_printf(dev, "PHY is at address %d.\n",
841                             sc->jme_phyaddr);
842                 }
843         } else {
844                 sc->jme_phyaddr = 0;
845         }
846
847         /* Set max allowable DMA size. */
848         pcie_ptr = pci_get_pciecap_ptr(dev);
849         if (pcie_ptr != 0) {
850                 uint16_t ctrl;
851
852                 sc->jme_caps |= JME_CAP_PCIE;
853                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
854                 if (bootverbose) {
855                         device_printf(dev, "Read request size : %d bytes.\n",
856                             128 << ((ctrl >> 12) & 0x07));
857                         device_printf(dev, "TLP payload size : %d bytes.\n",
858                             128 << ((ctrl >> 5) & 0x07));
859                 }
860                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
861                 case PCIEM_DEVCTL_MAX_READRQ_128:
862                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
863                         break;
864                 case PCIEM_DEVCTL_MAX_READRQ_256:
865                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
866                         break;
867                 default:
868                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
869                         break;
870                 }
871                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
872         } else {
873                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
874                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
875         }
876
877 #ifdef notyet
878         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
879                 sc->jme_caps |= JME_CAP_PMCAP;
880 #endif
881
882         /*
883          * Create sysctl tree
884          */
885         jme_sysctl_node(sc);
886
887         /* Allocate DMA stuffs */
888         error = jme_dma_alloc(sc);
889         if (error)
890                 goto fail;
891
892         ifp->if_softc = sc;
893         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
894         ifp->if_init = jme_init;
895         ifp->if_ioctl = jme_ioctl;
896         ifp->if_start = jme_start;
897 #ifdef DEVICE_POLLING
898         ifp->if_poll = jme_poll;
899 #endif
900         ifp->if_watchdog = jme_watchdog;
901         ifp->if_serialize = jme_serialize;
902         ifp->if_deserialize = jme_deserialize;
903         ifp->if_tryserialize = jme_tryserialize;
904 #ifdef INVARIANTS
905         ifp->if_serialize_assert = jme_serialize_assert;
906 #endif
907         ifq_set_maxlen(&ifp->if_snd,
908             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
909         ifq_set_ready(&ifp->if_snd);
910
911         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
912         ifp->if_capabilities = IFCAP_HWCSUM |
913                                IFCAP_TSO |
914                                IFCAP_VLAN_MTU |
915                                IFCAP_VLAN_HWTAGGING;
916         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
917                 ifp->if_capabilities |= IFCAP_RSS;
918         ifp->if_capenable = ifp->if_capabilities;
919
920         /*
921          * Disable TXCSUM by default to improve bulk data
922          * transmit performance (+20Mbps improvement).
923          */
924         ifp->if_capenable &= ~IFCAP_TXCSUM;
925
926         if (ifp->if_capenable & IFCAP_TXCSUM)
927                 ifp->if_hwassist |= JME_CSUM_FEATURES;
928         ifp->if_hwassist |= CSUM_TSO;
929
930         /* Set up MII bus. */
931         error = mii_phy_probe(dev, &sc->jme_miibus,
932                               jme_mediachange, jme_mediastatus);
933         if (error) {
934                 device_printf(dev, "no PHY found!\n");
935                 goto fail;
936         }
937
938         /*
939          * Save PHYADDR for FPGA mode PHY.
940          */
941         if (sc->jme_caps & JME_CAP_FPGA) {
942                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
943
944                 if (mii->mii_instance != 0) {
945                         struct mii_softc *miisc;
946
947                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948                                 if (miisc->mii_phy != 0) {
949                                         sc->jme_phyaddr = miisc->mii_phy;
950                                         break;
951                                 }
952                         }
953                         if (sc->jme_phyaddr != 0) {
954                                 device_printf(sc->jme_dev,
955                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
956                                 /* vendor magic. */
957                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
958                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
959
960                                 /* XXX should we clear JME_WA_EXTFIFO */
961                         }
962                 }
963         }
964
965         ether_ifattach(ifp, eaddr, NULL);
966
967         /* Tell the upper layer(s) we support long frames. */
968         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
969
970         error = jme_intr_setup(dev);
971         if (error) {
972                 ether_ifdetach(ifp);
973                 goto fail;
974         }
975
976         return 0;
977 fail:
978         jme_detach(dev);
979         return (error);
980 }
981
982 static int
983 jme_detach(device_t dev)
984 {
985         struct jme_softc *sc = device_get_softc(dev);
986
987         if (device_is_attached(dev)) {
988                 struct ifnet *ifp = &sc->arpcom.ac_if;
989
990                 ifnet_serialize_all(ifp);
991                 jme_stop(sc);
992                 jme_intr_teardown(dev);
993                 ifnet_deserialize_all(ifp);
994
995                 ether_ifdetach(ifp);
996         }
997
998         if (sc->jme_sysctl_tree != NULL)
999                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1000
1001         if (sc->jme_miibus != NULL)
1002                 device_delete_child(dev, sc->jme_miibus);
1003         bus_generic_detach(dev);
1004
1005         jme_intr_free(dev);
1006
1007         if (sc->jme_mem_res != NULL) {
1008                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1009                                      sc->jme_mem_res);
1010         }
1011
1012         jme_dma_free(sc);
1013
1014         return (0);
1015 }
1016
1017 static void
1018 jme_sysctl_node(struct jme_softc *sc)
1019 {
1020         int coal_max;
1021 #ifdef JME_RSS_DEBUG
1022         int r;
1023 #endif
1024
1025         sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028                                 device_get_nameunit(sc->jme_dev),
1029                                 CTLFLAG_RD, 0, "");
1030         if (sc->jme_sysctl_tree == NULL) {
1031                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1032                 return;
1033         }
1034
1035         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1039
1040         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1044
1045         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1047             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1049
1050         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1052             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1054
1055         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057                        "rx_desc_count", CTLFLAG_RD,
1058                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1059                        0, "RX desc count");
1060         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062                        "tx_desc_count", CTLFLAG_RD,
1063                        &sc->jme_cdata.jme_tx_desc_cnt,
1064                        0, "TX desc count");
1065         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1067                        "rx_ring_count", CTLFLAG_RD,
1068                        &sc->jme_cdata.jme_rx_ring_cnt,
1069                        0, "RX ring count");
1070 #ifdef JME_RSS_DEBUG
1071         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1073                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1074                        0, "RSS debug level");
1075         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076                 char rx_ring_pkt[32];
1077
1078                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1079                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1080                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1081                     rx_ring_pkt, CTLFLAG_RW,
1082                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1083         }
1084 #endif
1085
1086         /*
1087          * Set default coalesce valves
1088          */
1089         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1090         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1091         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1092         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1093
1094         /*
1095          * Adjust coalesce valves, in case that the number of TX/RX
1096          * descs are set to small values by users.
1097          *
1098          * NOTE: coal_max will not be zero, since number of descs
1099          * must aligned by JME_NDESC_ALIGN (16 currently)
1100          */
1101         coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1102         if (coal_max < sc->jme_tx_coal_pkt)
1103                 sc->jme_tx_coal_pkt = coal_max;
1104
1105         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1106         if (coal_max < sc->jme_rx_coal_pkt)
1107                 sc->jme_rx_coal_pkt = coal_max;
1108 }
1109
1110 static int
1111 jme_dma_alloc(struct jme_softc *sc)
1112 {
1113         struct jme_txdesc *txd;
1114         bus_dmamem_t dmem;
1115         int error, i, asize;
1116
1117         sc->jme_cdata.jme_txdesc =
1118         kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1119                 M_DEVBUF, M_WAITOK | M_ZERO);
1120         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1121                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1122
1123                 rdata->jme_rxdesc =
1124                 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1125                         M_DEVBUF, M_WAITOK | M_ZERO);
1126         }
1127
1128         /* Create parent ring tag. */
1129         error = bus_dma_tag_create(NULL,/* parent */
1130             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1131             sc->jme_lowaddr,            /* lowaddr */
1132             BUS_SPACE_MAXADDR,          /* highaddr */
1133             NULL, NULL,                 /* filter, filterarg */
1134             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1135             0,                          /* nsegments */
1136             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1137             0,                          /* flags */
1138             &sc->jme_cdata.jme_ring_tag);
1139         if (error) {
1140                 device_printf(sc->jme_dev,
1141                     "could not create parent ring DMA tag.\n");
1142                 return error;
1143         }
1144
1145         /*
1146          * Create DMA stuffs for TX ring
1147          */
1148         asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1149         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1150                         JME_TX_RING_ALIGN, 0,
1151                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1152                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1153         if (error) {
1154                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1155                 return error;
1156         }
1157         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1158         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1159         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1160         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1161
1162         /*
1163          * Create DMA stuffs for RX rings
1164          */
1165         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1166                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1167                 if (error)
1168                         return error;
1169         }
1170
1171         /* Create parent buffer tag. */
1172         error = bus_dma_tag_create(NULL,/* parent */
1173             1, 0,                       /* algnmnt, boundary */
1174             sc->jme_lowaddr,            /* lowaddr */
1175             BUS_SPACE_MAXADDR,          /* highaddr */
1176             NULL, NULL,                 /* filter, filterarg */
1177             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1178             0,                          /* nsegments */
1179             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1180             0,                          /* flags */
1181             &sc->jme_cdata.jme_buffer_tag);
1182         if (error) {
1183                 device_printf(sc->jme_dev,
1184                     "could not create parent buffer DMA tag.\n");
1185                 return error;
1186         }
1187
1188         /*
1189          * Create DMA stuffs for shadow status block
1190          */
1191         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1192         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1193                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1194                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1195         if (error) {
1196                 device_printf(sc->jme_dev,
1197                     "could not create shadow status block.\n");
1198                 return error;
1199         }
1200         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1201         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1202         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1203         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1204
1205         /*
1206          * Create DMA stuffs for TX buffers
1207          */
1208
1209         /* Create tag for Tx buffers. */
1210         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1211             1, 0,                       /* algnmnt, boundary */
1212             BUS_SPACE_MAXADDR,          /* lowaddr */
1213             BUS_SPACE_MAXADDR,          /* highaddr */
1214             NULL, NULL,                 /* filter, filterarg */
1215             JME_TSO_MAXSIZE,            /* maxsize */
1216             JME_MAXTXSEGS,              /* nsegments */
1217             JME_MAXSEGSIZE,             /* maxsegsize */
1218             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1219             &sc->jme_cdata.jme_tx_tag);
1220         if (error != 0) {
1221                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1222                 return error;
1223         }
1224
1225         /* Create DMA maps for Tx buffers. */
1226         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1227                 txd = &sc->jme_cdata.jme_txdesc[i];
1228                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1229                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1230                                 &txd->tx_dmamap);
1231                 if (error) {
1232                         int j;
1233
1234                         device_printf(sc->jme_dev,
1235                             "could not create %dth Tx dmamap.\n", i);
1236
1237                         for (j = 0; j < i; ++j) {
1238                                 txd = &sc->jme_cdata.jme_txdesc[j];
1239                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1240                                                    txd->tx_dmamap);
1241                         }
1242                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1243                         sc->jme_cdata.jme_tx_tag = NULL;
1244                         return error;
1245                 }
1246         }
1247
1248         /*
1249          * Create DMA stuffs for RX buffers
1250          */
1251         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1252                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1253                 if (error)
1254                         return error;
1255         }
1256         return 0;
1257 }
1258
1259 static void
1260 jme_dma_free(struct jme_softc *sc)
1261 {
1262         struct jme_txdesc *txd;
1263         struct jme_rxdesc *rxd;
1264         struct jme_rxdata *rdata;
1265         int i, r;
1266
1267         /* Tx ring */
1268         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1269                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1270                     sc->jme_cdata.jme_tx_ring_map);
1271                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1272                     sc->jme_cdata.jme_tx_ring,
1273                     sc->jme_cdata.jme_tx_ring_map);
1274                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1275                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1276         }
1277
1278         /* Rx ring */
1279         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1280                 rdata = &sc->jme_cdata.jme_rx_data[r];
1281                 if (rdata->jme_rx_ring_tag != NULL) {
1282                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1283                                           rdata->jme_rx_ring_map);
1284                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1285                                         rdata->jme_rx_ring,
1286                                         rdata->jme_rx_ring_map);
1287                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1288                         rdata->jme_rx_ring_tag = NULL;
1289                 }
1290         }
1291
1292         /* Tx buffers */
1293         if (sc->jme_cdata.jme_tx_tag != NULL) {
1294                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1295                         txd = &sc->jme_cdata.jme_txdesc[i];
1296                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1297                             txd->tx_dmamap);
1298                 }
1299                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1300                 sc->jme_cdata.jme_tx_tag = NULL;
1301         }
1302
1303         /* Rx buffers */
1304         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1305                 rdata = &sc->jme_cdata.jme_rx_data[r];
1306                 if (rdata->jme_rx_tag != NULL) {
1307                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1308                                 rxd = &rdata->jme_rxdesc[i];
1309                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1310                                                    rxd->rx_dmamap);
1311                         }
1312                         bus_dmamap_destroy(rdata->jme_rx_tag,
1313                                            rdata->jme_rx_sparemap);
1314                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1315                         rdata->jme_rx_tag = NULL;
1316                 }
1317         }
1318
1319         /* Shadow status block. */
1320         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1321                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1322                     sc->jme_cdata.jme_ssb_map);
1323                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1324                     sc->jme_cdata.jme_ssb_block,
1325                     sc->jme_cdata.jme_ssb_map);
1326                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1327                 sc->jme_cdata.jme_ssb_tag = NULL;
1328         }
1329
1330         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1331                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1332                 sc->jme_cdata.jme_buffer_tag = NULL;
1333         }
1334         if (sc->jme_cdata.jme_ring_tag != NULL) {
1335                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1336                 sc->jme_cdata.jme_ring_tag = NULL;
1337         }
1338
1339         if (sc->jme_cdata.jme_txdesc != NULL) {
1340                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1341                 sc->jme_cdata.jme_txdesc = NULL;
1342         }
1343         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1344                 rdata = &sc->jme_cdata.jme_rx_data[r];
1345                 if (rdata->jme_rxdesc != NULL) {
1346                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1347                         rdata->jme_rxdesc = NULL;
1348                 }
1349         }
1350 }
1351
1352 /*
1353  *      Make sure the interface is stopped at reboot time.
1354  */
1355 static int
1356 jme_shutdown(device_t dev)
1357 {
1358         return jme_suspend(dev);
1359 }
1360
1361 #ifdef notyet
1362 /*
1363  * Unlike other ethernet controllers, JMC250 requires
1364  * explicit resetting link speed to 10/100Mbps as gigabit
1365  * link will cunsume more power than 375mA.
1366  * Note, we reset the link speed to 10/100Mbps with
1367  * auto-negotiation but we don't know whether that operation
1368  * would succeed or not as we have no control after powering
1369  * off. If the renegotiation fail WOL may not work. Running
1370  * at 1Gbps draws more power than 375mA at 3.3V which is
1371  * specified in PCI specification and that would result in
1372  * complete shutdowning power to ethernet controller.
1373  *
1374  * TODO
1375  *  Save current negotiated media speed/duplex/flow-control
1376  *  to softc and restore the same link again after resuming.
1377  *  PHY handling such as power down/resetting to 100Mbps
1378  *  may be better handled in suspend method in phy driver.
1379  */
1380 static void
1381 jme_setlinkspeed(struct jme_softc *sc)
1382 {
1383         struct mii_data *mii;
1384         int aneg, i;
1385
1386         JME_LOCK_ASSERT(sc);
1387
1388         mii = device_get_softc(sc->jme_miibus);
1389         mii_pollstat(mii);
1390         aneg = 0;
1391         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1392                 switch IFM_SUBTYPE(mii->mii_media_active) {
1393                 case IFM_10_T:
1394                 case IFM_100_TX:
1395                         return;
1396                 case IFM_1000_T:
1397                         aneg++;
1398                 default:
1399                         break;
1400                 }
1401         }
1402         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1403         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1404             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1405         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1406             BMCR_AUTOEN | BMCR_STARTNEG);
1407         DELAY(1000);
1408         if (aneg != 0) {
1409                 /* Poll link state until jme(4) get a 10/100 link. */
1410                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1411                         mii_pollstat(mii);
1412                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1413                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1414                                 case IFM_10_T:
1415                                 case IFM_100_TX:
1416                                         jme_mac_config(sc);
1417                                         return;
1418                                 default:
1419                                         break;
1420                                 }
1421                         }
1422                         JME_UNLOCK(sc);
1423                         pause("jmelnk", hz);
1424                         JME_LOCK(sc);
1425                 }
1426                 if (i == MII_ANEGTICKS_GIGE)
1427                         device_printf(sc->jme_dev, "establishing link failed, "
1428                             "WOL may not work!");
1429         }
1430         /*
1431          * No link, force MAC to have 100Mbps, full-duplex link.
1432          * This is the last resort and may/may not work.
1433          */
1434         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1435         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1436         jme_mac_config(sc);
1437 }
1438
1439 static void
1440 jme_setwol(struct jme_softc *sc)
1441 {
1442         struct ifnet *ifp = &sc->arpcom.ac_if;
1443         uint32_t gpr, pmcs;
1444         uint16_t pmstat;
1445         int pmc;
1446
1447         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1448                 /* No PME capability, PHY power down. */
1449                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1450                     MII_BMCR, BMCR_PDOWN);
1451                 return;
1452         }
1453
1454         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1455         pmcs = CSR_READ_4(sc, JME_PMCS);
1456         pmcs &= ~PMCS_WOL_ENB_MASK;
1457         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1458                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1459                 /* Enable PME message. */
1460                 gpr |= GPREG0_PME_ENB;
1461                 /* For gigabit controllers, reset link speed to 10/100. */
1462                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1463                         jme_setlinkspeed(sc);
1464         }
1465
1466         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1467         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1468
1469         /* Request PME. */
1470         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1471         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1472         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1473                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1474         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1475         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1476                 /* No WOL, PHY power down. */
1477                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1478                     MII_BMCR, BMCR_PDOWN);
1479         }
1480 }
1481 #endif
1482
1483 static int
1484 jme_suspend(device_t dev)
1485 {
1486         struct jme_softc *sc = device_get_softc(dev);
1487         struct ifnet *ifp = &sc->arpcom.ac_if;
1488
1489         ifnet_serialize_all(ifp);
1490         jme_stop(sc);
1491 #ifdef notyet
1492         jme_setwol(sc);
1493 #endif
1494         ifnet_deserialize_all(ifp);
1495
1496         return (0);
1497 }
1498
1499 static int
1500 jme_resume(device_t dev)
1501 {
1502         struct jme_softc *sc = device_get_softc(dev);
1503         struct ifnet *ifp = &sc->arpcom.ac_if;
1504 #ifdef notyet
1505         int pmc;
1506 #endif
1507
1508         ifnet_serialize_all(ifp);
1509
1510 #ifdef notyet
1511         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1512                 uint16_t pmstat;
1513
1514                 pmstat = pci_read_config(sc->jme_dev,
1515                     pmc + PCIR_POWER_STATUS, 2);
1516                 /* Disable PME clear PME status. */
1517                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1518                 pci_write_config(sc->jme_dev,
1519                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1520         }
1521 #endif
1522
1523         if (ifp->if_flags & IFF_UP)
1524                 jme_init(sc);
1525
1526         ifnet_deserialize_all(ifp);
1527
1528         return (0);
1529 }
1530
1531 static __inline int
1532 jme_tso_pullup(struct mbuf **mp)
1533 {
1534         int hoff, iphlen, thoff;
1535         struct mbuf *m;
1536
1537         m = *mp;
1538         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1539
1540         iphlen = m->m_pkthdr.csum_iphlen;
1541         thoff = m->m_pkthdr.csum_thlen;
1542         hoff = m->m_pkthdr.csum_lhlen;
1543
1544         KASSERT(iphlen > 0, ("invalid ip hlen"));
1545         KASSERT(thoff > 0, ("invalid tcp hlen"));
1546         KASSERT(hoff > 0, ("invalid ether hlen"));
1547
1548         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1549                 m = m_pullup(m, hoff + iphlen + thoff);
1550                 if (m == NULL) {
1551                         *mp = NULL;
1552                         return ENOBUFS;
1553                 }
1554                 *mp = m;
1555         }
1556         return 0;
1557 }
1558
1559 static int
1560 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1561 {
1562         struct jme_txdesc *txd;
1563         struct jme_desc *desc;
1564         struct mbuf *m;
1565         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1566         int maxsegs, nsegs;
1567         int error, i, prod, symbol_desc;
1568         uint32_t cflags, flag64, mss;
1569
1570         M_ASSERTPKTHDR((*m_head));
1571
1572         if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1573                 /* XXX Is this necessary? */
1574                 error = jme_tso_pullup(m_head);
1575                 if (error)
1576                         return error;
1577         }
1578
1579         prod = sc->jme_cdata.jme_tx_prod;
1580         txd = &sc->jme_cdata.jme_txdesc[prod];
1581
1582         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1583                 symbol_desc = 1;
1584         else
1585                 symbol_desc = 0;
1586
1587         maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1588                   (JME_TXD_RSVD + symbol_desc);
1589         if (maxsegs > JME_MAXTXSEGS)
1590                 maxsegs = JME_MAXTXSEGS;
1591         KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
1592                 ("not enough segments %d", maxsegs));
1593
1594         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1595                         txd->tx_dmamap, m_head,
1596                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1597         if (error)
1598                 goto fail;
1599
1600         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1601                         BUS_DMASYNC_PREWRITE);
1602
1603         m = *m_head;
1604         cflags = 0;
1605         mss = 0;
1606
1607         /* Configure checksum offload. */
1608         if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1609                 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1610                 cflags |= JME_TD_TSO;
1611         } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1612                 if (m->m_pkthdr.csum_flags & CSUM_IP)
1613                         cflags |= JME_TD_IPCSUM;
1614                 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1615                         cflags |= JME_TD_TCPCSUM;
1616                 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1617                         cflags |= JME_TD_UDPCSUM;
1618         }
1619
1620         /* Configure VLAN. */
1621         if (m->m_flags & M_VLANTAG) {
1622                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1623                 cflags |= JME_TD_VLAN_TAG;
1624         }
1625
1626         desc = &sc->jme_cdata.jme_tx_ring[prod];
1627         desc->flags = htole32(cflags);
1628         desc->addr_hi = htole32(m->m_pkthdr.len);
1629         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1630                 /*
1631                  * Use 64bits TX desc chain format.
1632                  *
1633                  * The first TX desc of the chain, which is setup here,
1634                  * is just a symbol TX desc carrying no payload.
1635                  */
1636                 flag64 = JME_TD_64BIT;
1637                 desc->buflen = htole32(mss);
1638                 desc->addr_lo = 0;
1639
1640                 /* No effective TX desc is consumed */
1641                 i = 0;
1642         } else {
1643                 /*
1644                  * Use 32bits TX desc chain format.
1645                  *
1646                  * The first TX desc of the chain, which is setup here,
1647                  * is an effective TX desc carrying the first segment of
1648                  * the mbuf chain.
1649                  */
1650                 flag64 = 0;
1651                 desc->buflen = htole32(mss | txsegs[0].ds_len);
1652                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1653
1654                 /* One effective TX desc is consumed */
1655                 i = 1;
1656         }
1657         sc->jme_cdata.jme_tx_cnt++;
1658         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1659                  sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1660         JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1661
1662         txd->tx_ndesc = 1 - i;
1663         for (; i < nsegs; i++) {
1664                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1665                 desc->buflen = htole32(txsegs[i].ds_len);
1666                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1667                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1668                 desc->flags = htole32(JME_TD_OWN | flag64);
1669
1670                 sc->jme_cdata.jme_tx_cnt++;
1671                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1672                          sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1673                 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1674         }
1675
1676         /* Update producer index. */
1677         sc->jme_cdata.jme_tx_prod = prod;
1678         /*
1679          * Finally request interrupt and give the first descriptor
1680          * owenership to hardware.
1681          */
1682         desc = txd->tx_desc;
1683         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1684
1685         txd->tx_m = m;
1686         txd->tx_ndesc += nsegs;
1687
1688         return 0;
1689 fail:
1690         m_freem(*m_head);
1691         *m_head = NULL;
1692         return error;
1693 }
1694
1695 static void
1696 jme_start(struct ifnet *ifp)
1697 {
1698         struct jme_softc *sc = ifp->if_softc;
1699         struct mbuf *m_head;
1700         int enq = 0;
1701
1702         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1703
1704         if (!sc->jme_has_link) {
1705                 ifq_purge(&ifp->if_snd);
1706                 return;
1707         }
1708
1709         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1710                 return;
1711
1712         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1713                 jme_txeof(sc);
1714
1715         while (!ifq_is_empty(&ifp->if_snd)) {
1716                 /*
1717                  * Check number of available TX descs, always
1718                  * leave JME_TXD_RSVD free TX descs.
1719                  */
1720                 if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE >
1721                     sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1722                         ifp->if_flags |= IFF_OACTIVE;
1723                         break;
1724                 }
1725
1726                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1727                 if (m_head == NULL)
1728                         break;
1729
1730                 /*
1731                  * Pack the data into the transmit ring. If we
1732                  * don't have room, set the OACTIVE flag and wait
1733                  * for the NIC to drain the ring.
1734                  */
1735                 if (jme_encap(sc, &m_head)) {
1736                         KKASSERT(m_head == NULL);
1737                         ifp->if_oerrors++;
1738                         ifp->if_flags |= IFF_OACTIVE;
1739                         break;
1740                 }
1741                 enq++;
1742
1743                 /*
1744                  * If there's a BPF listener, bounce a copy of this frame
1745                  * to him.
1746                  */
1747                 ETHER_BPF_MTAP(ifp, m_head);
1748         }
1749
1750         if (enq > 0) {
1751                 /*
1752                  * Reading TXCSR takes very long time under heavy load
1753                  * so cache TXCSR value and writes the ORed value with
1754                  * the kick command to the TXCSR. This saves one register
1755                  * access cycle.
1756                  */
1757                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1758                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1759                 /* Set a timeout in case the chip goes out to lunch. */
1760                 ifp->if_timer = JME_TX_TIMEOUT;
1761         }
1762 }
1763
1764 static void
1765 jme_watchdog(struct ifnet *ifp)
1766 {
1767         struct jme_softc *sc = ifp->if_softc;
1768
1769         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1770
1771         if (!sc->jme_has_link) {
1772                 if_printf(ifp, "watchdog timeout (missed link)\n");
1773                 ifp->if_oerrors++;
1774                 jme_init(sc);
1775                 return;
1776         }
1777
1778         jme_txeof(sc);
1779         if (sc->jme_cdata.jme_tx_cnt == 0) {
1780                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1781                           "-- recovering\n");
1782                 if (!ifq_is_empty(&ifp->if_snd))
1783                         if_devstart(ifp);
1784                 return;
1785         }
1786
1787         if_printf(ifp, "watchdog timeout\n");
1788         ifp->if_oerrors++;
1789         jme_init(sc);
1790         if (!ifq_is_empty(&ifp->if_snd))
1791                 if_devstart(ifp);
1792 }
1793
1794 static int
1795 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1796 {
1797         struct jme_softc *sc = ifp->if_softc;
1798         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1799         struct ifreq *ifr = (struct ifreq *)data;
1800         int error = 0, mask;
1801
1802         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1803
1804         switch (cmd) {
1805         case SIOCSIFMTU:
1806                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1807                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1808                      ifr->ifr_mtu > JME_MAX_MTU)) {
1809                         error = EINVAL;
1810                         break;
1811                 }
1812
1813                 if (ifp->if_mtu != ifr->ifr_mtu) {
1814                         /*
1815                          * No special configuration is required when interface
1816                          * MTU is changed but availability of Tx checksum
1817                          * offload should be chcked against new MTU size as
1818                          * FIFO size is just 2K.
1819                          */
1820                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1821                                 ifp->if_capenable &=
1822                                     ~(IFCAP_TXCSUM | IFCAP_TSO);
1823                                 ifp->if_hwassist &=
1824                                     ~(JME_CSUM_FEATURES | CSUM_TSO);
1825                         }
1826                         ifp->if_mtu = ifr->ifr_mtu;
1827                         if (ifp->if_flags & IFF_RUNNING)
1828                                 jme_init(sc);
1829                 }
1830                 break;
1831
1832         case SIOCSIFFLAGS:
1833                 if (ifp->if_flags & IFF_UP) {
1834                         if (ifp->if_flags & IFF_RUNNING) {
1835                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1836                                     (IFF_PROMISC | IFF_ALLMULTI))
1837                                         jme_set_filter(sc);
1838                         } else {
1839                                 jme_init(sc);
1840                         }
1841                 } else {
1842                         if (ifp->if_flags & IFF_RUNNING)
1843                                 jme_stop(sc);
1844                 }
1845                 sc->jme_if_flags = ifp->if_flags;
1846                 break;
1847
1848         case SIOCADDMULTI:
1849         case SIOCDELMULTI:
1850                 if (ifp->if_flags & IFF_RUNNING)
1851                         jme_set_filter(sc);
1852                 break;
1853
1854         case SIOCSIFMEDIA:
1855         case SIOCGIFMEDIA:
1856                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1857                 break;
1858
1859         case SIOCSIFCAP:
1860                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1861
1862                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1863                         ifp->if_capenable ^= IFCAP_TXCSUM;
1864                         if (ifp->if_capenable & IFCAP_TXCSUM)
1865                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1866                         else
1867                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1868                 }
1869                 if (mask & IFCAP_RXCSUM) {
1870                         uint32_t reg;
1871
1872                         ifp->if_capenable ^= IFCAP_RXCSUM;
1873                         reg = CSR_READ_4(sc, JME_RXMAC);
1874                         reg &= ~RXMAC_CSUM_ENB;
1875                         if (ifp->if_capenable & IFCAP_RXCSUM)
1876                                 reg |= RXMAC_CSUM_ENB;
1877                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1878                 }
1879
1880                 if (mask & IFCAP_VLAN_HWTAGGING) {
1881                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1882                         jme_set_vlan(sc);
1883                 }
1884
1885                 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1886                         ifp->if_capenable ^= IFCAP_TSO;
1887                         if (ifp->if_capenable & IFCAP_TSO)
1888                                 ifp->if_hwassist |= CSUM_TSO;
1889                         else
1890                                 ifp->if_hwassist &= ~CSUM_TSO;
1891                 }
1892
1893                 if (mask & IFCAP_RSS)
1894                         ifp->if_capenable ^= IFCAP_RSS;
1895                 break;
1896
1897         default:
1898                 error = ether_ioctl(ifp, cmd, data);
1899                 break;
1900         }
1901         return (error);
1902 }
1903
1904 static void
1905 jme_mac_config(struct jme_softc *sc)
1906 {
1907         struct mii_data *mii;
1908         uint32_t ghc, rxmac, txmac, txpause, gp1;
1909         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1910
1911         mii = device_get_softc(sc->jme_miibus);
1912
1913         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1914         DELAY(10);
1915         CSR_WRITE_4(sc, JME_GHC, 0);
1916         ghc = 0;
1917         rxmac = CSR_READ_4(sc, JME_RXMAC);
1918         rxmac &= ~RXMAC_FC_ENB;
1919         txmac = CSR_READ_4(sc, JME_TXMAC);
1920         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1921         txpause = CSR_READ_4(sc, JME_TXPFC);
1922         txpause &= ~TXPFC_PAUSE_ENB;
1923         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1924                 ghc |= GHC_FULL_DUPLEX;
1925                 rxmac &= ~RXMAC_COLL_DET_ENB;
1926                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1927                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1928                     TXMAC_FRAME_BURST);
1929 #ifdef notyet
1930                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1931                         txpause |= TXPFC_PAUSE_ENB;
1932                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1933                         rxmac |= RXMAC_FC_ENB;
1934 #endif
1935                 /* Disable retry transmit timer/retry limit. */
1936                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1937                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1938         } else {
1939                 rxmac |= RXMAC_COLL_DET_ENB;
1940                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1941                 /* Enable retry transmit timer/retry limit. */
1942                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1943                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1944         }
1945
1946         /*
1947          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1948          */
1949         gp1 = CSR_READ_4(sc, JME_GPREG1);
1950         gp1 &= ~GPREG1_WA_HDX;
1951
1952         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1953                 hdx = 1;
1954
1955         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1956         case IFM_10_T:
1957                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1958                 if (hdx)
1959                         gp1 |= GPREG1_WA_HDX;
1960                 break;
1961
1962         case IFM_100_TX:
1963                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1964                 if (hdx)
1965                         gp1 |= GPREG1_WA_HDX;
1966
1967                 /*
1968                  * Use extended FIFO depth to workaround CRC errors
1969                  * emitted by chips before JMC250B
1970                  */
1971                 phyconf = JMPHY_CONF_EXTFIFO;
1972                 break;
1973
1974         case IFM_1000_T:
1975                 if (sc->jme_caps & JME_CAP_FASTETH)
1976                         break;
1977
1978                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1979                 if (hdx)
1980                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1981                 break;
1982
1983         default:
1984                 break;
1985         }
1986         CSR_WRITE_4(sc, JME_GHC, ghc);
1987         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1988         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1989         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1990
1991         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1992                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1993                                     JMPHY_CONF, phyconf);
1994         }
1995         if (sc->jme_workaround & JME_WA_HDX)
1996                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1997 }
1998
1999 static void
2000 jme_intr(void *xsc)
2001 {
2002         struct jme_softc *sc = xsc;
2003         struct ifnet *ifp = &sc->arpcom.ac_if;
2004         uint32_t status;
2005         int r;
2006
2007         ASSERT_SERIALIZED(&sc->jme_serialize);
2008
2009         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2010         if (status == 0 || status == 0xFFFFFFFF)
2011                 return;
2012
2013         /* Disable interrupts. */
2014         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2015
2016         status = CSR_READ_4(sc, JME_INTR_STATUS);
2017         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2018                 goto back;
2019
2020         /* Reset PCC counter/timer and Ack interrupts. */
2021         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2022
2023         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2024                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2025
2026         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2027                 if (status & jme_rx_status[r].jme_coal) {
2028                         status |= jme_rx_status[r].jme_coal |
2029                                   jme_rx_status[r].jme_comp;
2030                 }
2031         }
2032
2033         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2034
2035         if (ifp->if_flags & IFF_RUNNING) {
2036                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2037                         jme_rx_intr(sc, status);
2038
2039                 if (status & INTR_RXQ_DESC_EMPTY) {
2040                         /*
2041                          * Notify hardware availability of new Rx buffers.
2042                          * Reading RXCSR takes very long time under heavy
2043                          * load so cache RXCSR value and writes the ORed
2044                          * value with the kick command to the RXCSR. This
2045                          * saves one register access cycle.
2046                          */
2047                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2048                             RXCSR_RX_ENB | RXCSR_RXQ_START);
2049                 }
2050
2051                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2052                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
2053                         jme_txeof(sc);
2054                         if (!ifq_is_empty(&ifp->if_snd))
2055                                 if_devstart(ifp);
2056                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
2057                 }
2058         }
2059 back:
2060         /* Reenable interrupts. */
2061         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2062 }
2063
2064 static void
2065 jme_txeof(struct jme_softc *sc)
2066 {
2067         struct ifnet *ifp = &sc->arpcom.ac_if;
2068         int cons;
2069
2070         cons = sc->jme_cdata.jme_tx_cons;
2071         if (cons == sc->jme_cdata.jme_tx_prod)
2072                 return;
2073
2074         /*
2075          * Go through our Tx list and free mbufs for those
2076          * frames which have been transmitted.
2077          */
2078         while (cons != sc->jme_cdata.jme_tx_prod) {
2079                 struct jme_txdesc *txd, *next_txd;
2080                 uint32_t status, next_status;
2081                 int next_cons, nsegs;
2082
2083                 txd = &sc->jme_cdata.jme_txdesc[cons];
2084                 KASSERT(txd->tx_m != NULL,
2085                         ("%s: freeing NULL mbuf!", __func__));
2086
2087                 status = le32toh(txd->tx_desc->flags);
2088                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2089                         break;
2090
2091                 /*
2092                  * NOTE:
2093                  * This chip will always update the TX descriptor's
2094                  * buflen field and this updating always happens
2095                  * after clearing the OWN bit, so even if the OWN
2096                  * bit is cleared by the chip, we still don't sure
2097                  * about whether the buflen field has been updated
2098                  * by the chip or not.  To avoid this race, we wait
2099                  * for the next TX descriptor's OWN bit to be cleared
2100                  * by the chip before reusing this TX descriptor.
2101                  */
2102                 next_cons = cons;
2103                 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2104                     sc->jme_cdata.jme_tx_desc_cnt);
2105                 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2106                 if (next_txd->tx_m == NULL)
2107                         break;
2108                 next_status = le32toh(next_txd->tx_desc->flags);
2109                 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2110                         break;
2111
2112                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2113                         ifp->if_oerrors++;
2114                 } else {
2115                         ifp->if_opackets++;
2116                         if (status & JME_TD_COLLISION) {
2117                                 ifp->if_collisions +=
2118                                     le32toh(txd->tx_desc->buflen) &
2119                                     JME_TD_BUF_LEN_MASK;
2120                         }
2121                 }
2122
2123                 /*
2124                  * Only the first descriptor of multi-descriptor
2125                  * transmission is updated so driver have to skip entire
2126                  * chained buffers for the transmiited frame. In other
2127                  * words, JME_TD_OWN bit is valid only at the first
2128                  * descriptor of a multi-descriptor transmission.
2129                  */
2130                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2131                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2132                         JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2133                 }
2134
2135                 /* Reclaim transferred mbufs. */
2136                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2137                 m_freem(txd->tx_m);
2138                 txd->tx_m = NULL;
2139                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2140                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2141                         ("%s: Active Tx desc counter was garbled", __func__));
2142                 txd->tx_ndesc = 0;
2143         }
2144         sc->jme_cdata.jme_tx_cons = cons;
2145
2146         /* 1 for symbol TX descriptor */
2147         if (sc->jme_cdata.jme_tx_cnt <= JME_MAXTXSEGS + 1)
2148                 ifp->if_timer = 0;
2149
2150         if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE <=
2151             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2152                 ifp->if_flags &= ~IFF_OACTIVE;
2153 }
2154
2155 static __inline void
2156 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2157 {
2158         int i;
2159
2160         for (i = 0; i < count; ++i) {
2161                 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2162                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2163         }
2164 }
2165
2166 static __inline struct pktinfo *
2167 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2168 {
2169         if (flags & JME_RD_IPV4)
2170                 pi->pi_netisr = NETISR_IP;
2171         else if (flags & JME_RD_IPV6)
2172                 pi->pi_netisr = NETISR_IPV6;
2173         else
2174                 return NULL;
2175
2176         pi->pi_flags = 0;
2177         pi->pi_l3proto = IPPROTO_UNKNOWN;
2178
2179         if (flags & JME_RD_MORE_FRAG)
2180                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2181         else if (flags & JME_RD_TCP)
2182                 pi->pi_l3proto = IPPROTO_TCP;
2183         else if (flags & JME_RD_UDP)
2184                 pi->pi_l3proto = IPPROTO_UDP;
2185         else
2186                 pi = NULL;
2187         return pi;
2188 }
2189
2190 /* Receive a frame. */
2191 static void
2192 jme_rxpkt(struct jme_rxdata *rdata)
2193 {
2194         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2195         struct jme_desc *desc;
2196         struct jme_rxdesc *rxd;
2197         struct mbuf *mp, *m;
2198         uint32_t flags, status, hash, hashinfo;
2199         int cons, count, nsegs;
2200
2201         cons = rdata->jme_rx_cons;
2202         desc = &rdata->jme_rx_ring[cons];
2203
2204         flags = le32toh(desc->flags);
2205         status = le32toh(desc->buflen);
2206         hash = le32toh(desc->addr_hi);
2207         hashinfo = le32toh(desc->addr_lo);
2208         nsegs = JME_RX_NSEGS(status);
2209
2210         if (nsegs > 1) {
2211                 /* Skip the first descriptor. */
2212                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2213
2214                 /*
2215                  * Clear the OWN bit of the following RX descriptors;
2216                  * hardware will not clear the OWN bit except the first
2217                  * RX descriptor.
2218                  *
2219                  * Since the first RX descriptor is setup, i.e. OWN bit
2220                  * on, before its followins RX descriptors, leaving the
2221                  * OWN bit on the following RX descriptors will trick
2222                  * the hardware into thinking that the following RX
2223                  * descriptors are ready to be used too.
2224                  */
2225                 for (count = 1; count < nsegs; count++,
2226                      JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2227                         rdata->jme_rx_ring[cons].flags = 0;
2228
2229                 cons = rdata->jme_rx_cons;
2230         }
2231
2232         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2233                         "hash 0x%08x, hash info 0x%08x\n",
2234                         rdata->jme_rx_idx, flags, hash, hashinfo);
2235
2236         if (status & JME_RX_ERR_STAT) {
2237                 ifp->if_ierrors++;
2238                 jme_discard_rxbufs(rdata, cons, nsegs);
2239 #ifdef JME_SHOW_ERRORS
2240                 if_printf(ifp, "%s : receive error = 0x%b\n",
2241                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2242 #endif
2243                 rdata->jme_rx_cons += nsegs;
2244                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2245                 return;
2246         }
2247
2248         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2249         for (count = 0; count < nsegs; count++,
2250              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2251                 rxd = &rdata->jme_rxdesc[cons];
2252                 mp = rxd->rx_m;
2253
2254                 /* Add a new receive buffer to the ring. */
2255                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2256                         ifp->if_iqdrops++;
2257                         /* Reuse buffer. */
2258                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2259                         if (rdata->jme_rxhead != NULL) {
2260                                 m_freem(rdata->jme_rxhead);
2261                                 JME_RXCHAIN_RESET(rdata);
2262                         }
2263                         break;
2264                 }
2265
2266                 /*
2267                  * Assume we've received a full sized frame.
2268                  * Actual size is fixed when we encounter the end of
2269                  * multi-segmented frame.
2270                  */
2271                 mp->m_len = MCLBYTES;
2272
2273                 /* Chain received mbufs. */
2274                 if (rdata->jme_rxhead == NULL) {
2275                         rdata->jme_rxhead = mp;
2276                         rdata->jme_rxtail = mp;
2277                 } else {
2278                         /*
2279                          * Receive processor can receive a maximum frame
2280                          * size of 65535 bytes.
2281                          */
2282                         rdata->jme_rxtail->m_next = mp;
2283                         rdata->jme_rxtail = mp;
2284                 }
2285
2286                 if (count == nsegs - 1) {
2287                         struct pktinfo pi0, *pi;
2288
2289                         /* Last desc. for this frame. */
2290                         m = rdata->jme_rxhead;
2291                         m->m_pkthdr.len = rdata->jme_rxlen;
2292                         if (nsegs > 1) {
2293                                 /* Set first mbuf size. */
2294                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2295                                 /* Set last mbuf size. */
2296                                 mp->m_len = rdata->jme_rxlen -
2297                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2298                                     (MCLBYTES * (nsegs - 2)));
2299                         } else {
2300                                 m->m_len = rdata->jme_rxlen;
2301                         }
2302                         m->m_pkthdr.rcvif = ifp;
2303
2304                         /*
2305                          * Account for 10bytes auto padding which is used
2306                          * to align IP header on 32bit boundary. Also note,
2307                          * CRC bytes is automatically removed by the
2308                          * hardware.
2309                          */
2310                         m->m_data += JME_RX_PAD_BYTES;
2311
2312                         /* Set checksum information. */
2313                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2314                             (flags & JME_RD_IPV4)) {
2315                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2316                                 if (flags & JME_RD_IPCSUM)
2317                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2318                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2319                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2320                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2321                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2322                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2323                                         m->m_pkthdr.csum_flags |=
2324                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2325                                         m->m_pkthdr.csum_data = 0xffff;
2326                                 }
2327                         }
2328
2329                         /* Check for VLAN tagged packets. */
2330                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2331                             (flags & JME_RD_VLAN_TAG)) {
2332                                 m->m_pkthdr.ether_vlantag =
2333                                     flags & JME_RD_VLAN_MASK;
2334                                 m->m_flags |= M_VLANTAG;
2335                         }
2336
2337                         ifp->if_ipackets++;
2338
2339                         if (ifp->if_capenable & IFCAP_RSS)
2340                                 pi = jme_pktinfo(&pi0, flags);
2341                         else
2342                                 pi = NULL;
2343
2344                         if (pi != NULL &&
2345                             (hashinfo & JME_RD_HASH_FN_MASK) ==
2346                             JME_RD_HASH_FN_TOEPLITZ) {
2347                                 m->m_flags |= (M_HASH | M_CKHASH);
2348                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2349                         }
2350
2351 #ifdef JME_RSS_DEBUG
2352                         if (pi != NULL) {
2353                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2354                                     "isr %d flags %08x, l3 %d %s\n",
2355                                     pi->pi_netisr, pi->pi_flags,
2356                                     pi->pi_l3proto,
2357                                     (m->m_flags & M_HASH) ? "hash" : "");
2358                         }
2359 #endif
2360
2361                         /* Pass it on. */
2362                         ether_input_pkt(ifp, m, pi);
2363
2364                         /* Reset mbuf chains. */
2365                         JME_RXCHAIN_RESET(rdata);
2366 #ifdef JME_RSS_DEBUG
2367                         rdata->jme_rx_pkt++;
2368 #endif
2369                 }
2370         }
2371
2372         rdata->jme_rx_cons += nsegs;
2373         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2374 }
2375
2376 static void
2377 jme_rxeof(struct jme_rxdata *rdata, int count)
2378 {
2379         struct jme_desc *desc;
2380         int nsegs, pktlen;
2381
2382         for (;;) {
2383 #ifdef DEVICE_POLLING
2384                 if (count >= 0 && count-- == 0)
2385                         break;
2386 #endif
2387                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2388                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2389                         break;
2390                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2391                         break;
2392
2393                 /*
2394                  * Check number of segments against received bytes.
2395                  * Non-matching value would indicate that hardware
2396                  * is still trying to update Rx descriptors. I'm not
2397                  * sure whether this check is needed.
2398                  */
2399                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2400                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2401                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2402                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2403                             "RX fragment count(%d) and "
2404                             "packet size(%d) mismach\n", nsegs, pktlen);
2405                         break;
2406                 }
2407
2408                 /*
2409                  * NOTE:
2410                  * RSS hash and hash information may _not_ be set by the
2411                  * hardware even if the OWN bit is cleared and VALID bit
2412                  * is set.
2413                  *
2414                  * If the RSS information is not delivered by the hardware
2415                  * yet, we MUST NOT accept this packet, let alone reusing
2416                  * its RX descriptor.  If this packet was accepted and its
2417                  * RX descriptor was reused before hardware delivering the
2418                  * RSS information, the RX buffer's address would be trashed
2419                  * by the RSS information delivered by the hardware.
2420                  */
2421                 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2422                         struct jme_rxdesc *rxd;
2423                         uint32_t hashinfo;
2424
2425                         hashinfo = le32toh(desc->addr_lo);
2426                         rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2427
2428                         /*
2429                          * This test should be enough to detect the pending
2430                          * RSS information delivery, given:
2431                          * - If RSS hash is not calculated, the hashinfo
2432                          *   will be 0.  Howvever, the lower 32bits of RX
2433                          *   buffers' physical address will never be 0.
2434                          *   (see jme_rxbuf_dma_filter)
2435                          * - If RSS hash is calculated, the lowest 4 bits
2436                          *   of hashinfo will be set, while the RX buffers
2437                          *   are at least 2K aligned.
2438                          */
2439                         if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2440 #ifdef JME_SHOW_RSSWB
2441                                 if_printf(&rdata->jme_sc->arpcom.ac_if,
2442                                     "RSS is not written back yet\n");
2443 #endif
2444                                 break;
2445                         }
2446                 }
2447
2448                 /* Received a frame. */
2449                 jme_rxpkt(rdata);
2450         }
2451 }
2452
2453 static void
2454 jme_tick(void *xsc)
2455 {
2456         struct jme_softc *sc = xsc;
2457         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2458
2459         lwkt_serialize_enter(&sc->jme_serialize);
2460
2461         sc->jme_in_tick = TRUE;
2462         mii_tick(mii);
2463         sc->jme_in_tick = FALSE;
2464
2465         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2466
2467         lwkt_serialize_exit(&sc->jme_serialize);
2468 }
2469
2470 static void
2471 jme_reset(struct jme_softc *sc)
2472 {
2473         uint32_t val;
2474
2475         /* Make sure that TX and RX are stopped */
2476         jme_stop_tx(sc);
2477         jme_stop_rx(sc);
2478
2479         /* Start reset */
2480         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2481         DELAY(20);
2482
2483         /*
2484          * Hold reset bit before stop reset
2485          */
2486
2487         /* Disable TXMAC and TXOFL clock sources */
2488         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2489         /* Disable RXMAC clock source */
2490         val = CSR_READ_4(sc, JME_GPREG1);
2491         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2492         /* Flush */
2493         CSR_READ_4(sc, JME_GHC);
2494
2495         /* Stop reset */
2496         CSR_WRITE_4(sc, JME_GHC, 0);
2497         /* Flush */
2498         CSR_READ_4(sc, JME_GHC);
2499
2500         /*
2501          * Clear reset bit after stop reset
2502          */
2503
2504         /* Enable TXMAC and TXOFL clock sources */
2505         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2506         /* Enable RXMAC clock source */
2507         val = CSR_READ_4(sc, JME_GPREG1);
2508         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2509         /* Flush */
2510         CSR_READ_4(sc, JME_GHC);
2511
2512         /* Disable TXMAC and TXOFL clock sources */
2513         CSR_WRITE_4(sc, JME_GHC, 0);
2514         /* Disable RXMAC clock source */
2515         val = CSR_READ_4(sc, JME_GPREG1);
2516         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2517         /* Flush */
2518         CSR_READ_4(sc, JME_GHC);
2519
2520         /* Enable TX and RX */
2521         val = CSR_READ_4(sc, JME_TXCSR);
2522         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2523         val = CSR_READ_4(sc, JME_RXCSR);
2524         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2525         /* Flush */
2526         CSR_READ_4(sc, JME_TXCSR);
2527         CSR_READ_4(sc, JME_RXCSR);
2528
2529         /* Enable TXMAC and TXOFL clock sources */
2530         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2531         /* Eisable RXMAC clock source */
2532         val = CSR_READ_4(sc, JME_GPREG1);
2533         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2534         /* Flush */
2535         CSR_READ_4(sc, JME_GHC);
2536
2537         /* Stop TX and RX */
2538         jme_stop_tx(sc);
2539         jme_stop_rx(sc);
2540 }
2541
2542 static void
2543 jme_init(void *xsc)
2544 {
2545         struct jme_softc *sc = xsc;
2546         struct ifnet *ifp = &sc->arpcom.ac_if;
2547         struct mii_data *mii;
2548         uint8_t eaddr[ETHER_ADDR_LEN];
2549         bus_addr_t paddr;
2550         uint32_t reg;
2551         int error, r;
2552
2553         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2554
2555         /*
2556          * Cancel any pending I/O.
2557          */
2558         jme_stop(sc);
2559
2560         /*
2561          * Reset the chip to a known state.
2562          */
2563         jme_reset(sc);
2564
2565         /*
2566          * Setup MSI/MSI-X vectors to interrupts mapping
2567          */
2568         jme_set_msinum(sc);
2569
2570         if (JME_ENABLE_HWRSS(sc))
2571                 jme_enable_rss(sc);
2572         else
2573                 jme_disable_rss(sc);
2574
2575         /* Init RX descriptors */
2576         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2577                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2578                 if (error) {
2579                         if_printf(ifp, "initialization failed: "
2580                                   "no memory for %dth RX ring.\n", r);
2581                         jme_stop(sc);
2582                         return;
2583                 }
2584         }
2585
2586         /* Init TX descriptors */
2587         jme_init_tx_ring(sc);
2588
2589         /* Initialize shadow status block. */
2590         jme_init_ssb(sc);
2591
2592         /* Reprogram the station address. */
2593         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2594         CSR_WRITE_4(sc, JME_PAR0,
2595             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2596         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2597
2598         /*
2599          * Configure Tx queue.
2600          *  Tx priority queue weight value : 0
2601          *  Tx FIFO threshold for processing next packet : 16QW
2602          *  Maximum Tx DMA length : 512
2603          *  Allow Tx DMA burst.
2604          */
2605         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2606         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2607         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2608         sc->jme_txcsr |= sc->jme_tx_dma_size;
2609         sc->jme_txcsr |= TXCSR_DMA_BURST;
2610         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2611
2612         /* Set Tx descriptor counter. */
2613         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2614
2615         /* Set Tx ring address to the hardware. */
2616         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2617         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2618         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2619
2620         /* Configure TxMAC parameters. */
2621         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2622         reg |= TXMAC_THRESH_1_PKT;
2623         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2624         CSR_WRITE_4(sc, JME_TXMAC, reg);
2625
2626         /*
2627          * Configure Rx queue.
2628          *  FIFO full threshold for transmitting Tx pause packet : 128T
2629          *  FIFO threshold for processing next packet : 128QW
2630          *  Rx queue 0 select
2631          *  Max Rx DMA length : 128
2632          *  Rx descriptor retry : 32
2633          *  Rx descriptor retry time gap : 256ns
2634          *  Don't receive runt/bad frame.
2635          */
2636         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2637 #if 0
2638         /*
2639          * Since Rx FIFO size is 4K bytes, receiving frames larger
2640          * than 4K bytes will suffer from Rx FIFO overruns. So
2641          * decrease FIFO threshold to reduce the FIFO overruns for
2642          * frames larger than 4000 bytes.
2643          * For best performance of standard MTU sized frames use
2644          * maximum allowable FIFO threshold, 128QW.
2645          */
2646         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2647             JME_RX_FIFO_SIZE)
2648                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2649         else
2650                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2651 #else
2652         /* Improve PCI Express compatibility */
2653         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2654 #endif
2655         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2656         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2657         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2658         /* XXX TODO DROP_BAD */
2659
2660         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2661                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2662
2663                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2664
2665                 /* Set Rx descriptor counter. */
2666                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2667
2668                 /* Set Rx ring address to the hardware. */
2669                 paddr = rdata->jme_rx_ring_paddr;
2670                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2671                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2672         }
2673
2674         /* Clear receive filter. */
2675         CSR_WRITE_4(sc, JME_RXMAC, 0);
2676
2677         /* Set up the receive filter. */
2678         jme_set_filter(sc);
2679         jme_set_vlan(sc);
2680
2681         /*
2682          * Disable all WOL bits as WOL can interfere normal Rx
2683          * operation. Also clear WOL detection status bits.
2684          */
2685         reg = CSR_READ_4(sc, JME_PMCS);
2686         reg &= ~PMCS_WOL_ENB_MASK;
2687         CSR_WRITE_4(sc, JME_PMCS, reg);
2688
2689         /*
2690          * Pad 10bytes right before received frame. This will greatly
2691          * help Rx performance on strict-alignment architectures as
2692          * it does not need to copy the frame to align the payload.
2693          */
2694         reg = CSR_READ_4(sc, JME_RXMAC);
2695         reg |= RXMAC_PAD_10BYTES;
2696
2697         if (ifp->if_capenable & IFCAP_RXCSUM)
2698                 reg |= RXMAC_CSUM_ENB;
2699         CSR_WRITE_4(sc, JME_RXMAC, reg);
2700
2701         /* Configure general purpose reg0 */
2702         reg = CSR_READ_4(sc, JME_GPREG0);
2703         reg &= ~GPREG0_PCC_UNIT_MASK;
2704         /* Set PCC timer resolution to micro-seconds unit. */
2705         reg |= GPREG0_PCC_UNIT_US;
2706         /*
2707          * Disable all shadow register posting as we have to read
2708          * JME_INTR_STATUS register in jme_intr. Also it seems
2709          * that it's hard to synchronize interrupt status between
2710          * hardware and software with shadow posting due to
2711          * requirements of bus_dmamap_sync(9).
2712          */
2713         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2714             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2715             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2716             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2717         /* Disable posting of DW0. */
2718         reg &= ~GPREG0_POST_DW0_ENB;
2719         /* Clear PME message. */
2720         reg &= ~GPREG0_PME_ENB;
2721         /* Set PHY address. */
2722         reg &= ~GPREG0_PHY_ADDR_MASK;
2723         reg |= sc->jme_phyaddr;
2724         CSR_WRITE_4(sc, JME_GPREG0, reg);
2725
2726         /* Configure Tx queue 0 packet completion coalescing. */
2727         jme_set_tx_coal(sc);
2728
2729         /* Configure Rx queues packet completion coalescing. */
2730         jme_set_rx_coal(sc);
2731
2732         /* Configure shadow status block but don't enable posting. */
2733         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2734         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2735         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2736
2737         /* Disable Timer 1 and Timer 2. */
2738         CSR_WRITE_4(sc, JME_TIMER1, 0);
2739         CSR_WRITE_4(sc, JME_TIMER2, 0);
2740
2741         /* Configure retry transmit period, retry limit value. */
2742         CSR_WRITE_4(sc, JME_TXTRHD,
2743             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2744             TXTRHD_RT_PERIOD_MASK) |
2745             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2746             TXTRHD_RT_LIMIT_SHIFT));
2747
2748 #ifdef DEVICE_POLLING
2749         if (!(ifp->if_flags & IFF_POLLING))
2750 #endif
2751         /* Initialize the interrupt mask. */
2752         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2753         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2754
2755         /*
2756          * Enabling Tx/Rx DMA engines and Rx queue processing is
2757          * done after detection of valid link in jme_miibus_statchg.
2758          */
2759         sc->jme_has_link = FALSE;
2760
2761         /* Set the current media. */
2762         mii = device_get_softc(sc->jme_miibus);
2763         mii_mediachg(mii);
2764
2765         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2766
2767         ifp->if_flags |= IFF_RUNNING;
2768         ifp->if_flags &= ~IFF_OACTIVE;
2769 }
2770
2771 static void
2772 jme_stop(struct jme_softc *sc)
2773 {
2774         struct ifnet *ifp = &sc->arpcom.ac_if;
2775         struct jme_txdesc *txd;
2776         struct jme_rxdesc *rxd;
2777         struct jme_rxdata *rdata;
2778         int i, r;
2779
2780         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2781
2782         /*
2783          * Mark the interface down and cancel the watchdog timer.
2784          */
2785         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2786         ifp->if_timer = 0;
2787
2788         callout_stop(&sc->jme_tick_ch);
2789         sc->jme_has_link = FALSE;
2790
2791         /*
2792          * Disable interrupts.
2793          */
2794         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2795         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2796
2797         /* Disable updating shadow status block. */
2798         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2799             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2800
2801         /* Stop receiver, transmitter. */
2802         jme_stop_rx(sc);
2803         jme_stop_tx(sc);
2804
2805         /*
2806          * Free partial finished RX segments
2807          */
2808         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2809                 rdata = &sc->jme_cdata.jme_rx_data[r];
2810                 if (rdata->jme_rxhead != NULL)
2811                         m_freem(rdata->jme_rxhead);
2812                 JME_RXCHAIN_RESET(rdata);
2813         }
2814
2815         /*
2816          * Free RX and TX mbufs still in the queues.
2817          */
2818         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2819                 rdata = &sc->jme_cdata.jme_rx_data[r];
2820                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2821                         rxd = &rdata->jme_rxdesc[i];
2822                         if (rxd->rx_m != NULL) {
2823                                 bus_dmamap_unload(rdata->jme_rx_tag,
2824                                                   rxd->rx_dmamap);
2825                                 m_freem(rxd->rx_m);
2826                                 rxd->rx_m = NULL;
2827                         }
2828                 }
2829         }
2830         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2831                 txd = &sc->jme_cdata.jme_txdesc[i];
2832                 if (txd->tx_m != NULL) {
2833                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2834                             txd->tx_dmamap);
2835                         m_freem(txd->tx_m);
2836                         txd->tx_m = NULL;
2837                         txd->tx_ndesc = 0;
2838                 }
2839         }
2840 }
2841
2842 static void
2843 jme_stop_tx(struct jme_softc *sc)
2844 {
2845         uint32_t reg;
2846         int i;
2847
2848         reg = CSR_READ_4(sc, JME_TXCSR);
2849         if ((reg & TXCSR_TX_ENB) == 0)
2850                 return;
2851         reg &= ~TXCSR_TX_ENB;
2852         CSR_WRITE_4(sc, JME_TXCSR, reg);
2853         for (i = JME_TIMEOUT; i > 0; i--) {
2854                 DELAY(1);
2855                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2856                         break;
2857         }
2858         if (i == 0)
2859                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2860 }
2861
2862 static void
2863 jme_stop_rx(struct jme_softc *sc)
2864 {
2865         uint32_t reg;
2866         int i;
2867
2868         reg = CSR_READ_4(sc, JME_RXCSR);
2869         if ((reg & RXCSR_RX_ENB) == 0)
2870                 return;
2871         reg &= ~RXCSR_RX_ENB;
2872         CSR_WRITE_4(sc, JME_RXCSR, reg);
2873         for (i = JME_TIMEOUT; i > 0; i--) {
2874                 DELAY(1);
2875                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2876                         break;
2877         }
2878         if (i == 0)
2879                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2880 }
2881
2882 static void
2883 jme_init_tx_ring(struct jme_softc *sc)
2884 {
2885         struct jme_chain_data *cd;
2886         struct jme_txdesc *txd;
2887         int i;
2888
2889         sc->jme_cdata.jme_tx_prod = 0;
2890         sc->jme_cdata.jme_tx_cons = 0;
2891         sc->jme_cdata.jme_tx_cnt = 0;
2892
2893         cd = &sc->jme_cdata;
2894         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2895         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2896                 txd = &sc->jme_cdata.jme_txdesc[i];
2897                 txd->tx_m = NULL;
2898                 txd->tx_desc = &cd->jme_tx_ring[i];
2899                 txd->tx_ndesc = 0;
2900         }
2901 }
2902
2903 static void
2904 jme_init_ssb(struct jme_softc *sc)
2905 {
2906         struct jme_chain_data *cd;
2907
2908         cd = &sc->jme_cdata;
2909         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2910 }
2911
2912 static int
2913 jme_init_rx_ring(struct jme_rxdata *rdata)
2914 {
2915         struct jme_rxdesc *rxd;
2916         int i;
2917
2918         KKASSERT(rdata->jme_rxhead == NULL &&
2919                  rdata->jme_rxtail == NULL &&
2920                  rdata->jme_rxlen == 0);
2921         rdata->jme_rx_cons = 0;
2922
2923         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2924         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2925                 int error;
2926
2927                 rxd = &rdata->jme_rxdesc[i];
2928                 rxd->rx_m = NULL;
2929                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2930                 error = jme_newbuf(rdata, rxd, 1);
2931                 if (error)
2932                         return error;
2933         }
2934         return 0;
2935 }
2936
2937 static int
2938 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2939 {
2940         struct mbuf *m;
2941         bus_dma_segment_t segs;
2942         bus_dmamap_t map;
2943         int error, nsegs;
2944
2945         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2946         if (m == NULL)
2947                 return ENOBUFS;
2948         /*
2949          * JMC250 has 64bit boundary alignment limitation so jme(4)
2950          * takes advantage of 10 bytes padding feature of hardware
2951          * in order not to copy entire frame to align IP header on
2952          * 32bit boundary.
2953          */
2954         m->m_len = m->m_pkthdr.len = MCLBYTES;
2955
2956         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2957                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2958                         BUS_DMA_NOWAIT);
2959         if (error) {
2960                 m_freem(m);
2961                 if (init) {
2962                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2963                             "can't load RX mbuf\n");
2964                 }
2965                 return error;
2966         }
2967
2968         if (rxd->rx_m != NULL) {
2969                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2970                                 BUS_DMASYNC_POSTREAD);
2971                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2972         }
2973         map = rxd->rx_dmamap;
2974         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2975         rdata->jme_rx_sparemap = map;
2976         rxd->rx_m = m;
2977         rxd->rx_paddr = segs.ds_addr;
2978
2979         jme_setup_rxdesc(rxd);
2980         return 0;
2981 }
2982
2983 static void
2984 jme_set_vlan(struct jme_softc *sc)
2985 {
2986         struct ifnet *ifp = &sc->arpcom.ac_if;
2987         uint32_t reg;
2988
2989         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2990
2991         reg = CSR_READ_4(sc, JME_RXMAC);
2992         reg &= ~RXMAC_VLAN_ENB;
2993         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2994                 reg |= RXMAC_VLAN_ENB;
2995         CSR_WRITE_4(sc, JME_RXMAC, reg);
2996 }
2997
2998 static void
2999 jme_set_filter(struct jme_softc *sc)
3000 {
3001         struct ifnet *ifp = &sc->arpcom.ac_if;
3002         struct ifmultiaddr *ifma;
3003         uint32_t crc;
3004         uint32_t mchash[2];
3005         uint32_t rxcfg;
3006
3007         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3008
3009         rxcfg = CSR_READ_4(sc, JME_RXMAC);
3010         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3011             RXMAC_ALLMULTI);
3012
3013         /*
3014          * Always accept frames destined to our station address.
3015          * Always accept broadcast frames.
3016          */
3017         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3018
3019         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3020                 if (ifp->if_flags & IFF_PROMISC)
3021                         rxcfg |= RXMAC_PROMISC;
3022                 if (ifp->if_flags & IFF_ALLMULTI)
3023                         rxcfg |= RXMAC_ALLMULTI;
3024                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3025                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3026                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3027                 return;
3028         }
3029
3030         /*
3031          * Set up the multicast address filter by passing all multicast
3032          * addresses through a CRC generator, and then using the low-order
3033          * 6 bits as an index into the 64 bit multicast hash table.  The
3034          * high order bits select the register, while the rest of the bits
3035          * select the bit within the register.
3036          */
3037         rxcfg |= RXMAC_MULTICAST;
3038         bzero(mchash, sizeof(mchash));
3039
3040         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3041                 if (ifma->ifma_addr->sa_family != AF_LINK)
3042                         continue;
3043                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3044                     ifma->ifma_addr), ETHER_ADDR_LEN);
3045
3046                 /* Just want the 6 least significant bits. */
3047                 crc &= 0x3f;
3048
3049                 /* Set the corresponding bit in the hash table. */
3050                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3051         }
3052
3053         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3054         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3055         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3056 }
3057
3058 static int
3059 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3060 {
3061         struct jme_softc *sc = arg1;
3062         struct ifnet *ifp = &sc->arpcom.ac_if;
3063         int error, v;
3064
3065         ifnet_serialize_all(ifp);
3066
3067         v = sc->jme_tx_coal_to;
3068         error = sysctl_handle_int(oidp, &v, 0, req);
3069         if (error || req->newptr == NULL)
3070                 goto back;
3071
3072         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3073                 error = EINVAL;
3074                 goto back;
3075         }
3076
3077         if (v != sc->jme_tx_coal_to) {
3078                 sc->jme_tx_coal_to = v;
3079                 if (ifp->if_flags & IFF_RUNNING)
3080                         jme_set_tx_coal(sc);
3081         }
3082 back:
3083         ifnet_deserialize_all(ifp);
3084         return error;
3085 }
3086
3087 static int
3088 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3089 {
3090         struct jme_softc *sc = arg1;
3091         struct ifnet *ifp = &sc->arpcom.ac_if;
3092         int error, v;
3093
3094         ifnet_serialize_all(ifp);
3095
3096         v = sc->jme_tx_coal_pkt;
3097         error = sysctl_handle_int(oidp, &v, 0, req);
3098         if (error || req->newptr == NULL)
3099                 goto back;
3100
3101         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3102                 error = EINVAL;
3103                 goto back;
3104         }
3105
3106         if (v != sc->jme_tx_coal_pkt) {
3107                 sc->jme_tx_coal_pkt = v;
3108                 if (ifp->if_flags & IFF_RUNNING)
3109                         jme_set_tx_coal(sc);
3110         }
3111 back:
3112         ifnet_deserialize_all(ifp);
3113         return error;
3114 }
3115
3116 static int
3117 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3118 {
3119         struct jme_softc *sc = arg1;
3120         struct ifnet *ifp = &sc->arpcom.ac_if;
3121         int error, v;
3122
3123         ifnet_serialize_all(ifp);
3124
3125         v = sc->jme_rx_coal_to;
3126         error = sysctl_handle_int(oidp, &v, 0, req);
3127         if (error || req->newptr == NULL)
3128                 goto back;
3129
3130         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3131                 error = EINVAL;
3132                 goto back;
3133         }
3134
3135         if (v != sc->jme_rx_coal_to) {
3136                 sc->jme_rx_coal_to = v;
3137                 if (ifp->if_flags & IFF_RUNNING)
3138                         jme_set_rx_coal(sc);
3139         }
3140 back:
3141         ifnet_deserialize_all(ifp);
3142         return error;
3143 }
3144
3145 static int
3146 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3147 {
3148         struct jme_softc *sc = arg1;
3149         struct ifnet *ifp = &sc->arpcom.ac_if;
3150         int error, v;
3151
3152         ifnet_serialize_all(ifp);
3153
3154         v = sc->jme_rx_coal_pkt;
3155         error = sysctl_handle_int(oidp, &v, 0, req);
3156         if (error || req->newptr == NULL)
3157                 goto back;
3158
3159         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3160                 error = EINVAL;
3161                 goto back;
3162         }
3163
3164         if (v != sc->jme_rx_coal_pkt) {
3165                 sc->jme_rx_coal_pkt = v;
3166                 if (ifp->if_flags & IFF_RUNNING)
3167                         jme_set_rx_coal(sc);
3168         }
3169 back:
3170         ifnet_deserialize_all(ifp);
3171         return error;
3172 }
3173
3174 static void
3175 jme_set_tx_coal(struct jme_softc *sc)
3176 {
3177         uint32_t reg;
3178
3179         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3180             PCCTX_COAL_TO_MASK;
3181         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3182             PCCTX_COAL_PKT_MASK;
3183         reg |= PCCTX_COAL_TXQ0;
3184         CSR_WRITE_4(sc, JME_PCCTX, reg);
3185 }
3186
3187 static void
3188 jme_set_rx_coal(struct jme_softc *sc)
3189 {
3190         uint32_t reg;
3191         int r;
3192
3193         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3194             PCCRX_COAL_TO_MASK;
3195         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3196             PCCRX_COAL_PKT_MASK;
3197         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3198                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3199 }
3200
3201 #ifdef DEVICE_POLLING
3202
3203 static void
3204 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3205 {
3206         struct jme_softc *sc = ifp->if_softc;
3207         uint32_t status;
3208         int r;
3209
3210         ASSERT_SERIALIZED(&sc->jme_serialize);
3211
3212         switch (cmd) {
3213         case POLL_REGISTER:
3214                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3215                 break;
3216
3217         case POLL_DEREGISTER:
3218                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3219                 break;
3220
3221         case POLL_AND_CHECK_STATUS:
3222         case POLL_ONLY:
3223                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3224
3225                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3226                         struct jme_rxdata *rdata =
3227                             &sc->jme_cdata.jme_rx_data[r];
3228
3229                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3230                         jme_rxeof(rdata, count);
3231                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3232                 }
3233
3234                 if (status & INTR_RXQ_DESC_EMPTY) {
3235                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3236                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3237                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3238                 }
3239
3240                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3241                 jme_txeof(sc);
3242                 if (!ifq_is_empty(&ifp->if_snd))
3243                         if_devstart(ifp);
3244                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3245                 break;
3246         }
3247 }
3248
3249 #endif  /* DEVICE_POLLING */
3250
3251 static int
3252 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3253 {
3254         bus_dmamem_t dmem;
3255         int error, asize;
3256
3257         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3258         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3259                         JME_RX_RING_ALIGN, 0,
3260                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3261                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3262         if (error) {
3263                 device_printf(rdata->jme_sc->jme_dev,
3264                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3265                 return error;
3266         }
3267         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3268         rdata->jme_rx_ring_map = dmem.dmem_map;
3269         rdata->jme_rx_ring = dmem.dmem_addr;
3270         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3271
3272         return 0;
3273 }
3274
3275 static int
3276 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3277 {
3278         if ((paddr & 0xffffffff) == 0) {
3279                 /*
3280                  * Don't allow lower 32bits of the RX buffer's
3281                  * physical address to be 0, else it will break
3282                  * hardware pending RSS information delivery
3283                  * detection on RX path.
3284                  */
3285                 return 1;
3286         }
3287         return 0;
3288 }
3289
3290 static int
3291 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3292 {
3293         bus_addr_t lowaddr;
3294         int i, error;
3295
3296         lowaddr = BUS_SPACE_MAXADDR;
3297         if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3298                 /* jme_rxbuf_dma_filter will be called */
3299                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3300         }
3301
3302         /* Create tag for Rx buffers. */
3303         error = bus_dma_tag_create(
3304             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3305             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3306             lowaddr,                    /* lowaddr */
3307             BUS_SPACE_MAXADDR,          /* highaddr */
3308             jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3309             MCLBYTES,                   /* maxsize */
3310             1,                          /* nsegments */
3311             MCLBYTES,                   /* maxsegsize */
3312             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3313             &rdata->jme_rx_tag);
3314         if (error) {
3315                 device_printf(rdata->jme_sc->jme_dev,
3316                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3317                 return error;
3318         }
3319
3320         /* Create DMA maps for Rx buffers. */
3321         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3322                                   &rdata->jme_rx_sparemap);
3323         if (error) {
3324                 device_printf(rdata->jme_sc->jme_dev,
3325                     "could not create %dth spare Rx dmamap.\n",
3326                     rdata->jme_rx_idx);
3327                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3328                 rdata->jme_rx_tag = NULL;
3329                 return error;
3330         }
3331         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3332                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3333
3334                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3335                                           &rxd->rx_dmamap);
3336                 if (error) {
3337                         int j;
3338
3339                         device_printf(rdata->jme_sc->jme_dev,
3340                             "could not create %dth Rx dmamap "
3341                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3342
3343                         for (j = 0; j < i; ++j) {
3344                                 rxd = &rdata->jme_rxdesc[j];
3345                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3346                                                    rxd->rx_dmamap);
3347                         }
3348                         bus_dmamap_destroy(rdata->jme_rx_tag,
3349                                            rdata->jme_rx_sparemap);
3350                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3351                         rdata->jme_rx_tag = NULL;
3352                         return error;
3353                 }
3354         }
3355         return 0;
3356 }
3357
3358 static void
3359 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3360 {
3361         int r;
3362
3363         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3364                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3365
3366                 if (status & rdata->jme_rx_coal) {
3367                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3368                         jme_rxeof(rdata, -1);
3369                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3370                 }
3371         }
3372 }
3373
3374 static void
3375 jme_enable_rss(struct jme_softc *sc)
3376 {
3377         uint32_t rssc, ind;
3378         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3379         int i;
3380
3381         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3382                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3383                 ("%s: invalid # of RX rings (%d)",
3384                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3385
3386         rssc = RSSC_HASH_64_ENTRY;
3387         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3388         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3389         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3390         CSR_WRITE_4(sc, JME_RSSC, rssc);
3391
3392         toeplitz_get_key(key, sizeof(key));
3393         for (i = 0; i < RSSKEY_NREGS; ++i) {
3394                 uint32_t keyreg;
3395
3396                 keyreg = RSSKEY_REGVAL(key, i);
3397                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3398
3399                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3400         }
3401
3402         /*
3403          * Create redirect table in following fashion:
3404          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3405          */
3406         ind = 0;
3407         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3408                 int q;
3409
3410                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3411                 ind |= q << (i * 8);
3412         }
3413         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3414
3415         for (i = 0; i < RSSTBL_NREGS; ++i)
3416                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3417 }
3418
3419 static void
3420 jme_disable_rss(struct jme_softc *sc)
3421 {
3422         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3423 }
3424
3425 static void
3426 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3427 {
3428         struct jme_softc *sc = ifp->if_softc;
3429
3430         ifnet_serialize_array_enter(sc->jme_serialize_arr,
3431             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3432 }
3433
3434 static void
3435 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3436 {
3437         struct jme_softc *sc = ifp->if_softc;
3438
3439         ifnet_serialize_array_exit(sc->jme_serialize_arr,
3440             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3441 }
3442
3443 static int
3444 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3445 {
3446         struct jme_softc *sc = ifp->if_softc;
3447
3448         return ifnet_serialize_array_try(sc->jme_serialize_arr,
3449             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3450 }
3451
3452 #ifdef INVARIANTS
3453
3454 static void
3455 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3456     boolean_t serialized)
3457 {
3458         struct jme_softc *sc = ifp->if_softc;
3459
3460         ifnet_serialize_array_assert(sc->jme_serialize_arr,
3461             sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3462             slz, serialized);
3463 }
3464
3465 #endif  /* INVARIANTS */
3466
3467 static void
3468 jme_msix_try_alloc(device_t dev)
3469 {
3470         struct jme_softc *sc = device_get_softc(dev);
3471         struct jme_msix_data *msix;
3472         int error, i, r, msix_enable, msix_count;
3473         int offset, offset_def;
3474
3475         msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3476         KKASSERT(msix_count <= JME_NMSIX);
3477
3478         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3479
3480         /*
3481          * We leave the 1st MSI-X vector unused, so we
3482          * actually need msix_count + 1 MSI-X vectors.
3483          */
3484         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3485                 return;
3486
3487         for (i = 0; i < msix_count; ++i)
3488                 sc->jme_msix[i].jme_msix_rid = -1;
3489
3490         i = 0;
3491
3492         /*
3493          * Setup TX MSI-X
3494          */
3495
3496         offset_def = device_get_unit(dev) % ncpus2;
3497         offset = device_getenv_int(dev, "msix.txoff", offset_def);
3498         if (offset >= ncpus2) {
3499                 device_printf(dev, "invalid msix.txoff %d, use %d\n",
3500                     offset, offset_def);
3501                 offset = offset_def;
3502         }
3503
3504         msix = &sc->jme_msix[i++];
3505         msix->jme_msix_cpuid = offset;
3506         sc->jme_tx_cpuid = msix->jme_msix_cpuid;
3507         msix->jme_msix_arg = &sc->jme_cdata;
3508         msix->jme_msix_func = jme_msix_tx;
3509         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3510         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3511         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3512             device_get_nameunit(dev));
3513
3514         /*
3515          * Setup RX MSI-X
3516          */
3517
3518         if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
3519                 offset = 0;
3520         } else {
3521                 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
3522                     device_get_unit(dev)) % ncpus2;
3523
3524                 offset = device_getenv_int(dev, "msix.rxoff", offset_def);
3525                 if (offset >= ncpus2 ||
3526                     offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3527                         device_printf(dev, "invalid msix.rxoff %d, use %d\n",
3528                             offset, offset_def);
3529                         offset = offset_def;
3530                 }
3531         }
3532
3533         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3534                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3535
3536                 msix = &sc->jme_msix[i++];
3537                 msix->jme_msix_cpuid = r + offset;
3538                 KKASSERT(msix->jme_msix_cpuid < ncpus2);
3539                 msix->jme_msix_arg = rdata;
3540                 msix->jme_msix_func = jme_msix_rx;
3541                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3542                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3543                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3544                     "%s rx%d", device_get_nameunit(dev), r);
3545         }
3546
3547         KKASSERT(i == msix_count);
3548
3549         error = pci_setup_msix(dev);
3550         if (error)
3551                 return;
3552
3553         /* Setup jme_msix_cnt early, so we could cleanup */
3554         sc->jme_msix_cnt = msix_count;
3555
3556         for (i = 0; i < msix_count; ++i) {
3557                 msix = &sc->jme_msix[i];
3558
3559                 msix->jme_msix_vector = i + 1;
3560                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3561                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3562                 if (error)
3563                         goto back;
3564
3565                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3566                     &msix->jme_msix_rid, RF_ACTIVE);
3567                 if (msix->jme_msix_res == NULL) {
3568                         error = ENOMEM;
3569                         goto back;
3570                 }
3571         }
3572
3573         for (i = 0; i < JME_INTR_CNT; ++i) {
3574                 uint32_t intr_mask = (1 << i);
3575                 int x;
3576
3577                 if ((JME_INTRS & intr_mask) == 0)
3578                         continue;
3579
3580                 for (x = 0; x < msix_count; ++x) {
3581                         msix = &sc->jme_msix[x];
3582                         if (msix->jme_msix_intrs & intr_mask) {
3583                                 int reg, shift;
3584
3585                                 reg = i / JME_MSINUM_FACTOR;
3586                                 KKASSERT(reg < JME_MSINUM_CNT);
3587
3588                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3589
3590                                 sc->jme_msinum[reg] |=
3591                                     (msix->jme_msix_vector << shift);
3592
3593                                 break;
3594                         }
3595                 }
3596         }
3597
3598         if (bootverbose) {
3599                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3600                         device_printf(dev, "MSINUM%d: %#x\n", i,
3601                             sc->jme_msinum[i]);
3602                 }
3603         }
3604
3605         pci_enable_msix(dev);
3606         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3607
3608 back:
3609         if (error)
3610                 jme_msix_free(dev);
3611 }
3612
3613 static int
3614 jme_intr_alloc(device_t dev)
3615 {
3616         struct jme_softc *sc = device_get_softc(dev);
3617         u_int irq_flags;
3618
3619         jme_msix_try_alloc(dev);
3620
3621         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3622                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3623                     &sc->jme_irq_rid, &irq_flags);
3624
3625                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3626                     &sc->jme_irq_rid, irq_flags);
3627                 if (sc->jme_irq_res == NULL) {
3628                         device_printf(dev, "can't allocate irq\n");
3629                         return ENXIO;
3630                 }
3631         }
3632         return 0;
3633 }
3634
3635 static void
3636 jme_msix_free(device_t dev)
3637 {
3638         struct jme_softc *sc = device_get_softc(dev);
3639         int i;
3640
3641         KKASSERT(sc->jme_msix_cnt > 1);
3642
3643         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3644                 struct jme_msix_data *msix = &sc->jme_msix[i];
3645
3646                 if (msix->jme_msix_res != NULL) {
3647                         bus_release_resource(dev, SYS_RES_IRQ,
3648                             msix->jme_msix_rid, msix->jme_msix_res);
3649                         msix->jme_msix_res = NULL;
3650                 }
3651                 if (msix->jme_msix_rid >= 0) {
3652                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3653                         msix->jme_msix_rid = -1;
3654                 }
3655         }
3656         pci_teardown_msix(dev);
3657 }
3658
3659 static void
3660 jme_intr_free(device_t dev)
3661 {
3662         struct jme_softc *sc = device_get_softc(dev);
3663
3664         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3665                 if (sc->jme_irq_res != NULL) {
3666                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3667                                              sc->jme_irq_res);
3668                 }
3669                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3670                         pci_release_msi(dev);
3671         } else {
3672                 jme_msix_free(dev);
3673         }
3674 }
3675
3676 static void
3677 jme_msix_tx(void *xcd)
3678 {
3679         struct jme_chain_data *cd = xcd;
3680         struct jme_softc *sc = cd->jme_sc;
3681         struct ifnet *ifp = &sc->arpcom.ac_if;
3682
3683         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3684
3685         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3686
3687         CSR_WRITE_4(sc, JME_INTR_STATUS,
3688             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3689
3690         if (ifp->if_flags & IFF_RUNNING) {
3691                 jme_txeof(sc);
3692                 if (!ifq_is_empty(&ifp->if_snd))
3693                         if_devstart(ifp);
3694         }
3695
3696         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3697 }
3698
3699 static void
3700 jme_msix_rx(void *xrdata)
3701 {
3702         struct jme_rxdata *rdata = xrdata;
3703         struct jme_softc *sc = rdata->jme_sc;
3704         struct ifnet *ifp = &sc->arpcom.ac_if;
3705         uint32_t status;
3706
3707         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3708
3709         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3710             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3711
3712         status = CSR_READ_4(sc, JME_INTR_STATUS);
3713         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3714
3715         if (status & rdata->jme_rx_coal)
3716                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3717         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3718
3719         if (ifp->if_flags & IFF_RUNNING) {
3720                 if (status & rdata->jme_rx_coal)
3721                         jme_rxeof(rdata, -1);
3722
3723                 if (status & rdata->jme_rx_empty) {
3724                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3725                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3726                 }
3727         }
3728
3729         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3730             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3731 }
3732
3733 static void
3734 jme_set_msinum(struct jme_softc *sc)
3735 {
3736         int i;
3737
3738         for (i = 0; i < JME_MSINUM_CNT; ++i)
3739                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3740 }
3741
3742 static int
3743 jme_intr_setup(device_t dev)
3744 {
3745         struct jme_softc *sc = device_get_softc(dev);
3746         struct ifnet *ifp = &sc->arpcom.ac_if;
3747         int error;
3748
3749         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3750                 return jme_msix_setup(dev);
3751
3752         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3753             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3754         if (error) {
3755                 device_printf(dev, "could not set up interrupt handler.\n");
3756                 return error;
3757         }
3758
3759         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3760         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3761         return 0;
3762 }
3763
3764 static void
3765 jme_intr_teardown(device_t dev)
3766 {
3767         struct jme_softc *sc = device_get_softc(dev);
3768
3769         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3770                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3771         else
3772                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3773 }
3774
3775 static int
3776 jme_msix_setup(device_t dev)
3777 {
3778         struct jme_softc *sc = device_get_softc(dev);
3779         struct ifnet *ifp = &sc->arpcom.ac_if;
3780         int x;
3781
3782         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3783                 struct jme_msix_data *msix = &sc->jme_msix[x];
3784                 int error;
3785
3786                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3787                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3788                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3789                     msix->jme_msix_desc);
3790                 if (error) {
3791                         device_printf(dev, "could not set up %s "
3792                             "interrupt handler.\n", msix->jme_msix_desc);
3793                         jme_msix_teardown(dev, x);
3794                         return error;
3795                 }
3796         }
3797         ifp->if_cpuid = sc->jme_tx_cpuid;
3798         return 0;
3799 }
3800
3801 static void
3802 jme_msix_teardown(device_t dev, int msix_count)
3803 {
3804         struct jme_softc *sc = device_get_softc(dev);
3805         int x;
3806
3807         for (x = 0; x < msix_count; ++x) {
3808                 struct jme_msix_data *msix = &sc->jme_msix[x];
3809
3810                 bus_teardown_intr(dev, msix->jme_msix_res,
3811                     msix->jme_msix_handle);
3812         }
3813 }
3814
3815 static void
3816 jme_serialize_skipmain(struct jme_softc *sc)
3817 {
3818         lwkt_serialize_array_enter(sc->jme_serialize_arr,
3819             sc->jme_serialize_cnt, 1);
3820 }
3821
3822 static void
3823 jme_deserialize_skipmain(struct jme_softc *sc)
3824 {
3825         lwkt_serialize_array_exit(sc->jme_serialize_arr,
3826             sc->jme_serialize_cnt, 1);
3827 }