2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * SERIALIZATION API RULES:
70 * - If the driver uses the same serializer for the interrupt as for the
71 * ifnet, most of the serialization will be done automatically for the
74 * - ifmedia entry points will be serialized by the ifmedia code using the
77 * - if_* entry points except for if_input will be serialized by the IF
78 * and protocol layers.
80 * - The device driver must be sure to serialize access from timeout code
81 * installed by the device driver.
83 * - The device driver typically holds the serializer at the time it wishes
86 * - We must call lwkt_serialize_handler_enable() prior to enabling the
87 * hardware interrupt and lwkt_serialize_handler_disable() after disabling
88 * the hardware interrupt in order to avoid handler execution races from
89 * scheduled interrupt threads.
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
99 * MSI-X MUST NOT be enabled on 82574:
100 * <<82574 specification update>> errata #15
103 #include "opt_polling.h"
105 #include <sys/param.h>
107 #include <sys/endian.h>
108 #include <sys/interrupt.h>
109 #include <sys/kernel.h>
111 #include <sys/malloc.h>
112 #include <sys/mbuf.h>
113 #include <sys/proc.h>
114 #include <sys/rman.h>
115 #include <sys/serialize.h>
116 #include <sys/socket.h>
117 #include <sys/sockio.h>
118 #include <sys/sysctl.h>
119 #include <sys/systm.h>
122 #include <net/ethernet.h>
124 #include <net/if_arp.h>
125 #include <net/if_dl.h>
126 #include <net/if_media.h>
127 #include <net/ifq_var.h>
128 #include <net/vlan/if_vlan_var.h>
129 #include <net/vlan/if_vlan_ether.h>
131 #include <netinet/in_systm.h>
132 #include <netinet/in.h>
133 #include <netinet/ip.h>
134 #include <netinet/tcp.h>
135 #include <netinet/udp.h>
137 #include <bus/pci/pcivar.h>
138 #include <bus/pci/pcireg.h>
140 #include <dev/netif/ig_hal/e1000_api.h>
141 #include <dev/netif/ig_hal/e1000_82571.h>
142 #include <dev/netif/em/if_em.h>
144 #define EM_NAME "Intel(R) PRO/1000 Network Connection "
145 #define EM_VER " 7.2.4"
147 #define _EM_DEVICE(id, ret) \
148 { EM_VENDOR_ID, E1000_DEV_ID_##id, ret, EM_NAME #id EM_VER }
149 #define EM_EMX_DEVICE(id) _EM_DEVICE(id, -100)
150 #define EM_DEVICE(id) _EM_DEVICE(id, 0)
151 #define EM_DEVICE_NULL { 0, 0, 0, NULL }
153 static const struct em_vendor_info em_vendor_info_array[] = {
155 EM_DEVICE(82540EM_LOM),
157 EM_DEVICE(82540EP_LOM),
158 EM_DEVICE(82540EP_LP),
162 EM_DEVICE(82541ER_LOM),
163 EM_DEVICE(82541EI_MOBILE),
165 EM_DEVICE(82541GI_LF),
166 EM_DEVICE(82541GI_MOBILE),
170 EM_DEVICE(82543GC_FIBER),
171 EM_DEVICE(82543GC_COPPER),
173 EM_DEVICE(82544EI_COPPER),
174 EM_DEVICE(82544EI_FIBER),
175 EM_DEVICE(82544GC_COPPER),
176 EM_DEVICE(82544GC_LOM),
178 EM_DEVICE(82545EM_COPPER),
179 EM_DEVICE(82545EM_FIBER),
180 EM_DEVICE(82545GM_COPPER),
181 EM_DEVICE(82545GM_FIBER),
182 EM_DEVICE(82545GM_SERDES),
184 EM_DEVICE(82546EB_COPPER),
185 EM_DEVICE(82546EB_FIBER),
186 EM_DEVICE(82546EB_QUAD_COPPER),
187 EM_DEVICE(82546GB_COPPER),
188 EM_DEVICE(82546GB_FIBER),
189 EM_DEVICE(82546GB_SERDES),
190 EM_DEVICE(82546GB_PCIE),
191 EM_DEVICE(82546GB_QUAD_COPPER),
192 EM_DEVICE(82546GB_QUAD_COPPER_KSP3),
195 EM_DEVICE(82547EI_MOBILE),
198 EM_EMX_DEVICE(82571EB_COPPER),
199 EM_EMX_DEVICE(82571EB_FIBER),
200 EM_EMX_DEVICE(82571EB_SERDES),
201 EM_EMX_DEVICE(82571EB_SERDES_DUAL),
202 EM_EMX_DEVICE(82571EB_SERDES_QUAD),
203 EM_EMX_DEVICE(82571EB_QUAD_COPPER),
204 EM_EMX_DEVICE(82571EB_QUAD_COPPER_BP),
205 EM_EMX_DEVICE(82571EB_QUAD_COPPER_LP),
206 EM_EMX_DEVICE(82571EB_QUAD_FIBER),
207 EM_EMX_DEVICE(82571PT_QUAD_COPPER),
209 EM_EMX_DEVICE(82572EI_COPPER),
210 EM_EMX_DEVICE(82572EI_FIBER),
211 EM_EMX_DEVICE(82572EI_SERDES),
212 EM_EMX_DEVICE(82572EI),
214 EM_EMX_DEVICE(82573E),
215 EM_EMX_DEVICE(82573E_IAMT),
216 EM_EMX_DEVICE(82573L),
220 EM_EMX_DEVICE(80003ES2LAN_COPPER_SPT),
221 EM_EMX_DEVICE(80003ES2LAN_SERDES_SPT),
222 EM_EMX_DEVICE(80003ES2LAN_COPPER_DPT),
223 EM_EMX_DEVICE(80003ES2LAN_SERDES_DPT),
225 EM_DEVICE(ICH8_IGP_M_AMT),
226 EM_DEVICE(ICH8_IGP_AMT),
227 EM_DEVICE(ICH8_IGP_C),
229 EM_DEVICE(ICH8_IFE_GT),
230 EM_DEVICE(ICH8_IFE_G),
231 EM_DEVICE(ICH8_IGP_M),
232 EM_DEVICE(ICH8_82567V_3),
234 EM_DEVICE(ICH9_IGP_M_AMT),
235 EM_DEVICE(ICH9_IGP_AMT),
236 EM_DEVICE(ICH9_IGP_C),
237 EM_DEVICE(ICH9_IGP_M),
238 EM_DEVICE(ICH9_IGP_M_V),
240 EM_DEVICE(ICH9_IFE_GT),
241 EM_DEVICE(ICH9_IFE_G),
244 EM_EMX_DEVICE(82574L),
245 EM_EMX_DEVICE(82574LA),
247 EM_DEVICE(ICH10_R_BM_LM),
248 EM_DEVICE(ICH10_R_BM_LF),
249 EM_DEVICE(ICH10_R_BM_V),
250 EM_DEVICE(ICH10_D_BM_LM),
251 EM_DEVICE(ICH10_D_BM_LF),
252 EM_DEVICE(ICH10_D_BM_V),
254 EM_DEVICE(PCH_M_HV_LM),
255 EM_DEVICE(PCH_M_HV_LC),
256 EM_DEVICE(PCH_D_HV_DM),
257 EM_DEVICE(PCH_D_HV_DC),
259 EM_DEVICE(PCH2_LV_LM),
260 EM_DEVICE(PCH2_LV_V),
262 /* required last entry */
266 static int em_probe(device_t);
267 static int em_attach(device_t);
268 static int em_detach(device_t);
269 static int em_shutdown(device_t);
270 static int em_suspend(device_t);
271 static int em_resume(device_t);
273 static void em_init(void *);
274 static void em_stop(struct adapter *);
275 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
276 static void em_start(struct ifnet *);
277 #ifdef DEVICE_POLLING
278 static void em_poll(struct ifnet *, enum poll_cmd, int);
280 static void em_watchdog(struct ifnet *);
281 static void em_media_status(struct ifnet *, struct ifmediareq *);
282 static int em_media_change(struct ifnet *);
283 static void em_timer(void *);
285 static void em_intr(void *);
286 static void em_intr_mask(void *);
287 static void em_intr_body(struct adapter *, boolean_t);
288 static void em_rxeof(struct adapter *, int);
289 static void em_txeof(struct adapter *);
290 static void em_tx_collect(struct adapter *);
291 static void em_tx_purge(struct adapter *);
292 static void em_enable_intr(struct adapter *);
293 static void em_disable_intr(struct adapter *);
295 static int em_dma_malloc(struct adapter *, bus_size_t,
296 struct em_dma_alloc *);
297 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
298 static void em_init_tx_ring(struct adapter *);
299 static int em_init_rx_ring(struct adapter *);
300 static int em_create_tx_ring(struct adapter *);
301 static int em_create_rx_ring(struct adapter *);
302 static void em_destroy_tx_ring(struct adapter *, int);
303 static void em_destroy_rx_ring(struct adapter *, int);
304 static int em_newbuf(struct adapter *, int, int);
305 static int em_encap(struct adapter *, struct mbuf **);
306 static void em_rxcsum(struct adapter *, struct e1000_rx_desc *,
308 static int em_txcsum_pullup(struct adapter *, struct mbuf **);
309 static int em_txcsum(struct adapter *, struct mbuf *,
310 uint32_t *, uint32_t *);
312 static int em_get_hw_info(struct adapter *);
313 static int em_is_valid_eaddr(const uint8_t *);
314 static int em_alloc_pci_res(struct adapter *);
315 static void em_free_pci_res(struct adapter *);
316 static int em_reset(struct adapter *);
317 static void em_setup_ifp(struct adapter *);
318 static void em_init_tx_unit(struct adapter *);
319 static void em_init_rx_unit(struct adapter *);
320 static void em_update_stats(struct adapter *);
321 static void em_set_promisc(struct adapter *);
322 static void em_disable_promisc(struct adapter *);
323 static void em_set_multi(struct adapter *);
324 static void em_update_link_status(struct adapter *);
325 static void em_smartspeed(struct adapter *);
326 static void em_set_itr(struct adapter *, uint32_t);
327 static void em_disable_aspm(struct adapter *);
329 /* Hardware workarounds */
330 static int em_82547_fifo_workaround(struct adapter *, int);
331 static void em_82547_update_fifo_head(struct adapter *, int);
332 static int em_82547_tx_fifo_reset(struct adapter *);
333 static void em_82547_move_tail(void *);
334 static void em_82547_move_tail_serialized(struct adapter *);
335 static uint32_t em_82544_fill_desc(bus_addr_t, uint32_t, PDESC_ARRAY);
337 static void em_print_debug_info(struct adapter *);
338 static void em_print_nvm_info(struct adapter *);
339 static void em_print_hw_stats(struct adapter *);
341 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
342 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
343 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
344 static int em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
345 static void em_add_sysctl(struct adapter *adapter);
347 /* Management and WOL Support */
348 static void em_get_mgmt(struct adapter *);
349 static void em_rel_mgmt(struct adapter *);
350 static void em_get_hw_control(struct adapter *);
351 static void em_rel_hw_control(struct adapter *);
352 static void em_enable_wol(device_t);
354 static device_method_t em_methods[] = {
355 /* Device interface */
356 DEVMETHOD(device_probe, em_probe),
357 DEVMETHOD(device_attach, em_attach),
358 DEVMETHOD(device_detach, em_detach),
359 DEVMETHOD(device_shutdown, em_shutdown),
360 DEVMETHOD(device_suspend, em_suspend),
361 DEVMETHOD(device_resume, em_resume),
365 static driver_t em_driver = {
368 sizeof(struct adapter),
371 static devclass_t em_devclass;
373 DECLARE_DUMMY_MODULE(if_em);
374 MODULE_DEPEND(em, ig_hal, 1, 1, 1);
375 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, NULL, NULL);
380 static int em_int_throttle_ceil = EM_DEFAULT_ITR;
381 static int em_rxd = EM_DEFAULT_RXD;
382 static int em_txd = EM_DEFAULT_TXD;
383 static int em_smart_pwr_down = 0;
385 /* Controls whether promiscuous also shows bad packets */
386 static int em_debug_sbp = FALSE;
388 static int em_82573_workaround = 1;
389 static int em_msi_enable = 1;
391 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
392 TUNABLE_INT("hw.em.rxd", &em_rxd);
393 TUNABLE_INT("hw.em.txd", &em_txd);
394 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
395 TUNABLE_INT("hw.em.sbp", &em_debug_sbp);
396 TUNABLE_INT("hw.em.82573_workaround", &em_82573_workaround);
397 TUNABLE_INT("hw.em.msi.enable", &em_msi_enable);
399 /* Global used in WOL setup with multiport cards */
400 static int em_global_quad_port_a = 0;
402 /* Set this to one to display debug statistics */
403 static int em_display_debug_stats = 0;
405 #if !defined(KTR_IF_EM)
406 #define KTR_IF_EM KTR_ALL
408 KTR_INFO_MASTER(if_em);
409 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin");
410 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end");
411 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet");
412 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet");
413 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean");
414 #define logif(name) KTR_LOG(if_em_ ## name)
417 em_probe(device_t dev)
419 const struct em_vendor_info *ent;
422 vid = pci_get_vendor(dev);
423 did = pci_get_device(dev);
425 for (ent = em_vendor_info_array; ent->desc != NULL; ++ent) {
426 if (vid == ent->vendor_id && did == ent->device_id) {
427 device_set_desc(dev, ent->desc);
428 device_set_async_attach(dev, TRUE);
436 em_attach(device_t dev)
438 struct adapter *adapter = device_get_softc(dev);
439 struct ifnet *ifp = &adapter->arpcom.ac_if;
442 uint16_t eeprom_data, device_id, apme_mask;
443 driver_intr_t *intr_func;
445 adapter->dev = adapter->osdep.dev = dev;
447 callout_init_mp(&adapter->timer);
448 callout_init_mp(&adapter->tx_fifo_timer);
450 /* Determine hardware and mac info */
451 error = em_get_hw_info(adapter);
453 device_printf(dev, "Identify hardware failed\n");
457 /* Setup PCI resources */
458 error = em_alloc_pci_res(adapter);
460 device_printf(dev, "Allocation of PCI resources failed\n");
465 * For ICH8 and family we need to map the flash memory,
466 * and this must happen after the MAC is identified.
468 if (adapter->hw.mac.type == e1000_ich8lan ||
469 adapter->hw.mac.type == e1000_ich9lan ||
470 adapter->hw.mac.type == e1000_ich10lan ||
471 adapter->hw.mac.type == e1000_pchlan ||
472 adapter->hw.mac.type == e1000_pch2lan) {
473 adapter->flash_rid = EM_BAR_FLASH;
475 adapter->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
476 &adapter->flash_rid, RF_ACTIVE);
477 if (adapter->flash == NULL) {
478 device_printf(dev, "Mapping of Flash failed\n");
482 adapter->osdep.flash_bus_space_tag =
483 rman_get_bustag(adapter->flash);
484 adapter->osdep.flash_bus_space_handle =
485 rman_get_bushandle(adapter->flash);
488 * This is used in the shared code
489 * XXX this goof is actually not used.
491 adapter->hw.flash_address = (uint8_t *)adapter->flash;
494 /* Do Shared Code initialization */
495 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) {
496 device_printf(dev, "Setup of Shared code failed\n");
501 e1000_get_bus_info(&adapter->hw);
504 * Validate number of transmit and receive descriptors. It
505 * must not exceed hardware maximum, and must be multiple
506 * of E1000_DBA_ALIGN.
508 if ((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN != 0 ||
509 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) ||
510 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) ||
511 em_txd < EM_MIN_TXD) {
512 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
513 EM_DEFAULT_TXD, em_txd);
514 adapter->num_tx_desc = EM_DEFAULT_TXD;
516 adapter->num_tx_desc = em_txd;
518 if ((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN != 0 ||
519 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) ||
520 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) ||
521 em_rxd < EM_MIN_RXD) {
522 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
523 EM_DEFAULT_RXD, em_rxd);
524 adapter->num_rx_desc = EM_DEFAULT_RXD;
526 adapter->num_rx_desc = em_rxd;
529 adapter->hw.mac.autoneg = DO_AUTO_NEG;
530 adapter->hw.phy.autoneg_wait_to_complete = FALSE;
531 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
532 adapter->rx_buffer_len = MCLBYTES;
535 * Interrupt throttle rate
537 if (em_int_throttle_ceil == 0) {
538 adapter->int_throttle_ceil = 0;
540 int throttle = em_int_throttle_ceil;
543 throttle = EM_DEFAULT_ITR;
545 /* Recalculate the tunable value to get the exact frequency. */
546 throttle = 1000000000 / 256 / throttle;
548 /* Upper 16bits of ITR is reserved and should be zero */
549 if (throttle & 0xffff0000)
550 throttle = 1000000000 / 256 / EM_DEFAULT_ITR;
552 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
555 e1000_init_script_state_82541(&adapter->hw, TRUE);
556 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE);
559 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
560 adapter->hw.phy.mdix = AUTO_ALL_MODES;
561 adapter->hw.phy.disable_polarity_correction = FALSE;
562 adapter->hw.phy.ms_type = EM_MASTER_SLAVE;
565 /* Set the frame limits assuming standard ethernet sized frames. */
566 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
567 adapter->min_frame_size = ETH_ZLEN + ETHER_CRC_LEN;
569 /* This controls when hardware reports transmit completion status. */
570 adapter->hw.mac.report_tx_early = 1;
573 * Create top level busdma tag
575 error = bus_dma_tag_create(NULL, 1, 0,
576 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
578 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
579 0, &adapter->parent_dtag);
581 device_printf(dev, "could not create top level DMA tag\n");
586 * Allocate Transmit Descriptor ring
588 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc),
590 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
592 device_printf(dev, "Unable to allocate tx_desc memory\n");
595 adapter->tx_desc_base = adapter->txdma.dma_vaddr;
598 * Allocate Receive Descriptor ring
600 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc),
602 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
604 device_printf(dev, "Unable to allocate rx_desc memory\n");
607 adapter->rx_desc_base = adapter->rxdma.dma_vaddr;
609 /* Allocate multicast array memory. */
610 adapter->mta = kmalloc(ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
613 /* Indicate SOL/IDER usage */
614 if (e1000_check_reset_block(&adapter->hw)) {
616 "PHY reset is blocked due to SOL/IDER session.\n");
620 * Start from a known state, this is important in reading the
621 * nvm and mac from that.
623 e1000_reset_hw(&adapter->hw);
625 /* Make sure we have a good EEPROM before we read from it */
626 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
628 * Some PCI-E parts fail the first check due to
629 * the link being in sleep state, call it again,
630 * if it fails a second time its a real issue.
632 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) {
634 "The EEPROM Checksum Is Not Valid\n");
640 /* Copy the permanent MAC address out of the EEPROM */
641 if (e1000_read_mac_addr(&adapter->hw) < 0) {
642 device_printf(dev, "EEPROM read error while reading MAC"
647 if (!em_is_valid_eaddr(adapter->hw.mac.addr)) {
648 device_printf(dev, "Invalid MAC address\n");
653 /* Allocate transmit descriptors and buffers */
654 error = em_create_tx_ring(adapter);
656 device_printf(dev, "Could not setup transmit structures\n");
660 /* Allocate receive descriptors and buffers */
661 error = em_create_rx_ring(adapter);
663 device_printf(dev, "Could not setup receive structures\n");
667 /* Manually turn off all interrupts */
668 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
670 /* Determine if we have to control management hardware */
671 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
676 apme_mask = EM_EEPROM_APME;
678 switch (adapter->hw.mac.type) {
685 adapter->has_amt = 1;
689 case e1000_82546_rev_3:
692 case e1000_80003es2lan:
693 if (adapter->hw.bus.func == 1) {
694 e1000_read_nvm(&adapter->hw,
695 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
697 e1000_read_nvm(&adapter->hw,
698 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
707 apme_mask = E1000_WUC_APME;
708 adapter->has_amt = TRUE;
709 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC);
713 e1000_read_nvm(&adapter->hw,
714 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
717 if (eeprom_data & apme_mask)
718 adapter->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
721 * We have the eeprom settings, now apply the special cases
722 * where the eeprom may be wrong or the board won't support
723 * wake on lan on a particular port
725 device_id = pci_get_device(dev);
727 case E1000_DEV_ID_82546GB_PCIE:
731 case E1000_DEV_ID_82546EB_FIBER:
732 case E1000_DEV_ID_82546GB_FIBER:
733 case E1000_DEV_ID_82571EB_FIBER:
735 * Wake events only supported on port A for dual fiber
736 * regardless of eeprom setting
738 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
743 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
744 case E1000_DEV_ID_82571EB_QUAD_COPPER:
745 case E1000_DEV_ID_82571EB_QUAD_FIBER:
746 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
747 /* if quad port adapter, disable WoL on all but port A */
748 if (em_global_quad_port_a != 0)
750 /* Reset for multiple quad port adapters */
751 if (++em_global_quad_port_a == 4)
752 em_global_quad_port_a = 0;
756 /* XXX disable wol */
759 /* Setup OS specific network interface */
760 em_setup_ifp(adapter);
762 /* Add sysctl tree, must after em_setup_ifp() */
763 em_add_sysctl(adapter);
765 /* Reset the hardware */
766 error = em_reset(adapter);
768 device_printf(dev, "Unable to reset the hardware\n");
772 /* Initialize statistics */
773 em_update_stats(adapter);
775 adapter->hw.mac.get_link_status = 1;
776 em_update_link_status(adapter);
778 /* Do we need workaround for 82544 PCI-X adapter? */
779 if (adapter->hw.bus.type == e1000_bus_type_pcix &&
780 adapter->hw.mac.type == e1000_82544)
781 adapter->pcix_82544 = TRUE;
783 adapter->pcix_82544 = FALSE;
785 if (adapter->pcix_82544) {
787 * 82544 on PCI-X may split one TX segment
788 * into two TX descs, so we double its number
789 * of spare TX desc here.
791 adapter->spare_tx_desc = 2 * EM_TX_SPARE;
793 adapter->spare_tx_desc = EM_TX_SPARE;
797 * Keep following relationship between spare_tx_desc, oact_tx_desc
799 * (spare_tx_desc + EM_TX_RESERVED) <=
800 * oact_tx_desc <= EM_TX_OACTIVE_MAX <= tx_int_nsegs
802 adapter->oact_tx_desc = adapter->num_tx_desc / 8;
803 if (adapter->oact_tx_desc > EM_TX_OACTIVE_MAX)
804 adapter->oact_tx_desc = EM_TX_OACTIVE_MAX;
805 if (adapter->oact_tx_desc < adapter->spare_tx_desc + EM_TX_RESERVED)
806 adapter->oact_tx_desc = adapter->spare_tx_desc + EM_TX_RESERVED;
808 adapter->tx_int_nsegs = adapter->num_tx_desc / 16;
809 if (adapter->tx_int_nsegs < adapter->oact_tx_desc)
810 adapter->tx_int_nsegs = adapter->oact_tx_desc;
812 /* Non-AMT based hardware can now take control from firmware */
813 if (adapter->has_manage && !adapter->has_amt &&
814 adapter->hw.mac.type >= e1000_82571)
815 em_get_hw_control(adapter);
818 * Missing Interrupt Following ICR read:
820 * 82571/82572 specification update #76
821 * 82573 specification update #31
822 * 82574 specification update #12
823 * 82583 specification update #4
826 if ((adapter->flags & EM_FLAG_SHARED_INTR) &&
827 (adapter->hw.mac.type == e1000_82571 ||
828 adapter->hw.mac.type == e1000_82572 ||
829 adapter->hw.mac.type == e1000_82573 ||
830 adapter->hw.mac.type == e1000_82574 ||
831 adapter->hw.mac.type == e1000_82583))
832 intr_func = em_intr_mask;
834 error = bus_setup_intr(dev, adapter->intr_res, INTR_MPSAFE,
835 intr_func, adapter, &adapter->intr_tag,
838 device_printf(dev, "Failed to register interrupt handler");
839 ether_ifdetach(&adapter->arpcom.ac_if);
843 ifp->if_cpuid = rman_get_cpuid(adapter->intr_res);
844 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
852 em_detach(device_t dev)
854 struct adapter *adapter = device_get_softc(dev);
856 if (device_is_attached(dev)) {
857 struct ifnet *ifp = &adapter->arpcom.ac_if;
859 lwkt_serialize_enter(ifp->if_serializer);
863 e1000_phy_hw_reset(&adapter->hw);
865 em_rel_mgmt(adapter);
866 em_rel_hw_control(adapter);
869 E1000_WRITE_REG(&adapter->hw, E1000_WUC,
871 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
875 bus_teardown_intr(dev, adapter->intr_res, adapter->intr_tag);
877 lwkt_serialize_exit(ifp->if_serializer);
881 em_rel_hw_control(adapter);
883 bus_generic_detach(dev);
885 em_free_pci_res(adapter);
887 em_destroy_tx_ring(adapter, adapter->num_tx_desc);
888 em_destroy_rx_ring(adapter, adapter->num_rx_desc);
890 /* Free Transmit Descriptor ring */
891 if (adapter->tx_desc_base)
892 em_dma_free(adapter, &adapter->txdma);
894 /* Free Receive Descriptor ring */
895 if (adapter->rx_desc_base)
896 em_dma_free(adapter, &adapter->rxdma);
898 /* Free top level busdma tag */
899 if (adapter->parent_dtag != NULL)
900 bus_dma_tag_destroy(adapter->parent_dtag);
902 /* Free sysctl tree */
903 if (adapter->sysctl_tree != NULL)
904 sysctl_ctx_free(&adapter->sysctl_ctx);
910 em_shutdown(device_t dev)
912 return em_suspend(dev);
916 em_suspend(device_t dev)
918 struct adapter *adapter = device_get_softc(dev);
919 struct ifnet *ifp = &adapter->arpcom.ac_if;
921 lwkt_serialize_enter(ifp->if_serializer);
925 em_rel_mgmt(adapter);
926 em_rel_hw_control(adapter);
929 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN);
930 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol);
934 lwkt_serialize_exit(ifp->if_serializer);
936 return bus_generic_suspend(dev);
940 em_resume(device_t dev)
942 struct adapter *adapter = device_get_softc(dev);
943 struct ifnet *ifp = &adapter->arpcom.ac_if;
945 lwkt_serialize_enter(ifp->if_serializer);
948 em_get_mgmt(adapter);
951 lwkt_serialize_exit(ifp->if_serializer);
953 return bus_generic_resume(dev);
957 em_start(struct ifnet *ifp)
959 struct adapter *adapter = ifp->if_softc;
962 ASSERT_SERIALIZED(ifp->if_serializer);
964 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
967 if (!adapter->link_active) {
968 ifq_purge(&ifp->if_snd);
972 while (!ifq_is_empty(&ifp->if_snd)) {
973 /* Now do we at least have a minimal? */
974 if (EM_IS_OACTIVE(adapter)) {
975 em_tx_collect(adapter);
976 if (EM_IS_OACTIVE(adapter)) {
977 ifp->if_flags |= IFF_OACTIVE;
978 adapter->no_tx_desc_avail1++;
984 m_head = ifq_dequeue(&ifp->if_snd, NULL);
988 if (em_encap(adapter, &m_head)) {
990 em_tx_collect(adapter);
994 /* Send a copy of the frame to the BPF listener */
995 ETHER_BPF_MTAP(ifp, m_head);
997 /* Set timeout in case hardware has problems transmitting. */
998 ifp->if_timer = EM_TX_TIMEOUT;
1003 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1005 struct adapter *adapter = ifp->if_softc;
1006 struct ifreq *ifr = (struct ifreq *)data;
1007 uint16_t eeprom_data = 0;
1008 int max_frame_size, mask, reinit;
1011 ASSERT_SERIALIZED(ifp->if_serializer);
1015 switch (adapter->hw.mac.type) {
1018 * 82573 only supports jumbo frames
1019 * if ASPM is disabled.
1021 e1000_read_nvm(&adapter->hw,
1022 NVM_INIT_3GIO_3, 1, &eeprom_data);
1023 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1024 max_frame_size = ETHER_MAX_LEN;
1029 /* Limit Jumbo Frame size */
1033 case e1000_ich10lan:
1037 case e1000_80003es2lan:
1038 max_frame_size = 9234;
1042 max_frame_size = 4096;
1045 /* Adapters that do not support jumbo frames */
1048 max_frame_size = ETHER_MAX_LEN;
1052 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1055 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1061 ifp->if_mtu = ifr->ifr_mtu;
1062 adapter->max_frame_size =
1063 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
1065 if (ifp->if_flags & IFF_RUNNING)
1070 if (ifp->if_flags & IFF_UP) {
1071 if ((ifp->if_flags & IFF_RUNNING)) {
1072 if ((ifp->if_flags ^ adapter->if_flags) &
1073 (IFF_PROMISC | IFF_ALLMULTI)) {
1074 em_disable_promisc(adapter);
1075 em_set_promisc(adapter);
1080 } else if (ifp->if_flags & IFF_RUNNING) {
1083 adapter->if_flags = ifp->if_flags;
1088 if (ifp->if_flags & IFF_RUNNING) {
1089 em_disable_intr(adapter);
1090 em_set_multi(adapter);
1091 if (adapter->hw.mac.type == e1000_82542 &&
1092 adapter->hw.revision_id == E1000_REVISION_2)
1093 em_init_rx_unit(adapter);
1094 #ifdef DEVICE_POLLING
1095 if (!(ifp->if_flags & IFF_POLLING))
1097 em_enable_intr(adapter);
1102 /* Check SOL/IDER usage */
1103 if (e1000_check_reset_block(&adapter->hw)) {
1104 device_printf(adapter->dev, "Media change is"
1105 " blocked due to SOL/IDER session.\n");
1111 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
1116 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1117 if (mask & IFCAP_HWCSUM) {
1118 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
1121 if (mask & IFCAP_VLAN_HWTAGGING) {
1122 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1125 if (reinit && (ifp->if_flags & IFF_RUNNING))
1130 error = ether_ioctl(ifp, command, data);
1137 em_watchdog(struct ifnet *ifp)
1139 struct adapter *adapter = ifp->if_softc;
1141 ASSERT_SERIALIZED(ifp->if_serializer);
1144 * The timer is set to 5 every time start queues a packet.
1145 * Then txeof keeps resetting it as long as it cleans at
1146 * least one descriptor.
1147 * Finally, anytime all descriptors are clean the timer is
1151 if (E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1152 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) {
1154 * If we reach here, all TX jobs are completed and
1155 * the TX engine should have been idled for some time.
1156 * We don't need to call if_devstart() here.
1158 ifp->if_flags &= ~IFF_OACTIVE;
1164 * If we are in this routine because of pause frames, then
1165 * don't reset the hardware.
1167 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) &
1168 E1000_STATUS_TXOFF) {
1169 ifp->if_timer = EM_TX_TIMEOUT;
1173 if (e1000_check_for_link(&adapter->hw) == 0)
1174 if_printf(ifp, "watchdog timeout -- resetting\n");
1177 adapter->watchdog_events++;
1181 if (!ifq_is_empty(&ifp->if_snd))
1188 struct adapter *adapter = xsc;
1189 struct ifnet *ifp = &adapter->arpcom.ac_if;
1190 device_t dev = adapter->dev;
1193 ASSERT_SERIALIZED(ifp->if_serializer);
1198 * Packet Buffer Allocation (PBA)
1199 * Writing PBA sets the receive portion of the buffer
1200 * the remainder is used for the transmit buffer.
1202 * Devices before the 82547 had a Packet Buffer of 64K.
1203 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1204 * After the 82547 the buffer was reduced to 40K.
1205 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1206 * Note: default does not leave enough room for Jumbo Frame >10k.
1208 switch (adapter->hw.mac.type) {
1210 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1211 if (adapter->max_frame_size > 8192)
1212 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1214 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1215 adapter->tx_fifo_head = 0;
1216 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1217 adapter->tx_fifo_size =
1218 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1221 /* Total Packet Buffer on these is 48K */
1224 case e1000_80003es2lan:
1225 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1228 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1229 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1234 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1242 case e1000_ich10lan:
1243 #define E1000_PBA_10K 0x000A
1244 pba = E1000_PBA_10K;
1249 pba = E1000_PBA_26K;
1253 /* Devices before 82547 had a Packet Buffer of 64K. */
1254 if (adapter->max_frame_size > 8192)
1255 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1257 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1259 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
1261 /* Get the latest mac address, User can use a LAA */
1262 bcopy(IF_LLADDR(ifp), adapter->hw.mac.addr, ETHER_ADDR_LEN);
1264 /* Put the address into the Receive Address Array */
1265 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
1268 * With the 82571 adapter, RAR[0] may be overwritten
1269 * when the other port is reset, we make a duplicate
1270 * in RAR[14] for that eventuality, this assures
1271 * the interface continues to function.
1273 if (adapter->hw.mac.type == e1000_82571) {
1274 e1000_set_laa_state_82571(&adapter->hw, TRUE);
1275 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr,
1276 E1000_RAR_ENTRIES - 1);
1279 /* Reset the hardware */
1280 if (em_reset(adapter)) {
1281 device_printf(dev, "Unable to reset the hardware\n");
1282 /* XXX em_stop()? */
1285 em_update_link_status(adapter);
1287 /* Setup VLAN support, basic and offload if available */
1288 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
1290 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1293 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL);
1294 ctrl |= E1000_CTRL_VME;
1295 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl);
1298 /* Set hardware offload abilities */
1299 if (ifp->if_capenable & IFCAP_TXCSUM)
1300 ifp->if_hwassist = EM_CSUM_FEATURES;
1302 ifp->if_hwassist = 0;
1304 /* Configure for OS presence */
1305 em_get_mgmt(adapter);
1307 /* Prepare transmit descriptors and buffers */
1308 em_init_tx_ring(adapter);
1309 em_init_tx_unit(adapter);
1311 /* Setup Multicast table */
1312 em_set_multi(adapter);
1314 /* Prepare receive descriptors and buffers */
1315 if (em_init_rx_ring(adapter)) {
1316 device_printf(dev, "Could not setup receive structures\n");
1320 em_init_rx_unit(adapter);
1322 /* Don't lose promiscuous settings */
1323 em_set_promisc(adapter);
1325 ifp->if_flags |= IFF_RUNNING;
1326 ifp->if_flags &= ~IFF_OACTIVE;
1328 callout_reset(&adapter->timer, hz, em_timer, adapter);
1329 e1000_clear_hw_cntrs_base_generic(&adapter->hw);
1331 /* MSI/X configuration for 82574 */
1332 if (adapter->hw.mac.type == e1000_82574) {
1335 tmp = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
1336 tmp |= E1000_CTRL_EXT_PBA_CLR;
1337 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, tmp);
1340 * Set the IVAR - interrupt vector routing.
1341 * Each nibble represents a vector, high bit
1342 * is enable, other 3 bits are the MSIX table
1343 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1344 * Link (other) to 2, hence the magic number.
1346 E1000_WRITE_REG(&adapter->hw, E1000_IVAR, 0x800A0908);
1349 #ifdef DEVICE_POLLING
1351 * Only enable interrupts if we are not polling, make sure
1352 * they are off otherwise.
1354 if (ifp->if_flags & IFF_POLLING)
1355 em_disable_intr(adapter);
1357 #endif /* DEVICE_POLLING */
1358 em_enable_intr(adapter);
1360 /* AMT based hardware can now take control from firmware */
1361 if (adapter->has_manage && adapter->has_amt &&
1362 adapter->hw.mac.type >= e1000_82571)
1363 em_get_hw_control(adapter);
1365 /* Don't reset the phy next time init gets called */
1366 adapter->hw.phy.reset_disable = TRUE;
1369 #ifdef DEVICE_POLLING
1372 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1374 struct adapter *adapter = ifp->if_softc;
1377 ASSERT_SERIALIZED(ifp->if_serializer);
1381 em_disable_intr(adapter);
1384 case POLL_DEREGISTER:
1385 em_enable_intr(adapter);
1388 case POLL_AND_CHECK_STATUS:
1389 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1390 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1391 callout_stop(&adapter->timer);
1392 adapter->hw.mac.get_link_status = 1;
1393 em_update_link_status(adapter);
1394 callout_reset(&adapter->timer, hz, em_timer, adapter);
1398 if (ifp->if_flags & IFF_RUNNING) {
1399 em_rxeof(adapter, count);
1402 if (!ifq_is_empty(&ifp->if_snd))
1409 #endif /* DEVICE_POLLING */
1414 em_intr_body(xsc, TRUE);
1418 em_intr_body(struct adapter *adapter, boolean_t chk_asserted)
1420 struct ifnet *ifp = &adapter->arpcom.ac_if;
1424 ASSERT_SERIALIZED(ifp->if_serializer);
1426 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR);
1429 ((adapter->hw.mac.type >= e1000_82571 &&
1430 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1437 * XXX: some laptops trigger several spurious interrupts
1438 * on em(4) when in the resume cycle. The ICR register
1439 * reports all-ones value in this case. Processing such
1440 * interrupts would lead to a freeze. I don't know why.
1442 if (reg_icr == 0xffffffff) {
1447 if (ifp->if_flags & IFF_RUNNING) {
1449 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO))
1450 em_rxeof(adapter, -1);
1451 if (reg_icr & E1000_ICR_TXDW) {
1453 if (!ifq_is_empty(&ifp->if_snd))
1458 /* Link status change */
1459 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1460 callout_stop(&adapter->timer);
1461 adapter->hw.mac.get_link_status = 1;
1462 em_update_link_status(adapter);
1464 /* Deal with TX cruft when link lost */
1465 em_tx_purge(adapter);
1467 callout_reset(&adapter->timer, hz, em_timer, adapter);
1470 if (reg_icr & E1000_ICR_RXO)
1471 adapter->rx_overruns++;
1477 em_intr_mask(void *xsc)
1479 struct adapter *adapter = xsc;
1481 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff);
1484 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1485 * so don't check it.
1487 em_intr_body(adapter, FALSE);
1488 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
1492 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1494 struct adapter *adapter = ifp->if_softc;
1495 u_char fiber_type = IFM_1000_SX;
1497 ASSERT_SERIALIZED(ifp->if_serializer);
1499 em_update_link_status(adapter);
1501 ifmr->ifm_status = IFM_AVALID;
1502 ifmr->ifm_active = IFM_ETHER;
1504 if (!adapter->link_active)
1507 ifmr->ifm_status |= IFM_ACTIVE;
1509 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
1510 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
1511 if (adapter->hw.mac.type == e1000_82545)
1512 fiber_type = IFM_1000_LX;
1513 ifmr->ifm_active |= fiber_type | IFM_FDX;
1515 switch (adapter->link_speed) {
1517 ifmr->ifm_active |= IFM_10_T;
1520 ifmr->ifm_active |= IFM_100_TX;
1524 ifmr->ifm_active |= IFM_1000_T;
1527 if (adapter->link_duplex == FULL_DUPLEX)
1528 ifmr->ifm_active |= IFM_FDX;
1530 ifmr->ifm_active |= IFM_HDX;
1535 em_media_change(struct ifnet *ifp)
1537 struct adapter *adapter = ifp->if_softc;
1538 struct ifmedia *ifm = &adapter->media;
1540 ASSERT_SERIALIZED(ifp->if_serializer);
1542 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1545 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1547 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1548 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1554 adapter->hw.mac.autoneg = DO_AUTO_NEG;
1555 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1559 adapter->hw.mac.autoneg = FALSE;
1560 adapter->hw.phy.autoneg_advertised = 0;
1561 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1562 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1564 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1568 adapter->hw.mac.autoneg = FALSE;
1569 adapter->hw.phy.autoneg_advertised = 0;
1570 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1571 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1573 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1577 if_printf(ifp, "Unsupported media type\n");
1582 * As the speed/duplex settings my have changed we need to
1585 adapter->hw.phy.reset_disable = FALSE;
1593 em_encap(struct adapter *adapter, struct mbuf **m_headp)
1595 bus_dma_segment_t segs[EM_MAX_SCATTER];
1597 struct em_buffer *tx_buffer, *tx_buffer_mapped;
1598 struct e1000_tx_desc *ctxd = NULL;
1599 struct mbuf *m_head = *m_headp;
1600 uint32_t txd_upper, txd_lower, txd_used, cmd = 0;
1601 int maxsegs, nsegs, i, j, first, last = 0, error;
1603 if (m_head->m_len < EM_TXCSUM_MINHL &&
1604 (m_head->m_flags & EM_CSUM_FEATURES)) {
1606 * Make sure that ethernet header and ip.ip_hl are in
1607 * contiguous memory, since if TXCSUM is enabled, later
1608 * TX context descriptor's setup need to access ip.ip_hl.
1610 error = em_txcsum_pullup(adapter, m_headp);
1612 KKASSERT(*m_headp == NULL);
1618 txd_upper = txd_lower = 0;
1622 * Capture the first descriptor index, this descriptor
1623 * will have the index of the EOP which is the only one
1624 * that now gets a DONE bit writeback.
1626 first = adapter->next_avail_tx_desc;
1627 tx_buffer = &adapter->tx_buffer_area[first];
1628 tx_buffer_mapped = tx_buffer;
1629 map = tx_buffer->map;
1631 maxsegs = adapter->num_tx_desc_avail - EM_TX_RESERVED;
1632 KASSERT(maxsegs >= adapter->spare_tx_desc,
1633 ("not enough spare TX desc"));
1634 if (adapter->pcix_82544) {
1635 /* Half it; see the comment in em_attach() */
1638 if (maxsegs > EM_MAX_SCATTER)
1639 maxsegs = EM_MAX_SCATTER;
1641 error = bus_dmamap_load_mbuf_defrag(adapter->txtag, map, m_headp,
1642 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1644 if (error == ENOBUFS)
1645 adapter->mbuf_alloc_failed++;
1647 adapter->no_tx_dma_setup++;
1653 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1656 adapter->tx_nsegs += nsegs;
1658 if (m_head->m_pkthdr.csum_flags & EM_CSUM_FEATURES) {
1659 /* TX csum offloading will consume one TX desc */
1660 adapter->tx_nsegs += em_txcsum(adapter, m_head,
1661 &txd_upper, &txd_lower);
1663 i = adapter->next_avail_tx_desc;
1665 /* Set up our transmit descriptors */
1666 for (j = 0; j < nsegs; j++) {
1667 /* If adapter is 82544 and on PCIX bus */
1668 if(adapter->pcix_82544) {
1669 DESC_ARRAY desc_array;
1670 uint32_t array_elements, counter;
1673 * Check the Address and Length combination and
1674 * split the data accordingly
1676 array_elements = em_82544_fill_desc(segs[j].ds_addr,
1677 segs[j].ds_len, &desc_array);
1678 for (counter = 0; counter < array_elements; counter++) {
1679 KKASSERT(txd_used < adapter->num_tx_desc_avail);
1681 tx_buffer = &adapter->tx_buffer_area[i];
1682 ctxd = &adapter->tx_desc_base[i];
1684 ctxd->buffer_addr = htole64(
1685 desc_array.descriptor[counter].address);
1686 ctxd->lower.data = htole32(
1687 E1000_TXD_CMD_IFCS | txd_lower |
1688 desc_array.descriptor[counter].length);
1689 ctxd->upper.data = htole32(txd_upper);
1692 if (++i == adapter->num_tx_desc)
1698 tx_buffer = &adapter->tx_buffer_area[i];
1699 ctxd = &adapter->tx_desc_base[i];
1701 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1702 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1703 txd_lower | segs[j].ds_len);
1704 ctxd->upper.data = htole32(txd_upper);
1707 if (++i == adapter->num_tx_desc)
1712 adapter->next_avail_tx_desc = i;
1713 if (adapter->pcix_82544) {
1714 KKASSERT(adapter->num_tx_desc_avail > txd_used);
1715 adapter->num_tx_desc_avail -= txd_used;
1717 KKASSERT(adapter->num_tx_desc_avail > nsegs);
1718 adapter->num_tx_desc_avail -= nsegs;
1721 /* Handle VLAN tag */
1722 if (m_head->m_flags & M_VLANTAG) {
1723 /* Set the vlan id. */
1724 ctxd->upper.fields.special =
1725 htole16(m_head->m_pkthdr.ether_vlantag);
1727 /* Tell hardware to add tag */
1728 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1731 tx_buffer->m_head = m_head;
1732 tx_buffer_mapped->map = tx_buffer->map;
1733 tx_buffer->map = map;
1735 if (adapter->tx_nsegs >= adapter->tx_int_nsegs) {
1736 adapter->tx_nsegs = 0;
1739 * Report Status (RS) is turned on
1740 * every tx_int_nsegs descriptors.
1742 cmd = E1000_TXD_CMD_RS;
1745 * Keep track of the descriptor, which will
1746 * be written back by hardware.
1748 adapter->tx_dd[adapter->tx_dd_tail] = last;
1749 EM_INC_TXDD_IDX(adapter->tx_dd_tail);
1750 KKASSERT(adapter->tx_dd_tail != adapter->tx_dd_head);
1754 * Last Descriptor of Packet needs End Of Packet (EOP)
1756 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1759 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
1760 * that this frame is available to transmit.
1762 if (adapter->hw.mac.type == e1000_82547 &&
1763 adapter->link_duplex == HALF_DUPLEX) {
1764 em_82547_move_tail_serialized(adapter);
1766 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i);
1767 if (adapter->hw.mac.type == e1000_82547) {
1768 em_82547_update_fifo_head(adapter,
1769 m_head->m_pkthdr.len);
1776 * 82547 workaround to avoid controller hang in half-duplex environment.
1777 * The workaround is to avoid queuing a large packet that would span
1778 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1779 * in this case. We do that only when FIFO is quiescent.
1782 em_82547_move_tail_serialized(struct adapter *adapter)
1784 struct e1000_tx_desc *tx_desc;
1785 uint16_t hw_tdt, sw_tdt, length = 0;
1788 ASSERT_SERIALIZED(adapter->arpcom.ac_if.if_serializer);
1790 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0));
1791 sw_tdt = adapter->next_avail_tx_desc;
1793 while (hw_tdt != sw_tdt) {
1794 tx_desc = &adapter->tx_desc_base[hw_tdt];
1795 length += tx_desc->lower.flags.length;
1796 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1797 if (++hw_tdt == adapter->num_tx_desc)
1801 if (em_82547_fifo_workaround(adapter, length)) {
1802 adapter->tx_fifo_wrk_cnt++;
1803 callout_reset(&adapter->tx_fifo_timer, 1,
1804 em_82547_move_tail, adapter);
1807 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt);
1808 em_82547_update_fifo_head(adapter, length);
1815 em_82547_move_tail(void *xsc)
1817 struct adapter *adapter = xsc;
1818 struct ifnet *ifp = &adapter->arpcom.ac_if;
1820 lwkt_serialize_enter(ifp->if_serializer);
1821 em_82547_move_tail_serialized(adapter);
1822 lwkt_serialize_exit(ifp->if_serializer);
1826 em_82547_fifo_workaround(struct adapter *adapter, int len)
1828 int fifo_space, fifo_pkt_len;
1830 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1832 if (adapter->link_duplex == HALF_DUPLEX) {
1833 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1835 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1836 if (em_82547_tx_fifo_reset(adapter))
1846 em_82547_update_fifo_head(struct adapter *adapter, int len)
1848 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1850 /* tx_fifo_head is always 16 byte aligned */
1851 adapter->tx_fifo_head += fifo_pkt_len;
1852 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1853 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1857 em_82547_tx_fifo_reset(struct adapter *adapter)
1861 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) ==
1862 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) &&
1863 (E1000_READ_REG(&adapter->hw, E1000_TDFT) ==
1864 E1000_READ_REG(&adapter->hw, E1000_TDFH)) &&
1865 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) ==
1866 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) &&
1867 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) {
1868 /* Disable TX unit */
1869 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
1870 E1000_WRITE_REG(&adapter->hw, E1000_TCTL,
1871 tctl & ~E1000_TCTL_EN);
1873 /* Reset FIFO pointers */
1874 E1000_WRITE_REG(&adapter->hw, E1000_TDFT,
1875 adapter->tx_head_addr);
1876 E1000_WRITE_REG(&adapter->hw, E1000_TDFH,
1877 adapter->tx_head_addr);
1878 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS,
1879 adapter->tx_head_addr);
1880 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS,
1881 adapter->tx_head_addr);
1883 /* Re-enable TX unit */
1884 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
1885 E1000_WRITE_FLUSH(&adapter->hw);
1887 adapter->tx_fifo_head = 0;
1888 adapter->tx_fifo_reset_cnt++;
1897 em_set_promisc(struct adapter *adapter)
1899 struct ifnet *ifp = &adapter->arpcom.ac_if;
1902 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1904 if (ifp->if_flags & IFF_PROMISC) {
1905 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1906 /* Turn this on if you want to see bad packets */
1908 reg_rctl |= E1000_RCTL_SBP;
1909 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1910 } else if (ifp->if_flags & IFF_ALLMULTI) {
1911 reg_rctl |= E1000_RCTL_MPE;
1912 reg_rctl &= ~E1000_RCTL_UPE;
1913 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1918 em_disable_promisc(struct adapter *adapter)
1922 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1924 reg_rctl &= ~E1000_RCTL_UPE;
1925 reg_rctl &= ~E1000_RCTL_MPE;
1926 reg_rctl &= ~E1000_RCTL_SBP;
1927 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1931 em_set_multi(struct adapter *adapter)
1933 struct ifnet *ifp = &adapter->arpcom.ac_if;
1934 struct ifmultiaddr *ifma;
1935 uint32_t reg_rctl = 0;
1940 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1942 if (adapter->hw.mac.type == e1000_82542 &&
1943 adapter->hw.revision_id == E1000_REVISION_2) {
1944 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1945 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1946 e1000_pci_clear_mwi(&adapter->hw);
1947 reg_rctl |= E1000_RCTL_RST;
1948 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1952 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1953 if (ifma->ifma_addr->sa_family != AF_LINK)
1956 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1959 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1960 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1964 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1965 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1966 reg_rctl |= E1000_RCTL_MPE;
1967 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1969 e1000_update_mc_addr_list(&adapter->hw, mta, mcnt);
1972 if (adapter->hw.mac.type == e1000_82542 &&
1973 adapter->hw.revision_id == E1000_REVISION_2) {
1974 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
1975 reg_rctl &= ~E1000_RCTL_RST;
1976 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl);
1978 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1979 e1000_pci_set_mwi(&adapter->hw);
1984 * This routine checks for link status and updates statistics.
1989 struct adapter *adapter = xsc;
1990 struct ifnet *ifp = &adapter->arpcom.ac_if;
1992 lwkt_serialize_enter(ifp->if_serializer);
1994 em_update_link_status(adapter);
1995 em_update_stats(adapter);
1997 /* Reset LAA into RAR[0] on 82571 */
1998 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE)
1999 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2001 if (em_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
2002 em_print_hw_stats(adapter);
2004 em_smartspeed(adapter);
2006 callout_reset(&adapter->timer, hz, em_timer, adapter);
2008 lwkt_serialize_exit(ifp->if_serializer);
2012 em_update_link_status(struct adapter *adapter)
2014 struct e1000_hw *hw = &adapter->hw;
2015 struct ifnet *ifp = &adapter->arpcom.ac_if;
2016 device_t dev = adapter->dev;
2017 uint32_t link_check = 0;
2019 /* Get the cached link value or read phy for real */
2020 switch (hw->phy.media_type) {
2021 case e1000_media_type_copper:
2022 if (hw->mac.get_link_status) {
2023 /* Do the work to read phy */
2024 e1000_check_for_link(hw);
2025 link_check = !hw->mac.get_link_status;
2026 if (link_check) /* ESB2 fix */
2027 e1000_cfg_on_link_up(hw);
2033 case e1000_media_type_fiber:
2034 e1000_check_for_link(hw);
2036 E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
2039 case e1000_media_type_internal_serdes:
2040 e1000_check_for_link(hw);
2041 link_check = adapter->hw.mac.serdes_has_link;
2044 case e1000_media_type_unknown:
2049 /* Now check for a transition */
2050 if (link_check && adapter->link_active == 0) {
2051 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
2052 &adapter->link_duplex);
2055 * Check if we should enable/disable SPEED_MODE bit on
2058 if (adapter->link_speed != SPEED_1000 &&
2059 (hw->mac.type == e1000_82571 ||
2060 hw->mac.type == e1000_82572)) {
2063 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
2064 tarc0 &= ~SPEED_MODE_BIT;
2065 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
2068 device_printf(dev, "Link is up %d Mbps %s\n",
2069 adapter->link_speed,
2070 ((adapter->link_duplex == FULL_DUPLEX) ?
2071 "Full Duplex" : "Half Duplex"));
2073 adapter->link_active = 1;
2074 adapter->smartspeed = 0;
2075 ifp->if_baudrate = adapter->link_speed * 1000000;
2076 ifp->if_link_state = LINK_STATE_UP;
2077 if_link_state_change(ifp);
2078 } else if (!link_check && adapter->link_active == 1) {
2079 ifp->if_baudrate = adapter->link_speed = 0;
2080 adapter->link_duplex = 0;
2082 device_printf(dev, "Link is Down\n");
2083 adapter->link_active = 0;
2085 /* Link down, disable watchdog */
2088 ifp->if_link_state = LINK_STATE_DOWN;
2089 if_link_state_change(ifp);
2094 em_stop(struct adapter *adapter)
2096 struct ifnet *ifp = &adapter->arpcom.ac_if;
2099 ASSERT_SERIALIZED(ifp->if_serializer);
2101 em_disable_intr(adapter);
2103 callout_stop(&adapter->timer);
2104 callout_stop(&adapter->tx_fifo_timer);
2106 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2109 e1000_reset_hw(&adapter->hw);
2110 if (adapter->hw.mac.type >= e1000_82544)
2111 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2113 for (i = 0; i < adapter->num_tx_desc; i++) {
2114 struct em_buffer *tx_buffer = &adapter->tx_buffer_area[i];
2116 if (tx_buffer->m_head != NULL) {
2117 bus_dmamap_unload(adapter->txtag, tx_buffer->map);
2118 m_freem(tx_buffer->m_head);
2119 tx_buffer->m_head = NULL;
2123 for (i = 0; i < adapter->num_rx_desc; i++) {
2124 struct em_buffer *rx_buffer = &adapter->rx_buffer_area[i];
2126 if (rx_buffer->m_head != NULL) {
2127 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
2128 m_freem(rx_buffer->m_head);
2129 rx_buffer->m_head = NULL;
2133 if (adapter->fmp != NULL)
2134 m_freem(adapter->fmp);
2135 adapter->fmp = NULL;
2136 adapter->lmp = NULL;
2138 adapter->csum_flags = 0;
2139 adapter->csum_ehlen = 0;
2140 adapter->csum_iphlen = 0;
2142 adapter->tx_dd_head = 0;
2143 adapter->tx_dd_tail = 0;
2144 adapter->tx_nsegs = 0;
2148 em_get_hw_info(struct adapter *adapter)
2150 device_t dev = adapter->dev;
2152 /* Save off the information about this board */
2153 adapter->hw.vendor_id = pci_get_vendor(dev);
2154 adapter->hw.device_id = pci_get_device(dev);
2155 adapter->hw.revision_id = pci_get_revid(dev);
2156 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
2157 adapter->hw.subsystem_device_id = pci_get_subdevice(dev);
2159 /* Do Shared Code Init and Setup */
2160 if (e1000_set_mac_type(&adapter->hw))
2166 em_alloc_pci_res(struct adapter *adapter)
2168 device_t dev = adapter->dev;
2170 int val, rid, msi_enable;
2172 /* Enable bus mastering */
2173 pci_enable_busmaster(dev);
2175 adapter->memory_rid = EM_BAR_MEM;
2176 adapter->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2177 &adapter->memory_rid, RF_ACTIVE);
2178 if (adapter->memory == NULL) {
2179 device_printf(dev, "Unable to allocate bus resource: memory\n");
2182 adapter->osdep.mem_bus_space_tag =
2183 rman_get_bustag(adapter->memory);
2184 adapter->osdep.mem_bus_space_handle =
2185 rman_get_bushandle(adapter->memory);
2187 /* XXX This is quite goofy, it is not actually used */
2188 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
2190 /* Only older adapters use IO mapping */
2191 if (adapter->hw.mac.type > e1000_82543 &&
2192 adapter->hw.mac.type < e1000_82571) {
2193 /* Figure our where our IO BAR is ? */
2194 for (rid = PCIR_BAR(0); rid < PCIR_CARDBUSCIS;) {
2195 val = pci_read_config(dev, rid, 4);
2196 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
2197 adapter->io_rid = rid;
2201 /* check for 64bit BAR */
2202 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
2205 if (rid >= PCIR_CARDBUSCIS) {
2206 device_printf(dev, "Unable to locate IO BAR\n");
2209 adapter->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
2210 &adapter->io_rid, RF_ACTIVE);
2211 if (adapter->ioport == NULL) {
2212 device_printf(dev, "Unable to allocate bus resource: "
2216 adapter->hw.io_base = 0;
2217 adapter->osdep.io_bus_space_tag =
2218 rman_get_bustag(adapter->ioport);
2219 adapter->osdep.io_bus_space_handle =
2220 rman_get_bushandle(adapter->ioport);
2224 * Don't enable MSI on PCI/PCI-X chips, see:
2225 * 82540EP and 82545GM specification update
2227 * Don't enable MSI on 82571/82572, see:
2228 * 82571EB/82572EI specification update
2230 msi_enable = em_msi_enable;
2232 (!pci_is_pcie(dev) ||
2233 adapter->hw.mac.type == e1000_82571 ||
2234 adapter->hw.mac.type == e1000_82572))
2237 adapter->intr_type = pci_alloc_1intr(dev, msi_enable,
2238 &adapter->intr_rid, &intr_flags);
2240 if (adapter->intr_type == PCI_INTR_TYPE_LEGACY) {
2243 unshared = device_getenv_int(dev, "irq.unshared", 0);
2245 adapter->flags |= EM_FLAG_SHARED_INTR;
2247 device_printf(dev, "IRQ shared\n");
2249 intr_flags &= ~RF_SHAREABLE;
2251 device_printf(dev, "IRQ unshared\n");
2255 adapter->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2256 &adapter->intr_rid, intr_flags);
2257 if (adapter->intr_res == NULL) {
2258 device_printf(dev, "Unable to allocate bus resource: "
2263 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
2264 adapter->hw.back = &adapter->osdep;
2269 em_free_pci_res(struct adapter *adapter)
2271 device_t dev = adapter->dev;
2273 if (adapter->intr_res != NULL) {
2274 bus_release_resource(dev, SYS_RES_IRQ,
2275 adapter->intr_rid, adapter->intr_res);
2278 if (adapter->intr_type == PCI_INTR_TYPE_MSI)
2279 pci_release_msi(dev);
2281 if (adapter->memory != NULL) {
2282 bus_release_resource(dev, SYS_RES_MEMORY,
2283 adapter->memory_rid, adapter->memory);
2286 if (adapter->flash != NULL) {
2287 bus_release_resource(dev, SYS_RES_MEMORY,
2288 adapter->flash_rid, adapter->flash);
2291 if (adapter->ioport != NULL) {
2292 bus_release_resource(dev, SYS_RES_IOPORT,
2293 adapter->io_rid, adapter->ioport);
2298 em_reset(struct adapter *adapter)
2300 device_t dev = adapter->dev;
2301 uint16_t rx_buffer_size;
2303 /* When hardware is reset, fifo_head is also reset */
2304 adapter->tx_fifo_head = 0;
2306 /* Set up smart power down as default off on newer adapters. */
2307 if (!em_smart_pwr_down &&
2308 (adapter->hw.mac.type == e1000_82571 ||
2309 adapter->hw.mac.type == e1000_82572)) {
2310 uint16_t phy_tmp = 0;
2312 /* Speed up time to link by disabling smart power down. */
2313 e1000_read_phy_reg(&adapter->hw,
2314 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2315 phy_tmp &= ~IGP02E1000_PM_SPD;
2316 e1000_write_phy_reg(&adapter->hw,
2317 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2321 * These parameters control the automatic generation (Tx) and
2322 * response (Rx) to Ethernet PAUSE frames.
2323 * - High water mark should allow for at least two frames to be
2324 * received after sending an XOFF.
2325 * - Low water mark works best when it is very near the high water mark.
2326 * This allows the receiver to restart by sending XON when it has
2327 * drained a bit. Here we use an arbitary value of 1500 which will
2328 * restart after one full frame is pulled from the buffer. There
2329 * could be several smaller frames in the buffer and if so they will
2330 * not trigger the XON until their total number reduces the buffer
2332 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2335 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) << 10;
2337 adapter->hw.fc.high_water = rx_buffer_size -
2338 roundup2(adapter->max_frame_size, 1024);
2339 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500;
2341 if (adapter->hw.mac.type == e1000_80003es2lan)
2342 adapter->hw.fc.pause_time = 0xFFFF;
2344 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME;
2346 adapter->hw.fc.send_xon = TRUE;
2348 adapter->hw.fc.requested_mode = e1000_fc_full;
2350 /* Workaround: no TX flow ctrl for PCH */
2351 if (adapter->hw.mac.type == e1000_pchlan)
2352 adapter->hw.fc.requested_mode = e1000_fc_rx_pause;
2354 /* Override - settings for PCH2LAN, ya its magic :) */
2355 if (adapter->hw.mac.type == e1000_pch2lan) {
2356 adapter->hw.fc.high_water = 0x5C20;
2357 adapter->hw.fc.low_water = 0x5048;
2358 adapter->hw.fc.pause_time = 0x0650;
2359 adapter->hw.fc.refresh_time = 0x0400;
2361 /* Jumbos need adjusted PBA */
2362 if (adapter->arpcom.ac_if.if_mtu > ETHERMTU)
2363 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 12);
2365 E1000_WRITE_REG(&adapter->hw, E1000_PBA, 26);
2368 /* Issue a global reset */
2369 e1000_reset_hw(&adapter->hw);
2370 if (adapter->hw.mac.type >= e1000_82544)
2371 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0);
2372 em_disable_aspm(adapter);
2374 if (e1000_init_hw(&adapter->hw) < 0) {
2375 device_printf(dev, "Hardware Initialization Failed\n");
2379 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN);
2380 e1000_get_phy_info(&adapter->hw);
2381 e1000_check_for_link(&adapter->hw);
2387 em_setup_ifp(struct adapter *adapter)
2389 struct ifnet *ifp = &adapter->arpcom.ac_if;
2391 if_initname(ifp, device_get_name(adapter->dev),
2392 device_get_unit(adapter->dev));
2393 ifp->if_softc = adapter;
2394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2395 ifp->if_init = em_init;
2396 ifp->if_ioctl = em_ioctl;
2397 ifp->if_start = em_start;
2398 #ifdef DEVICE_POLLING
2399 ifp->if_poll = em_poll;
2401 ifp->if_watchdog = em_watchdog;
2402 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2403 ifq_set_ready(&ifp->if_snd);
2405 ether_ifattach(ifp, adapter->hw.mac.addr, NULL);
2407 if (adapter->hw.mac.type >= e1000_82543)
2408 ifp->if_capabilities = IFCAP_HWCSUM;
2410 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2411 ifp->if_capenable = ifp->if_capabilities;
2413 if (ifp->if_capenable & IFCAP_TXCSUM)
2414 ifp->if_hwassist = EM_CSUM_FEATURES;
2417 * Tell the upper layer(s) we support long frames.
2419 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2422 * Specify the media types supported by this adapter and register
2423 * callbacks to update media and link information
2425 ifmedia_init(&adapter->media, IFM_IMASK,
2426 em_media_change, em_media_status);
2427 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2428 adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
2429 u_char fiber_type = IFM_1000_SX; /* default type */
2431 if (adapter->hw.mac.type == e1000_82545)
2432 fiber_type = IFM_1000_LX;
2433 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2435 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2437 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2438 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2440 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2442 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2444 if (adapter->hw.phy.type != e1000_phy_ife) {
2445 ifmedia_add(&adapter->media,
2446 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2447 ifmedia_add(&adapter->media,
2448 IFM_ETHER | IFM_1000_T, 0, NULL);
2451 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2452 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2457 * Workaround for SmartSpeed on 82541 and 82547 controllers
2460 em_smartspeed(struct adapter *adapter)
2464 if (adapter->link_active || adapter->hw.phy.type != e1000_phy_igp ||
2465 adapter->hw.mac.autoneg == 0 ||
2466 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2469 if (adapter->smartspeed == 0) {
2471 * If Master/Slave config fault is asserted twice,
2472 * we assume back-to-back
2474 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2475 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2477 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2478 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2479 e1000_read_phy_reg(&adapter->hw,
2480 PHY_1000T_CTRL, &phy_tmp);
2481 if (phy_tmp & CR_1000T_MS_ENABLE) {
2482 phy_tmp &= ~CR_1000T_MS_ENABLE;
2483 e1000_write_phy_reg(&adapter->hw,
2484 PHY_1000T_CTRL, phy_tmp);
2485 adapter->smartspeed++;
2486 if (adapter->hw.mac.autoneg &&
2487 !e1000_phy_setup_autoneg(&adapter->hw) &&
2488 !e1000_read_phy_reg(&adapter->hw,
2489 PHY_CONTROL, &phy_tmp)) {
2490 phy_tmp |= MII_CR_AUTO_NEG_EN |
2491 MII_CR_RESTART_AUTO_NEG;
2492 e1000_write_phy_reg(&adapter->hw,
2493 PHY_CONTROL, phy_tmp);
2498 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2499 /* If still no link, perhaps using 2/3 pair cable */
2500 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2501 phy_tmp |= CR_1000T_MS_ENABLE;
2502 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2503 if (adapter->hw.mac.autoneg &&
2504 !e1000_phy_setup_autoneg(&adapter->hw) &&
2505 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) {
2506 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2507 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp);
2511 /* Restart process after EM_SMARTSPEED_MAX iterations */
2512 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2513 adapter->smartspeed = 0;
2517 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2518 struct em_dma_alloc *dma)
2520 dma->dma_vaddr = bus_dmamem_coherent_any(adapter->parent_dtag,
2521 EM_DBA_ALIGN, size, BUS_DMA_WAITOK,
2522 &dma->dma_tag, &dma->dma_map,
2524 if (dma->dma_vaddr == NULL)
2531 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2533 if (dma->dma_tag == NULL)
2535 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2536 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2537 bus_dma_tag_destroy(dma->dma_tag);
2541 em_create_tx_ring(struct adapter *adapter)
2543 device_t dev = adapter->dev;
2544 struct em_buffer *tx_buffer;
2547 adapter->tx_buffer_area =
2548 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2549 M_DEVBUF, M_WAITOK | M_ZERO);
2552 * Create DMA tags for tx buffers
2554 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
2555 1, 0, /* alignment, bounds */
2556 BUS_SPACE_MAXADDR, /* lowaddr */
2557 BUS_SPACE_MAXADDR, /* highaddr */
2558 NULL, NULL, /* filter, filterarg */
2559 EM_TSO_SIZE, /* maxsize */
2560 EM_MAX_SCATTER, /* nsegments */
2561 EM_MAX_SEGSIZE, /* maxsegsize */
2562 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2563 BUS_DMA_ONEBPAGE, /* flags */
2566 device_printf(dev, "Unable to allocate TX DMA tag\n");
2567 kfree(adapter->tx_buffer_area, M_DEVBUF);
2568 adapter->tx_buffer_area = NULL;
2573 * Create DMA maps for tx buffers
2575 for (i = 0; i < adapter->num_tx_desc; i++) {
2576 tx_buffer = &adapter->tx_buffer_area[i];
2578 error = bus_dmamap_create(adapter->txtag,
2579 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2582 device_printf(dev, "Unable to create TX DMA map\n");
2583 em_destroy_tx_ring(adapter, i);
2591 em_init_tx_ring(struct adapter *adapter)
2593 /* Clear the old ring contents */
2594 bzero(adapter->tx_desc_base,
2595 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc);
2598 adapter->next_avail_tx_desc = 0;
2599 adapter->next_tx_to_clean = 0;
2600 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2604 em_init_tx_unit(struct adapter *adapter)
2606 uint32_t tctl, tarc, tipg = 0;
2609 /* Setup the Base and Length of the Tx Descriptor Ring */
2610 bus_addr = adapter->txdma.dma_paddr;
2611 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0),
2612 adapter->num_tx_desc * sizeof(struct e1000_tx_desc));
2613 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0),
2614 (uint32_t)(bus_addr >> 32));
2615 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0),
2616 (uint32_t)bus_addr);
2617 /* Setup the HW Tx Head and Tail descriptor pointers */
2618 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0);
2619 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0);
2621 /* Set the default values for the Tx Inter Packet Gap timer */
2622 switch (adapter->hw.mac.type) {
2624 tipg = DEFAULT_82542_TIPG_IPGT;
2625 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2626 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2629 case e1000_80003es2lan:
2630 tipg = DEFAULT_82543_TIPG_IPGR1;
2631 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2632 E1000_TIPG_IPGR2_SHIFT;
2636 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
2637 adapter->hw.phy.media_type ==
2638 e1000_media_type_internal_serdes)
2639 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2641 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2642 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2643 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2647 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg);
2649 /* NOTE: 0 is not allowed for TIDV */
2650 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, 1);
2651 if(adapter->hw.mac.type >= e1000_82540)
2652 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 0);
2654 if (adapter->hw.mac.type == e1000_82571 ||
2655 adapter->hw.mac.type == e1000_82572) {
2656 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2657 tarc |= SPEED_MODE_BIT;
2658 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2659 } else if (adapter->hw.mac.type == e1000_80003es2lan) {
2660 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0));
2662 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc);
2663 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1));
2665 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc);
2668 /* Program the Transmit Control Register */
2669 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL);
2670 tctl &= ~E1000_TCTL_CT;
2671 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2672 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2674 if (adapter->hw.mac.type >= e1000_82571)
2675 tctl |= E1000_TCTL_MULR;
2677 /* This write will effectively turn on the transmit unit. */
2678 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl);
2682 em_destroy_tx_ring(struct adapter *adapter, int ndesc)
2684 struct em_buffer *tx_buffer;
2687 if (adapter->tx_buffer_area == NULL)
2690 for (i = 0; i < ndesc; i++) {
2691 tx_buffer = &adapter->tx_buffer_area[i];
2693 KKASSERT(tx_buffer->m_head == NULL);
2694 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2696 bus_dma_tag_destroy(adapter->txtag);
2698 kfree(adapter->tx_buffer_area, M_DEVBUF);
2699 adapter->tx_buffer_area = NULL;
2703 * The offload context needs to be set when we transfer the first
2704 * packet of a particular protocol (TCP/UDP). This routine has been
2705 * enhanced to deal with inserted VLAN headers.
2707 * If the new packet's ether header length, ip header length and
2708 * csum offloading type are same as the previous packet, we should
2709 * avoid allocating a new csum context descriptor; mainly to take
2710 * advantage of the pipeline effect of the TX data read request.
2712 * This function returns number of TX descrptors allocated for
2716 em_txcsum(struct adapter *adapter, struct mbuf *mp,
2717 uint32_t *txd_upper, uint32_t *txd_lower)
2719 struct e1000_context_desc *TXD;
2720 struct em_buffer *tx_buffer;
2721 struct ether_vlan_header *eh;
2723 int curr_txd, ehdrlen, csum_flags;
2724 uint32_t cmd, hdr_len, ip_hlen;
2728 * Determine where frame payload starts.
2729 * Jump over vlan headers if already present,
2730 * helpful for QinQ too.
2732 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2733 ("em_txcsum_pullup is not called (eh)?"));
2734 eh = mtod(mp, struct ether_vlan_header *);
2735 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2736 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2737 ("em_txcsum_pullup is not called (evh)?"));
2738 etype = ntohs(eh->evl_proto);
2739 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2741 etype = ntohs(eh->evl_encap_proto);
2742 ehdrlen = ETHER_HDR_LEN;
2746 * We only support TCP/UDP for IPv4 for the moment.
2747 * TODO: Support SCTP too when it hits the tree.
2749 if (etype != ETHERTYPE_IP)
2752 KASSERT(mp->m_len >= ehdrlen + EM_IPVHL_SIZE,
2753 ("em_txcsum_pullup is not called (eh+ip_vhl)?"));
2755 /* NOTE: We could only safely access ip.ip_vhl part */
2756 ip = (struct ip *)(mp->m_data + ehdrlen);
2757 ip_hlen = ip->ip_hl << 2;
2759 csum_flags = mp->m_pkthdr.csum_flags & EM_CSUM_FEATURES;
2761 if (adapter->csum_ehlen == ehdrlen &&
2762 adapter->csum_iphlen == ip_hlen &&
2763 adapter->csum_flags == csum_flags) {
2765 * Same csum offload context as the previous packets;
2768 *txd_upper = adapter->csum_txd_upper;
2769 *txd_lower = adapter->csum_txd_lower;
2774 * Setup a new csum offload context.
2777 curr_txd = adapter->next_avail_tx_desc;
2778 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2779 TXD = (struct e1000_context_desc *)&adapter->tx_desc_base[curr_txd];
2783 /* Setup of IP header checksum. */
2784 if (csum_flags & CSUM_IP) {
2786 * Start offset for header checksum calculation.
2787 * End offset for header checksum calculation.
2788 * Offset of place to put the checksum.
2790 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2791 TXD->lower_setup.ip_fields.ipcse =
2792 htole16(ehdrlen + ip_hlen - 1);
2793 TXD->lower_setup.ip_fields.ipcso =
2794 ehdrlen + offsetof(struct ip, ip_sum);
2795 cmd |= E1000_TXD_CMD_IP;
2796 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2798 hdr_len = ehdrlen + ip_hlen;
2800 if (csum_flags & CSUM_TCP) {
2802 * Start offset for payload checksum calculation.
2803 * End offset for payload checksum calculation.
2804 * Offset of place to put the checksum.
2806 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2807 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2808 TXD->upper_setup.tcp_fields.tucso =
2809 hdr_len + offsetof(struct tcphdr, th_sum);
2810 cmd |= E1000_TXD_CMD_TCP;
2811 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2812 } else if (csum_flags & CSUM_UDP) {
2814 * Start offset for header checksum calculation.
2815 * End offset for header checksum calculation.
2816 * Offset of place to put the checksum.
2818 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2819 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2820 TXD->upper_setup.tcp_fields.tucso =
2821 hdr_len + offsetof(struct udphdr, uh_sum);
2822 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2825 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2826 E1000_TXD_DTYP_D; /* Data descr */
2828 /* Save the information for this csum offloading context */
2829 adapter->csum_ehlen = ehdrlen;
2830 adapter->csum_iphlen = ip_hlen;
2831 adapter->csum_flags = csum_flags;
2832 adapter->csum_txd_upper = *txd_upper;
2833 adapter->csum_txd_lower = *txd_lower;
2835 TXD->tcp_seg_setup.data = htole32(0);
2836 TXD->cmd_and_length =
2837 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2839 if (++curr_txd == adapter->num_tx_desc)
2842 KKASSERT(adapter->num_tx_desc_avail > 0);
2843 adapter->num_tx_desc_avail--;
2845 adapter->next_avail_tx_desc = curr_txd;
2850 em_txcsum_pullup(struct adapter *adapter, struct mbuf **m0)
2852 struct mbuf *m = *m0;
2853 struct ether_header *eh;
2856 adapter->tx_csum_try_pullup++;
2858 len = ETHER_HDR_LEN + EM_IPVHL_SIZE;
2860 if (__predict_false(!M_WRITABLE(m))) {
2861 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2862 adapter->tx_csum_drop1++;
2867 eh = mtod(m, struct ether_header *);
2869 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2870 len += EVL_ENCAPLEN;
2872 if (m->m_len < len) {
2873 adapter->tx_csum_drop2++;
2881 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2882 adapter->tx_csum_pullup1++;
2883 m = m_pullup(m, ETHER_HDR_LEN);
2885 adapter->tx_csum_pullup1_failed++;
2891 eh = mtod(m, struct ether_header *);
2893 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2894 len += EVL_ENCAPLEN;
2896 if (m->m_len < len) {
2897 adapter->tx_csum_pullup2++;
2898 m = m_pullup(m, len);
2900 adapter->tx_csum_pullup2_failed++;
2910 em_txeof(struct adapter *adapter)
2912 struct ifnet *ifp = &adapter->arpcom.ac_if;
2913 struct em_buffer *tx_buffer;
2914 int first, num_avail;
2916 if (adapter->tx_dd_head == adapter->tx_dd_tail)
2919 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2922 num_avail = adapter->num_tx_desc_avail;
2923 first = adapter->next_tx_to_clean;
2925 while (adapter->tx_dd_head != adapter->tx_dd_tail) {
2926 struct e1000_tx_desc *tx_desc;
2927 int dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2929 tx_desc = &adapter->tx_desc_base[dd_idx];
2930 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2931 EM_INC_TXDD_IDX(adapter->tx_dd_head);
2933 if (++dd_idx == adapter->num_tx_desc)
2936 while (first != dd_idx) {
2941 tx_buffer = &adapter->tx_buffer_area[first];
2942 if (tx_buffer->m_head) {
2944 bus_dmamap_unload(adapter->txtag,
2946 m_freem(tx_buffer->m_head);
2947 tx_buffer->m_head = NULL;
2950 if (++first == adapter->num_tx_desc)
2957 adapter->next_tx_to_clean = first;
2958 adapter->num_tx_desc_avail = num_avail;
2960 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
2961 adapter->tx_dd_head = 0;
2962 adapter->tx_dd_tail = 0;
2965 if (!EM_IS_OACTIVE(adapter)) {
2966 ifp->if_flags &= ~IFF_OACTIVE;
2968 /* All clean, turn off the timer */
2969 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2975 em_tx_collect(struct adapter *adapter)
2977 struct ifnet *ifp = &adapter->arpcom.ac_if;
2978 struct em_buffer *tx_buffer;
2979 int tdh, first, num_avail, dd_idx = -1;
2981 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2984 tdh = E1000_READ_REG(&adapter->hw, E1000_TDH(0));
2985 if (tdh == adapter->next_tx_to_clean)
2988 if (adapter->tx_dd_head != adapter->tx_dd_tail)
2989 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
2991 num_avail = adapter->num_tx_desc_avail;
2992 first = adapter->next_tx_to_clean;
2994 while (first != tdh) {
2999 tx_buffer = &adapter->tx_buffer_area[first];
3000 if (tx_buffer->m_head) {
3002 bus_dmamap_unload(adapter->txtag,
3004 m_freem(tx_buffer->m_head);
3005 tx_buffer->m_head = NULL;
3008 if (first == dd_idx) {
3009 EM_INC_TXDD_IDX(adapter->tx_dd_head);
3010 if (adapter->tx_dd_head == adapter->tx_dd_tail) {
3011 adapter->tx_dd_head = 0;
3012 adapter->tx_dd_tail = 0;
3015 dd_idx = adapter->tx_dd[adapter->tx_dd_head];
3019 if (++first == adapter->num_tx_desc)
3022 adapter->next_tx_to_clean = first;
3023 adapter->num_tx_desc_avail = num_avail;
3025 if (!EM_IS_OACTIVE(adapter)) {
3026 ifp->if_flags &= ~IFF_OACTIVE;
3028 /* All clean, turn off the timer */
3029 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
3035 * When Link is lost sometimes there is work still in the TX ring
3036 * which will result in a watchdog, rather than allow that do an
3037 * attempted cleanup and then reinit here. Note that this has been
3038 * seens mostly with fiber adapters.
3041 em_tx_purge(struct adapter *adapter)
3043 struct ifnet *ifp = &adapter->arpcom.ac_if;
3045 if (!adapter->link_active && ifp->if_timer) {
3046 em_tx_collect(adapter);
3047 if (ifp->if_timer) {
3048 if_printf(ifp, "Link lost, TX pending, reinit\n");
3056 em_newbuf(struct adapter *adapter, int i, int init)
3059 bus_dma_segment_t seg;
3061 struct em_buffer *rx_buffer;
3064 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3066 adapter->mbuf_cluster_failed++;
3068 if_printf(&adapter->arpcom.ac_if,
3069 "Unable to allocate RX mbuf\n");
3073 m->m_len = m->m_pkthdr.len = MCLBYTES;
3075 if (adapter->max_frame_size <= MCLBYTES - ETHER_ALIGN)
3076 m_adj(m, ETHER_ALIGN);
3078 error = bus_dmamap_load_mbuf_segment(adapter->rxtag,
3079 adapter->rx_sparemap, m,
3080 &seg, 1, &nseg, BUS_DMA_NOWAIT);
3084 if_printf(&adapter->arpcom.ac_if,
3085 "Unable to load RX mbuf\n");
3090 rx_buffer = &adapter->rx_buffer_area[i];
3091 if (rx_buffer->m_head != NULL)
3092 bus_dmamap_unload(adapter->rxtag, rx_buffer->map);
3094 map = rx_buffer->map;
3095 rx_buffer->map = adapter->rx_sparemap;
3096 adapter->rx_sparemap = map;
3098 rx_buffer->m_head = m;
3100 adapter->rx_desc_base[i].buffer_addr = htole64(seg.ds_addr);
3105 em_create_rx_ring(struct adapter *adapter)
3107 device_t dev = adapter->dev;
3108 struct em_buffer *rx_buffer;
3111 adapter->rx_buffer_area =
3112 kmalloc(sizeof(struct em_buffer) * adapter->num_rx_desc,
3113 M_DEVBUF, M_WAITOK | M_ZERO);
3116 * Create DMA tag for rx buffers
3118 error = bus_dma_tag_create(adapter->parent_dtag, /* parent */
3119 1, 0, /* alignment, bounds */
3120 BUS_SPACE_MAXADDR, /* lowaddr */
3121 BUS_SPACE_MAXADDR, /* highaddr */
3122 NULL, NULL, /* filter, filterarg */
3123 MCLBYTES, /* maxsize */
3125 MCLBYTES, /* maxsegsize */
3126 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
3129 device_printf(dev, "Unable to allocate RX DMA tag\n");
3130 kfree(adapter->rx_buffer_area, M_DEVBUF);
3131 adapter->rx_buffer_area = NULL;
3136 * Create spare DMA map for rx buffers
3138 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3139 &adapter->rx_sparemap);
3141 device_printf(dev, "Unable to create spare RX DMA map\n");
3142 bus_dma_tag_destroy(adapter->rxtag);
3143 kfree(adapter->rx_buffer_area, M_DEVBUF);
3144 adapter->rx_buffer_area = NULL;
3149 * Create DMA maps for rx buffers
3151 for (i = 0; i < adapter->num_rx_desc; i++) {
3152 rx_buffer = &adapter->rx_buffer_area[i];
3154 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_WAITOK,
3157 device_printf(dev, "Unable to create RX DMA map\n");
3158 em_destroy_rx_ring(adapter, i);
3166 em_init_rx_ring(struct adapter *adapter)
3170 /* Reset descriptor ring */
3171 bzero(adapter->rx_desc_base,
3172 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc);
3174 /* Allocate new ones. */
3175 for (i = 0; i < adapter->num_rx_desc; i++) {
3176 error = em_newbuf(adapter, i, 1);
3181 /* Setup our descriptor pointers */
3182 adapter->next_rx_desc_to_check = 0;
3188 em_init_rx_unit(struct adapter *adapter)
3190 struct ifnet *ifp = &adapter->arpcom.ac_if;
3195 * Make sure receives are disabled while setting
3196 * up the descriptor ring
3198 rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL);
3199 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3201 if (adapter->hw.mac.type >= e1000_82540) {
3205 * Set the interrupt throttling rate. Value is calculated
3206 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3208 if (adapter->int_throttle_ceil)
3209 itr = 1000000000 / 256 / adapter->int_throttle_ceil;
3212 em_set_itr(adapter, itr);
3215 /* Disable accelerated ackknowledge */
3216 if (adapter->hw.mac.type == e1000_82574) {
3217 E1000_WRITE_REG(&adapter->hw,
3218 E1000_RFCTL, E1000_RFCTL_ACK_DIS);
3221 /* Receive Checksum Offload for TCP and UDP */
3222 if (ifp->if_capenable & IFCAP_RXCSUM) {
3225 rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM);
3226 rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3227 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, rxcsum);
3231 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3232 * long latencies are observed, like Lenovo X60. This
3233 * change eliminates the problem, but since having positive
3234 * values in RDTR is a known source of problems on other
3235 * platforms another solution is being sought.
3237 if (em_82573_workaround && adapter->hw.mac.type == e1000_82573) {
3238 E1000_WRITE_REG(&adapter->hw, E1000_RADV, EM_RADV_82573);
3239 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, EM_RDTR_82573);
3243 * Setup the Base and Length of the Rx Descriptor Ring
3245 bus_addr = adapter->rxdma.dma_paddr;
3246 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0),
3247 adapter->num_rx_desc * sizeof(struct e1000_rx_desc));
3248 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0),
3249 (uint32_t)(bus_addr >> 32));
3250 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0),
3251 (uint32_t)bus_addr);
3254 * Setup the HW Rx Head and Tail Descriptor Pointers
3256 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0);
3257 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1);
3259 /* Set early receive threshold on appropriate hw */
3260 if (((adapter->hw.mac.type == e1000_ich9lan) ||
3261 (adapter->hw.mac.type == e1000_pch2lan) ||
3262 (adapter->hw.mac.type == e1000_ich10lan)) &&
3263 (ifp->if_mtu > ETHERMTU)) {
3266 rxdctl = E1000_READ_REG(&adapter->hw, E1000_RXDCTL(0));
3267 E1000_WRITE_REG(&adapter->hw, E1000_RXDCTL(0), rxdctl | 3);
3268 E1000_WRITE_REG(&adapter->hw, E1000_ERT, 0x100 | (1 << 13));
3271 if (adapter->hw.mac.type == e1000_pch2lan) {
3272 if (ifp->if_mtu > ETHERMTU)
3273 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, TRUE);
3275 e1000_lv_jumbo_workaround_ich8lan(&adapter->hw, FALSE);
3278 /* Setup the Receive Control Register */
3279 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3280 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3281 E1000_RCTL_RDMTS_HALF |
3282 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3284 /* Make sure VLAN Filters are off */
3285 rctl &= ~E1000_RCTL_VFE;
3287 if (e1000_tbi_sbp_enabled_82543(&adapter->hw))
3288 rctl |= E1000_RCTL_SBP;
3290 rctl &= ~E1000_RCTL_SBP;
3292 switch (adapter->rx_buffer_len) {
3295 rctl |= E1000_RCTL_SZ_2048;
3299 rctl |= E1000_RCTL_SZ_4096 |
3300 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3304 rctl |= E1000_RCTL_SZ_8192 |
3305 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3309 rctl |= E1000_RCTL_SZ_16384 |
3310 E1000_RCTL_BSEX | E1000_RCTL_LPE;
3314 if (ifp->if_mtu > ETHERMTU)
3315 rctl |= E1000_RCTL_LPE;
3317 rctl &= ~E1000_RCTL_LPE;
3319 /* Enable Receives */
3320 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, rctl);
3324 em_destroy_rx_ring(struct adapter *adapter, int ndesc)
3326 struct em_buffer *rx_buffer;
3329 if (adapter->rx_buffer_area == NULL)
3332 for (i = 0; i < ndesc; i++) {
3333 rx_buffer = &adapter->rx_buffer_area[i];
3335 KKASSERT(rx_buffer->m_head == NULL);
3336 bus_dmamap_destroy(adapter->rxtag, rx_buffer->map);
3338 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap);
3339 bus_dma_tag_destroy(adapter->rxtag);
3341 kfree(adapter->rx_buffer_area, M_DEVBUF);
3342 adapter->rx_buffer_area = NULL;
3346 em_rxeof(struct adapter *adapter, int count)
3348 struct ifnet *ifp = &adapter->arpcom.ac_if;
3349 uint8_t status, accept_frame = 0, eop = 0;
3350 uint16_t len, desc_len, prev_len_adj;
3351 struct e1000_rx_desc *current_desc;
3355 i = adapter->next_rx_desc_to_check;
3356 current_desc = &adapter->rx_desc_base[i];
3358 if (!(current_desc->status & E1000_RXD_STAT_DD))
3361 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3362 struct mbuf *m = NULL;
3366 mp = adapter->rx_buffer_area[i].m_head;
3369 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3370 * needs to access the last received byte in the mbuf.
3372 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3373 BUS_DMASYNC_POSTREAD);
3377 desc_len = le16toh(current_desc->length);
3378 status = current_desc->status;
3379 if (status & E1000_RXD_STAT_EOP) {
3382 if (desc_len < ETHER_CRC_LEN) {
3384 prev_len_adj = ETHER_CRC_LEN - desc_len;
3386 len = desc_len - ETHER_CRC_LEN;
3393 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3395 uint32_t pkt_len = desc_len;
3397 if (adapter->fmp != NULL)
3398 pkt_len += adapter->fmp->m_pkthdr.len;
3400 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3401 if (TBI_ACCEPT(&adapter->hw, status,
3402 current_desc->errors, pkt_len, last_byte,
3403 adapter->min_frame_size, adapter->max_frame_size)) {
3404 e1000_tbi_adjust_stats_82543(&adapter->hw,
3405 &adapter->stats, pkt_len,
3406 adapter->hw.mac.addr,
3407 adapter->max_frame_size);
3416 if (em_newbuf(adapter, i, 0) != 0) {
3421 /* Assign correct length to the current fragment */
3424 if (adapter->fmp == NULL) {
3425 mp->m_pkthdr.len = len;
3426 adapter->fmp = mp; /* Store the first mbuf */
3430 * Chain mbuf's together
3434 * Adjust length of previous mbuf in chain if
3435 * we received less than 4 bytes in the last
3438 if (prev_len_adj > 0) {
3439 adapter->lmp->m_len -= prev_len_adj;
3440 adapter->fmp->m_pkthdr.len -=
3443 adapter->lmp->m_next = mp;
3444 adapter->lmp = adapter->lmp->m_next;
3445 adapter->fmp->m_pkthdr.len += len;
3449 adapter->fmp->m_pkthdr.rcvif = ifp;
3452 if (ifp->if_capenable & IFCAP_RXCSUM) {
3453 em_rxcsum(adapter, current_desc,
3457 if (status & E1000_RXD_STAT_VP) {
3458 adapter->fmp->m_pkthdr.ether_vlantag =
3459 (le16toh(current_desc->special) &
3460 E1000_RXD_SPC_VLAN_MASK);
3461 adapter->fmp->m_flags |= M_VLANTAG;
3464 adapter->fmp = NULL;
3465 adapter->lmp = NULL;
3471 /* Reuse loaded DMA map and just update mbuf chain */
3472 mp = adapter->rx_buffer_area[i].m_head;
3473 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
3474 mp->m_data = mp->m_ext.ext_buf;
3476 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN))
3477 m_adj(mp, ETHER_ALIGN);
3479 if (adapter->fmp != NULL) {
3480 m_freem(adapter->fmp);
3481 adapter->fmp = NULL;
3482 adapter->lmp = NULL;
3487 /* Zero out the receive descriptors status. */
3488 current_desc->status = 0;
3491 ifp->if_input(ifp, m);
3493 /* Advance our pointers to the next descriptor. */
3494 if (++i == adapter->num_rx_desc)
3496 current_desc = &adapter->rx_desc_base[i];
3498 adapter->next_rx_desc_to_check = i;
3500 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3502 i = adapter->num_rx_desc - 1;
3503 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i);
3507 em_rxcsum(struct adapter *adapter, struct e1000_rx_desc *rx_desc,
3510 /* 82543 or newer only */
3511 if (adapter->hw.mac.type < e1000_82543 ||
3512 /* Ignore Checksum bit is set */
3513 (rx_desc->status & E1000_RXD_STAT_IXSM))
3516 if ((rx_desc->status & E1000_RXD_STAT_IPCS) &&
3517 !(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3518 /* IP Checksum Good */
3519 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
3522 if ((rx_desc->status & E1000_RXD_STAT_TCPCS) &&
3523 !(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3524 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3526 CSUM_FRAG_NOT_CHECKED;
3527 mp->m_pkthdr.csum_data = htons(0xffff);
3532 em_enable_intr(struct adapter *adapter)
3534 uint32_t ims_mask = IMS_ENABLE_MASK;
3536 lwkt_serialize_handler_enable(adapter->arpcom.ac_if.if_serializer);
3540 if (adapter->hw.mac.type == e1000_82574) {
3541 E1000_WRITE_REG(&adapter->hw, EM_EIAC, EM_MSIX_MASK);
3542 ims_mask |= EM_MSIX_MASK;
3545 E1000_WRITE_REG(&adapter->hw, E1000_IMS, ims_mask);
3549 em_disable_intr(struct adapter *adapter)
3551 uint32_t clear = 0xffffffff;
3554 * The first version of 82542 had an errata where when link was forced
3555 * it would stay up even up even if the cable was disconnected.
3556 * Sequence errors were used to detect the disconnect and then the
3557 * driver would unforce the link. This code in the in the ISR. For
3558 * this to work correctly the Sequence error interrupt had to be
3559 * enabled all the time.
3561 if (adapter->hw.mac.type == e1000_82542 &&
3562 adapter->hw.revision_id == E1000_REVISION_2)
3563 clear &= ~E1000_ICR_RXSEQ;
3564 else if (adapter->hw.mac.type == e1000_82574)
3565 E1000_WRITE_REG(&adapter->hw, EM_EIAC, 0);
3567 E1000_WRITE_REG(&adapter->hw, E1000_IMC, clear);
3569 lwkt_serialize_handler_disable(adapter->arpcom.ac_if.if_serializer);
3573 * Bit of a misnomer, what this really means is
3574 * to enable OS management of the system... aka
3575 * to disable special hardware management features
3578 em_get_mgmt(struct adapter *adapter)
3580 /* A shared code workaround */
3581 #define E1000_82542_MANC2H E1000_MANC2H
3582 if (adapter->has_manage) {
3583 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H);
3584 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3586 /* disable hardware interception of ARP */
3587 manc &= ~(E1000_MANC_ARP_EN);
3589 /* enable receiving management packets to the host */
3590 if (adapter->hw.mac.type >= e1000_82571) {
3591 manc |= E1000_MANC_EN_MNG2HOST;
3592 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3593 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3594 manc2h |= E1000_MNG2HOST_PORT_623;
3595 manc2h |= E1000_MNG2HOST_PORT_664;
3596 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h);
3599 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3604 * Give control back to hardware management
3605 * controller if there is one.
3608 em_rel_mgmt(struct adapter *adapter)
3610 if (adapter->has_manage) {
3611 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
3613 /* re-enable hardware interception of ARP */
3614 manc |= E1000_MANC_ARP_EN;
3616 if (adapter->hw.mac.type >= e1000_82571)
3617 manc &= ~E1000_MANC_EN_MNG2HOST;
3619 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
3624 * em_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3625 * For ASF and Pass Through versions of f/w this means that
3626 * the driver is loaded. For AMT version (only with 82573)
3627 * of the f/w this means that the network i/f is open.
3630 em_get_hw_control(struct adapter *adapter)
3632 /* Let firmware know the driver has taken over */
3633 if (adapter->hw.mac.type == e1000_82573) {
3636 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3637 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3638 swsm | E1000_SWSM_DRV_LOAD);
3642 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3643 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3644 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3646 adapter->control_hw = 1;
3650 * em_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3651 * For ASF and Pass Through versions of f/w this means that the
3652 * driver is no longer loaded. For AMT version (only with 82573)
3653 * of the f/w this means that the network i/f is closed.
3656 em_rel_hw_control(struct adapter *adapter)
3658 if (!adapter->control_hw)
3660 adapter->control_hw = 0;
3662 /* Let firmware taken over control of h/w */
3663 if (adapter->hw.mac.type == e1000_82573) {
3666 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM);
3667 E1000_WRITE_REG(&adapter->hw, E1000_SWSM,
3668 swsm & ~E1000_SWSM_DRV_LOAD);
3672 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT);
3673 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT,
3674 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3679 em_is_valid_eaddr(const uint8_t *addr)
3681 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3683 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3690 * Enable PCI Wake On Lan capability
3693 em_enable_wol(device_t dev)
3695 uint16_t cap, status;
3698 /* First find the capabilities pointer*/
3699 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3701 /* Read the PM Capabilities */
3702 id = pci_read_config(dev, cap, 1);
3703 if (id != PCIY_PMG) /* Something wrong */
3707 * OK, we have the power capabilities,
3708 * so now get the status register
3710 cap += PCIR_POWER_STATUS;
3711 status = pci_read_config(dev, cap, 2);
3712 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3713 pci_write_config(dev, cap, status, 2);
3718 * 82544 Coexistence issue workaround.
3719 * There are 2 issues.
3720 * 1. Transmit Hang issue.
3721 * To detect this issue, following equation can be used...
3722 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3723 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3726 * To detect this issue, following equation can be used...
3727 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3728 * If SUM[3:0] is in between 9 to c, we will have this issue.
3731 * Make sure we do not have ending address
3732 * as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3735 em_82544_fill_desc(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3737 uint32_t safe_terminator;
3740 * Since issue is sensitive to length and address.
3741 * Let us first check the address...
3744 desc_array->descriptor[0].address = address;
3745 desc_array->descriptor[0].length = length;
3746 desc_array->elements = 1;
3747 return (desc_array->elements);
3751 (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3753 /* If it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3754 if (safe_terminator == 0 ||
3755 (safe_terminator > 4 && safe_terminator < 9) ||
3756 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3757 desc_array->descriptor[0].address = address;
3758 desc_array->descriptor[0].length = length;
3759 desc_array->elements = 1;
3760 return (desc_array->elements);
3763 desc_array->descriptor[0].address = address;
3764 desc_array->descriptor[0].length = length - 4;
3765 desc_array->descriptor[1].address = address + (length - 4);
3766 desc_array->descriptor[1].length = 4;
3767 desc_array->elements = 2;
3768 return (desc_array->elements);
3772 em_update_stats(struct adapter *adapter)
3774 struct ifnet *ifp = &adapter->arpcom.ac_if;
3776 if (adapter->hw.phy.media_type == e1000_media_type_copper ||
3777 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3778 adapter->stats.symerrs +=
3779 E1000_READ_REG(&adapter->hw, E1000_SYMERRS);
3780 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC);
3782 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS);
3783 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC);
3784 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC);
3785 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL);
3787 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC);
3788 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL);
3789 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC);
3790 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC);
3791 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC);
3792 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC);
3793 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC);
3794 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC);
3795 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC);
3796 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC);
3797 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64);
3798 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127);
3799 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255);
3800 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511);
3801 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023);
3802 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522);
3803 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC);
3804 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC);
3805 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC);
3806 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC);
3808 /* For the 64-bit byte counters the low dword must be read first. */
3809 /* Both registers clear on the read of the high dword */
3811 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH);
3812 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH);
3814 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC);
3815 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC);
3816 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC);
3817 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC);
3818 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC);
3820 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH);
3821 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH);
3823 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR);
3824 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT);
3825 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64);
3826 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127);
3827 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255);
3828 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511);
3829 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023);
3830 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522);
3831 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC);
3832 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC);
3834 if (adapter->hw.mac.type >= e1000_82543) {
3835 adapter->stats.algnerrc +=
3836 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC);
3837 adapter->stats.rxerrc +=
3838 E1000_READ_REG(&adapter->hw, E1000_RXERRC);
3839 adapter->stats.tncrs +=
3840 E1000_READ_REG(&adapter->hw, E1000_TNCRS);
3841 adapter->stats.cexterr +=
3842 E1000_READ_REG(&adapter->hw, E1000_CEXTERR);
3843 adapter->stats.tsctc +=
3844 E1000_READ_REG(&adapter->hw, E1000_TSCTC);
3845 adapter->stats.tsctfc +=
3846 E1000_READ_REG(&adapter->hw, E1000_TSCTFC);
3849 ifp->if_collisions = adapter->stats.colc;
3853 adapter->dropped_pkts + adapter->stats.rxerrc +
3854 adapter->stats.crcerrs + adapter->stats.algnerrc +
3855 adapter->stats.ruc + adapter->stats.roc +
3856 adapter->stats.mpc + adapter->stats.cexterr;
3860 adapter->stats.ecol + adapter->stats.latecol +
3861 adapter->watchdog_events;
3865 em_print_debug_info(struct adapter *adapter)
3867 device_t dev = adapter->dev;
3868 uint8_t *hw_addr = adapter->hw.hw_addr;
3870 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3871 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3872 E1000_READ_REG(&adapter->hw, E1000_CTRL),
3873 E1000_READ_REG(&adapter->hw, E1000_RCTL));
3874 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3875 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\
3876 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) );
3877 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3878 adapter->hw.fc.high_water,
3879 adapter->hw.fc.low_water);
3880 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3881 E1000_READ_REG(&adapter->hw, E1000_TIDV),
3882 E1000_READ_REG(&adapter->hw, E1000_TADV));
3883 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3884 E1000_READ_REG(&adapter->hw, E1000_RDTR),
3885 E1000_READ_REG(&adapter->hw, E1000_RADV));
3886 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3887 (long long)adapter->tx_fifo_wrk_cnt,
3888 (long long)adapter->tx_fifo_reset_cnt);
3889 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3890 E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
3891 E1000_READ_REG(&adapter->hw, E1000_TDT(0)));
3892 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3893 E1000_READ_REG(&adapter->hw, E1000_RDH(0)),
3894 E1000_READ_REG(&adapter->hw, E1000_RDT(0)));
3895 device_printf(dev, "Num Tx descriptors avail = %d\n",
3896 adapter->num_tx_desc_avail);
3897 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3898 adapter->no_tx_desc_avail1);
3899 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3900 adapter->no_tx_desc_avail2);
3901 device_printf(dev, "Std mbuf failed = %ld\n",
3902 adapter->mbuf_alloc_failed);
3903 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3904 adapter->mbuf_cluster_failed);
3905 device_printf(dev, "Driver dropped packets = %ld\n",
3906 adapter->dropped_pkts);
3907 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3908 adapter->no_tx_dma_setup);
3910 device_printf(dev, "TXCSUM try pullup = %lu\n",
3911 adapter->tx_csum_try_pullup);
3912 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3913 adapter->tx_csum_pullup1);
3914 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3915 adapter->tx_csum_pullup1_failed);
3916 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3917 adapter->tx_csum_pullup2);
3918 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3919 adapter->tx_csum_pullup2_failed);
3920 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3921 adapter->tx_csum_drop1);
3922 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3923 adapter->tx_csum_drop2);
3927 em_print_hw_stats(struct adapter *adapter)
3929 device_t dev = adapter->dev;
3931 device_printf(dev, "Excessive collisions = %lld\n",
3932 (long long)adapter->stats.ecol);
3933 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3934 device_printf(dev, "Symbol errors = %lld\n",
3935 (long long)adapter->stats.symerrs);
3937 device_printf(dev, "Sequence errors = %lld\n",
3938 (long long)adapter->stats.sec);
3939 device_printf(dev, "Defer count = %lld\n",
3940 (long long)adapter->stats.dc);
3941 device_printf(dev, "Missed Packets = %lld\n",
3942 (long long)adapter->stats.mpc);
3943 device_printf(dev, "Receive No Buffers = %lld\n",
3944 (long long)adapter->stats.rnbc);
3945 /* RLEC is inaccurate on some hardware, calculate our own. */
3946 device_printf(dev, "Receive Length Errors = %lld\n",
3947 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc));
3948 device_printf(dev, "Receive errors = %lld\n",
3949 (long long)adapter->stats.rxerrc);
3950 device_printf(dev, "Crc errors = %lld\n",
3951 (long long)adapter->stats.crcerrs);
3952 device_printf(dev, "Alignment errors = %lld\n",
3953 (long long)adapter->stats.algnerrc);
3954 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3955 (long long)adapter->stats.cexterr);
3956 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns);
3957 device_printf(dev, "watchdog timeouts = %ld\n",
3958 adapter->watchdog_events);
3959 device_printf(dev, "XON Rcvd = %lld\n",
3960 (long long)adapter->stats.xonrxc);
3961 device_printf(dev, "XON Xmtd = %lld\n",
3962 (long long)adapter->stats.xontxc);
3963 device_printf(dev, "XOFF Rcvd = %lld\n",
3964 (long long)adapter->stats.xoffrxc);
3965 device_printf(dev, "XOFF Xmtd = %lld\n",
3966 (long long)adapter->stats.xofftxc);
3967 device_printf(dev, "Good Packets Rcvd = %lld\n",
3968 (long long)adapter->stats.gprc);
3969 device_printf(dev, "Good Packets Xmtd = %lld\n",
3970 (long long)adapter->stats.gptc);
3974 em_print_nvm_info(struct adapter *adapter)
3976 uint16_t eeprom_data;
3979 /* Its a bit crude, but it gets the job done */
3980 kprintf("\nInterface EEPROM Dump:\n");
3981 kprintf("Offset\n0x0000 ");
3982 for (i = 0, j = 0; i < 32; i++, j++) {
3983 if (j == 8) { /* Make the offset block */
3985 kprintf("\n0x00%x0 ",row);
3987 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data);
3988 kprintf("%04x ", eeprom_data);
3994 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3996 struct adapter *adapter;
4001 error = sysctl_handle_int(oidp, &result, 0, req);
4002 if (error || !req->newptr)
4005 adapter = (struct adapter *)arg1;
4006 ifp = &adapter->arpcom.ac_if;
4008 lwkt_serialize_enter(ifp->if_serializer);
4011 em_print_debug_info(adapter);
4014 * This value will cause a hex dump of the
4015 * first 32 16-bit words of the EEPROM to
4019 em_print_nvm_info(adapter);
4021 lwkt_serialize_exit(ifp->if_serializer);
4027 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
4032 error = sysctl_handle_int(oidp, &result, 0, req);
4033 if (error || !req->newptr)
4037 struct adapter *adapter = (struct adapter *)arg1;
4038 struct ifnet *ifp = &adapter->arpcom.ac_if;
4040 lwkt_serialize_enter(ifp->if_serializer);
4041 em_print_hw_stats(adapter);
4042 lwkt_serialize_exit(ifp->if_serializer);
4048 em_add_sysctl(struct adapter *adapter)
4050 sysctl_ctx_init(&adapter->sysctl_ctx);
4051 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
4052 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
4053 device_get_nameunit(adapter->dev),
4055 if (adapter->sysctl_tree == NULL) {
4056 device_printf(adapter->dev, "can't add sysctl node\n");
4058 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4059 SYSCTL_CHILDREN(adapter->sysctl_tree),
4060 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4061 em_sysctl_debug_info, "I", "Debug Information");
4063 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4064 SYSCTL_CHILDREN(adapter->sysctl_tree),
4065 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4066 em_sysctl_stats, "I", "Statistics");
4068 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4069 SYSCTL_CHILDREN(adapter->sysctl_tree),
4070 OID_AUTO, "rxd", CTLFLAG_RD,
4071 &adapter->num_rx_desc, 0, NULL);
4072 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
4073 SYSCTL_CHILDREN(adapter->sysctl_tree),
4074 OID_AUTO, "txd", CTLFLAG_RD,
4075 &adapter->num_tx_desc, 0, NULL);
4077 if (adapter->hw.mac.type >= e1000_82540) {
4078 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4079 SYSCTL_CHILDREN(adapter->sysctl_tree),
4080 OID_AUTO, "int_throttle_ceil",
4081 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4082 em_sysctl_int_throttle, "I",
4083 "interrupt throttling rate");
4085 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
4086 SYSCTL_CHILDREN(adapter->sysctl_tree),
4087 OID_AUTO, "int_tx_nsegs",
4088 CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
4089 em_sysctl_int_tx_nsegs, "I",
4090 "# segments per TX interrupt");
4095 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
4097 struct adapter *adapter = (void *)arg1;
4098 struct ifnet *ifp = &adapter->arpcom.ac_if;
4099 int error, throttle;
4101 throttle = adapter->int_throttle_ceil;
4102 error = sysctl_handle_int(oidp, &throttle, 0, req);
4103 if (error || req->newptr == NULL)
4105 if (throttle < 0 || throttle > 1000000000 / 256)
4110 * Set the interrupt throttling rate in 256ns increments,
4111 * recalculate sysctl value assignment to get exact frequency.
4113 throttle = 1000000000 / 256 / throttle;
4115 /* Upper 16bits of ITR is reserved and should be zero */
4116 if (throttle & 0xffff0000)
4120 lwkt_serialize_enter(ifp->if_serializer);
4123 adapter->int_throttle_ceil = 1000000000 / 256 / throttle;
4125 adapter->int_throttle_ceil = 0;
4127 if (ifp->if_flags & IFF_RUNNING)
4128 em_set_itr(adapter, throttle);
4130 lwkt_serialize_exit(ifp->if_serializer);
4133 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
4134 adapter->int_throttle_ceil);
4140 em_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
4142 struct adapter *adapter = (void *)arg1;
4143 struct ifnet *ifp = &adapter->arpcom.ac_if;
4146 segs = adapter->tx_int_nsegs;
4147 error = sysctl_handle_int(oidp, &segs, 0, req);
4148 if (error || req->newptr == NULL)
4153 lwkt_serialize_enter(ifp->if_serializer);
4156 * Don't allow int_tx_nsegs to become:
4157 * o Less the oact_tx_desc
4158 * o Too large that no TX desc will cause TX interrupt to
4159 * be generated (OACTIVE will never recover)
4160 * o Too small that will cause tx_dd[] overflow
4162 if (segs < adapter->oact_tx_desc ||
4163 segs >= adapter->num_tx_desc - adapter->oact_tx_desc ||
4164 segs < adapter->num_tx_desc / EM_TXDD_SAFE) {
4168 adapter->tx_int_nsegs = segs;
4171 lwkt_serialize_exit(ifp->if_serializer);
4177 em_set_itr(struct adapter *adapter, uint32_t itr)
4179 E1000_WRITE_REG(&adapter->hw, E1000_ITR, itr);
4180 if (adapter->hw.mac.type == e1000_82574) {
4184 * When using MSIX interrupts we need to
4185 * throttle using the EITR register
4187 for (i = 0; i < 4; ++i) {
4188 E1000_WRITE_REG(&adapter->hw,
4189 E1000_EITR_82574(i), itr);
4195 em_disable_aspm(struct adapter *adapter)
4197 uint16_t link_cap, link_ctrl, disable;
4198 uint8_t pcie_ptr, reg;
4199 device_t dev = adapter->dev;
4201 switch (adapter->hw.mac.type) {
4206 * 82573 specification update
4210 * 82571/82572 specification update
4214 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4220 * 82574 specification update #20
4221 * 82583 specification update #9
4223 * There is no need to disable L1
4225 disable = PCIEM_LNKCTL_ASPM_L0S;
4232 pcie_ptr = pci_get_pciecap_ptr(dev);
4236 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4237 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4241 if_printf(&adapter->arpcom.ac_if,
4242 "disable ASPM %#02x\n", disable);
4245 reg = pcie_ptr + PCIER_LINKCTRL;
4246 link_ctrl = pci_read_config(dev, reg, 2);
4247 link_ctrl &= ~disable;
4248 pci_write_config(dev, reg, link_ctrl, 2);