pc32: Split out isa_intr.h and move isa/intr_machdep.h to include/
[dragonfly.git] / sys / platform / pc32 / apic / apic_abi.c
1 /*
2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
4  * Copyright (c) 1991 The Regents of the University of California.
5  * All rights reserved.
6  * 
7  * This code is derived from software contributed to The DragonFly Project
8  * by Matthew Dillon <dillon@backplane.com>
9  *
10  * This code is derived from software contributed to Berkeley by
11  * William Jolitz.
12  * 
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  * 3. Neither the name of The DragonFly Project nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific, prior written permission.
26  * 
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
41  */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
48 #include <sys/bus.h>
49
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <machine_base/icu/icu.h>
55 #include <machine/globaldata.h>
56
57 #include <sys/thread2.h>
58
59 #include "apic_ipl.h"
60
61 #ifdef SMP /* APIC-IO */
62
63 extern inthand_t
64         IDTVEC(apic_intr0),
65         IDTVEC(apic_intr1),
66         IDTVEC(apic_intr2),
67         IDTVEC(apic_intr3),
68         IDTVEC(apic_intr4),
69         IDTVEC(apic_intr5),
70         IDTVEC(apic_intr6),
71         IDTVEC(apic_intr7),
72         IDTVEC(apic_intr8),
73         IDTVEC(apic_intr9),
74         IDTVEC(apic_intr10),
75         IDTVEC(apic_intr11),
76         IDTVEC(apic_intr12),
77         IDTVEC(apic_intr13),
78         IDTVEC(apic_intr14),
79         IDTVEC(apic_intr15),
80         IDTVEC(apic_intr16),
81         IDTVEC(apic_intr17),
82         IDTVEC(apic_intr18),
83         IDTVEC(apic_intr19),
84         IDTVEC(apic_intr20),
85         IDTVEC(apic_intr21),
86         IDTVEC(apic_intr22),
87         IDTVEC(apic_intr23),
88         IDTVEC(apic_intr24),
89         IDTVEC(apic_intr25),
90         IDTVEC(apic_intr26),
91         IDTVEC(apic_intr27),
92         IDTVEC(apic_intr28),
93         IDTVEC(apic_intr29),
94         IDTVEC(apic_intr30),
95         IDTVEC(apic_intr31),
96         IDTVEC(apic_intr32),
97         IDTVEC(apic_intr33),
98         IDTVEC(apic_intr34),
99         IDTVEC(apic_intr35),
100         IDTVEC(apic_intr36),
101         IDTVEC(apic_intr37),
102         IDTVEC(apic_intr38),
103         IDTVEC(apic_intr39),
104         IDTVEC(apic_intr40),
105         IDTVEC(apic_intr41),
106         IDTVEC(apic_intr42),
107         IDTVEC(apic_intr43),
108         IDTVEC(apic_intr44),
109         IDTVEC(apic_intr45),
110         IDTVEC(apic_intr46),
111         IDTVEC(apic_intr47),
112         IDTVEC(apic_intr48),
113         IDTVEC(apic_intr49),
114         IDTVEC(apic_intr50),
115         IDTVEC(apic_intr51),
116         IDTVEC(apic_intr52),
117         IDTVEC(apic_intr53),
118         IDTVEC(apic_intr54),
119         IDTVEC(apic_intr55),
120         IDTVEC(apic_intr56),
121         IDTVEC(apic_intr57),
122         IDTVEC(apic_intr58),
123         IDTVEC(apic_intr59),
124         IDTVEC(apic_intr60),
125         IDTVEC(apic_intr61),
126         IDTVEC(apic_intr62),
127         IDTVEC(apic_intr63),
128         IDTVEC(apic_intr64),
129         IDTVEC(apic_intr65),
130         IDTVEC(apic_intr66),
131         IDTVEC(apic_intr67),
132         IDTVEC(apic_intr68),
133         IDTVEC(apic_intr69),
134         IDTVEC(apic_intr70),
135         IDTVEC(apic_intr71),
136         IDTVEC(apic_intr72),
137         IDTVEC(apic_intr73),
138         IDTVEC(apic_intr74),
139         IDTVEC(apic_intr75),
140         IDTVEC(apic_intr76),
141         IDTVEC(apic_intr77),
142         IDTVEC(apic_intr78),
143         IDTVEC(apic_intr79),
144         IDTVEC(apic_intr80),
145         IDTVEC(apic_intr81),
146         IDTVEC(apic_intr82),
147         IDTVEC(apic_intr83),
148         IDTVEC(apic_intr84),
149         IDTVEC(apic_intr85),
150         IDTVEC(apic_intr86),
151         IDTVEC(apic_intr87),
152         IDTVEC(apic_intr88),
153         IDTVEC(apic_intr89),
154         IDTVEC(apic_intr90),
155         IDTVEC(apic_intr91),
156         IDTVEC(apic_intr92),
157         IDTVEC(apic_intr93),
158         IDTVEC(apic_intr94),
159         IDTVEC(apic_intr95),
160         IDTVEC(apic_intr96),
161         IDTVEC(apic_intr97),
162         IDTVEC(apic_intr98),
163         IDTVEC(apic_intr99),
164         IDTVEC(apic_intr100),
165         IDTVEC(apic_intr101),
166         IDTVEC(apic_intr102),
167         IDTVEC(apic_intr103),
168         IDTVEC(apic_intr104),
169         IDTVEC(apic_intr105),
170         IDTVEC(apic_intr106),
171         IDTVEC(apic_intr107),
172         IDTVEC(apic_intr108),
173         IDTVEC(apic_intr109),
174         IDTVEC(apic_intr110),
175         IDTVEC(apic_intr111),
176         IDTVEC(apic_intr112),
177         IDTVEC(apic_intr113),
178         IDTVEC(apic_intr114),
179         IDTVEC(apic_intr115),
180         IDTVEC(apic_intr116),
181         IDTVEC(apic_intr117),
182         IDTVEC(apic_intr118),
183         IDTVEC(apic_intr119),
184         IDTVEC(apic_intr120),
185         IDTVEC(apic_intr121),
186         IDTVEC(apic_intr122),
187         IDTVEC(apic_intr123),
188         IDTVEC(apic_intr124),
189         IDTVEC(apic_intr125),
190         IDTVEC(apic_intr126),
191         IDTVEC(apic_intr127),
192         IDTVEC(apic_intr128),
193         IDTVEC(apic_intr129),
194         IDTVEC(apic_intr130),
195         IDTVEC(apic_intr131),
196         IDTVEC(apic_intr132),
197         IDTVEC(apic_intr133),
198         IDTVEC(apic_intr134),
199         IDTVEC(apic_intr135),
200         IDTVEC(apic_intr136),
201         IDTVEC(apic_intr137),
202         IDTVEC(apic_intr138),
203         IDTVEC(apic_intr139),
204         IDTVEC(apic_intr140),
205         IDTVEC(apic_intr141),
206         IDTVEC(apic_intr142),
207         IDTVEC(apic_intr143),
208         IDTVEC(apic_intr144),
209         IDTVEC(apic_intr145),
210         IDTVEC(apic_intr146),
211         IDTVEC(apic_intr147),
212         IDTVEC(apic_intr148),
213         IDTVEC(apic_intr149),
214         IDTVEC(apic_intr150),
215         IDTVEC(apic_intr151),
216         IDTVEC(apic_intr152),
217         IDTVEC(apic_intr153),
218         IDTVEC(apic_intr154),
219         IDTVEC(apic_intr155),
220         IDTVEC(apic_intr156),
221         IDTVEC(apic_intr157),
222         IDTVEC(apic_intr158),
223         IDTVEC(apic_intr159),
224         IDTVEC(apic_intr160),
225         IDTVEC(apic_intr161),
226         IDTVEC(apic_intr162),
227         IDTVEC(apic_intr163),
228         IDTVEC(apic_intr164),
229         IDTVEC(apic_intr165),
230         IDTVEC(apic_intr166),
231         IDTVEC(apic_intr167),
232         IDTVEC(apic_intr168),
233         IDTVEC(apic_intr169),
234         IDTVEC(apic_intr170),
235         IDTVEC(apic_intr171),
236         IDTVEC(apic_intr172),
237         IDTVEC(apic_intr173),
238         IDTVEC(apic_intr174),
239         IDTVEC(apic_intr175),
240         IDTVEC(apic_intr176),
241         IDTVEC(apic_intr177),
242         IDTVEC(apic_intr178),
243         IDTVEC(apic_intr179),
244         IDTVEC(apic_intr180),
245         IDTVEC(apic_intr181),
246         IDTVEC(apic_intr182),
247         IDTVEC(apic_intr183),
248         IDTVEC(apic_intr184),
249         IDTVEC(apic_intr185),
250         IDTVEC(apic_intr186),
251         IDTVEC(apic_intr187),
252         IDTVEC(apic_intr188),
253         IDTVEC(apic_intr189),
254         IDTVEC(apic_intr190),
255         IDTVEC(apic_intr191);
256
257 static inthand_t *apic_intr[APIC_HWI_VECTORS] = {
258         &IDTVEC(apic_intr0),
259         &IDTVEC(apic_intr1),
260         &IDTVEC(apic_intr2),
261         &IDTVEC(apic_intr3),
262         &IDTVEC(apic_intr4),
263         &IDTVEC(apic_intr5),
264         &IDTVEC(apic_intr6),
265         &IDTVEC(apic_intr7),
266         &IDTVEC(apic_intr8),
267         &IDTVEC(apic_intr9),
268         &IDTVEC(apic_intr10),
269         &IDTVEC(apic_intr11),
270         &IDTVEC(apic_intr12),
271         &IDTVEC(apic_intr13),
272         &IDTVEC(apic_intr14),
273         &IDTVEC(apic_intr15),
274         &IDTVEC(apic_intr16),
275         &IDTVEC(apic_intr17),
276         &IDTVEC(apic_intr18),
277         &IDTVEC(apic_intr19),
278         &IDTVEC(apic_intr20),
279         &IDTVEC(apic_intr21),
280         &IDTVEC(apic_intr22),
281         &IDTVEC(apic_intr23),
282         &IDTVEC(apic_intr24),
283         &IDTVEC(apic_intr25),
284         &IDTVEC(apic_intr26),
285         &IDTVEC(apic_intr27),
286         &IDTVEC(apic_intr28),
287         &IDTVEC(apic_intr29),
288         &IDTVEC(apic_intr30),
289         &IDTVEC(apic_intr31),
290         &IDTVEC(apic_intr32),
291         &IDTVEC(apic_intr33),
292         &IDTVEC(apic_intr34),
293         &IDTVEC(apic_intr35),
294         &IDTVEC(apic_intr36),
295         &IDTVEC(apic_intr37),
296         &IDTVEC(apic_intr38),
297         &IDTVEC(apic_intr39),
298         &IDTVEC(apic_intr40),
299         &IDTVEC(apic_intr41),
300         &IDTVEC(apic_intr42),
301         &IDTVEC(apic_intr43),
302         &IDTVEC(apic_intr44),
303         &IDTVEC(apic_intr45),
304         &IDTVEC(apic_intr46),
305         &IDTVEC(apic_intr47),
306         &IDTVEC(apic_intr48),
307         &IDTVEC(apic_intr49),
308         &IDTVEC(apic_intr50),
309         &IDTVEC(apic_intr51),
310         &IDTVEC(apic_intr52),
311         &IDTVEC(apic_intr53),
312         &IDTVEC(apic_intr54),
313         &IDTVEC(apic_intr55),
314         &IDTVEC(apic_intr56),
315         &IDTVEC(apic_intr57),
316         &IDTVEC(apic_intr58),
317         &IDTVEC(apic_intr59),
318         &IDTVEC(apic_intr60),
319         &IDTVEC(apic_intr61),
320         &IDTVEC(apic_intr62),
321         &IDTVEC(apic_intr63),
322         &IDTVEC(apic_intr64),
323         &IDTVEC(apic_intr65),
324         &IDTVEC(apic_intr66),
325         &IDTVEC(apic_intr67),
326         &IDTVEC(apic_intr68),
327         &IDTVEC(apic_intr69),
328         &IDTVEC(apic_intr70),
329         &IDTVEC(apic_intr71),
330         &IDTVEC(apic_intr72),
331         &IDTVEC(apic_intr73),
332         &IDTVEC(apic_intr74),
333         &IDTVEC(apic_intr75),
334         &IDTVEC(apic_intr76),
335         &IDTVEC(apic_intr77),
336         &IDTVEC(apic_intr78),
337         &IDTVEC(apic_intr79),
338         &IDTVEC(apic_intr80),
339         &IDTVEC(apic_intr81),
340         &IDTVEC(apic_intr82),
341         &IDTVEC(apic_intr83),
342         &IDTVEC(apic_intr84),
343         &IDTVEC(apic_intr85),
344         &IDTVEC(apic_intr86),
345         &IDTVEC(apic_intr87),
346         &IDTVEC(apic_intr88),
347         &IDTVEC(apic_intr89),
348         &IDTVEC(apic_intr90),
349         &IDTVEC(apic_intr91),
350         &IDTVEC(apic_intr92),
351         &IDTVEC(apic_intr93),
352         &IDTVEC(apic_intr94),
353         &IDTVEC(apic_intr95),
354         &IDTVEC(apic_intr96),
355         &IDTVEC(apic_intr97),
356         &IDTVEC(apic_intr98),
357         &IDTVEC(apic_intr99),
358         &IDTVEC(apic_intr100),
359         &IDTVEC(apic_intr101),
360         &IDTVEC(apic_intr102),
361         &IDTVEC(apic_intr103),
362         &IDTVEC(apic_intr104),
363         &IDTVEC(apic_intr105),
364         &IDTVEC(apic_intr106),
365         &IDTVEC(apic_intr107),
366         &IDTVEC(apic_intr108),
367         &IDTVEC(apic_intr109),
368         &IDTVEC(apic_intr110),
369         &IDTVEC(apic_intr111),
370         &IDTVEC(apic_intr112),
371         &IDTVEC(apic_intr113),
372         &IDTVEC(apic_intr114),
373         &IDTVEC(apic_intr115),
374         &IDTVEC(apic_intr116),
375         &IDTVEC(apic_intr117),
376         &IDTVEC(apic_intr118),
377         &IDTVEC(apic_intr119),
378         &IDTVEC(apic_intr120),
379         &IDTVEC(apic_intr121),
380         &IDTVEC(apic_intr122),
381         &IDTVEC(apic_intr123),
382         &IDTVEC(apic_intr124),
383         &IDTVEC(apic_intr125),
384         &IDTVEC(apic_intr126),
385         &IDTVEC(apic_intr127),
386         &IDTVEC(apic_intr128),
387         &IDTVEC(apic_intr129),
388         &IDTVEC(apic_intr130),
389         &IDTVEC(apic_intr131),
390         &IDTVEC(apic_intr132),
391         &IDTVEC(apic_intr133),
392         &IDTVEC(apic_intr134),
393         &IDTVEC(apic_intr135),
394         &IDTVEC(apic_intr136),
395         &IDTVEC(apic_intr137),
396         &IDTVEC(apic_intr138),
397         &IDTVEC(apic_intr139),
398         &IDTVEC(apic_intr140),
399         &IDTVEC(apic_intr141),
400         &IDTVEC(apic_intr142),
401         &IDTVEC(apic_intr143),
402         &IDTVEC(apic_intr144),
403         &IDTVEC(apic_intr145),
404         &IDTVEC(apic_intr146),
405         &IDTVEC(apic_intr147),
406         &IDTVEC(apic_intr148),
407         &IDTVEC(apic_intr149),
408         &IDTVEC(apic_intr150),
409         &IDTVEC(apic_intr151),
410         &IDTVEC(apic_intr152),
411         &IDTVEC(apic_intr153),
412         &IDTVEC(apic_intr154),
413         &IDTVEC(apic_intr155),
414         &IDTVEC(apic_intr156),
415         &IDTVEC(apic_intr157),
416         &IDTVEC(apic_intr158),
417         &IDTVEC(apic_intr159),
418         &IDTVEC(apic_intr160),
419         &IDTVEC(apic_intr161),
420         &IDTVEC(apic_intr162),
421         &IDTVEC(apic_intr163),
422         &IDTVEC(apic_intr164),
423         &IDTVEC(apic_intr165),
424         &IDTVEC(apic_intr166),
425         &IDTVEC(apic_intr167),
426         &IDTVEC(apic_intr168),
427         &IDTVEC(apic_intr169),
428         &IDTVEC(apic_intr170),
429         &IDTVEC(apic_intr171),
430         &IDTVEC(apic_intr172),
431         &IDTVEC(apic_intr173),
432         &IDTVEC(apic_intr174),
433         &IDTVEC(apic_intr175),
434         &IDTVEC(apic_intr176),
435         &IDTVEC(apic_intr177),
436         &IDTVEC(apic_intr178),
437         &IDTVEC(apic_intr179),
438         &IDTVEC(apic_intr180),
439         &IDTVEC(apic_intr181),
440         &IDTVEC(apic_intr182),
441         &IDTVEC(apic_intr183),
442         &IDTVEC(apic_intr184),
443         &IDTVEC(apic_intr185),
444         &IDTVEC(apic_intr186),
445         &IDTVEC(apic_intr187),
446         &IDTVEC(apic_intr188),
447         &IDTVEC(apic_intr189),
448         &IDTVEC(apic_intr190),
449         &IDTVEC(apic_intr191)
450 };
451
452 extern void     APIC_INTREN(int);
453 extern void     APIC_INTRDIS(int);
454
455 static int      apic_setvar(int, const void *);
456 static int      apic_getvar(int, void *);
457 static int      apic_vectorctl(int, int, int);
458 static void     apic_finalize(void);
459 static void     apic_cleanup(void);
460 static void     apic_setdefault(void);
461
462 static int      apic_imcr_present;
463
464 struct machintr_abi MachIntrABI_APIC = {
465         MACHINTR_APIC,
466         .intrdis        = APIC_INTRDIS,
467         .intren         = APIC_INTREN,
468         .vectorctl      = apic_vectorctl,
469         .setvar         = apic_setvar,
470         .getvar         = apic_getvar,
471         .finalize       = apic_finalize,
472         .cleanup        = apic_cleanup,
473         .setdefault     = apic_setdefault
474 };
475
476 static int
477 apic_setvar(int varid, const void *buf)
478 {
479         int error = 0;
480
481         switch (varid) {
482         case MACHINTR_VAR_IMCR_PRESENT:
483                 apic_imcr_present = *(const int *)buf;
484                 break;
485
486         default:
487                 error = ENOENT;
488                 break;
489         }
490         return error;
491 }
492
493 static int
494 apic_getvar(int varid, void *buf)
495 {
496         int error = 0;
497
498         switch (varid) {
499         case MACHINTR_VAR_IMCR_PRESENT:
500                 *(int *)buf = apic_imcr_present;
501                 break;
502
503         default:
504                 error = ENOENT;
505                 break;
506         }
507         return error;
508 }
509
510 /*
511  * Called before interrupts are physically enabled, this routine does the
512  * final configuration of the BSP's local APIC:
513  *
514  *  - disable 'pic mode'.
515  *  - disable 'virtual wire mode'.
516  *  - enable NMI.
517  */
518 static void
519 apic_finalize(void)
520 {
521         uint32_t temp;
522
523         KKASSERT(MachIntrABI.type == MACHINTR_ICU);
524         KKASSERT(apic_io_enable);
525
526         /*
527          * If an IMCR is present, program bit 0 to disconnect the 8259
528          * from the BSP.  The 8259 may still be connected to LINT0 on
529          * the BSP's LAPIC.
530          */
531         if (apic_imcr_present) {
532                 outb(0x22, 0x70);       /* select IMCR */
533                 outb(0x23, 0x01);       /* disconnect 8259 */
534         }
535
536         /*
537          * Setup lint0 (the 8259 'virtual wire' connection).  We
538          * mask the interrupt, completing the disconnection of the
539          * 8259.
540          */
541         temp = lapic.lvt_lint0;
542         temp |= APIC_LVT_MASKED;
543         lapic.lvt_lint0 = temp;
544
545         /*
546          * 8259 is completely disconnected; switch to IOAPIC MachIntrABI
547          * and reconfigure the default IDT entries.
548          */
549         MachIntrABI = MachIntrABI_APIC;
550         MachIntrABI.setdefault();
551
552         /*
553          * Setup lint1 to handle NMI
554          */
555         temp = lapic.lvt_lint1;
556         temp &= ~APIC_LVT_MASKED;
557         lapic.lvt_lint1 = temp;
558
559         if (bootverbose)
560                 apic_dump("bsp_apic_configure()");
561 }
562
563 /*
564  * This routine is called after physical interrupts are enabled but before
565  * the critical section is released.  We need to clean out any interrupts
566  * that had already been posted to the cpu.
567  */
568 static void
569 apic_cleanup(void)
570 {
571         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
572 }
573
574 static int
575 apic_vectorctl(int op, int intr, int flags)
576 {
577         int error;
578         int vector;
579         int select;
580         uint32_t value;
581         u_long ef;
582
583         if (intr < 0 || intr >= APIC_HWI_VECTORS ||
584             intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
585                 return EINVAL;
586
587         ef = read_eflags();
588         cpu_disable_intr();
589         error = 0;
590
591         switch(op) {
592         case MACHINTR_VECTOR_SETUP:
593                 vector = IDT_OFFSET + intr;
594                 setidt(vector, apic_intr[intr], SDT_SYS386IGT,
595                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
596
597                 /*
598                  * Now reprogram the vector in the IO APIC.  In order to avoid
599                  * losing an EOI for a level interrupt, which is vector based,
600                  * make sure that the IO APIC is programmed for edge-triggering
601                  * first, then reprogrammed with the new vector.  This should
602                  * clear the IRR bit.
603                  */
604                 if (int_to_apicintpin[intr].ioapic >= 0) {
605                         if (bootverbose) {
606                                 kprintf("IOAPIC: try clearing IRR for "
607                                         "irq %d\n", intr);
608                         }
609
610                         imen_lock();
611
612                         select = int_to_apicintpin[intr].redirindex;
613                         value = io_apic_read(int_to_apicintpin[intr].ioapic,
614                                              select);
615                         value |= IOART_INTMSET;
616
617                         io_apic_write(int_to_apicintpin[intr].ioapic,
618                                       select, (value & ~APIC_TRIGMOD_MASK));
619                         io_apic_write(int_to_apicintpin[intr].ioapic,
620                                       select, (value & ~IOART_INTVEC) | vector);
621
622                         imen_unlock();
623                 }
624
625                 machintr_intren(intr);
626                 break;
627
628         case MACHINTR_VECTOR_TEARDOWN:
629                 /*
630                  * Teardown an interrupt vector.  The vector should already be
631                  * installed in the cpu's IDT, but make sure.
632                  */
633                 machintr_intrdis(intr);
634
635                 vector = IDT_OFFSET + intr;
636                 setidt(vector, apic_intr[intr], SDT_SYS386IGT, SEL_KPL,
637                        GSEL(GCODE_SEL, SEL_KPL));
638
639                 /*
640                  * In order to avoid losing an EOI for a level interrupt, which
641                  * is vector based, make sure that the IO APIC is programmed for
642                  * edge-triggering first, then reprogrammed with the new vector.
643                  * This should clear the IRR bit.
644                  */
645                 if (int_to_apicintpin[intr].ioapic >= 0) {
646                         imen_lock();
647
648                         select = int_to_apicintpin[intr].redirindex;
649                         value = io_apic_read(int_to_apicintpin[intr].ioapic,
650                                              select);
651
652                         io_apic_write(int_to_apicintpin[intr].ioapic,
653                                       select, (value & ~APIC_TRIGMOD_MASK));
654                         io_apic_write(int_to_apicintpin[intr].ioapic,
655                                       select, (value & ~IOART_INTVEC) | vector);
656
657                         imen_unlock();
658                 }
659                 break;
660
661         default:
662                 error = EOPNOTSUPP;
663                 break;
664         }
665
666         write_eflags(ef);
667         return error;
668 }
669
670 static void
671 apic_setdefault(void)
672 {
673         int intr;
674
675         for (intr = 0; intr < APIC_HWI_VECTORS; ++intr) {
676                 if (intr == IDT_OFFSET_SYSCALL - IDT_OFFSET)
677                         continue;
678                 setidt(IDT_OFFSET + intr, apic_intr[intr], SDT_SYS386IGT,
679                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
680         }
681 }
682
683 #endif  /* SMP */