x86_64/ioapic_abi: Augment intr_{setup,teardown} w/ assertions
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
1 /*
2  * Copyright (c) 1991 The Regents of the University of California.
3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
4  * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
5  * All rights reserved.
6  * 
7  * This code is derived from software contributed to The DragonFly Project
8  * by Matthew Dillon <dillon@backplane.com>
9  *
10  * This code is derived from software contributed to Berkeley by
11  * William Jolitz.
12  * 
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  * 3. Neither the name of The DragonFly Project nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific, prior written permission.
26  * 
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41  */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
48 #include <sys/bus.h>
49 #include <sys/rman.h>
50 #include <sys/thread2.h>
51
52 #include <machine/smp.h>
53 #include <machine/segments.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
56 #include <machine/globaldata.h>
57
58 #include <machine_base/isa/isa_intr.h>
59 #include <machine_base/icu/icu.h>
60 #include <machine_base/icu/icu_var.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine_base/apic/ioapic_abi.h>
63 #include <machine_base/apic/ioapic_ipl.h>
64 #include <machine_base/apic/apicreg.h>
65
66 #include <dev/acpica5/acpi_sci_var.h>
67
68 #define IOAPIC_HWI_VECTORS      IDT_HWI_VECTORS
69
70 extern inthand_t
71         IDTVEC(ioapic_intr0),
72         IDTVEC(ioapic_intr1),
73         IDTVEC(ioapic_intr2),
74         IDTVEC(ioapic_intr3),
75         IDTVEC(ioapic_intr4),
76         IDTVEC(ioapic_intr5),
77         IDTVEC(ioapic_intr6),
78         IDTVEC(ioapic_intr7),
79         IDTVEC(ioapic_intr8),
80         IDTVEC(ioapic_intr9),
81         IDTVEC(ioapic_intr10),
82         IDTVEC(ioapic_intr11),
83         IDTVEC(ioapic_intr12),
84         IDTVEC(ioapic_intr13),
85         IDTVEC(ioapic_intr14),
86         IDTVEC(ioapic_intr15),
87         IDTVEC(ioapic_intr16),
88         IDTVEC(ioapic_intr17),
89         IDTVEC(ioapic_intr18),
90         IDTVEC(ioapic_intr19),
91         IDTVEC(ioapic_intr20),
92         IDTVEC(ioapic_intr21),
93         IDTVEC(ioapic_intr22),
94         IDTVEC(ioapic_intr23),
95         IDTVEC(ioapic_intr24),
96         IDTVEC(ioapic_intr25),
97         IDTVEC(ioapic_intr26),
98         IDTVEC(ioapic_intr27),
99         IDTVEC(ioapic_intr28),
100         IDTVEC(ioapic_intr29),
101         IDTVEC(ioapic_intr30),
102         IDTVEC(ioapic_intr31),
103         IDTVEC(ioapic_intr32),
104         IDTVEC(ioapic_intr33),
105         IDTVEC(ioapic_intr34),
106         IDTVEC(ioapic_intr35),
107         IDTVEC(ioapic_intr36),
108         IDTVEC(ioapic_intr37),
109         IDTVEC(ioapic_intr38),
110         IDTVEC(ioapic_intr39),
111         IDTVEC(ioapic_intr40),
112         IDTVEC(ioapic_intr41),
113         IDTVEC(ioapic_intr42),
114         IDTVEC(ioapic_intr43),
115         IDTVEC(ioapic_intr44),
116         IDTVEC(ioapic_intr45),
117         IDTVEC(ioapic_intr46),
118         IDTVEC(ioapic_intr47),
119         IDTVEC(ioapic_intr48),
120         IDTVEC(ioapic_intr49),
121         IDTVEC(ioapic_intr50),
122         IDTVEC(ioapic_intr51),
123         IDTVEC(ioapic_intr52),
124         IDTVEC(ioapic_intr53),
125         IDTVEC(ioapic_intr54),
126         IDTVEC(ioapic_intr55),
127         IDTVEC(ioapic_intr56),
128         IDTVEC(ioapic_intr57),
129         IDTVEC(ioapic_intr58),
130         IDTVEC(ioapic_intr59),
131         IDTVEC(ioapic_intr60),
132         IDTVEC(ioapic_intr61),
133         IDTVEC(ioapic_intr62),
134         IDTVEC(ioapic_intr63),
135         IDTVEC(ioapic_intr64),
136         IDTVEC(ioapic_intr65),
137         IDTVEC(ioapic_intr66),
138         IDTVEC(ioapic_intr67),
139         IDTVEC(ioapic_intr68),
140         IDTVEC(ioapic_intr69),
141         IDTVEC(ioapic_intr70),
142         IDTVEC(ioapic_intr71),
143         IDTVEC(ioapic_intr72),
144         IDTVEC(ioapic_intr73),
145         IDTVEC(ioapic_intr74),
146         IDTVEC(ioapic_intr75),
147         IDTVEC(ioapic_intr76),
148         IDTVEC(ioapic_intr77),
149         IDTVEC(ioapic_intr78),
150         IDTVEC(ioapic_intr79),
151         IDTVEC(ioapic_intr80),
152         IDTVEC(ioapic_intr81),
153         IDTVEC(ioapic_intr82),
154         IDTVEC(ioapic_intr83),
155         IDTVEC(ioapic_intr84),
156         IDTVEC(ioapic_intr85),
157         IDTVEC(ioapic_intr86),
158         IDTVEC(ioapic_intr87),
159         IDTVEC(ioapic_intr88),
160         IDTVEC(ioapic_intr89),
161         IDTVEC(ioapic_intr90),
162         IDTVEC(ioapic_intr91),
163         IDTVEC(ioapic_intr92),
164         IDTVEC(ioapic_intr93),
165         IDTVEC(ioapic_intr94),
166         IDTVEC(ioapic_intr95),
167         IDTVEC(ioapic_intr96),
168         IDTVEC(ioapic_intr97),
169         IDTVEC(ioapic_intr98),
170         IDTVEC(ioapic_intr99),
171         IDTVEC(ioapic_intr100),
172         IDTVEC(ioapic_intr101),
173         IDTVEC(ioapic_intr102),
174         IDTVEC(ioapic_intr103),
175         IDTVEC(ioapic_intr104),
176         IDTVEC(ioapic_intr105),
177         IDTVEC(ioapic_intr106),
178         IDTVEC(ioapic_intr107),
179         IDTVEC(ioapic_intr108),
180         IDTVEC(ioapic_intr109),
181         IDTVEC(ioapic_intr110),
182         IDTVEC(ioapic_intr111),
183         IDTVEC(ioapic_intr112),
184         IDTVEC(ioapic_intr113),
185         IDTVEC(ioapic_intr114),
186         IDTVEC(ioapic_intr115),
187         IDTVEC(ioapic_intr116),
188         IDTVEC(ioapic_intr117),
189         IDTVEC(ioapic_intr118),
190         IDTVEC(ioapic_intr119),
191         IDTVEC(ioapic_intr120),
192         IDTVEC(ioapic_intr121),
193         IDTVEC(ioapic_intr122),
194         IDTVEC(ioapic_intr123),
195         IDTVEC(ioapic_intr124),
196         IDTVEC(ioapic_intr125),
197         IDTVEC(ioapic_intr126),
198         IDTVEC(ioapic_intr127),
199         IDTVEC(ioapic_intr128),
200         IDTVEC(ioapic_intr129),
201         IDTVEC(ioapic_intr130),
202         IDTVEC(ioapic_intr131),
203         IDTVEC(ioapic_intr132),
204         IDTVEC(ioapic_intr133),
205         IDTVEC(ioapic_intr134),
206         IDTVEC(ioapic_intr135),
207         IDTVEC(ioapic_intr136),
208         IDTVEC(ioapic_intr137),
209         IDTVEC(ioapic_intr138),
210         IDTVEC(ioapic_intr139),
211         IDTVEC(ioapic_intr140),
212         IDTVEC(ioapic_intr141),
213         IDTVEC(ioapic_intr142),
214         IDTVEC(ioapic_intr143),
215         IDTVEC(ioapic_intr144),
216         IDTVEC(ioapic_intr145),
217         IDTVEC(ioapic_intr146),
218         IDTVEC(ioapic_intr147),
219         IDTVEC(ioapic_intr148),
220         IDTVEC(ioapic_intr149),
221         IDTVEC(ioapic_intr150),
222         IDTVEC(ioapic_intr151),
223         IDTVEC(ioapic_intr152),
224         IDTVEC(ioapic_intr153),
225         IDTVEC(ioapic_intr154),
226         IDTVEC(ioapic_intr155),
227         IDTVEC(ioapic_intr156),
228         IDTVEC(ioapic_intr157),
229         IDTVEC(ioapic_intr158),
230         IDTVEC(ioapic_intr159),
231         IDTVEC(ioapic_intr160),
232         IDTVEC(ioapic_intr161),
233         IDTVEC(ioapic_intr162),
234         IDTVEC(ioapic_intr163),
235         IDTVEC(ioapic_intr164),
236         IDTVEC(ioapic_intr165),
237         IDTVEC(ioapic_intr166),
238         IDTVEC(ioapic_intr167),
239         IDTVEC(ioapic_intr168),
240         IDTVEC(ioapic_intr169),
241         IDTVEC(ioapic_intr170),
242         IDTVEC(ioapic_intr171),
243         IDTVEC(ioapic_intr172),
244         IDTVEC(ioapic_intr173),
245         IDTVEC(ioapic_intr174),
246         IDTVEC(ioapic_intr175),
247         IDTVEC(ioapic_intr176),
248         IDTVEC(ioapic_intr177),
249         IDTVEC(ioapic_intr178),
250         IDTVEC(ioapic_intr179),
251         IDTVEC(ioapic_intr180),
252         IDTVEC(ioapic_intr181),
253         IDTVEC(ioapic_intr182),
254         IDTVEC(ioapic_intr183),
255         IDTVEC(ioapic_intr184),
256         IDTVEC(ioapic_intr185),
257         IDTVEC(ioapic_intr186),
258         IDTVEC(ioapic_intr187),
259         IDTVEC(ioapic_intr188),
260         IDTVEC(ioapic_intr189),
261         IDTVEC(ioapic_intr190),
262         IDTVEC(ioapic_intr191);
263
264 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
265         &IDTVEC(ioapic_intr0),
266         &IDTVEC(ioapic_intr1),
267         &IDTVEC(ioapic_intr2),
268         &IDTVEC(ioapic_intr3),
269         &IDTVEC(ioapic_intr4),
270         &IDTVEC(ioapic_intr5),
271         &IDTVEC(ioapic_intr6),
272         &IDTVEC(ioapic_intr7),
273         &IDTVEC(ioapic_intr8),
274         &IDTVEC(ioapic_intr9),
275         &IDTVEC(ioapic_intr10),
276         &IDTVEC(ioapic_intr11),
277         &IDTVEC(ioapic_intr12),
278         &IDTVEC(ioapic_intr13),
279         &IDTVEC(ioapic_intr14),
280         &IDTVEC(ioapic_intr15),
281         &IDTVEC(ioapic_intr16),
282         &IDTVEC(ioapic_intr17),
283         &IDTVEC(ioapic_intr18),
284         &IDTVEC(ioapic_intr19),
285         &IDTVEC(ioapic_intr20),
286         &IDTVEC(ioapic_intr21),
287         &IDTVEC(ioapic_intr22),
288         &IDTVEC(ioapic_intr23),
289         &IDTVEC(ioapic_intr24),
290         &IDTVEC(ioapic_intr25),
291         &IDTVEC(ioapic_intr26),
292         &IDTVEC(ioapic_intr27),
293         &IDTVEC(ioapic_intr28),
294         &IDTVEC(ioapic_intr29),
295         &IDTVEC(ioapic_intr30),
296         &IDTVEC(ioapic_intr31),
297         &IDTVEC(ioapic_intr32),
298         &IDTVEC(ioapic_intr33),
299         &IDTVEC(ioapic_intr34),
300         &IDTVEC(ioapic_intr35),
301         &IDTVEC(ioapic_intr36),
302         &IDTVEC(ioapic_intr37),
303         &IDTVEC(ioapic_intr38),
304         &IDTVEC(ioapic_intr39),
305         &IDTVEC(ioapic_intr40),
306         &IDTVEC(ioapic_intr41),
307         &IDTVEC(ioapic_intr42),
308         &IDTVEC(ioapic_intr43),
309         &IDTVEC(ioapic_intr44),
310         &IDTVEC(ioapic_intr45),
311         &IDTVEC(ioapic_intr46),
312         &IDTVEC(ioapic_intr47),
313         &IDTVEC(ioapic_intr48),
314         &IDTVEC(ioapic_intr49),
315         &IDTVEC(ioapic_intr50),
316         &IDTVEC(ioapic_intr51),
317         &IDTVEC(ioapic_intr52),
318         &IDTVEC(ioapic_intr53),
319         &IDTVEC(ioapic_intr54),
320         &IDTVEC(ioapic_intr55),
321         &IDTVEC(ioapic_intr56),
322         &IDTVEC(ioapic_intr57),
323         &IDTVEC(ioapic_intr58),
324         &IDTVEC(ioapic_intr59),
325         &IDTVEC(ioapic_intr60),
326         &IDTVEC(ioapic_intr61),
327         &IDTVEC(ioapic_intr62),
328         &IDTVEC(ioapic_intr63),
329         &IDTVEC(ioapic_intr64),
330         &IDTVEC(ioapic_intr65),
331         &IDTVEC(ioapic_intr66),
332         &IDTVEC(ioapic_intr67),
333         &IDTVEC(ioapic_intr68),
334         &IDTVEC(ioapic_intr69),
335         &IDTVEC(ioapic_intr70),
336         &IDTVEC(ioapic_intr71),
337         &IDTVEC(ioapic_intr72),
338         &IDTVEC(ioapic_intr73),
339         &IDTVEC(ioapic_intr74),
340         &IDTVEC(ioapic_intr75),
341         &IDTVEC(ioapic_intr76),
342         &IDTVEC(ioapic_intr77),
343         &IDTVEC(ioapic_intr78),
344         &IDTVEC(ioapic_intr79),
345         &IDTVEC(ioapic_intr80),
346         &IDTVEC(ioapic_intr81),
347         &IDTVEC(ioapic_intr82),
348         &IDTVEC(ioapic_intr83),
349         &IDTVEC(ioapic_intr84),
350         &IDTVEC(ioapic_intr85),
351         &IDTVEC(ioapic_intr86),
352         &IDTVEC(ioapic_intr87),
353         &IDTVEC(ioapic_intr88),
354         &IDTVEC(ioapic_intr89),
355         &IDTVEC(ioapic_intr90),
356         &IDTVEC(ioapic_intr91),
357         &IDTVEC(ioapic_intr92),
358         &IDTVEC(ioapic_intr93),
359         &IDTVEC(ioapic_intr94),
360         &IDTVEC(ioapic_intr95),
361         &IDTVEC(ioapic_intr96),
362         &IDTVEC(ioapic_intr97),
363         &IDTVEC(ioapic_intr98),
364         &IDTVEC(ioapic_intr99),
365         &IDTVEC(ioapic_intr100),
366         &IDTVEC(ioapic_intr101),
367         &IDTVEC(ioapic_intr102),
368         &IDTVEC(ioapic_intr103),
369         &IDTVEC(ioapic_intr104),
370         &IDTVEC(ioapic_intr105),
371         &IDTVEC(ioapic_intr106),
372         &IDTVEC(ioapic_intr107),
373         &IDTVEC(ioapic_intr108),
374         &IDTVEC(ioapic_intr109),
375         &IDTVEC(ioapic_intr110),
376         &IDTVEC(ioapic_intr111),
377         &IDTVEC(ioapic_intr112),
378         &IDTVEC(ioapic_intr113),
379         &IDTVEC(ioapic_intr114),
380         &IDTVEC(ioapic_intr115),
381         &IDTVEC(ioapic_intr116),
382         &IDTVEC(ioapic_intr117),
383         &IDTVEC(ioapic_intr118),
384         &IDTVEC(ioapic_intr119),
385         &IDTVEC(ioapic_intr120),
386         &IDTVEC(ioapic_intr121),
387         &IDTVEC(ioapic_intr122),
388         &IDTVEC(ioapic_intr123),
389         &IDTVEC(ioapic_intr124),
390         &IDTVEC(ioapic_intr125),
391         &IDTVEC(ioapic_intr126),
392         &IDTVEC(ioapic_intr127),
393         &IDTVEC(ioapic_intr128),
394         &IDTVEC(ioapic_intr129),
395         &IDTVEC(ioapic_intr130),
396         &IDTVEC(ioapic_intr131),
397         &IDTVEC(ioapic_intr132),
398         &IDTVEC(ioapic_intr133),
399         &IDTVEC(ioapic_intr134),
400         &IDTVEC(ioapic_intr135),
401         &IDTVEC(ioapic_intr136),
402         &IDTVEC(ioapic_intr137),
403         &IDTVEC(ioapic_intr138),
404         &IDTVEC(ioapic_intr139),
405         &IDTVEC(ioapic_intr140),
406         &IDTVEC(ioapic_intr141),
407         &IDTVEC(ioapic_intr142),
408         &IDTVEC(ioapic_intr143),
409         &IDTVEC(ioapic_intr144),
410         &IDTVEC(ioapic_intr145),
411         &IDTVEC(ioapic_intr146),
412         &IDTVEC(ioapic_intr147),
413         &IDTVEC(ioapic_intr148),
414         &IDTVEC(ioapic_intr149),
415         &IDTVEC(ioapic_intr150),
416         &IDTVEC(ioapic_intr151),
417         &IDTVEC(ioapic_intr152),
418         &IDTVEC(ioapic_intr153),
419         &IDTVEC(ioapic_intr154),
420         &IDTVEC(ioapic_intr155),
421         &IDTVEC(ioapic_intr156),
422         &IDTVEC(ioapic_intr157),
423         &IDTVEC(ioapic_intr158),
424         &IDTVEC(ioapic_intr159),
425         &IDTVEC(ioapic_intr160),
426         &IDTVEC(ioapic_intr161),
427         &IDTVEC(ioapic_intr162),
428         &IDTVEC(ioapic_intr163),
429         &IDTVEC(ioapic_intr164),
430         &IDTVEC(ioapic_intr165),
431         &IDTVEC(ioapic_intr166),
432         &IDTVEC(ioapic_intr167),
433         &IDTVEC(ioapic_intr168),
434         &IDTVEC(ioapic_intr169),
435         &IDTVEC(ioapic_intr170),
436         &IDTVEC(ioapic_intr171),
437         &IDTVEC(ioapic_intr172),
438         &IDTVEC(ioapic_intr173),
439         &IDTVEC(ioapic_intr174),
440         &IDTVEC(ioapic_intr175),
441         &IDTVEC(ioapic_intr176),
442         &IDTVEC(ioapic_intr177),
443         &IDTVEC(ioapic_intr178),
444         &IDTVEC(ioapic_intr179),
445         &IDTVEC(ioapic_intr180),
446         &IDTVEC(ioapic_intr181),
447         &IDTVEC(ioapic_intr182),
448         &IDTVEC(ioapic_intr183),
449         &IDTVEC(ioapic_intr184),
450         &IDTVEC(ioapic_intr185),
451         &IDTVEC(ioapic_intr186),
452         &IDTVEC(ioapic_intr187),
453         &IDTVEC(ioapic_intr188),
454         &IDTVEC(ioapic_intr189),
455         &IDTVEC(ioapic_intr190),
456         &IDTVEC(ioapic_intr191)
457 };
458
459 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
460
461 static struct ioapic_irqmap {
462         int                     im_type;        /* IOAPIC_IMT_ */
463         enum intr_trigger       im_trig;
464         enum intr_polarity      im_pola;
465         int                     im_gsi;
466         uint32_t                im_flags;       /* IOAPIC_IMF_ */
467 } ioapic_irqmaps[MAXCPU][IOAPIC_HWI_VECTORS];
468
469 #define IOAPIC_IMT_UNUSED       0
470 #define IOAPIC_IMT_RESERVED     1
471 #define IOAPIC_IMT_LINE         2
472 #define IOAPIC_IMT_SYSCALL      3
473
474 #define IOAPIC_IMT_ISHWI(map)   ((map)->im_type != IOAPIC_IMT_RESERVED && \
475                                  (map)->im_type != IOAPIC_IMT_SYSCALL)
476
477 #define IOAPIC_IMF_CONF         0x1
478
479 extern void     IOAPIC_INTREN(int);
480 extern void     IOAPIC_INTRDIS(int);
481
482 extern int      imcr_present;
483
484 static void     ioapic_abi_intr_enable(int);
485 static void     ioapic_abi_intr_disable(int);
486 static void     ioapic_abi_intr_setup(int, int);
487 static void     ioapic_abi_intr_teardown(int);
488 static void     ioapic_abi_intr_config(int,
489                     enum intr_trigger, enum intr_polarity);
490 static int      ioapic_abi_intr_cpuid(int);
491
492 static void     ioapic_abi_finalize(void);
493 static void     ioapic_abi_cleanup(void);
494 static void     ioapic_abi_setdefault(void);
495 static void     ioapic_abi_stabilize(void);
496 static void     ioapic_abi_initmap(void);
497 static void     ioapic_abi_rman_setup(struct rman *);
498
499 static int      ioapic_abi_gsi_cpuid(int, int);
500
501 struct machintr_abi MachIntrABI_IOAPIC = {
502         MACHINTR_IOAPIC,
503         .intr_disable   = ioapic_abi_intr_disable,
504         .intr_enable    = ioapic_abi_intr_enable,
505         .intr_setup     = ioapic_abi_intr_setup,
506         .intr_teardown  = ioapic_abi_intr_teardown,
507         .intr_config    = ioapic_abi_intr_config,
508         .intr_cpuid     = ioapic_abi_intr_cpuid,
509
510         .finalize       = ioapic_abi_finalize,
511         .cleanup        = ioapic_abi_cleanup,
512         .setdefault     = ioapic_abi_setdefault,
513         .stabilize      = ioapic_abi_stabilize,
514         .initmap        = ioapic_abi_initmap,
515         .rman_setup     = ioapic_abi_rman_setup
516 };
517
518 static int      ioapic_abi_extint_irq = -1;
519 static int      ioapic_abi_line_irq_max;
520 static int      ioapic_abi_gsi_balance;
521
522 struct ioapic_irqinfo   ioapic_irqs[IOAPIC_HWI_VECTORS];
523
524 static void
525 ioapic_abi_intr_enable(int irq)
526 {
527         const struct ioapic_irqmap *map;
528
529         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
530             ("ioapic enable, invalid irq %d\n", irq));
531
532         map = &ioapic_irqmaps[mycpuid][irq];
533         KASSERT(IOAPIC_IMT_ISHWI(map),
534             ("ioapic enable, not hwi irq %d, type %d, cpu%d\n",
535              irq, map->im_type, mycpuid));
536         if (map->im_type != IOAPIC_IMT_LINE) {
537                 kprintf("ioapic enable, irq %d cpu%d not LINE\n",
538                     irq, mycpuid);
539                 return;
540         }
541
542         IOAPIC_INTREN(irq);
543 }
544
545 static void
546 ioapic_abi_intr_disable(int irq)
547 {
548         const struct ioapic_irqmap *map;
549
550         KASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS,
551             ("ioapic disable, invalid irq %d\n", irq));
552
553         map = &ioapic_irqmaps[mycpuid][irq];
554         KASSERT(IOAPIC_IMT_ISHWI(map),
555             ("ioapic disable, not hwi irq %d, type %d, cpu%d\n",
556              irq, map->im_type, mycpuid));
557         if (map->im_type != IOAPIC_IMT_LINE) {
558                 kprintf("ioapic disable, irq %d cpu%d not LINE\n",
559                     irq, mycpuid);
560                 return;
561         }
562
563         IOAPIC_INTRDIS(irq);
564 }
565
566 static void
567 ioapic_abi_finalize(void)
568 {
569         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
570         KKASSERT(ioapic_enable);
571
572         /*
573          * If an IMCR is present, program bit 0 to disconnect the 8259
574          * from the BSP.
575          */
576         if (imcr_present) {
577                 outb(0x22, 0x70);       /* select IMCR */
578                 outb(0x23, 0x01);       /* disconnect 8259 */
579         }
580 }
581
582 /*
583  * This routine is called after physical interrupts are enabled but before
584  * the critical section is released.  We need to clean out any interrupts
585  * that had already been posted to the cpu.
586  */
587 static void
588 ioapic_abi_cleanup(void)
589 {
590         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
591 }
592
593 /* Must never be called */
594 static void
595 ioapic_abi_stabilize(void)
596 {
597         panic("ioapic_stabilize is called\n");
598 }
599
600 static void
601 ioapic_abi_intr_setup(int intr, int flags)
602 {
603         const struct ioapic_irqmap *map;
604         int vector, select;
605         uint32_t value;
606         register_t ef;
607
608         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
609             ("ioapic setup, invalid irq %d\n", intr));
610
611         map = &ioapic_irqmaps[mycpuid][intr];
612         KASSERT(IOAPIC_IMT_ISHWI(map),
613             ("ioapic setup, not hwi irq %d, type %d, cpu%d",
614              intr, map->im_type, mycpuid));
615         if (map->im_type != IOAPIC_IMT_LINE) {
616                 kprintf("ioapic setup, irq %d cpu%d not LINE\n",
617                     intr, mycpuid);
618                 return;
619         }
620
621         KASSERT(ioapic_irqs[intr].io_addr != NULL,
622             ("ioapic setup, no GSI information, irq %d\n", intr));
623
624         ef = read_rflags();
625         cpu_disable_intr();
626
627         vector = IDT_OFFSET + intr;
628
629         /*
630          * Now reprogram the vector in the IO APIC.  In order to avoid
631          * losing an EOI for a level interrupt, which is vector based,
632          * make sure that the IO APIC is programmed for edge-triggering
633          * first, then reprogrammed with the new vector.  This should
634          * clear the IRR bit.
635          */
636         imen_lock();
637
638         select = ioapic_irqs[intr].io_idx;
639         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
640         value |= IOART_INTMSET;
641
642         ioapic_write(ioapic_irqs[intr].io_addr, select,
643             (value & ~APIC_TRIGMOD_MASK));
644         ioapic_write(ioapic_irqs[intr].io_addr, select,
645             (value & ~IOART_INTVEC) | vector);
646
647         imen_unlock();
648
649         machintr_intr_enable(intr);
650
651         write_rflags(ef);
652 }
653
654 static void
655 ioapic_abi_intr_teardown(int intr)
656 {
657         const struct ioapic_irqmap *map;
658         int vector, select;
659         uint32_t value;
660         register_t ef;
661
662         KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS,
663             ("ioapic teardown, invalid irq %d\n", intr));
664
665         map = &ioapic_irqmaps[mycpuid][intr];
666         KASSERT(IOAPIC_IMT_ISHWI(map),
667             ("ioapic teardown, not hwi irq %d, type %d, cpu%d",
668              intr, map->im_type, mycpuid));
669         if (map->im_type != IOAPIC_IMT_LINE) {
670                 kprintf("ioapic teardown, irq %d cpu%d not LINE\n",
671                     intr, mycpuid);
672                 return;
673         }
674
675         KASSERT(ioapic_irqs[intr].io_addr != NULL,
676             ("ioapic teardown, no GSI information, irq %d\n", intr));
677
678         ef = read_rflags();
679         cpu_disable_intr();
680
681         /*
682          * Teardown an interrupt vector.  The vector should already be
683          * installed in the cpu's IDT, but make sure.
684          */
685         machintr_intr_disable(intr);
686
687         vector = IDT_OFFSET + intr;
688
689         /*
690          * In order to avoid losing an EOI for a level interrupt, which
691          * is vector based, make sure that the IO APIC is programmed for
692          * edge-triggering first, then reprogrammed with the new vector.
693          * This should clear the IRR bit.
694          */
695         imen_lock();
696
697         select = ioapic_irqs[intr].io_idx;
698         value = ioapic_read(ioapic_irqs[intr].io_addr, select);
699
700         ioapic_write(ioapic_irqs[intr].io_addr, select,
701             (value & ~APIC_TRIGMOD_MASK));
702         ioapic_write(ioapic_irqs[intr].io_addr, select,
703             (value & ~IOART_INTVEC) | vector);
704
705         imen_unlock();
706
707         write_rflags(ef);
708 }
709
710 static void
711 ioapic_abi_setdefault(void)
712 {
713         int intr;
714
715         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
716                 if (intr == IOAPIC_HWI_SYSCALL)
717                         continue;
718                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
719                        SEL_KPL, 0);
720         }
721 }
722
723 static void
724 ioapic_abi_initmap(void)
725 {
726         int cpu;
727
728         kgetenv_int("hw.ioapic.gsi.balance", &ioapic_abi_gsi_balance);
729
730         /*
731          * NOTE: ncpus is not ready yet
732          */
733         for (cpu = 0; cpu < MAXCPU; ++cpu) {
734                 int i;
735
736                 for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
737                         ioapic_irqmaps[cpu][i].im_gsi = -1;
738                 ioapic_irqmaps[cpu][IOAPIC_HWI_SYSCALL].im_type =
739                     IOAPIC_IMT_SYSCALL;
740         }
741 }
742
743 void
744 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
745     enum intr_polarity pola)
746 {
747         struct ioapic_irqinfo *info;
748         struct ioapic_irqmap *map;
749         void *ioaddr;
750         int pin, cpuid;
751
752         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
753         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
754
755         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
756         if (irq > ioapic_abi_line_irq_max)
757                 ioapic_abi_line_irq_max = irq;
758
759         cpuid = ioapic_abi_gsi_cpuid(irq, gsi);
760
761         map = &ioapic_irqmaps[cpuid][irq];
762
763         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
764         map->im_type = IOAPIC_IMT_LINE;
765
766         map->im_gsi = gsi;
767         map->im_trig = trig;
768         map->im_pola = pola;
769
770         if (bootverbose) {
771                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
772                         irq, map->im_gsi,
773                         intr_str_trigger(map->im_trig),
774                         intr_str_polarity(map->im_pola));
775         }
776
777         pin = ioapic_gsi_pin(map->im_gsi);
778         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
779
780         info = &ioapic_irqs[irq];
781
782         imen_lock();
783
784         info->io_addr = ioaddr;
785         info->io_idx = IOAPIC_REDTBL + (2 * pin);
786         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
787         if (map->im_trig == INTR_TRIGGER_LEVEL)
788                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
789
790         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
791             map->im_trig, map->im_pola, cpuid);
792
793         imen_unlock();
794 }
795
796 void
797 ioapic_abi_fixup_irqmap(void)
798 {
799         int cpu;
800
801         for (cpu = 0; cpu < ncpus; ++cpu) {
802                 int i;
803
804                 for (i = 0; i < ISA_IRQ_CNT; ++i) {
805                         struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][i];
806
807                         if (map->im_type == IOAPIC_IMT_UNUSED) {
808                                 map->im_type = IOAPIC_IMT_RESERVED;
809                                 if (bootverbose) {
810                                         kprintf("IOAPIC: "
811                                             "cpu%d irq %d reserved\n", cpu, i);
812                                 }
813                         }
814                 }
815         }
816
817         ioapic_abi_line_irq_max += 1;
818         if (bootverbose)
819                 kprintf("IOAPIC: line irq max %d\n", ioapic_abi_line_irq_max);
820 }
821
822 int
823 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
824 {
825         int cpu;
826
827         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
828         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
829
830         for (cpu = 0; cpu < ncpus; ++cpu) {
831                 int irq;
832
833                 for (irq = 0; irq < ioapic_abi_line_irq_max; ++irq) {
834                         const struct ioapic_irqmap *map =
835                             &ioapic_irqmaps[cpu][irq];
836
837                         if (map->im_gsi == gsi) {
838                                 KKASSERT(map->im_type == IOAPIC_IMT_LINE);
839
840                                 if (map->im_flags & IOAPIC_IMF_CONF) {
841                                         if (map->im_trig != trig ||
842                                             map->im_pola != pola)
843                                                 return -1;
844                                 }
845                                 return irq;
846                         }
847                 }
848         }
849         return -1;
850 }
851
852 int
853 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
854 {
855         int cpu;
856
857         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
858         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
859
860         if (irq < 0 || irq >= ioapic_abi_line_irq_max)
861                 return -1;
862
863         for (cpu = 0; cpu < ncpus; ++cpu) {
864                 const struct ioapic_irqmap *map = &ioapic_irqmaps[cpu][irq];
865
866                 if (map->im_type == IOAPIC_IMT_LINE) {
867                         if (map->im_flags & IOAPIC_IMF_CONF) {
868                                 if (map->im_trig != trig ||
869                                     map->im_pola != pola)
870                                         return -1;
871                         }
872                         return irq;
873                 }
874         }
875         return -1;
876 }
877
878 static void
879 ioapic_abi_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
880 {
881         struct ioapic_irqinfo *info;
882         struct ioapic_irqmap *map = NULL;
883         void *ioaddr;
884         int pin, cpuid;
885
886         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
887         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
888
889         KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
890         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
891                 map = &ioapic_irqmaps[cpuid][irq];
892                 if (map->im_type == IOAPIC_IMT_LINE)
893                         break;
894         }
895         KKASSERT(cpuid < ncpus);
896
897 #ifdef notyet
898         if (map->im_flags & IOAPIC_IMF_CONF) {
899                 if (trig != map->im_trig) {
900                         panic("ioapic_intr_config: trig %s -> %s\n",
901                               intr_str_trigger(map->im_trig),
902                               intr_str_trigger(trig));
903                 }
904                 if (pola != map->im_pola) {
905                         panic("ioapic_intr_config: pola %s -> %s\n",
906                               intr_str_polarity(map->im_pola),
907                               intr_str_polarity(pola));
908                 }
909                 return;
910         }
911 #endif
912         map->im_flags |= IOAPIC_IMF_CONF;
913
914         if (trig == map->im_trig && pola == map->im_pola)
915                 return;
916
917         if (bootverbose) {
918                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
919                         irq, map->im_gsi,
920                         intr_str_trigger(map->im_trig),
921                         intr_str_polarity(map->im_pola),
922                         intr_str_trigger(trig),
923                         intr_str_polarity(pola));
924         }
925         map->im_trig = trig;
926         map->im_pola = pola;
927
928         pin = ioapic_gsi_pin(map->im_gsi);
929         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
930
931         info = &ioapic_irqs[irq];
932
933         imen_lock();
934
935         info->io_flags &= ~IOAPIC_IRQI_FLAG_LEVEL;
936         if (map->im_trig == INTR_TRIGGER_LEVEL)
937                 info->io_flags |= IOAPIC_IRQI_FLAG_LEVEL;
938
939         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
940             map->im_trig, map->im_pola, cpuid);
941
942         imen_unlock();
943 }
944
945 int
946 ioapic_abi_extint_irqmap(int irq)
947 {
948         struct ioapic_irqinfo *info;
949         struct ioapic_irqmap *map;
950         void *ioaddr;
951         int pin, error, vec;
952
953         /* XXX only irq0 is allowed */
954         KKASSERT(irq == 0);
955
956         vec = IDT_OFFSET + irq;
957
958         if (ioapic_abi_extint_irq == irq)
959                 return 0;
960         else if (ioapic_abi_extint_irq >= 0)
961                 return EEXIST;
962
963         error = icu_ioapic_extint(irq, vec);
964         if (error)
965                 return error;
966
967         /* ExtINT is always targeted to cpu0 */
968         map = &ioapic_irqmaps[0][irq];
969
970         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
971                  map->im_type == IOAPIC_IMT_LINE);
972         if (map->im_type == IOAPIC_IMT_LINE) {
973                 if (map->im_flags & IOAPIC_IMF_CONF)
974                         return EEXIST;
975         }
976         ioapic_abi_extint_irq = irq;
977
978         map->im_type = IOAPIC_IMT_LINE;
979         map->im_trig = INTR_TRIGGER_EDGE;
980         map->im_pola = INTR_POLARITY_HIGH;
981         map->im_flags = IOAPIC_IMF_CONF;
982
983         map->im_gsi = ioapic_extpin_gsi();
984         KKASSERT(map->im_gsi >= 0);
985
986         if (bootverbose) {
987                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
988                         irq, map->im_gsi,
989                         intr_str_trigger(map->im_trig),
990                         intr_str_polarity(map->im_pola));
991         }
992
993         pin = ioapic_gsi_pin(map->im_gsi);
994         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
995
996         info = &ioapic_irqs[irq];
997
998         imen_lock();
999
1000         info->io_addr = ioaddr;
1001         info->io_idx = IOAPIC_REDTBL + (2 * pin);
1002         info->io_flags = IOAPIC_IRQI_FLAG_MASKED;
1003
1004         ioapic_extpin_setup(ioaddr, pin, vec);
1005
1006         imen_unlock();
1007
1008         return 0;
1009 }
1010
1011 static int
1012 ioapic_abi_intr_cpuid(int irq)
1013 {
1014         const struct ioapic_irqmap *map = NULL;
1015         int cpuid;
1016
1017         KKASSERT(irq >= 0 && irq < ioapic_abi_line_irq_max);
1018
1019         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1020                 map = &ioapic_irqmaps[cpuid][irq];
1021                 if (map->im_type == IOAPIC_IMT_LINE)
1022                         return cpuid;
1023         }
1024
1025         /* XXX some drivers tries to peek at reserved IRQs */
1026         for (cpuid = 0; cpuid < ncpus; ++cpuid) {
1027                 map = &ioapic_irqmaps[cpuid][irq];
1028                 KKASSERT(map->im_type == IOAPIC_IMT_RESERVED);
1029         }
1030         return 0;
1031 }
1032
1033 static int
1034 ioapic_abi_gsi_cpuid(int irq, int gsi)
1035 {
1036         char envpath[32];
1037         int cpuid = -1;
1038
1039         KKASSERT(gsi >= 0);
1040
1041         if (irq == 0 || gsi == 0) {
1042                 if (bootverbose) {
1043                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (0)\n",
1044                             irq, gsi);
1045                 }
1046                 return 0;
1047         }
1048
1049         if (irq == acpi_sci_irqno()) {
1050                 if (bootverbose) {
1051                         kprintf("IOAPIC: irq %d, gsi %d -> cpu0 (sci)\n",
1052                             irq, gsi);
1053                 }
1054                 return 0;
1055         }
1056
1057         ksnprintf(envpath, sizeof(envpath), "hw.ioapic.gsi.%d.cpu", gsi);
1058         kgetenv_int(envpath, &cpuid);
1059
1060         if (cpuid < 0) {
1061                 if (!ioapic_abi_gsi_balance) {
1062                         if (bootverbose) {
1063                                 kprintf("IOAPIC: irq %d, gsi %d -> cpu0 "
1064                                     "(fixed)\n", irq, gsi);
1065                         }
1066                         return 0;
1067                 }
1068
1069                 cpuid = gsi % ncpus;
1070                 if (bootverbose) {
1071                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (auto)\n",
1072                             irq, gsi, cpuid);
1073                 }
1074         } else if (cpuid >= ncpus) {
1075                 cpuid = ncpus - 1;
1076                 if (bootverbose) {
1077                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (fixup)\n",
1078                             irq, gsi, cpuid);
1079                 }
1080         } else {
1081                 if (bootverbose) {
1082                         kprintf("IOAPIC: irq %d, gsi %d -> cpu%d (user)\n",
1083                             irq, gsi, cpuid);
1084                 }
1085         }
1086         return cpuid;
1087 }
1088
1089 static void
1090 ioapic_abi_rman_setup(struct rman *rm)
1091 {
1092         int start, end, i;
1093
1094         KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
1095             ("invalid rman cpuid %d", rm->rm_cpuid));
1096
1097         start = end = -1;
1098         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i) {
1099                 const struct ioapic_irqmap *map =
1100                     &ioapic_irqmaps[rm->rm_cpuid][i];
1101
1102                 if (start < 0) {
1103                         if (IOAPIC_IMT_ISHWI(map))
1104                                 start = end = i;
1105                 } else {
1106                         if (IOAPIC_IMT_ISHWI(map)) {
1107                                 end = i;
1108                         } else {
1109                                 KKASSERT(end >= 0);
1110                                 if (bootverbose) {
1111                                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1112                                             rm->rm_cpuid, start, end);
1113                                 }
1114                                 if (rman_manage_region(rm, start, end)) {
1115                                         panic("rman_manage_region"
1116                                             "(cpu%d %d - %d)", rm->rm_cpuid,
1117                                             start, end);
1118                                 }
1119                                 start = end = -1;
1120                         }
1121                 }
1122         }
1123         if (start >= 0) {
1124                 KKASSERT(end >= 0);
1125                 if (bootverbose) {
1126                         kprintf("IOAPIC: rman cpu%d %d - %d\n",
1127                             rm->rm_cpuid, start, end);
1128                 }
1129                 if (rman_manage_region(rm, start, end)) {
1130                         panic("rman_manage_region(cpu%d %d - %d)",
1131                             rm->rm_cpuid, start, end);
1132                 }
1133         }
1134 }