2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/queue.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
71 #include <dev/netif/bfe/if_bfereg.h>
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81 struct bfe_dmamap_ctx {
83 bus_dma_segment_t *segs;
86 static struct bfe_type bfe_devs[] = {
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
88 "Broadcom BCM4401 Fast Ethernet" },
89 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
90 "Broadcom BCM4401-B0 Fast Ethernet" },
91 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
92 "Broadcom BCM4402 Fast Ethernet" },
96 static int bfe_probe(device_t);
97 static int bfe_attach(device_t);
98 static int bfe_detach(device_t);
99 static void bfe_intr(void *);
100 static void bfe_start(struct ifnet *);
101 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void bfe_init(void *);
103 static void bfe_stop(struct bfe_softc *);
104 static void bfe_watchdog(struct ifnet *);
105 static void bfe_shutdown(device_t);
106 static void bfe_tick(void *);
107 static void bfe_txeof(struct bfe_softc *);
108 static void bfe_rxeof(struct bfe_softc *);
109 static void bfe_set_rx_mode(struct bfe_softc *);
110 static int bfe_list_rx_init(struct bfe_softc *);
111 static int bfe_newbuf(struct bfe_softc *, int, int);
112 static void bfe_setup_rxdesc(struct bfe_softc *, int);
113 static void bfe_rx_ring_free(struct bfe_softc *);
115 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
116 static int bfe_ifmedia_upd(struct ifnet *);
117 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
118 static int bfe_miibus_readreg(device_t, int, int);
119 static int bfe_miibus_writereg(device_t, int, int, int);
120 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
122 static void bfe_get_config(struct bfe_softc *sc);
123 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
124 static void bfe_stats_update(struct bfe_softc *);
125 static void bfe_clear_stats (struct bfe_softc *);
126 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
127 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
128 static int bfe_resetphy(struct bfe_softc *);
129 static int bfe_setupphy(struct bfe_softc *);
130 static void bfe_chip_reset(struct bfe_softc *);
131 static void bfe_chip_halt(struct bfe_softc *);
132 static void bfe_core_reset(struct bfe_softc *);
133 static void bfe_core_disable(struct bfe_softc *);
134 static int bfe_dma_alloc(device_t);
135 static void bfe_dma_free(struct bfe_softc *);
136 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
137 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
138 static void bfe_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
141 static device_method_t bfe_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, bfe_probe),
144 DEVMETHOD(device_attach, bfe_attach),
145 DEVMETHOD(device_detach, bfe_detach),
146 DEVMETHOD(device_shutdown, bfe_shutdown),
149 DEVMETHOD(bus_print_child, bus_generic_print_child),
150 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
153 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
154 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
159 static driver_t bfe_driver = {
162 sizeof(struct bfe_softc)
165 static devclass_t bfe_devclass;
167 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
168 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
171 * Probe for a Broadcom 4401 chip.
174 bfe_probe(device_t dev)
177 uint16_t vendor, product;
179 vendor = pci_get_vendor(dev);
180 product = pci_get_device(dev);
182 for (t = bfe_devs; t->bfe_name != NULL; t++) {
183 if (vendor == t->bfe_vid && product == t->bfe_did) {
184 device_set_desc(dev, t->bfe_name);
193 bfe_dma_alloc(device_t dev)
195 struct bfe_softc *sc = device_get_softc(dev);
196 int error, i, tx_pos = 0, rx_pos = 0;
199 * Parent tag. Apparently the chip cannot handle any DMA address
200 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
202 error = bus_dma_tag_create(NULL, /* parent */
203 1, 0, /* alignment, boundary */
204 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
205 BUS_SPACE_MAXADDR, /* highaddr */
206 NULL, NULL, /* filter, filterarg */
207 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
208 0, /* num of segments */
209 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
211 &sc->bfe_parent_tag);
213 device_printf(dev, "could not allocate parent dma tag\n");
217 /* tag for TX ring */
218 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
221 BFE_TX_LIST_SIZE, 1, BFE_TX_LIST_SIZE,
224 device_printf(dev, "could not allocate dma tag for TX list\n");
228 /* tag for RX ring */
229 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
230 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
232 BFE_RX_LIST_SIZE, 1, BFE_RX_LIST_SIZE,
235 device_printf(dev, "could not allocate dma tag for RX list\n");
239 /* Tag for RX mbufs */
240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
243 MCLBYTES, 1, MCLBYTES,
244 BUS_DMA_ALLOCNOW, &sc->bfe_rxbuf_tag);
246 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
250 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0, &sc->bfe_rx_tmpmap);
252 device_printf(dev, "could not create RX mbuf tmp map\n");
253 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
254 sc->bfe_rxbuf_tag = NULL;
258 /* Allocate dma maps for RX list */
259 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
260 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0,
261 &sc->bfe_rx_ring[i].bfe_map);
264 device_printf(dev, "cannot create DMA map for RX\n");
268 rx_pos = BFE_RX_LIST_CNT;
270 /* Tag for TX mbufs */
271 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
274 MCLBYTES, BFE_MAXSEGS, MCLBYTES,
275 BUS_DMA_ALLOCNOW, &sc->bfe_txbuf_tag);
277 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
281 /* Allocate dmamaps for TX list */
282 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
283 error = bus_dmamap_create(sc->bfe_txbuf_tag, 0,
284 &sc->bfe_tx_ring[i].bfe_map);
287 device_printf(dev, "cannot create DMA map for TX\n");
292 /* Alloc dma for rx ring */
293 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
294 BUS_DMA_WAITOK | BUS_DMA_ZERO,
297 device_printf(dev, "cannot allocate DMA mem for RX\n");
301 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
302 sc->bfe_rx_list, sizeof(struct bfe_desc),
303 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
305 device_printf(dev, "cannot load DMA map for RX\n");
309 /* Alloc dma for tx ring */
310 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
311 BUS_DMA_WAITOK | BUS_DMA_ZERO,
314 device_printf(dev, "cannot allocate DMA mem for TX\n");
318 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
319 sc->bfe_tx_list, sizeof(struct bfe_desc),
320 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
322 device_printf(dev, "cannot load DMA map for TX\n");
329 if (sc->bfe_rxbuf_tag != NULL) {
330 for (i = 0; i < rx_pos; ++i) {
331 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
332 sc->bfe_rx_ring[i].bfe_map);
334 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
335 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
336 sc->bfe_rxbuf_tag = NULL;
339 if (sc->bfe_txbuf_tag != NULL) {
340 for (i = 0; i < tx_pos; ++i) {
341 bus_dmamap_destroy(sc->bfe_txbuf_tag,
342 sc->bfe_tx_ring[i].bfe_map);
344 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
345 sc->bfe_txbuf_tag = NULL;
351 bfe_attach(device_t dev)
354 struct bfe_softc *sc;
357 sc = device_get_softc(dev);
360 callout_init(&sc->bfe_stat_timer);
364 * Handle power management nonsense.
366 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
367 uint32_t membase, irq;
369 /* Save important PCI config data. */
370 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
371 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
373 /* Reset the power state. */
374 device_printf(dev, "chip is in D%d power mode"
375 " -- setting to D0\n", pci_get_powerstate(dev));
377 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
379 /* Restore PCI config data. */
380 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
381 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
383 #endif /* !BURN_BRIDGE */
386 * Map control/status registers.
388 pci_enable_busmaster(dev);
391 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
393 if (sc->bfe_res == NULL) {
394 device_printf(dev, "couldn't map memory\n");
398 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
399 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
401 /* Allocate interrupt */
404 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
405 RF_SHAREABLE | RF_ACTIVE);
406 if (sc->bfe_irq == NULL) {
407 device_printf(dev, "couldn't map interrupt\n");
412 error = bfe_dma_alloc(dev);
414 device_printf(dev, "failed to allocate DMA resources\n");
418 /* Set up ifnet structure */
419 ifp = &sc->arpcom.ac_if;
421 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
422 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
423 ifp->if_ioctl = bfe_ioctl;
424 ifp->if_start = bfe_start;
425 ifp->if_watchdog = bfe_watchdog;
426 ifp->if_init = bfe_init;
427 ifp->if_mtu = ETHERMTU;
428 ifp->if_baudrate = 100000000;
429 ifp->if_capabilities |= IFCAP_VLAN_MTU;
430 ifp->if_capenable |= IFCAP_VLAN_MTU;
431 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
432 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
433 ifq_set_ready(&ifp->if_snd);
437 /* Reset the chip and turn on the PHY */
440 if (mii_phy_probe(dev, &sc->bfe_miibus,
441 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
442 device_printf(dev, "MII without any PHY!\n");
447 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
450 * Hook interrupt last to avoid having to lock softc
452 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
453 bfe_intr, sc, &sc->bfe_intrhand,
454 sc->arpcom.ac_if.if_serializer);
458 device_printf(dev, "couldn't set up irq\n");
462 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
463 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
471 bfe_detach(device_t dev)
473 struct bfe_softc *sc = device_get_softc(dev);
474 struct ifnet *ifp = &sc->arpcom.ac_if;
476 if (device_is_attached(dev)) {
477 lwkt_serialize_enter(ifp->if_serializer);
480 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
481 lwkt_serialize_exit(ifp->if_serializer);
485 if (sc->bfe_miibus != NULL)
486 device_delete_child(dev, sc->bfe_miibus);
487 bus_generic_detach(dev);
489 if (sc->bfe_irq != NULL)
490 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
492 if (sc->bfe_res != NULL) {
493 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
502 * Stop all chip I/O so that the kernel's probe routines don't
503 * get confused by errant DMAs when rebooting.
506 bfe_shutdown(device_t dev)
508 struct bfe_softc *sc = device_get_softc(dev);
509 struct ifnet *ifp = &sc->arpcom.ac_if;
511 lwkt_serialize_enter(ifp->if_serializer);
513 lwkt_serialize_exit(ifp->if_serializer);
517 bfe_miibus_readreg(device_t dev, int phy, int reg)
519 struct bfe_softc *sc;
522 sc = device_get_softc(dev);
523 if (phy != sc->bfe_phyaddr)
525 bfe_readphy(sc, reg, &ret);
531 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
533 struct bfe_softc *sc;
535 sc = device_get_softc(dev);
536 if (phy != sc->bfe_phyaddr)
538 bfe_writephy(sc, reg, val);
544 bfe_tx_ring_free(struct bfe_softc *sc)
548 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
549 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
550 bus_dmamap_unload(sc->bfe_txbuf_tag,
551 sc->bfe_tx_ring[i].bfe_map);
552 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
553 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
556 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
557 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
561 bfe_rx_ring_free(struct bfe_softc *sc)
565 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
566 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
567 bus_dmamap_unload(sc->bfe_rxbuf_tag,
568 sc->bfe_rx_ring[i].bfe_map);
569 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
570 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
573 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
574 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
578 bfe_list_rx_init(struct bfe_softc *sc)
582 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
583 error = bfe_newbuf(sc, i, 1);
588 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
589 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
597 bfe_newbuf(struct bfe_softc *sc, int c, int init)
601 bus_dma_segment_t seg;
602 struct bfe_dmamap_ctx ctx;
606 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
609 m->m_len = m->m_pkthdr.len = MCLBYTES;
613 error = bus_dmamap_load_mbuf(sc->bfe_rxbuf_tag,
615 m, bfe_dmamap_buf_cb, &ctx,
617 if (error || ctx.nsegs == 0) {
619 bus_dmamap_unload(sc->bfe_rxbuf_tag,
622 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
627 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
631 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
632 r = &sc->bfe_rx_ring[c];
634 if (r->bfe_mbuf != NULL)
635 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
638 r->bfe_map = sc->bfe_rx_tmpmap;
639 sc->bfe_rx_tmpmap = map;
642 r->bfe_paddr = seg.ds_addr;
644 bfe_setup_rxdesc(sc, c);
649 bfe_setup_rxdesc(struct bfe_softc *sc, int c)
651 struct bfe_rxheader *rx_header;
657 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
658 r = &sc->bfe_rx_ring[c];
659 d = &sc->bfe_rx_list[c];
661 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
664 rx_header = mtod(m, struct bfe_rxheader *);
666 rx_header->flags = 0;
667 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
669 ctrl = ETHER_MAX_LEN + 32;
670 if (c == BFE_RX_LIST_CNT - 1)
671 ctrl |= BFE_DESC_EOT;
673 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
675 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
679 bfe_get_config(struct bfe_softc *sc)
683 bfe_read_eeprom(sc, eeprom);
685 sc->arpcom.ac_enaddr[0] = eeprom[79];
686 sc->arpcom.ac_enaddr[1] = eeprom[78];
687 sc->arpcom.ac_enaddr[2] = eeprom[81];
688 sc->arpcom.ac_enaddr[3] = eeprom[80];
689 sc->arpcom.ac_enaddr[4] = eeprom[83];
690 sc->arpcom.ac_enaddr[5] = eeprom[82];
692 sc->bfe_phyaddr = eeprom[90] & 0x1f;
693 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
695 sc->bfe_core_unit = 0;
696 sc->bfe_dma_offset = BFE_PCI_DMA;
700 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
702 uint32_t bar_orig, pci_rev, val;
704 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
705 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
706 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
708 val = CSR_READ_4(sc, BFE_SBINTVEC);
710 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
712 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
713 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
714 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
716 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
720 bfe_clear_stats(struct bfe_softc *sc)
724 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
725 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
727 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
732 bfe_resetphy(struct bfe_softc *sc)
736 bfe_writephy(sc, 0, BMCR_RESET);
738 bfe_readphy(sc, 0, &val);
739 if (val & BMCR_RESET) {
740 if_printf(&sc->arpcom.ac_if,
741 "PHY Reset would not complete.\n");
748 bfe_chip_halt(struct bfe_softc *sc)
750 /* disable interrupts - not that it actually does..*/
751 CSR_WRITE_4(sc, BFE_IMASK, 0);
752 CSR_READ_4(sc, BFE_IMASK);
754 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
755 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
757 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
758 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
763 bfe_chip_reset(struct bfe_softc *sc)
767 /* Set the interrupt vector for the enet core */
768 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
771 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
772 if (val == BFE_CLOCK) {
773 /* It is, so shut it down */
774 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
775 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
776 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
777 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
778 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
779 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
780 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
781 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
789 * We want the phy registers to be accessible even when
790 * the driver is "downed" so initialize MDC preamble, frequency,
791 * and whether internal or external phy here.
794 /* 4402 has 62.5Mhz SB clock and internal phy */
795 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
797 /* Internal or external PHY? */
798 val = CSR_READ_4(sc, BFE_DEVCTRL);
799 if (!(val & BFE_IPP))
800 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
801 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
802 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
806 /* Enable CRC32 generation and set proper LED modes */
807 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
809 /* Reset or clear powerdown control bit */
810 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
812 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
816 * We don't want lazy interrupts, so just send them at the end of a
819 BFE_OR(sc, BFE_RCV_LAZY, 0);
821 /* Set max lengths, accounting for VLAN tags */
822 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
823 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
825 /* Set watermark XXX - magic */
826 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
829 * Initialise DMA channels - not forgetting dma addresses need to be
830 * added to BFE_PCI_DMA
832 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
833 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
835 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
837 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
844 bfe_core_disable(struct bfe_softc *sc)
846 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
850 * Set reject, wait for it set, then wait for the core to stop being busy
851 * Then set reset and reject and enable the clocks
853 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
854 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
855 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
856 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
858 CSR_READ_4(sc, BFE_SBTMSLOW);
860 /* Leave reset and reject set */
861 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
866 bfe_core_reset(struct bfe_softc *sc)
870 /* Disable the core */
871 bfe_core_disable(sc);
873 /* and bring it back up */
874 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
875 CSR_READ_4(sc, BFE_SBTMSLOW);
878 /* Chip bug, clear SERR, IB and TO if they are set. */
879 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
880 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
881 val = CSR_READ_4(sc, BFE_SBIMSTATE);
882 if (val & (BFE_IBE | BFE_TO))
883 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
885 /* Clear reset and allow it to move through the core */
886 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
887 CSR_READ_4(sc, BFE_SBTMSLOW);
890 /* Leave the clock set */
891 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
892 CSR_READ_4(sc, BFE_SBTMSLOW);
897 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
901 val = ((uint32_t) data[2]) << 24;
902 val |= ((uint32_t) data[3]) << 16;
903 val |= ((uint32_t) data[4]) << 8;
904 val |= ((uint32_t) data[5]);
905 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
906 val = (BFE_CAM_HI_VALID |
907 (((uint32_t) data[0]) << 8) |
908 (((uint32_t) data[1])));
909 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
910 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
911 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
912 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
916 bfe_set_rx_mode(struct bfe_softc *sc)
918 struct ifnet *ifp = &sc->arpcom.ac_if;
919 struct ifmultiaddr *ifma;
923 val = CSR_READ_4(sc, BFE_RXCONF);
925 if (ifp->if_flags & IFF_PROMISC)
926 val |= BFE_RXCONF_PROMISC;
928 val &= ~BFE_RXCONF_PROMISC;
930 if (ifp->if_flags & IFF_BROADCAST)
931 val &= ~BFE_RXCONF_DBCAST;
933 val |= BFE_RXCONF_DBCAST;
936 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
937 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
939 if (ifp->if_flags & IFF_ALLMULTI) {
940 val |= BFE_RXCONF_ALLMULTI;
942 val &= ~BFE_RXCONF_ALLMULTI;
943 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
944 if (ifma->ifma_addr->sa_family != AF_LINK)
947 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
951 CSR_WRITE_4(sc, BFE_RXCONF, val);
952 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
956 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
961 *ptr = segs->ds_addr;
965 bfe_dma_free(struct bfe_softc *sc)
969 if (sc->bfe_tx_tag != NULL) {
970 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
971 if (sc->bfe_tx_list != NULL) {
972 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
974 sc->bfe_tx_list = NULL;
976 bus_dma_tag_destroy(sc->bfe_tx_tag);
977 sc->bfe_tx_tag = NULL;
980 if (sc->bfe_rx_tag != NULL) {
981 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
982 if (sc->bfe_rx_list != NULL) {
983 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
985 sc->bfe_rx_list = NULL;
987 bus_dma_tag_destroy(sc->bfe_rx_tag);
988 sc->bfe_rx_tag = NULL;
991 if (sc->bfe_txbuf_tag != NULL) {
992 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
993 bus_dmamap_destroy(sc->bfe_txbuf_tag,
994 sc->bfe_tx_ring[i].bfe_map);
996 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
997 sc->bfe_txbuf_tag = NULL;
1000 if (sc->bfe_rxbuf_tag != NULL) {
1001 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
1002 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
1003 sc->bfe_rx_ring[i].bfe_map);
1005 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
1006 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
1007 sc->bfe_rxbuf_tag = NULL;
1010 if (sc->bfe_parent_tag != NULL) {
1011 bus_dma_tag_destroy(sc->bfe_parent_tag);
1012 sc->bfe_parent_tag = NULL;
1017 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
1020 uint16_t *ptr = (uint16_t *)data;
1022 for (i = 0; i < 128; i += 2)
1023 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1027 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
1028 u_long timeout, const int clear)
1032 for (i = 0; i < timeout; i++) {
1033 uint32_t val = CSR_READ_4(sc, reg);
1035 if (clear && !(val & bit))
1037 if (!clear && (val & bit))
1042 if_printf(&sc->arpcom.ac_if,
1043 "BUG! Timeout waiting for bit %08x of register "
1044 "%x to %s.\n", bit, reg,
1045 (clear ? "clear" : "set"));
1052 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1057 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1058 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1059 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1060 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1061 (reg << BFE_MDIO_RA_SHIFT) |
1062 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1063 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1064 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1069 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1073 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1074 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1075 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1076 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1077 (reg << BFE_MDIO_RA_SHIFT) |
1078 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1079 (val & BFE_MDIO_DATA_DATA)));
1080 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1086 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1090 bfe_setupphy(struct bfe_softc *sc)
1094 /* Enable activity LED */
1095 bfe_readphy(sc, 26, &val);
1096 bfe_writephy(sc, 26, val & 0x7fff);
1097 bfe_readphy(sc, 26, &val);
1099 /* Enable traffic meter LED mode */
1100 bfe_readphy(sc, 27, &val);
1101 bfe_writephy(sc, 27, val | (1 << 6));
1107 bfe_stats_update(struct bfe_softc *sc)
1112 val = &sc->bfe_hwstats.tx_good_octets;
1113 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1114 *val++ += CSR_READ_4(sc, reg);
1115 val = &sc->bfe_hwstats.rx_good_octets;
1116 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1117 *val++ += CSR_READ_4(sc, reg);
1121 bfe_txeof(struct bfe_softc *sc)
1123 struct ifnet *ifp = &sc->arpcom.ac_if;
1124 uint32_t i, chipidx;
1126 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1127 chipidx /= sizeof(struct bfe_desc);
1129 i = sc->bfe_tx_cons;
1131 /* Go through the mbufs and free those that have been transmitted */
1132 while (i != chipidx) {
1133 struct bfe_data *r = &sc->bfe_tx_ring[i];
1135 if (r->bfe_mbuf != NULL) {
1137 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1138 m_freem(r->bfe_mbuf);
1142 KKASSERT(sc->bfe_tx_cnt > 0);
1144 BFE_INC(i, BFE_TX_LIST_CNT);
1147 if (i != sc->bfe_tx_cons) {
1148 sc->bfe_tx_cons = i;
1150 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT)
1151 ifp->if_flags &= ~IFF_OACTIVE;
1153 if (sc->bfe_tx_cnt == 0)
1157 /* Pass a received packet up the stack */
1159 bfe_rxeof(struct bfe_softc *sc)
1161 struct ifnet *ifp = &sc->arpcom.ac_if;
1163 struct bfe_rxheader *rxheader;
1165 uint32_t cons, status, current, len, flags;
1166 struct mbuf_chain chain[MAXCPU];
1168 cons = sc->bfe_rx_cons;
1169 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1170 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1172 ether_input_chain_init(chain);
1174 while (current != cons) {
1175 r = &sc->bfe_rx_ring[cons];
1176 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1177 BUS_DMASYNC_POSTREAD);
1179 KKASSERT(r->bfe_mbuf != NULL);
1181 rxheader = mtod(m, struct bfe_rxheader*);
1182 len = rxheader->len - ETHER_CRC_LEN;
1183 flags = rxheader->flags;
1185 /* flag an error and try again */
1186 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
1188 if (flags & BFE_RX_FLAG_SERR)
1189 ifp->if_collisions++;
1191 bfe_setup_rxdesc(sc, cons);
1192 BFE_INC(cons, BFE_RX_LIST_CNT);
1196 /* Go past the rx header */
1197 if (bfe_newbuf(sc, cons, 0) != 0) {
1198 bfe_setup_rxdesc(sc, cons);
1200 BFE_INC(cons, BFE_RX_LIST_CNT);
1204 m_adj(m, BFE_RX_OFFSET);
1205 m->m_len = m->m_pkthdr.len = len;
1208 m->m_pkthdr.rcvif = ifp;
1210 ether_input_chain(ifp, m, chain);
1211 BFE_INC(cons, BFE_RX_LIST_CNT);
1214 ether_input_dispatch(chain);
1216 sc->bfe_rx_cons = cons;
1222 struct bfe_softc *sc = xsc;
1223 struct ifnet *ifp = &sc->arpcom.ac_if;
1224 uint32_t istat, imask, flag;
1226 istat = CSR_READ_4(sc, BFE_ISTAT);
1227 imask = CSR_READ_4(sc, BFE_IMASK);
1230 * Defer unsolicited interrupts - This is necessary because setting the
1231 * chips interrupt mask register to 0 doesn't actually stop the
1235 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1236 CSR_READ_4(sc, BFE_ISTAT);
1238 /* not expecting this interrupt, disregard it */
1243 if (istat & BFE_ISTAT_ERRORS) {
1244 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1245 if (flag & BFE_STAT_EMASK)
1248 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1249 if (flag & BFE_RX_FLAG_ERRORS)
1252 ifp->if_flags &= ~IFF_RUNNING;
1256 /* A packet was received */
1257 if (istat & BFE_ISTAT_RX)
1260 /* A packet was sent */
1261 if (istat & BFE_ISTAT_TX)
1264 /* We have packets pending, fire them out */
1265 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1270 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1272 struct mbuf *m = *m_head;
1273 struct bfe_dmamap_ctx ctx;
1274 bus_dma_segment_t segs[BFE_MAXSEGS];
1276 int i, first_idx, last_idx, cur, error, maxsegs;
1278 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT);
1279 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC;
1280 if (maxsegs > BFE_MAXSEGS)
1281 maxsegs = BFE_MAXSEGS;
1284 map = sc->bfe_tx_ring[first_idx].bfe_map;
1287 ctx.nsegs = maxsegs;
1288 error = bus_dmamap_load_mbuf(sc->bfe_txbuf_tag, map, m,
1289 bfe_dmamap_buf_cb, &ctx, BUS_DMA_NOWAIT);
1290 if (!error && ctx.nsegs == 0) {
1291 bus_dmamap_unload(sc->bfe_txbuf_tag, map);
1294 if (error && error != EFBIG)
1296 if (error) { /* error == EFBIG */
1299 m_new = m_defrag(m, MB_DONTWAIT);
1300 if (m_new == NULL) {
1305 *m_head = m = m_new;
1309 ctx.nsegs = maxsegs;
1310 error = bus_dmamap_load_mbuf(sc->bfe_txbuf_tag, map, m,
1311 bfe_dmamap_buf_cb, &ctx,
1313 if (error || ctx.nsegs == 0) {
1315 bus_dmamap_unload(sc->bfe_txbuf_tag, map);
1321 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1325 for (i = 0; i < ctx.nsegs; ++i) {
1329 ctrl = BFE_DESC_LEN & segs[i].ds_len;
1330 ctrl |= BFE_DESC_IOC; /* always interrupt */
1331 if (cur == BFE_TX_LIST_CNT - 1) {
1333 * Tell the chip to wrap to the
1334 * start of the descriptor list.
1336 ctrl |= BFE_DESC_EOT;
1339 d = &sc->bfe_tx_list[cur];
1340 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA;
1344 BFE_INC(cur, BFE_TX_LIST_CNT);
1346 KKASSERT(last_idx >= 0);
1348 /* End of the frame */
1349 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF;
1352 * Set start of the frame on the first fragment,
1353 * _after_ all of the fragments are setup.
1355 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF;
1357 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map;
1358 sc->bfe_tx_ring[last_idx].bfe_map = map;
1359 sc->bfe_tx_ring[last_idx].bfe_mbuf = m;
1361 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1364 sc->bfe_tx_cnt += ctx.nsegs;
1369 * Set up to transmit a packet
1372 bfe_start(struct ifnet *ifp)
1374 struct bfe_softc *sc = ifp->if_softc;
1375 struct mbuf *m_head = NULL;
1376 int idx, need_trans;
1378 ASSERT_SERIALIZED(ifp->if_serializer);
1381 * Not much point trying to send if the link is down
1382 * or we have nothing to send.
1384 if (!sc->bfe_link) {
1385 ifq_purge(&ifp->if_snd);
1389 if (ifp->if_flags & IFF_OACTIVE)
1392 idx = sc->bfe_tx_prod;
1395 while (!ifq_is_empty(&ifp->if_snd)) {
1396 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) {
1397 ifp->if_flags |= IFF_OACTIVE;
1401 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1406 * Pack the data into the tx ring. If we don't have
1407 * enough room, let the chip drain the ring.
1409 if (bfe_encap(sc, &m_head, &idx)) {
1410 ifp->if_flags |= IFF_OACTIVE;
1412 ifq_prepend(&ifp->if_snd, m_head);
1420 * If there's a BPF listener, bounce a copy of this frame
1423 BPF_MTAP(ifp, m_head);
1429 sc->bfe_tx_prod = idx;
1431 /* Transmit - twice due to apparent hardware bug */
1432 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1433 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1436 * Set a timeout in case the chip goes out to lunch.
1444 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1445 struct ifnet *ifp = &sc->arpcom.ac_if;
1447 ASSERT_SERIALIZED(ifp->if_serializer);
1449 if (ifp->if_flags & IFF_RUNNING)
1455 if (bfe_list_rx_init(sc) == ENOBUFS) {
1456 if_printf(ifp, "bfe_init failed. "
1457 " Not enough memory for list buffers\n");
1462 bfe_set_rx_mode(sc);
1464 /* Enable the chip and core */
1465 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1466 /* Enable interrupts */
1467 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1469 bfe_ifmedia_upd(ifp);
1470 ifp->if_flags |= IFF_RUNNING;
1471 ifp->if_flags &= ~IFF_OACTIVE;
1473 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1477 * Set media options.
1480 bfe_ifmedia_upd(struct ifnet *ifp)
1482 struct bfe_softc *sc = ifp->if_softc;
1483 struct mii_data *mii;
1485 ASSERT_SERIALIZED(ifp->if_serializer);
1487 mii = device_get_softc(sc->bfe_miibus);
1489 if (mii->mii_instance) {
1490 struct mii_softc *miisc;
1491 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1492 miisc = LIST_NEXT(miisc, mii_list))
1493 mii_phy_reset(miisc);
1503 * Report current media status.
1506 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1508 struct bfe_softc *sc = ifp->if_softc;
1509 struct mii_data *mii;
1511 ASSERT_SERIALIZED(ifp->if_serializer);
1513 mii = device_get_softc(sc->bfe_miibus);
1515 ifmr->ifm_active = mii->mii_media_active;
1516 ifmr->ifm_status = mii->mii_media_status;
1520 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1522 struct bfe_softc *sc = ifp->if_softc;
1523 struct ifreq *ifr = (struct ifreq *) data;
1524 struct mii_data *mii;
1527 ASSERT_SERIALIZED(ifp->if_serializer);
1531 if (ifp->if_flags & IFF_UP)
1532 if (ifp->if_flags & IFF_RUNNING)
1533 bfe_set_rx_mode(sc);
1536 else if (ifp->if_flags & IFF_RUNNING)
1541 if (ifp->if_flags & IFF_RUNNING)
1542 bfe_set_rx_mode(sc);
1546 mii = device_get_softc(sc->bfe_miibus);
1547 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1551 error = ether_ioctl(ifp, command, data);
1558 bfe_watchdog(struct ifnet *ifp)
1560 struct bfe_softc *sc = ifp->if_softc;
1562 ASSERT_SERIALIZED(ifp->if_serializer);
1564 if_printf(ifp, "watchdog timeout -- resetting\n");
1566 ifp->if_flags &= ~IFF_RUNNING;
1575 struct bfe_softc *sc = xsc;
1576 struct mii_data *mii;
1577 struct ifnet *ifp = &sc->arpcom.ac_if;
1579 mii = device_get_softc(sc->bfe_miibus);
1581 lwkt_serialize_enter(ifp->if_serializer);
1583 bfe_stats_update(sc);
1584 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1586 if (sc->bfe_link == 0) {
1588 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1589 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1595 lwkt_serialize_exit(ifp->if_serializer);
1599 * Stop the adapter and free any mbufs allocated to the
1603 bfe_stop(struct bfe_softc *sc)
1605 struct ifnet *ifp = &sc->arpcom.ac_if;
1607 ASSERT_SERIALIZED(ifp->if_serializer);
1609 callout_stop(&sc->bfe_stat_timer);
1612 bfe_tx_ring_free(sc);
1613 bfe_rx_ring_free(sc);
1615 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1619 bfe_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
1620 bus_size_t mapsz __unused, int error)
1622 struct bfe_dmamap_ctx *ctx = xctx;
1628 if (nsegs > ctx->nsegs) {
1634 for (i = 0; i < nsegs; ++i)
1635 ctx->segs[i] = segs[i];