2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/pci/pcireg.h,v 1.64.2.4.2.1 2009/04/15 03:14:26 kensmith Exp $
34 #include <sys/types.h>
37 typedef u_int16_t pci_vendor_id_t;
38 typedef u_int16_t pci_product_id_t;
39 typedef u_int8_t pci_class_t;
40 typedef u_int8_t pci_subclass_t;
41 typedef u_int8_t pci_interface_t;
42 typedef u_int8_t pci_revision_t;
43 typedef u_int8_t pci_intr_pin_t;
44 typedef u_int8_t pci_intr_line_t;
45 typedef u_int32_t pcireg_t; /* ~typical configuration space */
48 * PCIM_xxx: mask to locate subfield in register
49 * PCIR_xxx: config register offset
50 * PCIC_xxx: device class
51 * PCIS_xxx: device subclass
52 * PCIP_xxx: device programming interface
53 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
55 * PCIY_xxx: capability identification number
58 /* some PCI bus constants */
60 #define PCI_BUSMAX 255
61 #define PCI_SLOTMAX 31
63 #define PCI_REGMAX 255
64 #define PCI_MAXHDRTYPE 2
66 /* PCI config header registers for all devices */
68 #define PCIR_DEVVENDOR 0x00
69 #define PCIR_VENDOR 0x00
70 #define PCIR_DEVICE 0x02
71 #define PCIR_COMMAND 0x04
72 #define PCIR_CARDBUSCIS 0x28
73 #define PCIM_CMD_PORTEN 0x0001
74 #define PCIM_CMD_MEMEN 0x0002
75 #define PCIM_CMD_BUSMASTEREN 0x0004
76 #define PCIM_CMD_SPECIALEN 0x0008
77 #define PCIM_CMD_MWRICEN 0x0010
78 #define PCIM_CMD_PERRESPEN 0x0040
79 #define PCIM_CMD_SERRESPEN 0x0100
80 #define PCIM_CMD_BACKTOBACK 0x0200
81 #define PCIM_CMD_INTxDIS 0x0400
82 #define PCIR_STATUS 0x06
83 #define PCIM_STATUS_CAPPRESENT 0x0010
84 #define PCIM_STATUS_66CAPABLE 0x0020
85 #define PCIM_STATUS_BACKTOBACK 0x0080
86 #define PCIM_STATUS_PERRREPORT 0x0100
87 #define PCIM_STATUS_SEL_FAST 0x0000
88 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
89 #define PCIM_STATUS_SEL_SLOW 0x0400
90 #define PCIM_STATUS_SEL_MASK 0x0600
91 #define PCIM_STATUS_STABORT 0x0800
92 #define PCIM_STATUS_RTABORT 0x1000
93 #define PCIM_STATUS_RMABORT 0x2000
94 #define PCIM_STATUS_SERR 0x4000
95 #define PCIM_STATUS_PERR 0x8000
96 #define PCIR_REVID 0x08
97 #define PCIR_PROGIF 0x09
98 #define PCIR_SUBCLASS 0x0a
99 #define PCIR_CLASS 0x0b
100 #define PCIR_CACHELNSZ 0x0c
101 #define PCIR_LATTIMER 0x0d
102 #define PCIR_HDRTYPE 0x0e
103 #define PCIM_HDRTYPE 0x7f
104 #define PCIM_HDRTYPE_NORMAL 0x00
105 #define PCIM_HDRTYPE_BRIDGE 0x01
106 #define PCIM_HDRTYPE_CARDBUS 0x02
107 #define PCIM_MFDEV 0x80
108 #define PCIR_BIST 0x0f
110 /* Capability Register Offsets */
112 #define PCICAP_ID 0x0
113 #define PCICAP_NEXTPTR 0x1
115 /* Capability Identification Numbers */
117 #define PCIY_PMG 0x01 /* PCI Power Management */
118 #define PCIY_AGP 0x02 /* AGP */
119 #define PCIY_VPD 0x03 /* Vital Product Data */
120 #define PCIY_SLOTID 0x04 /* Slot Identification */
121 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
122 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
123 #define PCIY_PCIX 0x07 /* PCI-X */
124 #define PCIY_HT 0x08 /* HyperTransport */
125 #define PCIY_VENDOR 0x09 /* Vendor Unique */
126 #define PCIY_DEBUG 0x0a /* Debug port */
127 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
128 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
129 #define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */
130 #define PCIY_AGP8X 0x0e /* AGP 8x */
131 #define PCIY_SECDEV 0x0f /* Secure Device */
132 #define PCIY_EXPRESS 0x10 /* PCI Express */
133 #define PCIY_MSIX 0x11 /* MSI-X */
135 /* config registers for header type 0 devices */
137 #define PCIR_BARS 0x10
138 #define PCIR_MAPS PCIR_BARS
139 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
140 #define PCIR_MAX_BAR_0 5
141 #define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4)
142 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
143 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
144 #define PCIM_BAR_SPACE 0x00000001
145 #define PCIM_BAR_MEM_SPACE 0
146 #define PCIM_BAR_IO_SPACE 1
147 #define PCIM_BAR_MEM_TYPE 0x00000006
148 #define PCIM_BAR_MEM_32 0
149 #define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */
150 #define PCIM_BAR_MEM_64 4
151 #define PCIM_BAR_MEM_PREFETCH 0x00000008
152 #define PCIM_BAR_MEM_BASE 0xfffffff0
153 #define PCIM_BAR_IO_RESERVED 0x00000002
154 #define PCIM_BAR_IO_BASE 0xfffffffc
155 #define PCIR_CIS 0x28
156 #define PCIM_CIS_ASI_MASK 0x7
157 #define PCIM_CIS_ASI_CONFIG 0
158 #define PCIM_CIS_ASI_BAR0 1
159 #define PCIM_CIS_ASI_BAR1 2
160 #define PCIM_CIS_ASI_BAR2 3
161 #define PCIM_CIS_ASI_BAR3 4
162 #define PCIM_CIS_ASI_BAR4 5
163 #define PCIM_CIS_ASI_BAR5 6
164 #define PCIM_CIS_ASI_ROM 7
165 #define PCIM_CIS_ADDR_MASK 0x0ffffff8
166 #define PCIM_CIS_ROM_MASK 0xf0000000
167 #define PCIM_CIS_CONFIG_MASK 0xff
168 #define PCIR_SUBVEND_0 0x2c
169 #define PCIR_SUBDEV_0 0x2e
170 #define PCIR_BIOS 0x30
171 #define PCIM_BIOS_ENABLE 0x01
172 #define PCIM_BIOS_ADDR_MASK 0xfffff800
173 #define PCIR_CAP_PTR 0x34
174 #define PCIR_INTLINE 0x3c
175 #define PCIR_INTPIN 0x3d
176 #define PCIR_MINGNT 0x3e
177 #define PCIR_MAXLAT 0x3f
179 /* config registers for header type 1 (PCI-to-PCI bridge) devices */
181 #define PCIR_MAX_BAR_1 1
182 #define PCIR_SECSTAT_1 0x1e
184 #define PCIR_PRIBUS_1 0x18
185 #define PCIR_SECBUS_1 0x19
186 #define PCIR_SUBBUS_1 0x1a
187 #define PCIR_SECLAT_1 0x1b
189 #define PCIR_IOBASEL_1 0x1c
190 #define PCIR_IOLIMITL_1 0x1d
191 #define PCIR_IOBASEH_1 0x30
192 #define PCIR_IOLIMITH_1 0x32
193 #define PCIM_BRIO_16 0x0
194 #define PCIM_BRIO_32 0x1
195 #define PCIM_BRIO_MASK 0xf
197 #define PCIR_MEMBASE_1 0x20
198 #define PCIR_MEMLIMIT_1 0x22
200 #define PCIR_PMBASEL_1 0x24
201 #define PCIR_PMLIMITL_1 0x26
202 #define PCIR_PMBASEH_1 0x28
203 #define PCIR_PMLIMITH_1 0x2c
204 #define PCIM_BRPM_32 0x0
205 #define PCIM_BRPM_64 0x1
206 #define PCIM_BRPM_MASK 0xf
208 #define PCIR_BRIDGECTL_1 0x3e
210 /* config registers for header type 2 (CardBus) devices */
212 #define PCIR_MAX_BAR_2 0
213 #define PCIR_CAP_PTR_2 0x14
214 #define PCIR_SECSTAT_2 0x16
216 #define PCIR_PRIBUS_2 0x18
217 #define PCIR_SECBUS_2 0x19
218 #define PCIR_SUBBUS_2 0x1a
219 #define PCIR_SECLAT_2 0x1b
221 #define PCIR_MEMBASE0_2 0x1c
222 #define PCIR_MEMLIMIT0_2 0x20
223 #define PCIR_MEMBASE1_2 0x24
224 #define PCIR_MEMLIMIT1_2 0x28
225 #define PCIR_IOBASE0_2 0x2c
226 #define PCIR_IOLIMIT0_2 0x30
227 #define PCIR_IOBASE1_2 0x34
228 #define PCIR_IOLIMIT1_2 0x38
230 #define PCIR_BRIDGECTL_2 0x3e
232 #define PCIR_SUBVEND_2 0x40
233 #define PCIR_SUBDEV_2 0x42
235 #define PCIR_PCCARDIF_2 0x44
237 /* PCI device class, subclass and programming interface definitions */
239 #define PCIC_OLD 0x00
240 #define PCIS_OLD_NONVGA 0x00
241 #define PCIS_OLD_VGA 0x01
243 #define PCIC_STORAGE 0x01
244 #define PCIS_STORAGE_SCSI 0x00
245 #define PCIS_STORAGE_IDE 0x01
246 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
247 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
248 #define PCIP_STORAGE_IDE_MODESEC 0x04
249 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
250 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
251 #define PCIS_STORAGE_FLOPPY 0x02
252 #define PCIS_STORAGE_IPI 0x03
253 #define PCIS_STORAGE_RAID 0x04
254 #define PCIS_STORAGE_ATA_ADMA 0x05
255 #define PCIS_STORAGE_SATA 0x06
256 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
257 #define PCIS_STORAGE_SAS 0x07
258 #define PCIS_STORAGE_OTHER 0x80
260 #define PCIC_NETWORK 0x02
261 #define PCIS_NETWORK_ETHERNET 0x00
262 #define PCIS_NETWORK_TOKENRING 0x01
263 #define PCIS_NETWORK_FDDI 0x02
264 #define PCIS_NETWORK_ATM 0x03
265 #define PCIS_NETWORK_ISDN 0x04
266 #define PCIS_NETWORK_WORLDFIP 0x05
267 #define PCIS_NETWORK_PICMG 0x06
268 #define PCIS_NETWORK_OTHER 0x80
270 #define PCIC_DISPLAY 0x03
271 #define PCIS_DISPLAY_VGA 0x00
272 #define PCIS_DISPLAY_XGA 0x01
273 #define PCIS_DISPLAY_3D 0x02
274 #define PCIS_DISPLAY_OTHER 0x80
276 #define PCIC_MULTIMEDIA 0x04
277 #define PCIS_MULTIMEDIA_VIDEO 0x00
278 #define PCIS_MULTIMEDIA_AUDIO 0x01
279 #define PCIS_MULTIMEDIA_TELE 0x02
280 #define PCIS_MULTIMEDIA_HDA 0x03
281 #define PCIS_MULTIMEDIA_OTHER 0x80
283 #define PCIC_MEMORY 0x05
284 #define PCIS_MEMORY_RAM 0x00
285 #define PCIS_MEMORY_FLASH 0x01
286 #define PCIS_MEMORY_OTHER 0x80
288 #define PCIC_BRIDGE 0x06
289 #define PCIS_BRIDGE_HOST 0x00
290 #define PCIS_BRIDGE_ISA 0x01
291 #define PCIS_BRIDGE_EISA 0x02
292 #define PCIS_BRIDGE_MCA 0x03
293 #define PCIS_BRIDGE_PCI 0x04
294 #define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01
295 #define PCIS_BRIDGE_PCMCIA 0x05
296 #define PCIS_BRIDGE_NUBUS 0x06
297 #define PCIS_BRIDGE_CARDBUS 0x07
298 #define PCIS_BRIDGE_RACEWAY 0x08
299 #define PCIS_BRIDGE_PCI_TRANSPARENT 0x09
300 #define PCIS_BRIDGE_INFINIBAND 0x0a
301 #define PCIS_BRIDGE_OTHER 0x80
303 #define PCIC_SIMPLECOMM 0x07
304 #define PCIS_SIMPLECOMM_UART 0x00
305 #define PCIP_SIMPLECOMM_UART_8250 0x00
306 #define PCIP_SIMPLECOMM_UART_16450A 0x01
307 #define PCIP_SIMPLECOMM_UART_16550A 0x02
308 #define PCIP_SIMPLECOMM_UART_16650A 0x03
309 #define PCIP_SIMPLECOMM_UART_16750A 0x04
310 #define PCIP_SIMPLECOMM_UART_16850A 0x05
311 #define PCIP_SIMPLECOMM_UART_16950A 0x06
312 #define PCIS_SIMPLECOMM_PAR 0x01
313 #define PCIS_SIMPLECOMM_MULSER 0x02
314 #define PCIS_SIMPLECOMM_MODEM 0x03
315 #define PCIS_SIMPLECOMM_GPIB 0x04
316 #define PCIS_SIMPLECOMM_SMART_CARD 0x05
317 #define PCIS_SIMPLECOMM_OTHER 0x80
319 #define PCIC_BASEPERIPH 0x08
320 #define PCIS_BASEPERIPH_PIC 0x00
321 #define PCIP_BASEPERIPH_PIC_8259A 0x00
322 #define PCIP_BASEPERIPH_PIC_ISA 0x01
323 #define PCIP_BASEPERIPH_PIC_EISA 0x02
324 #define PCIP_BASEPERIPH_PIC_IO_APIC 0x10
325 #define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20
326 #define PCIS_BASEPERIPH_DMA 0x01
327 #define PCIS_BASEPERIPH_TIMER 0x02
328 #define PCIS_BASEPERIPH_RTC 0x03
329 #define PCIS_BASEPERIPH_PCIHOT 0x04
330 #define PCIS_BASEPERIPH_SDHC 0x05
331 #define PCIS_BASEPERIPH_OTHER 0x80
333 #define PCIC_INPUTDEV 0x09
334 #define PCIS_INPUTDEV_KEYBOARD 0x00
335 #define PCIS_INPUTDEV_DIGITIZER 0x01
336 #define PCIS_INPUTDEV_MOUSE 0x02
337 #define PCIS_INPUTDEV_SCANNER 0x03
338 #define PCIS_INPUTDEV_GAMEPORT 0x04
339 #define PCIS_INPUTDEV_OTHER 0x80
341 #define PCIC_DOCKING 0x0a
342 #define PCIS_DOCKING_GENERIC 0x00
343 #define PCIS_DOCKING_OTHER 0x80
345 #define PCIC_PROCESSOR 0x0b
346 #define PCIS_PROCESSOR_386 0x00
347 #define PCIS_PROCESSOR_486 0x01
348 #define PCIS_PROCESSOR_PENTIUM 0x02
349 #define PCIS_PROCESSOR_ALPHA 0x10
350 #define PCIS_PROCESSOR_POWERPC 0x20
351 #define PCIS_PROCESSOR_MIPS 0x30
352 #define PCIS_PROCESSOR_COPROC 0x40
354 #define PCIC_SERIALBUS 0x0c
355 #define PCIS_SERIALBUS_FW 0x00
356 #define PCIS_SERIALBUS_ACCESS 0x01
357 #define PCIS_SERIALBUS_SSA 0x02
358 #define PCIS_SERIALBUS_USB 0x03
359 #define PCIP_SERIALBUS_USB_UHCI 0x00
360 #define PCIP_SERIALBUS_USB_OHCI 0x10
361 #define PCIP_SERIALBUS_USB_EHCI 0x20
362 #define PCIP_SERIALBUS_USB_DEVICE 0xfe
363 #define PCIS_SERIALBUS_FC 0x04
364 #define PCIS_SERIALBUS_SMBUS 0x05
365 #define PCIS_SERIALBUS_INFINIBAND 0x06
366 #define PCIS_SERIALBUS_IPMI 0x07
367 #define PCIP_SERIALBUS_IPMI_SMIC 0x00
368 #define PCIP_SERIALBUS_IPMI_KCS 0x01
369 #define PCIP_SERIALBUS_IPMI_BT 0x02
370 #define PCIS_SERIALBUS_SERCOS 0x08
371 #define PCIS_SERIALBUS_CANBUS 0x09
373 #define PCIC_WIRELESS 0x0d
374 #define PCIS_WIRELESS_IRDA 0x00
375 #define PCIS_WIRELESS_IR 0x01
376 #define PCIS_WIRELESS_RF 0x10
377 #define PCIS_WIRELESS_BLUETOOTH 0x11
378 #define PCIS_WIRELESS_BROADBAND 0x12
379 #define PCIS_WIRELESS_80211A 0x20
380 #define PCIS_WIRELESS_80211B 0x21
381 #define PCIS_WIRELESS_OTHER 0x80
383 #define PCIC_INTELLIIO 0x0e
384 #define PCIS_INTELLIIO_I2O 0x00
386 #define PCIC_SATCOM 0x0f
387 #define PCIS_SATCOM_TV 0x01
388 #define PCIS_SATCOM_AUDIO 0x02
389 #define PCIS_SATCOM_VOICE 0x03
390 #define PCIS_SATCOM_DATA 0x04
392 #define PCIC_CRYPTO 0x10
393 #define PCIS_CRYPTO_NETCOMP 0x00
394 #define PCIS_CRYPTO_ENTERTAIN 0x10
395 #define PCIS_CRYPTO_OTHER 0x80
397 #define PCIC_DASP 0x11
398 #define PCIS_DASP_DPIO 0x00
399 #define PCIS_DASP_PERFCNTRS 0x01
400 #define PCIS_DASP_COMM_SYNC 0x10
401 #define PCIS_DASP_MGMT_CARD 0x20
402 #define PCIS_DASP_OTHER 0x80
404 #define PCIC_OTHER 0xff
406 /* Bridge Control Values. */
407 #define PCIB_BCR_PERR_ENABLE 0x0001
408 #define PCIB_BCR_SERR_ENABLE 0x0002
409 #define PCIB_BCR_ISA_ENABLE 0x0004
410 #define PCIB_BCR_VGA_ENABLE 0x0008
411 #define PCIB_BCR_MASTER_ABORT_MODE 0x0020
412 #define PCIB_BCR_SECBUS_RESET 0x0040
413 #define PCIB_BCR_SECBUS_BACKTOBACK 0x0080
414 #define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100
415 #define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200
416 #define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400
417 #define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800
419 /* PCI power manangement */
420 #define PCIR_POWER_CAP 0x2
421 #define PCIM_PCAP_SPEC 0x0007
422 #define PCIM_PCAP_PMEREQCLK 0x0008
423 #define PCIM_PCAP_PMEREQPWR 0x0010
424 #define PCIM_PCAP_DEVSPECINIT 0x0020
425 #define PCIM_PCAP_DYNCLOCK 0x0040
426 #define PCIM_PCAP_SECCLOCK 0x00c0
427 #define PCIM_PCAP_CLOCKMASK 0x00c0
428 #define PCIM_PCAP_REQFULLCLOCK 0x0100
429 #define PCIM_PCAP_D1SUPP 0x0200
430 #define PCIM_PCAP_D2SUPP 0x0400
431 #define PCIM_PCAP_D0PME 0x0800
432 #define PCIM_PCAP_D1PME 0x1000
433 #define PCIM_PCAP_D2PME 0x2000
434 #define PCIM_PCAP_D3PME_HOT 0x4000
435 #define PCIM_PCAP_D3PME_COLD 0x8000
437 #define PCIR_POWER_STATUS 0x4
438 #define PCIM_PSTAT_D0 0x0000
439 #define PCIM_PSTAT_D1 0x0001
440 #define PCIM_PSTAT_D2 0x0002
441 #define PCIM_PSTAT_D3 0x0003
442 #define PCIM_PSTAT_DMASK 0x0003
443 #define PCIM_PSTAT_REPENABLE 0x0010
444 #define PCIM_PSTAT_PMEENABLE 0x0100
445 #define PCIM_PSTAT_D0POWER 0x0000
446 #define PCIM_PSTAT_D1POWER 0x0200
447 #define PCIM_PSTAT_D2POWER 0x0400
448 #define PCIM_PSTAT_D3POWER 0x0600
449 #define PCIM_PSTAT_D0HEAT 0x0800
450 #define PCIM_PSTAT_D1HEAT 0x1000
451 #define PCIM_PSTAT_D2HEAT 0x1200
452 #define PCIM_PSTAT_D3HEAT 0x1400
453 #define PCIM_PSTAT_DATAUNKN 0x0000
454 #define PCIM_PSTAT_DATADIV10 0x2000
455 #define PCIM_PSTAT_DATADIV100 0x4000
456 #define PCIM_PSTAT_DATADIV1000 0x6000
457 #define PCIM_PSTAT_DATADIVMASK 0x6000
458 #define PCIM_PSTAT_PME 0x8000
460 #define PCIR_POWER_PMCSR 0x6
461 #define PCIM_PMCSR_DCLOCK 0x10
462 #define PCIM_PMCSR_B2SUPP 0x20
463 #define PCIM_BMCSR_B3SUPP 0x40
464 #define PCIM_BMCSR_BPCE 0x80
466 #define PCIR_POWER_DATA 0x7
468 /* VPD capability registers */
469 #define PCIR_VPD_ADDR 0x2
470 #define PCIR_VPD_DATA 0x4
472 /* PCI Message Signalled Interrupts (MSI) */
473 #define PCIR_MSI_CTRL 0x2
474 #define PCIM_MSICTRL_VECTOR 0x0100
475 #define PCIM_MSICTRL_64BIT 0x0080
476 #define PCIM_MSICTRL_MME_MASK 0x0070
477 #define PCIM_MSICTRL_MME_1 0x0000
478 #define PCIM_MSICTRL_MME_2 0x0010
479 #define PCIM_MSICTRL_MME_4 0x0020
480 #define PCIM_MSICTRL_MME_8 0x0030
481 #define PCIM_MSICTRL_MME_16 0x0040
482 #define PCIM_MSICTRL_MME_32 0x0050
483 #define PCIM_MSICTRL_MMC_MASK 0x000E
484 #define PCIM_MSICTRL_MMC_1 0x0000
485 #define PCIM_MSICTRL_MMC_2 0x0002
486 #define PCIM_MSICTRL_MMC_4 0x0004
487 #define PCIM_MSICTRL_MMC_8 0x0006
488 #define PCIM_MSICTRL_MMC_16 0x0008
489 #define PCIM_MSICTRL_MMC_32 0x000A
490 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
491 #define PCIR_MSI_ADDR 0x4
492 #define PCIR_MSI_ADDR_HIGH 0x8
493 #define PCIR_MSI_DATA 0x8
494 #define PCIR_MSI_DATA_64BIT 0xc
495 #define PCIR_MSI_MASK 0x10
496 #define PCIR_MSI_PENDING 0x14
498 /* PCI-X definitions */
500 /* For header type 0 devices */
501 #define PCIXR_COMMAND 0x2
502 #define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */
503 #define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */
504 #define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */
505 #define PCIXM_COMMAND_MAX_READ_512 0x0000
506 #define PCIXM_COMMAND_MAX_READ_1024 0x0004
507 #define PCIXM_COMMAND_MAX_READ_2048 0x0008
508 #define PCIXM_COMMAND_MAX_READ_4096 0x000c
509 #define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */
510 #define PCIXM_COMMAND_MAX_SPLITS_1 0x0000
511 #define PCIXM_COMMAND_MAX_SPLITS_2 0x0010
512 #define PCIXM_COMMAND_MAX_SPLITS_3 0x0020
513 #define PCIXM_COMMAND_MAX_SPLITS_4 0x0030
514 #define PCIXM_COMMAND_MAX_SPLITS_8 0x0040
515 #define PCIXM_COMMAND_MAX_SPLITS_12 0x0050
516 #define PCIXM_COMMAND_MAX_SPLITS_16 0x0060
517 #define PCIXM_COMMAND_MAX_SPLITS_32 0x0070
518 #define PCIXM_COMMAND_VERSION 0x3000
519 #define PCIXR_STATUS 0x4
520 #define PCIXM_STATUS_DEVFN 0x000000FF
521 #define PCIXM_STATUS_BUS 0x0000FF00
522 #define PCIXM_STATUS_64BIT 0x00010000
523 #define PCIXM_STATUS_133CAP 0x00020000
524 #define PCIXM_STATUS_SC_DISCARDED 0x00040000
525 #define PCIXM_STATUS_UNEXP_SC 0x00080000
526 #define PCIXM_STATUS_COMPLEX_DEV 0x00100000
527 #define PCIXM_STATUS_MAX_READ 0x00600000
528 #define PCIXM_STATUS_MAX_READ_512 0x00000000
529 #define PCIXM_STATUS_MAX_READ_1024 0x00200000
530 #define PCIXM_STATUS_MAX_READ_2048 0x00400000
531 #define PCIXM_STATUS_MAX_READ_4096 0x00600000
532 #define PCIXM_STATUS_MAX_SPLITS 0x03800000
533 #define PCIXM_STATUS_MAX_SPLITS_1 0x00000000
534 #define PCIXM_STATUS_MAX_SPLITS_2 0x00800000
535 #define PCIXM_STATUS_MAX_SPLITS_3 0x01000000
536 #define PCIXM_STATUS_MAX_SPLITS_4 0x01800000
537 #define PCIXM_STATUS_MAX_SPLITS_8 0x02000000
538 #define PCIXM_STATUS_MAX_SPLITS_12 0x02800000
539 #define PCIXM_STATUS_MAX_SPLITS_16 0x03000000
540 #define PCIXM_STATUS_MAX_SPLITS_32 0x03800000
541 #define PCIXM_STATUS_MAX_CUM_READ 0x1C000000
542 #define PCIXM_STATUS_RCVD_SC_ERR 0x20000000
543 #define PCIXM_STATUS_266CAP 0x40000000
544 #define PCIXM_STATUS_533CAP 0x80000000
546 /* For header type 1 devices (PCI-X bridges) */
547 #define PCIXR_SEC_STATUS 0x2
548 #define PCIXM_SEC_STATUS_64BIT 0x0001
549 #define PCIXM_SEC_STATUS_133CAP 0x0002
550 #define PCIXM_SEC_STATUS_SC_DISC 0x0004
551 #define PCIXM_SEC_STATUS_UNEXP_SC 0x0008
552 #define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010
553 #define PCIXM_SEC_STATUS_SR_DELAYED 0x0020
554 #define PCIXM_SEC_STATUS_BUS_MODE 0x03c0
555 #define PCIXM_SEC_STATUS_VERSION 0x3000
556 #define PCIXM_SEC_STATUS_266CAP 0x4000
557 #define PCIXM_SEC_STATUS_533CAP 0x8000
558 #define PCIXR_BRIDGE_STATUS 0x4
559 #define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF
560 #define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00
561 #define PCIXM_BRIDGE_STATUS_64BIT 0x00010000
562 #define PCIXM_BRIDGE_STATUS_133CAP 0x00020000
563 #define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000
564 #define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000
565 #define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000
566 #define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000
567 #define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000
568 #define PCIXM_BRIDGE_STATUS_266CAP 0x40000000
569 #define PCIXM_BRIDGE_STATUS_533CAP 0x80000000
571 /* HT (HyperTransport) Capability definitions */
572 #define PCIR_HT_COMMAND 0x2
573 #define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */
574 #define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */
575 #define PCIM_HTCAP_HOST 0x2000 /* 001xx */
576 #define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */
577 #define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */
578 #define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */
579 #define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */
580 #define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */
581 #define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */
582 #define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */
583 #define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */
584 #define PCIM_HTCAP_VCSET 0xb800 /* 10111 */
585 #define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */
586 #define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */
588 /* HT MSI Mapping Capability definitions. */
589 #define PCIM_HTCMD_MSI_ENABLE 0x0001
590 #define PCIM_HTCMD_MSI_FIXED 0x0002
591 #define PCIR_HTMSI_ADDRESS_LO 0x4
592 #define PCIR_HTMSI_ADDRESS_HI 0x8
594 /* PCI Vendor capability definitions */
595 #define PCIR_VENDOR_LENGTH 0x2
596 #define PCIR_VENDOR_DATA 0x3
598 /* PCI EHCI Debug Port definitions */
599 #define PCIR_DEBUG_PORT 0x2
600 #define PCIM_DEBUG_PORT_OFFSET 0x1FFF
601 #define PCIM_DEBUG_PORT_BAR 0xe000
603 /* PCI-PCI Bridge Subvendor definitions */
604 #define PCIR_SUBVENDCAP_ID 0x4
606 /* MSI-X definitions */
607 #define PCIR_MSIX_CTRL 0x2
608 #define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000
609 #define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000
610 #define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF
611 #define PCIR_MSIX_TABLE 0x4
612 #define PCIR_MSIX_PBA 0x8
613 #define PCIM_MSIX_BIR_MASK 0x7
614 #define PCIM_MSIX_BIR_BAR_10 0
615 #define PCIM_MSIX_BIR_BAR_14 1
616 #define PCIM_MSIX_BIR_BAR_18 2
617 #define PCIM_MSIX_BIR_BAR_1C 3
618 #define PCIM_MSIX_BIR_BAR_20 4
619 #define PCIM_MSIX_BIR_BAR_24 5
620 #define PCIM_MSIX_VCTRL_MASK 0x1
623 * PCI Express definitions
625 * PCI Express base specification, REV. 1.0a
628 /* PCI Express capabilities, 16bits */
629 #define PCIER_CAPABILITY 0x2
630 #define PCIEM_CAP_VER_MASK 0x000f /* Version */
631 #define PCIEM_CAP_VER_1 0x0001
632 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */
633 #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented,
634 * valid only for root port and
635 * switch downstream port
637 /* PCI Express port types */
638 #define PCIE_END_POINT 0x0000 /* Endpoint device */
639 #define PCIE_LEG_END_POINT 0x0010 /* Legacy endpoint device */
640 #define PCIE_ROOT_PORT 0x0040 /* Root port */
641 #define PCIE_UP_STREAM_PORT 0x0050 /* Switch upstream port */
642 #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */
643 #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */
644 #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */
646 /* PCI Express device control, 16bits */
647 #define PCIER_DEVCTRL 0x08
648 #define PCIEM_DEVCTL_MAX_READRQ_MASK 0x7000 /* Max read request size */
649 #define PCIEM_DEVCTL_MAX_READRQ_128 0x0000
650 #define PCIEM_DEVCTL_MAX_READRQ_256 0x1000
651 #define PCIEM_DEVCTL_MAX_READRQ_512 0x2000
652 #define PCIEM_DEVCTL_MAX_READRQ_1024 0x3000
653 #define PCIEM_DEVCTL_MAX_READRQ_2048 0x4000
654 #define PCIEM_DEVCTL_MAX_READRQ_4096 0x5000
656 /* PCI Express slot capabilities, 32bits */
657 #define PCIER_SLOTCAP 0x14
658 #define PCIEM_SLTCAP_ATTEN_BTN 0x00000001 /* Attention button present */
659 #define PCIEM_SLTCAP_PWR_CTRL 0x00000002 /* Power controller present */
660 #define PCIEM_SLTCAP_MRL_SNS 0x00000004 /* MRL sensor present */
661 #define PCIEM_SLTCAP_ATTEN_IND 0x00000008 /* Attention indicator present */
662 #define PCIEM_SLTCAP_PWR_IND 0x00000010 /* Power indicator present */
663 #define PCIEM_SLTCAP_HP_SURP 0x00000020 /* Hot-Plug surprise */
664 #define PCIEM_SLTCAP_HP_CAP 0x00000040 /* Hot-Plug capable */
665 #define PCIEM_SLTCAP_HP_MASK 0x0000007f /* Hot-Plug related bits */
667 /* PCI Express slot control, 16bits */
668 #define PCIER_SLOTCTRL 0x18
669 #define PCIEM_SLTCTL_HPINTR_MASK 0x001f /* Hot-plug interrupts mask */
670 #define PCIEM_SLTCTL_HPINTR_EN 0x0020 /* Enable hot-plug interrupts */
671 /* PCI Expres hot-plug interrupts */
672 #define PCIE_HPINTR_ATTEN_BTN 0x0001 /* Attention button intr */
673 #define PCIE_HPINTR_PWR_FAULT 0x0002 /* Power fault intr */
674 #define PCIE_HPINTR_MRL_SNS 0x0004 /* MRL sensor changed intr */
675 #define PCIE_HPINTR_PRSN_DETECT 0x0008 /* Presence detect intr */
676 #define PCIE_HPINTR_CMD_COMPL 0x0010 /* Command completed intr */
678 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
680 #if defined(_KERNEL) && !defined(KLD_MODULE)
681 #include "opt_compat_oldpci.h"
686 #define PCI_ID_REG 0x00
687 #define PCI_COMMAND_STATUS_REG 0x04
688 #define PCI_COMMAND_IO_ENABLE 0x00000001
689 #define PCI_COMMAND_MEM_ENABLE 0x00000002
690 #define PCI_CLASS_REG 0x08
691 #define PCI_CLASS_MASK 0xff000000
692 #define PCI_SUBCLASS_MASK 0x00ff0000
693 #define PCI_REVISION_MASK 0x000000ff
694 #define PCI_CLASS_PREHISTORIC 0x00000000
695 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
696 #define PCI_CLASS_MASS_STORAGE 0x01000000
697 #define PCI_CLASS_DISPLAY 0x03000000
698 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
699 #define PCI_CLASS_BRIDGE 0x06000000
700 #define PCI_MAP_REG_START 0x10
701 #define PCI_MAP_REG_END 0x28
702 #define PCI_MAP_IO 0x00000001
703 #define PCI_INTERRUPT_REG 0x3c
705 #endif /* COMPAT_OLDPCI */
707 #endif /* _PCIREG_H_ */
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