2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.3.2.12 2003/01/20 03:59:42 orion Exp $
28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.9 2005/05/24 20:59:04 dillon Exp $
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/ich.h>
35 #include <bus/pci/pcireg.h>
36 #include <bus/pci/pcivar.h>
38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.9 2005/05/24 20:59:04 dillon Exp $");
40 /* -------------------------------------------------------------------- */
42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
43 #define ICH_DTBL_LENGTH 32
44 #define ICH_DEFAULT_BUFSZ 16384
45 #define ICH_MAX_BUFSZ 65536
47 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
48 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
49 #define ICH5ID 0x24d58086 /* ICH5 needs to be treated as ICH4 */
50 #define ICH6ID 0x266e8086 /* ICH6 needs to be treated as ICH4 */
52 /* buffer descriptor */
54 volatile u_int32_t buffer;
55 volatile u_int32_t length;
60 /* channel registers */
62 u_int32_t num:8, run:1, run_save:1;
63 u_int32_t blksz, blkcnt, spd;
64 u_int32_t regbase, spdreg;
68 struct snd_dbuf *buffer;
69 struct pcm_channel *channel;
70 struct sc_info *parent;
72 struct ich_desc *dtbl;
75 /* device private data */
78 int hasvra, hasvrm, hasmic;
79 unsigned int chnum, bufsz;
80 int sample_size, swap_reg;
82 struct resource *nambar, *nabmbar, *irq;
83 int regtype, nambarid, nabmbarid, irqid;
84 bus_space_tag_t nambart, nabmbart;
85 bus_space_handle_t nambarh, nabmbarh;
90 struct ac97_info *codec;
91 struct sc_chinfo ch[3];
93 struct ich_desc *dtbl;
94 struct intr_config_hook intrhook;
98 /* -------------------------------------------------------------------- */
100 static u_int32_t ich_fmt[] = {
101 AFMT_STEREO | AFMT_S16_LE,
104 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
105 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
107 /* -------------------------------------------------------------------- */
110 ich_rd(struct sc_info *sc, int regno, int size)
114 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
116 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
118 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
125 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
129 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
132 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
135 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
142 ich_waitcd(void *devinfo)
146 struct sc_info *sc = (struct sc_info *)devinfo;
148 for (i = 0; i < ICH_TIMEOUT; i++) {
149 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
150 if ((data & 0x01) == 0)
153 device_printf(sc->dev, "CODEC semaphore timeout\n");
158 ich_rdcd(kobj_t obj, void *devinfo, int regno)
160 struct sc_info *sc = (struct sc_info *)devinfo;
165 return bus_space_read_2(sc->nambart, sc->nambarh, regno);
169 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
171 struct sc_info *sc = (struct sc_info *)devinfo;
175 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
180 static kobj_method_t ich_ac97_methods[] = {
181 KOBJMETHOD(ac97_read, ich_rdcd),
182 KOBJMETHOD(ac97_write, ich_wrcd),
185 AC97_DECLARE(ich_ac97);
187 /* -------------------------------------------------------------------- */
188 /* common routines */
191 ich_filldtbl(struct sc_chinfo *ch)
196 base = vtophys(sndbuf_getbuf(ch->buffer));
197 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
198 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
200 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
203 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
204 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
205 ch->dtbl[i].length = ICH_BDC_IOC
206 | (ch->blksz / ch->parent->sample_size);
211 ich_resetchan(struct sc_info *sc, int num)
216 regbase = ICH_REG_PO_BASE;
218 regbase = ICH_REG_PI_BASE;
220 regbase = ICH_REG_MC_BASE;
224 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
226 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
227 for (i = 0; i < ICH_TIMEOUT; i++) {
228 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
233 device_printf(sc->dev, "cannot reset channel %d\n", num);
237 /* -------------------------------------------------------------------- */
238 /* channel interface */
241 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
243 struct sc_info *sc = devinfo;
244 struct sc_chinfo *ch;
254 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
256 ch->blksz = sc->bufsz / ch->blkcnt;
260 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
261 ch->regbase = ICH_REG_PO_BASE;
262 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
263 ch->imask = ICH_GLOB_STA_POINT;
267 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
268 ch->regbase = ICH_REG_PI_BASE;
269 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
270 ch->imask = ICH_GLOB_STA_PIINT;
274 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
275 ch->regbase = ICH_REG_MC_BASE;
276 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
277 ch->imask = ICH_GLOB_STA_MINT;
284 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz))
287 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
293 ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
299 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
301 struct sc_chinfo *ch = data;
302 struct sc_info *sc = ch->parent;
306 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
307 sc->ac97rate = 48000;
308 r = (speed * 48000) / sc->ac97rate;
310 * Cast the return value of ac97_setrate() to u_int so that
311 * the math don't overflow into the negative range.
313 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
314 sc->ac97rate) / 48000;
322 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
324 struct sc_chinfo *ch = data;
325 struct sc_info *sc = ch->parent;
327 ch->blksz = blocksize;
329 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
335 ichchan_trigger(kobj_t obj, void *data, int go)
337 struct sc_chinfo *ch = data;
338 struct sc_info *sc = ch->parent;
343 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
344 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
348 ich_resetchan(sc, ch->num);
356 ichchan_getptr(kobj_t obj, void *data)
358 struct sc_chinfo *ch = data;
359 struct sc_info *sc = ch->parent;
362 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
364 pos = ch->civ * ch->blksz;
369 static struct pcmchan_caps *
370 ichchan_getcaps(kobj_t obj, void *data)
372 struct sc_chinfo *ch = data;
374 return ch->spdreg? &ich_vrcaps : &ich_caps;
377 static kobj_method_t ichchan_methods[] = {
378 KOBJMETHOD(channel_init, ichchan_init),
379 KOBJMETHOD(channel_setformat, ichchan_setformat),
380 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
381 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
382 KOBJMETHOD(channel_trigger, ichchan_trigger),
383 KOBJMETHOD(channel_getptr, ichchan_getptr),
384 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
387 CHANNEL_DECLARE(ichchan);
389 /* -------------------------------------------------------------------- */
390 /* The interrupt handler */
395 struct sc_info *sc = (struct sc_info *)p;
396 struct sc_chinfo *ch;
397 u_int32_t cbi, lbi, lvi, st, gs;
400 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
401 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
402 /* Clear resume interrupt(s) - nothing doing with them */
403 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
405 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
407 for (i = 0; i < 3; i++) {
409 if ((ch->imask & gs) == 0)
412 st = ich_rd(sc, ch->regbase +
413 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
415 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
416 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
417 /* block complete - update buffer */
419 chn_intr(ch->channel);
420 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
421 cbi = ch->civ % ch->blkcnt;
423 cbi = ch->blkcnt - 1;
426 lbi = lvi % ch->blkcnt;
430 lvi += cbi + ch->blkcnt - lbi;
431 lvi %= ICH_DTBL_LENGTH;
432 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
435 /* clear status bit */
436 ich_wr(sc, ch->regbase +
437 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
441 device_printf(sc->dev,
442 "Unhandled interrupt, gs_intr = %x\n", gs);
446 /* ------------------------------------------------------------------------- */
447 /* Sysctl to control ac97 speed (some boards appear to end up using
448 * XTAL_IN rather than BIT_CLK for link timing).
452 ich_initsys(struct sc_info* sc)
455 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
456 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
457 OID_AUTO, "ac97rate", CTLFLAG_RW,
458 &sc->ac97rate, 48000,
459 "AC97 link rate (default = 48000)");
460 #endif /* SND_DYNSYSCTL */
464 /* -------------------------------------------------------------------- */
465 /* Calibrate card to determine the clock source. The source maybe a
466 * function of the ac97 codec initialization code (to be investigated).
470 void ich_calibrate(void *arg)
473 struct sc_chinfo *ch;
474 struct timeval t1, t2;
476 u_int32_t wait_us, actual_48k_rate, bytes;
478 sc = (struct sc_info *)arg;
481 if (sc->use_intrhook)
482 config_intrhook_disestablish(&sc->intrhook);
485 * Grab audio from input for fixed interval and compare how
486 * much we actually get with what we expect. Interval needs
487 * to be sufficiently short that no interrupts are
491 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
493 bytes = sndbuf_getsize(ch->buffer) / 2;
494 ichchan_setblocksize(0, ch, bytes);
497 * our data format is stereo, 16 bit so each sample is 4 bytes.
498 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
499 * we're going to start recording with interrupts disabled and measure
500 * the time taken for one block to complete. we know the block size,
501 * we know the time in microseconds, we calculate the sample rate:
503 * actual_rate [bps] = bytes / (time [s] * 4)
504 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
505 * actual_rate [Hz] = (bytes * 250000) / time [us]
509 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
511 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
515 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
518 while (nciv == ociv) {
520 if (t2.tv_sec - t1.tv_sec > 1)
522 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
527 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
531 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
533 /* turn time delta into us */
534 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
537 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
541 actual_48k_rate = (bytes * 250000) / wait_us;
543 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
544 sc->ac97rate = actual_48k_rate;
546 sc->ac97rate = 48000;
549 if (bootverbose || sc->ac97rate != 48000) {
550 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
551 if (sc->ac97rate != actual_48k_rate)
552 printf(", will use %d Hz", sc->ac97rate);
559 /* -------------------------------------------------------------------- */
560 /* Probe and attach the card */
563 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
569 ich_init(struct sc_info *sc)
574 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
576 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
578 if ((stat & ICH_GLOB_STA_PCR) == 0) {
579 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
580 if ((pci_get_devid(sc->dev) != ICH4ID) &&
581 (pci_get_devid(sc->dev) != ICH5ID) &&
582 (pci_get_devid(sc->dev) != ICH6ID)) {
587 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
589 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
591 if (sc->hasmic && ich_resetchan(sc, 2))
594 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
597 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
598 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) {
599 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
607 ich_pci_probe(device_t dev)
609 switch(pci_get_devid(dev)) {
611 device_set_desc(dev, "Intel 443MX");
615 device_set_desc(dev, "Intel ICH (82801AA)");
619 device_set_desc(dev, "Intel ICH (82801AB)");
623 device_set_desc(dev, "Intel ICH2 (82801BA)");
627 device_set_desc(dev, "Intel ICH3 (82801CA)");
631 device_set_desc(dev, "Intel ICH4 (82801DB)");
632 return -1000; /* allow a better driver to override us */
635 device_set_desc(dev, "Intel ICH5 (82801EB)");
636 return -1000; /* allow a better driver to override us */
639 device_set_desc(dev, "Intel ICH6 (82801FB)");
640 return -1000; /* allow a better driver to override us */
643 device_set_desc(dev, "SiS 7012");
647 device_set_desc(dev, "nVidia nForce");
651 device_set_desc(dev, "nVidia nForce2");
655 device_set_desc(dev, "nVidia nForce2 400");
659 device_set_desc(dev, "nVidia nForce3");
663 device_set_desc(dev, "nVidia nForce3 250");
667 device_set_desc(dev, "AMD-768");
671 device_set_desc(dev, "AMD-8111");
680 ich_pci_attach(device_t dev)
684 char status[SND_STATUSLEN];
686 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
687 device_printf(dev, "cannot allocate softc\n");
691 bzero(sc, sizeof(*sc));
695 * The SiS 7012 register set isn't quite like the standard ich.
696 * There really should be a general "quirks" mechanism.
698 if (pci_get_devid(dev) == SIS7012ID) {
707 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
708 * read-only. Need to enable "legacy support", by poking into
709 * pci config space. The driver should use MMBAR and MBBAR,
710 * but doing so will mess things up here. ich4 has enough new
711 * features it warrants it's own driver.
713 if (pci_get_devid(dev) == ICH4ID) {
714 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
718 * Enable bus master. On ich4/5 this may prevent the detection of
719 * the primary codec becoming ready in ich_init().
721 pci_enable_busmaster(dev);
723 if (pci_get_devid(dev) == ICH5ID || pci_get_devid(dev) == ICH6ID) {
724 sc->nambarid = PCIR_MMBAR;
725 sc->nabmbarid = PCIR_MBBAR;
726 sc->regtype = SYS_RES_MEMORY;
727 pci_enable_io(dev, SYS_RES_MEMORY);
729 sc->nambarid = PCIR_NAMBAR;
730 sc->nabmbarid = PCIR_NABMBAR;
731 sc->regtype = SYS_RES_IOPORT;
732 pci_enable_io(dev, SYS_RES_IOPORT);
735 sc->nambar = bus_alloc_resource(dev, sc->regtype, &sc->nambarid, 0, ~0, 1, RF_ACTIVE);
736 sc->nabmbar = bus_alloc_resource(dev, sc->regtype, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE);
738 if (!sc->nambar || !sc->nabmbar) {
739 device_printf(dev, "unable to map IO port space\n");
743 sc->nambart = rman_get_bustag(sc->nambar);
744 sc->nambarh = rman_get_bushandle(sc->nambar);
745 sc->nabmbart = rman_get_bustag(sc->nabmbar);
746 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
748 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
749 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
750 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) {
751 device_printf(dev, "unable to create dma tag\n");
756 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
757 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih, NULL)) {
758 device_printf(dev, "unable to map interrupt\n");
763 device_printf(dev, "unable to initialize the card\n");
767 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
768 if (sc->codec == NULL)
770 mixer_init(dev, ac97_getmixerclass(), sc->codec);
772 /* check and set VRA function */
773 extcaps = ac97_getextcaps(sc->codec);
774 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
775 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
776 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
777 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
779 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
782 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
783 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
785 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
787 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u",
788 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz);
790 pcm_setstatus(dev, status);
794 sc->intrhook.ich_func = ich_calibrate;
795 sc->intrhook.ich_arg = sc;
796 sc->intrhook.ich_desc = "ich";
797 sc->use_intrhook = 1;
798 if (config_intrhook_establish(&sc->intrhook) != 0) {
799 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n");
800 sc->use_intrhook = 0;
808 ac97_destroy(sc->codec);
810 bus_teardown_intr(dev, sc->irq, sc->ih);
812 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
814 bus_release_resource(dev, sc->regtype,
815 sc->nambarid, sc->nambar);
817 bus_release_resource(dev, sc->regtype,
818 sc->nabmbarid, sc->nabmbar);
824 ich_pci_detach(device_t dev)
829 r = pcm_unregister(dev);
832 sc = pcm_getdevinfo(dev);
834 bus_teardown_intr(dev, sc->irq, sc->ih);
835 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
836 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
837 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
838 bus_dma_tag_destroy(sc->dmat);
844 ich_pci_suspend(device_t dev)
849 sc = pcm_getdevinfo(dev);
850 for (i = 0 ; i < 3; i++) {
851 sc->ch[i].run_save = sc->ch[i].run;
853 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
860 ich_pci_resume(device_t dev)
865 sc = pcm_getdevinfo(dev);
867 /* Reinit audio device */
868 if (ich_init(sc) == -1) {
869 device_printf(dev, "unable to reinitialize the card\n");
873 if (mixer_reinit(dev) == -1) {
874 device_printf(dev, "unable to reinitialize the mixer\n");
877 /* Re-start DMA engines */
878 for (i = 0 ; i < 3; i++) {
879 struct sc_chinfo *ch = &sc->ch[i];
880 if (sc->ch[i].run_save) {
881 ichchan_setblocksize(0, ch, ch->blksz);
882 ichchan_setspeed(0, ch, ch->spd);
883 ichchan_trigger(0, ch, PCMTRIG_START);
889 static device_method_t ich_methods[] = {
890 /* Device interface */
891 DEVMETHOD(device_probe, ich_pci_probe),
892 DEVMETHOD(device_attach, ich_pci_attach),
893 DEVMETHOD(device_detach, ich_pci_detach),
894 DEVMETHOD(device_suspend, ich_pci_suspend),
895 DEVMETHOD(device_resume, ich_pci_resume),
899 static driver_t ich_driver = {
905 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
906 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
907 MODULE_VERSION(snd_ich, 1);