2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.21 2005/03/27 19:25:07 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
59 #include <sys/kernel.h>
64 #include <sys/sysctl.h>
66 #include <sys/systimer.h>
67 #include <sys/globaldata.h>
68 #include <sys/thread2.h>
69 #include <sys/systimer.h>
71 #include <machine/clock.h>
72 #ifdef CLK_CALIBRATION_LOOP
74 #include <machine/cputypes.h>
75 #include <machine/frame.h>
76 #include <machine/ipl.h>
77 #include <machine/limits.h>
78 #include <machine/md_var.h>
79 #include <machine/psl.h>
81 #include <machine/segments.h>
83 #if defined(SMP) || defined(APIC_IO)
84 #include <machine/smp.h>
85 #endif /* SMP || APIC_IO */
86 #include <machine/specialreg.h>
88 #include <i386/isa/icu.h>
89 #include <bus/isa/i386/isa.h>
90 #include <bus/isa/rtc.h>
91 #include <i386/isa/timerreg.h>
93 #include <i386/isa/intr_machdep.h>
96 #include <bus/mca/i386/mca_machdep.h>
100 #include <i386/isa/intr_machdep.h>
101 /* The interrupt triggered by the 8254 (timer) chip */
103 static u_long read_intr_count (int vec);
104 static void setup_8254_mixed_mode (void);
106 static void i8254_restore(void);
109 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
110 * can use a simple formula for leap years.
112 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
113 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
116 #define TIMER_FREQ 1193182
120 #define TIMER_SELX TIMER_SEL1
121 #define TIMER_CNTRX TIMER_CNTR1
123 #define TIMER_SELX TIMER_SEL2
124 #define TIMER_CNTRX TIMER_CNTR2
127 int adjkerntz; /* local offset from GMT in seconds */
128 int disable_rtc_set; /* disable resettodr() if != 0 */
129 volatile u_int idelayed;
130 int statclock_disable = 1; /* we don't use the statclock right now */
131 u_int stat_imask = SWI_CLOCK_MASK;
132 u_int cputimer_freq = TIMER_FREQ;
134 int64_t cputimer_freq64_usec = ((int64_t)TIMER_FREQ << 32) / 1000000;
135 int64_t cputimer_freq64_nsec = ((int64_t)TIMER_FREQ << 32) / 1000000000LL;
137 int64_t cputimer_freq64_usec = (1000000LL << 32) / TIMER_FREQ;
138 int64_t cputimer_freq64_nsec = (1000000000LL << 32) / TIMER_FREQ;
141 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
143 enum tstate { RELEASED, ACQUIRED };
144 enum tstate timer0_state;
145 enum tstate timer1_state;
146 enum tstate timer2_state;
148 static int beeping = 0;
149 static u_int clk_imask = HWI_MASK | SWI_MASK;
150 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
151 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
152 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
153 static u_int tsc_present;
155 static struct callout sysbeepstop_ch;
158 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
159 * counting as of this interrupt. We use timer1 in free-running mode (not
160 * generating any interrupts) as our main counter. Each cpu has timeouts
164 clkintr(struct intrframe frame)
166 static sysclock_t timer1_count;
167 struct globaldata *gd = mycpu;
168 struct globaldata *gscan;
172 * SWSTROBE mode is a one-shot, the timer is no longer running
177 * XXX the dispatcher needs work. right now we call systimer_intr()
178 * directly or via IPI for any cpu with systimers queued, which is
179 * usually *ALL* of them. We need a better way to do this.
181 timer1_count = cputimer_count();
182 for (n = 0; n < ncpus; ++n) {
183 gscan = globaldata_find(n);
184 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
187 lwkt_send_ipiq(gscan, (ipifunc_t)systimer_intr, &timer1_count);
189 systimer_intr(&timer1_count, &frame);
193 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
195 outb(0x61, inb(0x61) | 0x80);
204 acquire_timer2(int mode)
207 if (timer2_state != RELEASED)
209 timer2_state = ACQUIRED;
212 * This access to the timer registers is as atomic as possible
213 * because it is a single instruction. We could do better if we
216 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
219 /* Timer2 is being used for time count operation */
227 if (timer2_state != ACQUIRED)
229 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
230 timer2_state = RELEASED;
235 * This routine receives statistical clock interrupts from the RTC.
236 * As explained above, these occur at 128 interrupts per second.
237 * When profiling, we receive interrupts at a rate of 1024 Hz.
239 * This does not actually add as much overhead as it sounds, because
240 * when the statistical clock is active, the hardclock driver no longer
241 * needs to keep (inaccurate) statistics on its own. This decouples
242 * statistics gathering from scheduling interrupts.
244 * The RTC chip requires that we read status register C (RTC_INTR)
245 * to acknowledge an interrupt, before it will generate the next one.
246 * Under high interrupt load, rtcintr() can be indefinitely delayed and
247 * the clock can tick immediately after the read from RTC_INTR. In this
248 * case, the mc146818A interrupt signal will not drop for long enough
249 * to register with the 8259 PIC. If an interrupt is missed, the stat
250 * clock will halt, considerably degrading system performance. This is
251 * why we use 'while' rather than a more straightforward 'if' below.
252 * Stat clock ticks can still be lost, causing minor loss of accuracy
253 * in the statistics, but the stat clock will no longer stop.
256 rtcintr(struct intrframe frame)
258 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
260 /* statclock(&frame); no longer used */
267 DB_SHOW_COMMAND(rtc, rtc)
269 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
270 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
271 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
272 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
277 * Convert a frequency to a cpu timer count.
280 cputimer_fromhz(int freq)
282 return(cputimer_freq / freq + 1);
286 cputimer_fromus(int us)
288 return((int64_t)cputimer_freq * us / 1000000);
292 * Return the current cpu timer count as a 32 bit integer.
297 static sysclock_t cputimer_base;
298 static __uint16_t cputimer_last;
303 outb(TIMER_MODE, TIMER_SELX | TIMER_LATCH);
304 count = (__uint8_t)inb(TIMER_CNTRX); /* get countdown */
305 count |= ((__uint8_t)inb(TIMER_CNTRX) << 8);
306 count = -count; /* -> countup */
307 if (count < cputimer_last) /* rollover */
308 cputimer_base += 0x00010000;
309 ret = cputimer_base | count;
310 cputimer_last = count;
316 * Reload for the next timeout. It is possible for the reload value
317 * to be 0 or negative, indicating that an immediate timer interrupt
318 * is desired. For now make the minimum 2 ticks.
321 cputimer_intr_reload(sysclock_t reload)
329 if (timer0_running) {
330 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
331 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
332 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
333 if (reload < count) {
334 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
335 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
336 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
341 reload = 0; /* full count */
342 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
343 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
344 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
350 * Wait "n" microseconds.
351 * Relies on timer 1 counting down from (cputimer_freq / hz)
352 * Note: timer had better have been programmed before this is first used!
357 int delta, prev_tick, tick, ticks_left;
362 static int state = 0;
366 for (n1 = 1; n1 <= 10000000; n1 *= 10)
371 printf("DELAY(%d)...", n);
374 * Guard against the timer being uninitialized if we are called
375 * early for console i/o.
377 if (timer0_state == RELEASED)
381 * Read the counter first, so that the rest of the setup overhead is
382 * counted. Guess the initial overhead is 20 usec (on most systems it
383 * takes about 1.5 usec for each of the i/o's in getit(). The loop
384 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
385 * multiplications and divisions to scale the count take a while).
387 prev_tick = cputimer_count();
388 n -= 0; /* XXX actually guess no initial overhead */
390 * Calculate (n * (cputimer_freq / 1e6)) without using floating point
391 * and without any avoidable overflows.
395 } else if (n < 256) {
397 * Use fixed point to avoid a slow division by 1000000.
398 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
399 * 2^15 is the first power of 2 that gives exact results
400 * for n between 0 and 256.
402 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
405 * Don't bother using fixed point, although gcc-2.7.2
406 * generates particularly poor code for the long long
407 * division, since even the slow way will complete long
408 * before the delay is up (unless we're interrupted).
410 ticks_left = ((u_int)n * (long long)cputimer_freq + 999999)
414 while (ticks_left > 0) {
415 tick = cputimer_count();
419 delta = tick - prev_tick;
427 printf(" %d calls to getit() at %d usec each\n",
428 getit_calls, (n + 5) / getit_calls);
433 sysbeepstop(void *chan)
435 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
441 sysbeep(int pitch, int period)
443 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
446 * Nobody else is using timer2, we do not need the clock lock
448 outb(TIMER_CNTR2, pitch);
449 outb(TIMER_CNTR2, (pitch>>8));
451 /* enable counter2 output to speaker */
452 outb(IO_PPI, inb(IO_PPI) | 3);
454 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
460 * RTC support routines
473 val = inb(IO_RTC + 1);
480 writertc(u_char reg, u_char val)
488 outb(IO_RTC + 1, val);
489 inb(0x84); /* XXX work around wrong order in rtcin() */
496 return(bcd2bin(rtcin(port)));
500 calibrate_clocks(void)
503 u_int count, prev_count, tot_count;
504 int sec, start_sec, timeout;
507 printf("Calibrating clock(s) ... ");
508 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
512 /* Read the mc146818A seconds counter. */
514 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
515 sec = rtcin(RTC_SEC);
522 /* Wait for the mC146818A seconds counter to change. */
525 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
526 sec = rtcin(RTC_SEC);
527 if (sec != start_sec)
534 /* Start keeping track of the i8254 counter. */
535 prev_count = cputimer_count();
541 old_tsc = 0; /* shut up gcc */
544 * Wait for the mc146818A seconds counter to change. Read the i8254
545 * counter for each iteration since this is convenient and only
546 * costs a few usec of inaccuracy. The timing of the final reads
547 * of the counters almost matches the timing of the initial reads,
548 * so the main cause of inaccuracy is the varying latency from
549 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
550 * rtcin(RTC_SEC) that returns a changed seconds count. The
551 * maximum inaccuracy from this cause is < 10 usec on 486's.
555 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
556 sec = rtcin(RTC_SEC);
557 count = cputimer_count();
558 tot_count += (int)(count - prev_count);
560 if (sec != start_sec)
567 * Read the cpu cycle counter. The timing considerations are
568 * similar to those for the i8254 clock.
571 tsc_freq = rdtsc() - old_tsc;
574 printf("TSC clock: %u Hz, ", tsc_freq);
575 printf("i8254 clock: %u Hz\n", tot_count);
579 printf("failed, using default i8254 clock of %u Hz\n", cputimer_freq);
580 return (cputimer_freq);
586 timer0_state = ACQUIRED;
588 timer1_state = ACQUIRED;
590 timer2_state = ACQUIRED;
593 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
594 outb(TIMER_CNTR0, 2); /* lsb */
595 outb(TIMER_CNTR0, 0); /* msb */
596 outb(TIMER_MODE, TIMER_SELX | TIMER_RATEGEN | TIMER_16BIT);
597 outb(TIMER_CNTRX, 0); /* lsb */
598 outb(TIMER_CNTRX, 0); /* msb */
599 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
606 /* Restore all of the RTC's "status" (actually, control) registers. */
607 writertc(RTC_STATUSB, RTCSB_24HR);
608 writertc(RTC_STATUSA, rtc_statusa);
609 writertc(RTC_STATUSB, rtc_statusb);
613 * Restore all the timers.
615 * This function is called to resynchronize our core timekeeping after a
616 * long halt, e.g. from apm_default_resume() and friends. It is also
617 * called if after a BIOS call we have detected munging of the 8254.
618 * It is necessary because cputimer_count() counter's delta may have grown
619 * too large for nanouptime() and friends to handle, or (in the case of 8254
620 * munging) might cause the SYSTIMER code to prematurely trigger.
626 i8254_restore(); /* restore timer_freq and hz */
627 rtc_restore(); /* reenable RTC interrupts */
632 * Initialize 8254 timer 0 early so that it can be used in DELAY().
640 * Can we use the TSC?
642 if (cpu_feature & CPUID_TSC)
648 * Initial RTC state, don't do anything unexpected
650 writertc(RTC_STATUSA, rtc_statusa);
651 writertc(RTC_STATUSB, RTCSB_24HR);
654 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
655 * generate an interrupt, which we will ignore for now.
657 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
658 * (so it counts a full 2^16 and repeats). We will use this timer
662 freq = calibrate_clocks();
663 #ifdef CLK_CALIBRATION_LOOP
666 "Press a key on the console to abort clock calibration\n");
667 while (cncheckc() == -1)
673 * Use the calibrated i8254 frequency if it seems reasonable.
674 * Otherwise use the default, and don't use the calibrated i586
677 delta = freq > cputimer_freq ?
678 freq - cputimer_freq : cputimer_freq - freq;
679 if (delta < cputimer_freq / 100) {
680 #ifndef CLK_USE_I8254_CALIBRATION
683 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
684 freq = cputimer_freq;
686 cputimer_freq = freq;
687 cputimer_freq64_usec = (1000000LL << 32) / freq;
688 cputimer_freq64_nsec = (1000000000LL << 32) / freq;
692 "%d Hz differs from default of %d Hz by more than 1%%\n",
693 freq, cputimer_freq);
697 #ifndef CLK_USE_TSC_CALIBRATION
701 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
705 if (tsc_present && tsc_freq == 0) {
707 * Calibration of the i586 clock relative to the mc146818A
708 * clock failed. Do a less accurate calibration relative
709 * to the i8254 clock.
711 u_int64_t old_tsc = rdtsc();
714 tsc_freq = rdtsc() - old_tsc;
715 #ifdef CLK_USE_TSC_CALIBRATION
717 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
723 * We can not use the TSC in SMP mode, until we figure out a
724 * cheap (impossible), reliable and precise (yeah right!) way
725 * to synchronize the TSCs of all the CPUs.
726 * Curse Intel for leaving the counter out of the I/O APIC.
731 * We can not use the TSC if we support APM. Precise timekeeping
732 * on an APM'ed machine is at best a fools pursuit, since
733 * any and all of the time spent in various SMM code can't
734 * be reliably accounted for. Reading the RTC is your only
735 * source of reliable time info. The i8254 looses too of course
736 * but we need to have some kind of time...
737 * We don't know at this point whether APM is going to be used
738 * or not, nor when it might be activated. Play it safe.
741 #endif /* NAPM > 0 */
743 #endif /* !defined(SMP) */
747 * Initialize the time of day register, based on the time base which is, e.g.
751 inittodr(time_t base)
753 unsigned long sec, days;
765 /* Look if we have a RTC present and the time is valid */
766 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
769 /* wait for time update to complete */
770 /* If RTCSA_TUP is zero, we have at least 244us before next update */
772 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
778 #ifdef USE_RTC_CENTURY
779 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
781 year = readrtc(RTC_YEAR) + 1900;
789 month = readrtc(RTC_MONTH);
790 for (m = 1; m < month; m++)
791 days += daysinmonth[m-1];
792 if ((month > 2) && LEAPYEAR(year))
794 days += readrtc(RTC_DAY) - 1;
796 for (y = 1970; y < year; y++)
797 days += DAYSPERYEAR + LEAPYEAR(y);
798 sec = ((( days * 24 +
799 readrtc(RTC_HRS)) * 60 +
800 readrtc(RTC_MIN)) * 60 +
802 /* sec now contains the number of seconds, since Jan 1 1970,
803 in the local time zone */
805 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
807 y = time_second - sec;
808 if (y <= -2 || y >= 2) {
809 /* badly off, adjust it */
818 printf("Invalid time in real time clock.\n");
819 printf("Check and reset the date immediately!\n");
823 * Write system time back to RTC
840 /* Disable RTC updates and interrupts. */
841 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
843 /* Calculate local time to put in RTC */
845 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
847 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
848 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
849 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
851 /* We have now the days since 01-01-1970 in tm */
852 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
853 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
855 y++, m = DAYSPERYEAR + LEAPYEAR(y))
858 /* Now we have the years in y and the day-of-the-year in tm */
859 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
860 #ifdef USE_RTC_CENTURY
861 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
867 if (m == 1 && LEAPYEAR(y))
874 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
875 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
877 /* Reenable RTC updates and interrupts. */
878 writertc(RTC_STATUSB, rtc_statusb);
884 * Start both clocks running. DragonFly note: the stat clock is no longer
885 * used. Instead, 8254 based systimers are used for all major clock
886 * interrupts. statclock_disable is set by default.
894 struct intrec *clkdesc;
897 if (statclock_disable) {
899 * The stat interrupt mask is different without the
900 * statistics clock. Also, don't set the interrupt
901 * flag which would normally cause the RTC to generate
904 stat_imask = HWI_MASK | SWI_MASK;
905 rtc_statusb = RTCSB_24HR;
907 /* Setting stathz to nonzero early helps avoid races. */
908 stathz = RTC_NOPROFRATE;
909 profhz = RTC_PROFRATE;
912 /* Finish initializing 8253 timer 0. */
915 apic_8254_intr = isa_apic_irq(0);
917 if (apic_8254_intr >= 0 ) {
918 if (apic_int_type(0, 0) == 3)
921 /* look for ExtInt on pin 0 */
922 if (apic_int_type(0, 0) == 3) {
923 apic_8254_intr = apic_irq(0, 0);
924 setup_8254_mixed_mode();
926 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
929 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
930 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
931 INTREN(1 << apic_8254_intr);
935 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
936 INTR_EXCL | INTR_FAST);
941 /* Initialize RTC. */
942 writertc(RTC_STATUSA, rtc_statusa);
943 writertc(RTC_STATUSB, RTCSB_24HR);
945 if (statclock_disable == 0) {
946 diag = rtcin(RTC_DIAG);
948 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
951 if (isa_apic_irq(8) != 8)
952 panic("APIC RTC != 8");
955 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
956 INTR_EXCL | INTR_FAST);
964 writertc(RTC_STATUSB, rtc_statusb);
968 if (apic_8254_trial) {
970 int lastcnt = read_intr_count(apic_8254_intr);
973 * XXX this assumes the 8254 is the cpu timer. Force an
974 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
975 * then see if we got it.
977 printf("APIC_IO: Testing 8254 interrupt delivery\n");
978 cputimer_intr_reload(2); /* XXX assumes 8254 */
979 base = cputimer_count();
980 while (cputimer_count() - base < cputimer_freq / 100)
982 if (read_intr_count(apic_8254_intr) - lastcnt == 0) {
984 * The MP table is broken.
985 * The 8254 was not connected to the specified pin
987 * Workaround: Limited variant of mixed mode.
989 INTRDIS(1 << apic_8254_intr);
990 inthand_remove(clkdesc);
991 printf("APIC_IO: Broken MP table detected: "
992 "8254 is not connected to "
993 "IOAPIC #%d intpin %d\n",
994 int_to_apicintpin[apic_8254_intr].ioapic,
995 int_to_apicintpin[apic_8254_intr].int_pin);
997 * Revoke current ISA IRQ 0 assignment and
998 * configure a fallback interrupt routing from
999 * the 8254 Timer via the 8259 PIC to the
1000 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1001 * We reuse the low level interrupt handler number.
1003 if (apic_irq(0, 0) < 0) {
1004 revoke_apic_irq(apic_8254_intr);
1005 assign_apic_irq(0, 0, apic_8254_intr);
1007 apic_8254_intr = apic_irq(0, 0);
1008 setup_8254_mixed_mode();
1009 inthand_add("clk", apic_8254_intr,
1010 (inthand2_t *)clkintr,
1011 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1012 INTREN(1 << apic_8254_intr);
1016 if (apic_int_type(0, 0) != 3 ||
1017 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1018 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1019 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1020 int_to_apicintpin[apic_8254_intr].ioapic,
1021 int_to_apicintpin[apic_8254_intr].int_pin);
1024 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1027 callout_init(&sysbeepstop_ch);
1032 read_intr_count(int vec)
1035 up = intr_countp[vec];
1042 setup_8254_mixed_mode()
1045 * Allow 8254 timer to INTerrupt 8259:
1046 * re-initialize master 8259:
1047 * reset; prog 4 bytes, single ICU, edge triggered
1049 outb(IO_ICU1, 0x13);
1050 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1051 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1052 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1053 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1055 /* program IO APIC for type 3 INT on INT0 */
1056 if (ext_int_setup(0, 0) < 0)
1057 panic("8254 redirect via APIC pin0 impossible!");
1062 setstatclockrate(int newhz)
1064 if (newhz == RTC_PROFRATE)
1065 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1067 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1068 writertc(RTC_STATUSA, rtc_statusa);
1073 tsc_get_timecount(struct timecounter *tc)
1079 #ifdef KERN_TIMESTAMP
1080 #define KERN_TIMESTAMP_SIZE 16384
1081 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1082 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1083 sizeof(tsc), "LU", "Kernel timestamps");
1089 tsc[i] = (u_int32_t)rdtsc();
1092 if (i >= KERN_TIMESTAMP_SIZE)
1094 tsc[i] = 0; /* mark last entry */
1096 #endif /* KERN_TIMESTAMP */
1103 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1110 count = cputimer_count();
1116 snprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1117 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1120 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1121 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &cputimer_freq, 0, "");
1122 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1123 0, 0, hw_i8254_timestamp, "A", "");