2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
51 #include "opt_clock.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/eventhandler.h>
57 #include <sys/kernel.h>
59 #include <sys/sysctl.h>
61 #include <sys/systimer.h>
62 #include <sys/globaldata.h>
63 #include <sys/thread2.h>
64 #include <sys/systimer.h>
65 #include <sys/machintr.h>
66 #include <sys/interrupt.h>
68 #include <machine/clock.h>
69 #include <machine/cputypes.h>
70 #include <machine/frame.h>
71 #include <machine/ipl.h>
72 #include <machine/limits.h>
73 #include <machine/md_var.h>
74 #include <machine/psl.h>
75 #include <machine/segments.h>
76 #include <machine/smp.h>
77 #include <machine/specialreg.h>
79 #include <machine_base/apic/ioapic.h>
80 #include <machine_base/apic/ioapic_abi.h>
81 #include <machine_base/icu/icu.h>
82 #include <bus/isa/isa.h>
83 #include <bus/isa/rtc.h>
84 #include <machine_base/isa/timerreg.h>
86 #include <machine/intr_machdep.h>
88 static void i8254_restore(void);
89 static void resettodr_on_shutdown(void *arg __unused);
92 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
93 * can use a simple formula for leap years.
95 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
96 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
99 #define TIMER_FREQ 1193182
102 static uint8_t i8254_walltimer_sel;
103 static uint16_t i8254_walltimer_cntr;
105 int adjkerntz; /* local offset from GMT in seconds */
106 int disable_rtc_set; /* disable resettodr() if != 0 */
108 int64_t tsc_frequency;
110 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
112 enum tstate { RELEASED, ACQUIRED };
113 enum tstate timer0_state;
114 enum tstate timer1_state;
115 enum tstate timer2_state;
117 static int beeping = 0;
118 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
119 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
120 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
121 static int rtc_loaded;
123 static int i8254_cputimer_div;
125 static int i8254_nointr;
126 static int i8254_intr_disable = 1;
127 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
129 static struct callout sysbeepstop_ch;
131 static sysclock_t i8254_cputimer_count(void);
132 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
133 static void i8254_cputimer_destruct(struct cputimer *cputimer);
135 static struct cputimer i8254_cputimer = {
136 SLIST_ENTRY_INITIALIZER,
140 i8254_cputimer_count,
141 cputimer_default_fromhz,
142 cputimer_default_fromus,
143 i8254_cputimer_construct,
144 i8254_cputimer_destruct,
149 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
150 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
151 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
153 static struct cputimer_intr i8254_cputimer_intr = {
155 .reload = i8254_intr_reload,
156 .enable = cputimer_intr_default_enable,
157 .config = i8254_intr_config,
158 .restart = cputimer_intr_default_restart,
159 .pmfixup = cputimer_intr_default_pmfixup,
160 .initclock = i8254_intr_initclock,
161 .next = SLIST_ENTRY_INITIALIZER,
163 .type = CPUTIMER_INTR_8254,
164 .prio = CPUTIMER_INTR_PRIO_8254,
165 .caps = CPUTIMER_INTR_CAP_PS
169 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
170 * counting as of this interrupt. We use timer1 in free-running mode (not
171 * generating any interrupts) as our main counter. Each cpu has timeouts
174 * This code is INTR_MPSAFE and may be called without the BGL held.
177 clkintr(void *dummy, void *frame_arg)
179 static sysclock_t sysclock_count; /* NOTE! Must be static */
180 struct globaldata *gd = mycpu;
181 struct globaldata *gscan;
185 * SWSTROBE mode is a one-shot, the timer is no longer running
190 * XXX the dispatcher needs work. right now we call systimer_intr()
191 * directly or via IPI for any cpu with systimers queued, which is
192 * usually *ALL* of them. We need to use the LAPIC timer for this.
194 sysclock_count = sys_cputimer->count();
195 for (n = 0; n < ncpus; ++n) {
196 gscan = globaldata_find(n);
197 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
200 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
203 systimer_intr(&sysclock_count, 0, frame_arg);
213 acquire_timer2(int mode)
215 if (timer2_state != RELEASED)
217 timer2_state = ACQUIRED;
220 * This access to the timer registers is as atomic as possible
221 * because it is a single instruction. We could do better if we
224 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
231 if (timer2_state != ACQUIRED)
233 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
234 timer2_state = RELEASED;
242 DB_SHOW_COMMAND(rtc, rtc)
244 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
245 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
246 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
247 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
252 * Return the current cpu timer count as a 32 bit integer.
256 i8254_cputimer_count(void)
258 static __uint16_t cputimer_last;
263 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
264 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
265 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
266 count = -count; /* -> countup */
267 if (count < cputimer_last) /* rollover */
268 i8254_cputimer.base += 0x00010000;
269 ret = i8254_cputimer.base | count;
270 cputimer_last = count;
276 * This function is called whenever the system timebase changes, allowing
277 * us to calculate what is needed to convert a system timebase tick
278 * into an 8254 tick for the interrupt timer. If we can convert to a
279 * simple shift, multiplication, or division, we do so. Otherwise 64
280 * bit arithmatic is required every time the interrupt timer is reloaded.
283 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
289 * Will a simple divide do the trick?
291 div = (timer->freq + (cti->freq / 2)) / cti->freq;
292 freq = cti->freq * div;
294 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
295 i8254_cputimer_div = div;
297 i8254_cputimer_div = 0;
301 * Reload for the next timeout. It is possible for the reload value
302 * to be 0 or negative, indicating that an immediate timer interrupt
303 * is desired. For now make the minimum 2 ticks.
305 * We may have to convert from the system timebase to the 8254 timebase.
308 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
312 if (i8254_cputimer_div)
313 reload /= i8254_cputimer_div;
315 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
321 if (timer0_running) {
322 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
323 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
324 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
325 if (reload < count) {
326 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
327 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
328 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
333 reload = 0; /* full count */
334 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
335 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
336 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
342 * DELAY(usec) - Spin for the specified number of microseconds.
343 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
344 * but do a thread switch in the loop
346 * Relies on timer 1 counting down from (cputimer_freq / hz)
347 * Note: timer had better have been programmed before this is first used!
350 DODELAY(int n, int doswitch)
352 ssysclock_t delta, ticks_left;
353 sysclock_t prev_tick, tick;
358 static int state = 0;
362 for (n1 = 1; n1 <= 10000000; n1 *= 10)
367 kprintf("DELAY(%d)...", n);
370 * Guard against the timer being uninitialized if we are called
371 * early for console i/o.
373 if (timer0_state == RELEASED)
377 * Read the counter first, so that the rest of the setup overhead is
378 * counted. Then calculate the number of hardware timer ticks
379 * required, rounding up to be sure we delay at least the requested
380 * number of microseconds.
382 prev_tick = sys_cputimer->count();
383 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
389 while (ticks_left > 0) {
390 tick = sys_cputimer->count();
394 delta = tick - prev_tick;
399 if (doswitch && ticks_left > 0)
405 kprintf(" %d calls to getit() at %d usec each\n",
406 getit_calls, (n + 5) / getit_calls);
411 * DELAY() never switches
420 CHECKTIMEOUT(TOTALDELAY *tdd)
425 if (tdd->started == 0) {
426 if (timer0_state == RELEASED)
428 tdd->last_clock = sys_cputimer->count();
432 delta = sys_cputimer->count() - tdd->last_clock;
433 us = (u_int64_t)delta * (u_int64_t)1000000 /
434 (u_int64_t)sys_cputimer->freq;
435 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
438 return (tdd->us < 0);
442 * DRIVERSLEEP() does not switch if called with a spinlock held or
443 * from a hard interrupt.
446 DRIVERSLEEP(int usec)
448 globaldata_t gd = mycpu;
450 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
458 sysbeepstop(void *chan)
460 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
466 sysbeep(int pitch, int period)
468 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
470 if (sysbeep_enable == 0)
473 * Nobody else is using timer2, we do not need the clock lock
475 outb(TIMER_CNTR2, pitch);
476 outb(TIMER_CNTR2, (pitch>>8));
478 /* enable counter2 output to speaker */
479 outb(IO_PPI, inb(IO_PPI) | 3);
481 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
487 * RTC support routines
498 val = inb(IO_RTC + 1);
505 writertc(u_char reg, u_char val)
511 outb(IO_RTC + 1, val);
512 inb(0x84); /* XXX work around wrong order in rtcin() */
519 return(bcd2bin(rtcin(port)));
523 calibrate_clocks(void)
527 sysclock_t count, prev_count;
528 int sec, start_sec, timeout;
531 kprintf("Calibrating clock(s) ... ");
532 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
536 /* Read the mc146818A seconds counter. */
538 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
539 sec = rtcin(RTC_SEC);
546 /* Wait for the mC146818A seconds counter to change. */
549 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
550 sec = rtcin(RTC_SEC);
551 if (sec != start_sec)
558 /* Start keeping track of the i8254 counter. */
559 prev_count = sys_cputimer->count();
565 old_tsc = 0; /* shut up gcc */
568 * Wait for the mc146818A seconds counter to change. Read the i8254
569 * counter for each iteration since this is convenient and only
570 * costs a few usec of inaccuracy. The timing of the final reads
571 * of the counters almost matches the timing of the initial reads,
572 * so the main cause of inaccuracy is the varying latency from
573 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
574 * rtcin(RTC_SEC) that returns a changed seconds count. The
575 * maximum inaccuracy from this cause is < 10 usec on 486's.
579 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
580 sec = rtcin(RTC_SEC);
581 count = sys_cputimer->count();
582 tot_count += (int)(count - prev_count);
584 if (sec != start_sec)
591 * Read the cpu cycle counter. The timing considerations are
592 * similar to those for the i8254 clock.
595 tsc_frequency = rdtsc() - old_tsc;
599 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
600 kprintf("i8254 clock: %u Hz\n", tot_count);
604 kprintf("failed, using default i8254 clock of %u Hz\n",
605 i8254_cputimer.freq);
606 return (i8254_cputimer.freq);
612 timer0_state = ACQUIRED;
617 * Timer0 is our fine-grained variable clock interrupt
619 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
620 outb(TIMER_CNTR0, 2); /* lsb */
621 outb(TIMER_CNTR0, 0); /* msb */
625 cputimer_intr_register(&i8254_cputimer_intr);
626 cputimer_intr_select(&i8254_cputimer_intr, 0);
630 * Timer1 or timer2 is our free-running clock, but only if another
631 * has not been selected.
633 cputimer_register(&i8254_cputimer);
634 cputimer_select(&i8254_cputimer, 0);
638 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
643 * Should we use timer 1 or timer 2 ?
646 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
647 if (which != 1 && which != 2)
652 timer->name = "i8254_timer1";
653 timer->type = CPUTIMER_8254_SEL1;
654 i8254_walltimer_sel = TIMER_SEL1;
655 i8254_walltimer_cntr = TIMER_CNTR1;
656 timer1_state = ACQUIRED;
659 timer->name = "i8254_timer2";
660 timer->type = CPUTIMER_8254_SEL2;
661 i8254_walltimer_sel = TIMER_SEL2;
662 i8254_walltimer_cntr = TIMER_CNTR2;
663 timer2_state = ACQUIRED;
667 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
670 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
671 outb(i8254_walltimer_cntr, 0); /* lsb */
672 outb(i8254_walltimer_cntr, 0); /* msb */
673 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
678 i8254_cputimer_destruct(struct cputimer *timer)
680 switch(timer->type) {
681 case CPUTIMER_8254_SEL1:
682 timer1_state = RELEASED;
684 case CPUTIMER_8254_SEL2:
685 timer2_state = RELEASED;
696 /* Restore all of the RTC's "status" (actually, control) registers. */
697 writertc(RTC_STATUSB, RTCSB_24HR);
698 writertc(RTC_STATUSA, rtc_statusa);
699 writertc(RTC_STATUSB, rtc_statusb);
703 * Restore all the timers.
705 * This function is called to resynchronize our core timekeeping after a
706 * long halt, e.g. from apm_default_resume() and friends. It is also
707 * called if after a BIOS call we have detected munging of the 8254.
708 * It is necessary because cputimer_count() counter's delta may have grown
709 * too large for nanouptime() and friends to handle, or (in the case of 8254
710 * munging) might cause the SYSTIMER code to prematurely trigger.
716 i8254_restore(); /* restore timer_freq and hz */
717 rtc_restore(); /* reenable RTC interrupts */
722 * Initialize 8254 timer 0 early so that it can be used in DELAY().
730 * Can we use the TSC?
732 if (cpu_feature & CPUID_TSC)
738 * Initial RTC state, don't do anything unexpected
740 writertc(RTC_STATUSA, rtc_statusa);
741 writertc(RTC_STATUSB, RTCSB_24HR);
744 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
745 * generate an interrupt, which we will ignore for now.
747 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
748 * (so it counts a full 2^16 and repeats). We will use this timer
752 freq = calibrate_clocks();
753 #ifdef CLK_CALIBRATION_LOOP
756 "Press a key on the console to abort clock calibration\n");
757 while (cncheckc() == -1)
763 * Use the calibrated i8254 frequency if it seems reasonable.
764 * Otherwise use the default, and don't use the calibrated i586
767 delta = freq > i8254_cputimer.freq ?
768 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
769 if (delta < i8254_cputimer.freq / 100) {
770 #ifndef CLK_USE_I8254_CALIBRATION
773 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
774 freq = i8254_cputimer.freq;
778 * Interrupt timer's freq must be adjusted
779 * before we change the cuptimer's frequency.
781 i8254_cputimer_intr.freq = freq;
782 cputimer_set_frequency(&i8254_cputimer, freq);
786 "%d Hz differs from default of %d Hz by more than 1%%\n",
787 freq, i8254_cputimer.freq);
791 #ifndef CLK_USE_TSC_CALIBRATION
792 if (tsc_frequency != 0) {
795 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
799 if (tsc_present && tsc_frequency == 0) {
801 * Calibration of the i586 clock relative to the mc146818A
802 * clock failed. Do a less accurate calibration relative
803 * to the i8254 clock.
805 u_int64_t old_tsc = rdtsc();
808 tsc_frequency = rdtsc() - old_tsc;
809 #ifdef CLK_USE_TSC_CALIBRATION
811 kprintf("TSC clock: %llu Hz (Method B)\n",
817 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
821 * Sync the time of day back to the RTC on shutdown, but only if
822 * we have already loaded it and have not crashed.
825 resettodr_on_shutdown(void *arg __unused)
827 if (rtc_loaded && panicstr == NULL) {
833 * Initialize the time of day register, based on the time base which is, e.g.
837 inittodr(time_t base)
839 unsigned long sec, days;
850 /* Look if we have a RTC present and the time is valid */
851 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
854 /* wait for time update to complete */
855 /* If RTCSA_TUP is zero, we have at least 244us before next update */
857 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
863 #ifdef USE_RTC_CENTURY
864 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
866 year = readrtc(RTC_YEAR) + 1900;
874 month = readrtc(RTC_MONTH);
875 for (m = 1; m < month; m++)
876 days += daysinmonth[m-1];
877 if ((month > 2) && LEAPYEAR(year))
879 days += readrtc(RTC_DAY) - 1;
880 for (y = 1970; y < year; y++)
881 days += DAYSPERYEAR + LEAPYEAR(y);
882 sec = ((( days * 24 +
883 readrtc(RTC_HRS)) * 60 +
884 readrtc(RTC_MIN)) * 60 +
886 /* sec now contains the number of seconds, since Jan 1 1970,
887 in the local time zone */
889 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
891 y = time_second - sec;
892 if (y <= -2 || y >= 2) {
893 /* badly off, adjust it */
903 kprintf("Invalid time in real time clock.\n");
904 kprintf("Check and reset the date immediately!\n");
908 * Write system time back to RTC
925 /* Disable RTC updates and interrupts. */
926 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
928 /* Calculate local time to put in RTC */
930 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
932 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
933 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
934 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
936 /* We have now the days since 01-01-1970 in tm */
937 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
938 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
940 y++, m = DAYSPERYEAR + LEAPYEAR(y))
943 /* Now we have the years in y and the day-of-the-year in tm */
944 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
945 #ifdef USE_RTC_CENTURY
946 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
952 if (m == 1 && LEAPYEAR(y))
959 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
960 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
962 /* Reenable RTC updates and interrupts. */
963 writertc(RTC_STATUSB, rtc_statusb);
968 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
974 * Following code assumes the 8254 is the cpu timer,
975 * so make sure it is.
977 KKASSERT(sys_cputimer == &i8254_cputimer);
978 KKASSERT(cti == &i8254_cputimer_intr);
980 lastcnt = get_interrupt_counter(irq, mycpuid);
983 * Force an 8254 Timer0 interrupt and wait 1/100s for
984 * it to happen, then see if we got it.
986 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
988 i8254_intr_reload(cti, 2);
989 base = sys_cputimer->count();
990 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
993 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
999 * Start both clocks running. DragonFly note: the stat clock is no longer
1000 * used. Instead, 8254 based systimers are used for all major clock
1004 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1006 void *clkdesc = NULL;
1007 int irq = 0, mixed_mode = 0, error;
1009 KKASSERT(mycpuid == 0);
1010 callout_init(&sysbeepstop_ch);
1012 if (!selected && i8254_intr_disable)
1016 * The stat interrupt mask is different without the
1017 * statistics clock. Also, don't set the interrupt
1018 * flag which would normally cause the RTC to generate
1021 rtc_statusb = RTCSB_24HR;
1023 /* Finish initializing 8253 timer 0. */
1024 if (ioapic_enable) {
1025 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1026 INTR_POLARITY_HIGH);
1029 error = ioapic_conf_legacy_extint(0);
1031 irq = machintr_legacy_intr_find(0,
1032 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1039 kprintf("IOAPIC: setup mixed mode for "
1040 "irq 0 failed: %d\n", error);
1043 panic("IOAPIC: setup mixed mode for "
1044 "irq 0 failed: %d\n", error);
1049 clkdesc = register_int(irq, clkintr, NULL, "clk",
1051 INTR_EXCL | INTR_CLOCK |
1052 INTR_NOPOLL | INTR_MPSAFE |
1055 register_int(0, clkintr, NULL, "clk", NULL,
1056 INTR_EXCL | INTR_CLOCK |
1057 INTR_NOPOLL | INTR_MPSAFE |
1061 /* Initialize RTC. */
1062 writertc(RTC_STATUSA, rtc_statusa);
1063 writertc(RTC_STATUSB, RTCSB_24HR);
1065 if (ioapic_enable) {
1066 error = i8254_ioapic_trial(irq, cti);
1070 kprintf("IOAPIC: mixed mode for irq %d "
1071 "trial failed: %d\n",
1075 panic("IOAPIC: mixed mode for irq %d "
1076 "trial failed: %d\n", irq, error);
1079 kprintf("IOAPIC: warning 8254 is not connected "
1080 "to the correct pin, try mixed mode\n");
1081 unregister_int(clkdesc, 0);
1082 goto mixed_mode_setup;
1089 i8254_nointr = 1; /* don't try to register again */
1090 cputimer_intr_deregister(cti);
1094 setstatclockrate(int newhz)
1096 if (newhz == RTC_PROFRATE)
1097 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1099 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1100 writertc(RTC_STATUSA, rtc_statusa);
1105 tsc_get_timecount(struct timecounter *tc)
1111 #ifdef KERN_TIMESTAMP
1112 #define KERN_TIMESTAMP_SIZE 16384
1113 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1114 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1115 sizeof(tsc), "LU", "Kernel timestamps");
1121 tsc[i] = (u_int32_t)rdtsc();
1124 if (i >= KERN_TIMESTAMP_SIZE)
1126 tsc[i] = 0; /* mark last entry */
1128 #endif /* KERN_TIMESTAMP */
1135 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1142 if (sys_cputimer == &i8254_cputimer)
1143 count = sys_cputimer->count();
1151 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1152 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1155 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1156 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1158 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1159 0, 0, hw_i8254_timestamp, "A", "");
1161 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1162 &tsc_present, 0, "TSC Available");
1163 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1164 &tsc_frequency, 0, "TSC Frequency");