2 DELAY's might tsleep, so interrupts might run. fix poll loop to detect
3 completion via other interrupts.
5 Locking serialize_enter/exit. Lots of recursion. Needs help. Use
6 lockmgr()? Needs to be converted to per-port locking, also.
8 Port multiplier support (basics are now in)
10 Simulate various mode pages (serial number access and so forth).
12 NOTE RACE: When stopping a port explicitly which has not self stopped,
13 i.e. CR is still on, we can race command completion and not have a good
14 idea what bits to reload into CI etc to restart the commands that
15 were running. This should only be done if we intend to reset the port.
17 NOTE RACE: A transient IFS interrupt (fatal phy/protocol error) can occur
18 when soft-resetting through a port multiplier, between the first and second
19 FISes. We need to be able to lock access to the port.
21 ------ Misc probe info --------
24 <S64A,NCQ,SSNTF,SALP,SAL,SCLO,PMD,SSC,PSC,CCCS,EMS>,
25 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps)
27 ahci0: AHCI 1.2 capabilities 0xe3229f05
28 <S64A,NCQ,SSNTF,SAL,SCLO,SPM,PMD>, 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps)
31 Chipsets supporting FBSS (FIS-Based Switching):
35 ---------------------------
39 EEEEEEEE HHHHLLLL NIRxxxxx FFFFFFFF
40 rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr (reserved)
46 H4 Status hi (bit 3 is 'r' bit?)
47 L4 Status Lo (bit 3 is 'r' bit?)
50 ATAPI/DISK notification: Word78 of IDENTIFY,
51 Use SET FEATURES to set.
53 IDENTIFY DEVICE Changed in SATA 2:
55 Word 75 4:0 Max Queue depth
57 Word 76 9 Supports IPM requests
65 Word 78 4 supports in-order data delivery
66 3 supports IPMfrom device
67 2 supports DMA setup AA opt
68 1 supports non-zero buffer offssets in DMA setup
71 Word 79 (sata features enabled)
74 Device configuration overlay
75 Word 0-7 Defined by ATA
76 Word 8 3 suports async notification
78 1 supports nz buffer offsets in DMA setup FIS
80 Word 9 reserved for SATA
81 10-255 as defined by ATA
85 Feature 10h Enable use of SATA feature
86 feature 90h Disable use of SATA feature
88 sector count register contains specific feature to enable
90 01 No zero buffer offset in DMA setup fis
91 02 DMA setup fis AA opt
92 03 device initated power state transitions
93 04 guaranteed in-order data delivery
94 05 Asynchronous notification
103 4 SNotification <----