2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pcireg.h,v 1.24.2.5 2002/08/31 10:06:51 gibbs Exp $
27 * $DragonFly: src/sys/bus/pci/pcireg.h,v 1.18 2008/07/06 05:47:14 sephe Exp $
32 * PCIM_xxx: mask to locate subfield in register
33 * PCIR_xxx: config register offset
34 * PCIC_xxx: device class
35 * PCIS_xxx: device subclass
36 * PCIP_xxx: device programming interface
37 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
39 * PCIY_xxx: capability identification number
42 /* some PCI bus constants */
44 #define PCI_BUSMAX 255
45 #define PCI_SLOTMAX 31
47 #define PCI_REGMAX 255
48 #define PCI_MAXHDRTYPE 2
50 /* PCI config header registers for all devices */
52 #define PCIR_DEVVENDOR 0x00
53 #define PCIR_VENDOR 0x00
54 #define PCIR_DEVICE 0x02
55 #define PCIR_COMMAND 0x04
56 #define PCIM_CMD_PORTEN 0x0001
57 #define PCIM_CMD_MEMEN 0x0002
58 #define PCIM_CMD_BUSMASTEREN 0x0004
59 #define PCIM_CMD_MWRICEN 0x0010
60 #define PCIM_CMD_PERRESPEN 0x0040
61 #define PCIM_CMD_SERRESPEN 0x0100
62 #define PCIR_STATUS 0x06
63 #define PCIM_STATUS_CAPPRESENT 0x0010
64 #define PCIM_STATUS_66CAPABLE 0x0020
65 #define PCIM_STATUS_BACKTOBACK 0x0080
66 #define PCIM_STATUS_PERRREPORT 0x0100
67 #define PCIM_STATUS_SEL_FAST 0x0000
68 #define PCIM_STATUS_SEL_MEDIMUM 0x0200
69 #define PCIM_STATUS_SEL_SLOW 0x0400
70 #define PCIM_STATUS_SEL_MASK 0x0600
71 #define PCIM_STATUS_STABORT 0x0800
72 #define PCIM_STATUS_RTABORT 0x1000
73 #define PCIM_STATUS_RMABORT 0x2000
74 #define PCIM_STATUS_SERR 0x4000
75 #define PCIM_STATUS_PERR 0x8000
76 #define PCIR_REVID 0x08
77 #define PCIR_PROGIF 0x09
78 #define PCIR_SUBCLASS 0x0a
79 #define PCIR_CLASS 0x0b
80 #define PCIR_CACHELNSZ 0x0c
81 #define PCIR_LATTIMER 0x0d
82 #define PCIR_HDRTYPE 0x0e
83 #define PCIM_HDRTYPE 0x7f
84 #define PCIM_HDRTYPE_NORMAL 0x00
85 #define PCIM_HDRTYPE_BRIDGE 0x01
86 #define PCIM_HDRTYPE_CARDBUS 0x02
87 #define PCIM_MFDEV 0x80
88 #define PCIR_BIST 0x0f
90 /* Capability Register Offsets */
92 #define PCICAP_NEXTPTR 0x1
94 /* Capability Identification Numbers */
95 #define PCIY_PMG 0x01 /* PCI Power Management */
96 #define PCIY_AGP 0x02 /* AGP */
97 #define PCIY_VPD 0x03 /* Vital Product Data */
98 #define PCIY_SLOTID 0x04 /* Slot Identification */
99 #define PCIY_MSI 0x05 /* Message Signaled Interrupts */
100 #define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */
101 #define PCIY_PCIX 0x07 /* PCI-X */
102 #define PCIY_HT 0x08 /* HyperTransport */
103 #define PCIY_VENDOR 0x09 /* Vendor Unique */
104 #define PCIY_DEBUG 0x0a /* Debug port */
105 #define PCIY_CRES 0x0b /* CompactPCI central resource control */
106 #define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */
107 #define PCIY_AGP8X 0x0e /* AGP 8x */
108 #define PCIY_SECDEV 0x0f /* Secure Device */
109 #define PCIY_EXPRESS 0x10 /* PCI Express */
110 #define PCIY_MSIX 0x11 /* MSI-X */
112 /* config registers for header type 0 devices */
114 #define PCIR_BARS 0x10
115 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
116 #define PCIR_MAPS PCIR_BARS /* DEPRECATED XXX */
117 #define PCIR_CARDBUSCIS 0x28
118 #define PCIR_SUBVEND_0 0x2c
119 #define PCIR_SUBDEV_0 0x2e
120 #define PCIR_BIOS 0x30
121 #define PCIM_BIOS_ENABLE 0x01
122 #define PCIR_CAP_PTR 0x34
123 #define PCIR_INTLINE 0x3c
124 #define PCIR_INTPIN 0x3d
125 #define PCIR_MINGNT 0x3e
126 #define PCIR_MAXLAT 0x3f
128 /* config registers for header type 1 devices */
130 #define PCIR_SECSTAT_1 0x1e
132 #define PCIR_PRIBUS_1 0x18
133 #define PCIR_SECBUS_1 0x19
134 #define PCIR_SUBBUS_1 0x1a
135 #define PCIR_SECLAT_1 0x1b
137 #define PCIR_IOBASEL_1 0x1c
138 #define PCIR_IOLIMITL_1 0x1d
139 #define PCIR_IOBASEH_1 0x30
140 #define PCIR_IOLIMITH_1 0x32
141 #define PCIM_BRIO_16 0x0
142 #define PCIM_BRIO_32 0x1
143 #define PCIM_BRIO_MASK 0xf
145 #define PCIR_MEMBASE_1 0x20
146 #define PCIR_MEMLIMIT_1 0x22
148 #define PCIR_PMBASEL_1 0x24
149 #define PCIR_PMLIMITL_1 0x26
150 #define PCIR_PMBASEH_1 0x28
151 #define PCIR_PMLIMITH_1 0x2c
153 #define PCIR_BRIDGECTL_1 0x3e
155 #define PCIR_SUBVEND_1 0x34
156 #define PCIR_SUBDEV_1 0x36
158 /* config registers for header type 2 (Cardbus) devices */
160 #define PCIR_CAP_PTR_2 0x14
161 #define PCIR_SECSTAT_2 0x16
163 #define PCIR_PRIBUS_2 0x18
164 #define PCIR_SECBUS_2 0x19
165 #define PCIR_SUBBUS_2 0x1a
166 #define PCIR_SECLAT_2 0x1b
168 #define PCIR_MEMBASE0_2 0x1c
169 #define PCIR_MEMLIMIT0_2 0x20
170 #define PCIR_MEMBASE1_2 0x24
171 #define PCIR_MEMLIMIT1_2 0x28
172 #define PCIR_IOBASE0_2 0x2c
173 #define PCIR_IOLIMIT0_2 0x30
174 #define PCIR_IOBASE1_2 0x34
175 #define PCIR_IOLIMIT1_2 0x38
177 #define PCIR_BRIDGECTL_2 0x3e
179 #define PCIR_SUBVEND_2 0x40
180 #define PCIR_SUBDEV_2 0x42
182 #define PCIR_PCCARDIF_2 0x44
184 /* PCI device class, subclass and programming interface definitions */
186 #define PCIC_OLD 0x00
187 #define PCIS_OLD_NONVGA 0x00
188 #define PCIS_OLD_VGA 0x01
190 #define PCIC_STORAGE 0x01
191 #define PCIS_STORAGE_SCSI 0x00
192 #define PCIS_STORAGE_IDE 0x01
193 #define PCIP_STORAGE_IDE_MODEPRIM 0x01
194 #define PCIP_STORAGE_IDE_PROGINDPRIM 0x02
195 #define PCIP_STORAGE_IDE_MODESEC 0x04
196 #define PCIP_STORAGE_IDE_PROGINDSEC 0x08
197 #define PCIP_STORAGE_IDE_MASTERDEV 0x80
198 #define PCIS_STORAGE_FLOPPY 0x02
199 #define PCIS_STORAGE_IPI 0x03
200 #define PCIS_STORAGE_RAID 0x04
201 #define PCIS_STORAGE_ATA 0x05
202 #define PCIP_STORAGE_ATA_SINGLEDMA 0x20
203 #define PCIP_STORAGE_ATA_CHAINDMA 0x30
204 #define PCIS_STORAGE_SATA 0x06
205 #define PCIP_STORAGE_SATA_AHCI_1_0 0x01
206 #define PCIS_STORAGE_SAS 0x07
207 #define PCIP_STORAGE_SAS_VENDOR 0x00
208 #define PCIP_STORAGE_SAS_SSB 0x01
209 #define PCIS_STORAGE_OTHER 0x80
211 #define PCIC_NETWORK 0x02
212 #define PCIS_NETWORK_ETHERNET 0x00
213 #define PCIS_NETWORK_TOKENRING 0x01
214 #define PCIS_NETWORK_FDDI 0x02
215 #define PCIS_NETWORK_ATM 0x03
216 #define PCIS_NETWORK_ISDN 0x04
217 #define PCIS_NETWORK_WORLDFIP 0x05
218 #define PCIS_NETWORK_PICMG 0x06
219 #define PCIS_NETWORK_OTHER 0x80
221 #define PCIC_DISPLAY 0x03
222 #define PCIS_DISPLAY_VGA 0x00
223 #define PCIP_DISPLAY_VGA_COMP 0x00
224 #define PCIP_DISPLAY_VGA_8514 0x01
225 #define PCIS_DISPLAY_XGA 0x01
226 #define PCIS_DISPLAY_3D 0x02
227 #define PCIS_DISPLAY_OTHER 0x80
229 #define PCIC_MULTIMEDIA 0x04
230 #define PCIS_MULTIMEDIA_VIDEO 0x00
231 #define PCIS_MULTIMEDIA_AUDIO 0x01
232 #define PCIS_MULTIMEDIA_TEL 0x02
233 #define PCIS_MULTIMEDIA_OTHER 0x80
235 #define PCIC_MEMORY 0x05
236 #define PCIS_MEMORY_RAM 0x00
237 #define PCIS_MEMORY_FLASH 0x01
238 #define PCIS_MEMORY_OTHER 0x80
240 #define PCIC_BRIDGE 0x06
241 #define PCIS_BRIDGE_HOST 0x00
242 #define PCIS_BRIDGE_ISA 0x01
243 #define PCIS_BRIDGE_EISA 0x02
244 #define PCIS_BRIDGE_MCA 0x03
245 #define PCIS_BRIDGE_PCI 0x04
246 #define PCIS_BRIDGE_PCMCIA 0x05
247 #define PCIS_BRIDGE_NUBUS 0x06
248 #define PCIS_BRIDGE_CARDBUS 0x07
249 #define PCIS_BRIDGE_RACEWAY 0x08
250 #define PCIS_BRIDGE_SEMITRANS 0x09
251 #define PCIS_BRIDGE_INFINI 0x0a
252 #define PCIS_BRIDGE_OTHER 0x80
254 #define PCIC_SIMPLECOMM 0x07
255 #define PCIS_SIMPLECOMM_UART 0x00
256 #define PCIP_SIMPLECOMM_UART_16550A 0x02
257 #define PCIS_SIMPLECOMM_PAR 0x01
258 #define PCIS_SIMPLECOMM_MULTSER 0x02
259 #define PCIS_SIMPLECOMM_MODEM 0x03
260 #define PCIS_SIMPLECOMM_GPIB 0x04
261 #define PCIS_SIMPLECOMM_SMART 0x05
262 #define PCIS_SIMPLECOMM_OTHER 0x80
264 #define PCIC_BASEPERIPH 0x08
265 #define PCIS_BASEPERIPH_PIC 0x00
266 #define PCIS_BASEPERIPH_DMA 0x01
267 #define PCIS_BASEPERIPH_TIMER 0x02
268 #define PCIS_BASEPERIPH_RTC 0x03
269 #define PCIS_BASEPERIPH_HOTPLUG 0x04
270 #define PCIS_BASEPERIPH_OTHER 0x80
272 #define PCIC_INPUTDEV 0x09
273 #define PCIS_INPUTDEV_KEYBOARD 0x00
274 #define PCIS_INPUTDEV_DIGITIZER 0x01
275 #define PCIS_INPUTDEV_MOUSE 0x02
276 #define PCIS_INPUTDEV_SCANNER 0x03
277 #define PCIS_INPUTDEV_GAMEPORT 0x04
278 #define PCIS_INPUTDEV_OTHER 0x80
280 #define PCIC_DOCKING 0x0a
281 #define PCIS_DOCKING_GENERIC 0x00
282 #define PCIS_DOCKING_OTHER 0x80
284 #define PCIC_PROCESSOR 0x0b
285 #define PCIS_PROCESSOR_386 0x00
286 #define PCIS_PROCESSOR_486 0x01
287 #define PCIS_PROCESSOR_PENTIUM 0x02
288 #define PCIS_PROCESSOR_ALPHA 0x10
289 #define PCIS_PROCESSOR_POWERPC 0x20
290 #define PCIS_PROCESSOR_MIPS 0x30
291 #define PCIS_PROCESSOR_COPROC 0x40
293 #define PCIC_SERIALBUS 0x0c
294 #define PCIS_SERIALBUS_FW 0x00
295 #define PCIS_SERIALBUS_ACCESS 0x01
296 #define PCIS_SERIALBUS_SSA 0x02
297 #define PCIS_SERIALBUS_USB 0x03
298 #define PCIS_SERIALBUS_FC 0x04
299 #define PCIS_SERIALBUS_SMBUS 0x05
300 #define PCIS_SERIALBUS_INFINI 0x06
301 #define PCIS_SERIALBUS_IPMI 0x07
302 #define PCIS_SERIALBUS_SERCOS 0x08
303 #define PCIS_SERIALBUS_CANBUS 0x09
305 #define PCIC_WIRELESS 0x0d
306 #define PCIS_WIRELESS_IRDA 0x00
307 #define PCIS_WIRELESS_IR 0x01
308 #define PCIS_WIRELESS_RF 0x10
309 #define PCIS_WIRELESS_BLUETOOTH 0x11
310 #define PCIS_WIRELESS_BROADBAND 0x12
311 #define PCIS_WIRELESS_80211A 0x20
312 #define PCIS_WIRELESS_80211B 0x21
313 #define PCIS_WIRELESS_OTHER 0x80
315 #define PCIC_I2O 0x0e
316 #define PCIS_I2O_10 0x00
318 #define PCIC_SATELLITE 0x0f
319 #define PCIS_SATELLITE_TV 0x01
320 #define PCIS_SATELLITE_AUDIO 0x02
321 #define PCIS_SATELLITE_VOICE 0x03
322 #define PCIS_SATELLITE_DATA 0x04
324 #define PCIC_CRYPTO 0x10
325 #define PCIS_CRYPTO_NETWORK 0x00
326 #define PCIS_CRYPTO_ENTERTAIN 0x10
327 #define PCIS_CRYPTO_OTHER 0x80
329 #define PCIC_SIGPROC 0x11
330 #define PCIS_SIGPROC_DPIO 0x00
331 #define PCIS_SIGPROC_PERFCOUNT 0x01
332 #define PCIS_SIGPROC_COMMSYNC 0x10
333 #define PCIS_SIGPROC_MANAGEMENT 0x20
334 #define PCIS_SIGPROC_OTHER 0x80
336 #define PCIC_OTHER 0xff
338 /* PCI power manangement */
340 #define PCIR_POWER_CAP 0x2
341 #define PCIM_PCAP_SPEC 0x0007
342 #define PCIM_PCAP_PMEREQCLK 0x0008
343 #define PCIM_PCAP_PMEREQPWR 0x0010
344 #define PCIM_PCAP_DEVSPECINIT 0x0020
345 #define PCIM_PCAP_DYNCLOCK 0x0040
346 #define PCIM_PCAP_SECCLOCK 0x00c0
347 #define PCIM_PCAP_CLOCKMASK 0x00c0
348 #define PCIM_PCAP_REQFULLCLOCK 0x0100
349 #define PCIM_PCAP_D1SUPP 0x0200
350 #define PCIM_PCAP_D2SUPP 0x0400
351 #define PCIM_PCAP_D0PME 0x1000
352 #define PCIM_PCAP_D1PME 0x2000
353 #define PCIM_PCAP_D2PME 0x4000
355 #define PCIR_POWER_STATUS 0x4
356 #define PCIM_PSTAT_D0 0x0000
357 #define PCIM_PSTAT_D1 0x0001
358 #define PCIM_PSTAT_D2 0x0002
359 #define PCIM_PSTAT_D3 0x0003
360 #define PCIM_PSTAT_DMASK 0x0003
361 #define PCIM_PSTAT_REPENABLE 0x0010
362 #define PCIM_PSTAT_PMEENABLE 0x0100
363 #define PCIM_PSTAT_D0POWER 0x0000
364 #define PCIM_PSTAT_D1POWER 0x0200
365 #define PCIM_PSTAT_D2POWER 0x0400
366 #define PCIM_PSTAT_D3POWER 0x0600
367 #define PCIM_PSTAT_D0HEAT 0x0800
368 #define PCIM_PSTAT_D1HEAT 0x1000
369 #define PCIM_PSTAT_D2HEAT 0x1200
370 #define PCIM_PSTAT_D3HEAT 0x1400
371 #define PCIM_PSTAT_DATAUNKN 0x0000
372 #define PCIM_PSTAT_DATADIV10 0x2000
373 #define PCIM_PSTAT_DATADIV100 0x4000
374 #define PCIM_PSTAT_DATADIV1000 0x6000
375 #define PCIM_PSTAT_DATADIVMASK 0x6000
376 #define PCIM_PSTAT_PME 0x8000
378 #define PCIR_POWER_PMCSR 0x6
379 #define PCIM_PMCSR_DCLOCK 0x10
380 #define PCIM_PMCSR_B2SUPP 0x20
381 #define PCIM_BMCSR_B3SUPP 0x40
382 #define PCIM_BMCSR_BPCE 0x80
384 #define PCIR_POWER_DATA 0x7
386 /* PCI Message Signalled Interrupts (MSI) */
387 #define PCIR_MSI_CTRL 0x2
388 #define PCIM_MSICTRL_VECTOR 0x0100
389 #define PCIM_MSICTRL_64BIT 0x0080
390 #define PCIM_MSICTRL_MME_MASK 0x0070
391 #define PCIM_MSICTRL_MME_1 0x0000
392 #define PCIM_MSICTRL_MME_2 0x0010
393 #define PCIM_MSICTRL_MME_4 0x0020
394 #define PCIM_MSICTRL_MME_8 0x0030
395 #define PCIM_MSICTRL_MME_16 0x0040
396 #define PCIM_MSICTRL_MME_32 0x0050
397 #define PCIM_MSICTRL_MMC_MASK 0x000E
398 #define PCIM_MSICTRL_MMC_1 0x0000
399 #define PCIM_MSICTRL_MMC_2 0x0002
400 #define PCIM_MSICTRL_MMC_4 0x0004
401 #define PCIM_MSICTRL_MMC_8 0x0006
402 #define PCIM_MSICTRL_MMC_16 0x0008
403 #define PCIM_MSICTRL_MMC_32 0x000A
404 #define PCIM_MSICTRL_MSI_ENABLE 0x0001
405 #define PCIR_MSI_ADDR 0x4
406 #define PCIR_MSI_ADDR_HIGH 0x8
407 #define PCIR_MSI_DATA 0x8
408 #define PCIR_MSI_DATA_64BIT 0xc
409 #define PCIR_MSI_MASK 0x10
410 #define PCIR_MSI_PENDING 0x14
412 /* PCI-X definitions */
413 #define PCIXR_COMMAND 0x96
414 #define PCIXR_DEVADDR 0x98
415 #define PCIXM_DEVADDR_FNUM 0x0003 /* Function Number */
416 #define PCIXM_DEVADDR_DNUM 0x00F8 /* Device Number */
417 #define PCIXM_DEVADDR_BNUM 0xFF00 /* Bus Number */
418 #define PCIXR_STATUS 0x9A
419 #define PCIXM_STATUS_64BIT 0x0001 /* Active 64bit connection to device. */
420 #define PCIXM_STATUS_133CAP 0x0002 /* Device is 133MHz capable */
421 #define PCIXM_STATUS_SCDISC 0x0004 /* Split Completion Discarded */
422 #define PCIXM_STATUS_UNEXPSC 0x0008 /* Unexpected Split Completion */
423 #define PCIXM_STATUS_CMPLEXDEV 0x0010 /* Device Complexity (set == bridge) */
424 #define PCIXM_STATUS_MAXMRDBC 0x0060 /* Maximum Burst Read Count */
425 #define PCIXM_STATUS_MAXSPLITS 0x0380 /* Maximum Split Transactions */
426 #define PCIXM_STATUS_MAXCRDS 0x1C00 /* Maximum Cumulative Read Size */
427 #define PCIXM_STATUS_RCVDSCEM 0x2000 /* Received a Split Comp w/Error msg */
430 * PCI Express definitions
432 * PCI Express base specification, REV. 1.0a
435 /* PCI Express capabilities, 16bits */
436 #define PCIER_CAPABILITY 0x2
437 #define PCIEM_CAP_VER_MASK 0x000f /* Version */
438 #define PCIEM_CAP_VER_1 0x0001
439 #define PCIEM_CAP_PORT_TYPE 0x00f0 /* Port type mask */
440 #define PCIEM_CAP_SLOT_IMPL 0x0100 /* Slot implemented,
441 * valid only for root port and
442 * switch downstream port
444 /* PCI Express port types */
445 #define PCIE_END_POINT 0x0000 /* Endpoint device */
446 #define PCIE_LEG_END_POINT 0x0010 /* Legacy endpoint device */
447 #define PCIE_ROOT_PORT 0x0040 /* Root port */
448 #define PCIE_UP_STREAM_PORT 0x0050 /* Switch upstream port */
449 #define PCIE_DOWN_STREAM_PORT 0x0060 /* Switch downstream port */
450 #define PCIE_PCIE2PCI_BRIDGE 0x0070 /* PCI Express to PCI/PCI-X bridge */
451 #define PCIE_PCI2PCIE_BRIDGE 0x0080 /* PCI/PCI-X to PCI Express bridge */
453 /* PCI Express device control, 16bits */
454 #define PCIER_DEVCTRL 0x08
455 #define PCIEM_DEVCTL_MAX_READRQ_MASK 0x7000 /* Max read request size */
456 #define PCIEM_DEVCTL_MAX_READRQ_128 0x0000
457 #define PCIEM_DEVCTL_MAX_READRQ_256 0x1000
458 #define PCIEM_DEVCTL_MAX_READRQ_512 0x2000
459 #define PCIEM_DEVCTL_MAX_READRQ_1024 0x3000
460 #define PCIEM_DEVCTL_MAX_READRQ_2048 0x4000
461 #define PCIEM_DEVCTL_MAX_READRQ_4096 0x5000
463 /* PCI Express slot capabilities, 32bits */
464 #define PCIER_SLOTCAP 0x14
465 #define PCIEM_SLTCAP_ATTEN_BTN 0x00000001 /* Attention button present */
466 #define PCIEM_SLTCAP_PWR_CTRL 0x00000002 /* Power controller present */
467 #define PCIEM_SLTCAP_MRL_SNS 0x00000004 /* MRL sensor present */
468 #define PCIEM_SLTCAP_ATTEN_IND 0x00000008 /* Attention indicator present */
469 #define PCIEM_SLTCAP_PWR_IND 0x00000010 /* Power indicator present */
470 #define PCIEM_SLTCAP_HP_SURP 0x00000020 /* Hot-Plug surprise */
471 #define PCIEM_SLTCAP_HP_CAP 0x00000040 /* Hot-Plug capable */
472 #define PCIEM_SLTCAP_HP_MASK 0x0000007f /* Hot-Plug related bits */
474 /* PCI Express slot control, 16bits */
475 #define PCIER_SLOTCTRL 0x18
476 #define PCIEM_SLTCTL_HPINTR_MASK 0x001f /* Hot-plug interrupts mask */
477 #define PCIEM_SLTCTL_HPINTR_EN 0x0020 /* Enable hot-plug interrupts */
478 /* PCI Expres hot-plug interrupts */
479 #define PCIE_HPINTR_ATTEN_BTN 0x0001 /* Attention button intr */
480 #define PCIE_HPINTR_PWR_FAULT 0x0002 /* Power fault intr */
481 #define PCIE_HPINTR_MRL_SNS 0x0004 /* MRL sensor changed intr */
482 #define PCIE_HPINTR_PRSN_DETECT 0x0008 /* Presence detect intr */
483 #define PCIE_HPINTR_CMD_COMPL 0x0010 /* Command completed intr */
485 /* for compatibility to FreeBSD-2.2 and 3.x versions of PCI code */
487 #if defined(_KERNEL) && !defined(KLD_MODULE)
488 #include "opt_compat_oldpci.h"
493 #define PCI_ID_REG 0x00
494 #define PCI_COMMAND_STATUS_REG 0x04
495 #define PCI_COMMAND_IO_ENABLE 0x00000001
496 #define PCI_COMMAND_MEM_ENABLE 0x00000002
497 #define PCI_CLASS_REG 0x08
498 #define PCI_CLASS_MASK 0xff000000
499 #define PCI_SUBCLASS_MASK 0x00ff0000
500 #define PCI_REVISION_MASK 0x000000ff
501 #define PCI_CLASS_PREHISTORIC 0x00000000
502 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x00010000
503 #define PCI_CLASS_MASS_STORAGE 0x01000000
504 #define PCI_CLASS_DISPLAY 0x03000000
505 #define PCI_SUBCLASS_DISPLAY_VGA 0x00000000
506 #define PCI_CLASS_BRIDGE 0x06000000
507 #define PCI_MAP_REG_START 0x10
508 #define PCI_MAP_REG_END 0x28
509 #define PCI_MAP_IO 0x00000001
510 #define PCI_INTERRUPT_REG 0x3c
512 #endif /* COMPAT_OLDPCI */