3 * Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 1997, 1998-2003
6 * Bill Paul <wpaul@windriver.com>. All rights reserved.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Bill Paul.
19 * 4. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33 * THE POSSIBILITY OF SUCH DAMAGE.
35 * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
36 * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $
40 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
64 * o TCP/IP checksum offload for both RX and TX
66 * o High and normal priority transmit DMA rings
68 * o VLAN tag insertion and extraction
70 * o TCP large send (segmentation offload)
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
85 * o GMII and TBI ports/registers for interfacing with copper
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
91 * o Slight differences in register layout from the 8139C+
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7440, so the max MTU possible with this
111 * driver is 7422 bytes.
116 #include "opt_polling.h"
118 #include <sys/param.h>
120 #include <sys/endian.h>
121 #include <sys/kernel.h>
122 #include <sys/in_cksum.h>
123 #include <sys/interrupt.h>
124 #include <sys/malloc.h>
125 #include <sys/mbuf.h>
126 #include <sys/rman.h>
127 #include <sys/serialize.h>
128 #include <sys/socket.h>
129 #include <sys/sockio.h>
130 #include <sys/sysctl.h>
133 #include <net/ethernet.h>
135 #include <net/ifq_var.h>
136 #include <net/if_arp.h>
137 #include <net/if_dl.h>
138 #include <net/if_media.h>
139 #include <net/if_types.h>
140 #include <net/vlan/if_vlan_var.h>
141 #include <net/vlan/if_vlan_ether.h>
143 #include <netinet/ip.h>
145 #include <dev/netif/mii_layer/mii.h>
146 #include <dev/netif/mii_layer/miivar.h>
148 #include <bus/pci/pcidevs.h>
149 #include <bus/pci/pcireg.h>
150 #include <bus/pci/pcivar.h>
152 /* "device miibus" required. See GENERIC if you get errors here. */
153 #include "miibus_if.h"
155 #include <dev/netif/re/if_rereg.h>
156 #include <dev/netif/re/if_revar.h>
158 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * Various supported device vendors/types and their names.
163 static const struct re_type {
168 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
172 "RealTek 8139C+ 10/100BaseTX" },
174 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
175 "RealTek 810x PCIe 10/100baseTX" },
177 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
178 "RealTek 8111/8168 PCIe Gigabit Ethernet" },
180 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
181 "RealTek 8110/8169 Gigabit Ethernet" },
183 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
186 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
187 "Corega CG-LAPCIGT Gigabit Ethernet" },
189 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
190 "Linksys EG1032 Gigabit Ethernet" },
192 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
193 "US Robotics 997902 Gigabit Ethernet" },
195 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
196 "TTTech MC322 Gigabit Ethernet" },
201 static const struct re_hwrev re_hwrevs[] = {
202 { RE_HWREV_8139CPLUS, RE_MACVER_UNKN, ETHERMTU,
203 RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
205 { RE_HWREV_8169, RE_MACVER_UNKN, ETHERMTU,
206 RE_C_HWCSUM | RE_C_8169 },
208 { RE_HWREV_8110S, RE_MACVER_03, RE_MTU_6K,
209 RE_C_HWCSUM | RE_C_8169 },
211 { RE_HWREV_8169S, RE_MACVER_03, RE_MTU_6K,
212 RE_C_HWCSUM | RE_C_8169 },
214 { RE_HWREV_8169SB, RE_MACVER_04, RE_MTU_6K,
215 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
217 { RE_HWREV_8169SC1, RE_MACVER_05, RE_MTU_6K,
218 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
220 { RE_HWREV_8169SC2, RE_MACVER_06, RE_MTU_6K,
221 RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
223 { RE_HWREV_8168B1, RE_MACVER_21, RE_MTU_6K,
224 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
226 { RE_HWREV_8168B2, RE_MACVER_23, RE_MTU_6K,
227 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
229 { RE_HWREV_8168B3, RE_MACVER_23, RE_MTU_6K,
230 RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
232 { RE_HWREV_8168C, RE_MACVER_29, RE_MTU_6K,
233 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
234 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
236 { RE_HWREV_8168CP, RE_MACVER_2B, RE_MTU_6K,
237 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
238 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
240 { RE_HWREV_8168D, RE_MACVER_2A, RE_MTU_9K,
241 RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
242 RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
244 { RE_HWREV_8100E, RE_MACVER_UNKN, ETHERMTU,
245 RE_C_HWCSUM | RE_C_FASTE },
247 { RE_HWREV_8101E1, RE_MACVER_16, ETHERMTU,
248 RE_C_HWCSUM | RE_C_FASTE },
250 { RE_HWREV_8101E2, RE_MACVER_16, ETHERMTU,
251 RE_C_HWCSUM | RE_C_FASTE },
253 { RE_HWREV_8102E, RE_MACVER_15, ETHERMTU,
254 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
257 { RE_HWREV_8102EL, RE_MACVER_15, ETHERMTU,
258 RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
261 { RE_HWREV_NULL, 0, 0, 0 }
264 static int re_probe(device_t);
265 static int re_attach(device_t);
266 static int re_detach(device_t);
267 static int re_suspend(device_t);
268 static int re_resume(device_t);
269 static void re_shutdown(device_t);
271 static void re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
272 static void re_dma_map_desc(void *, bus_dma_segment_t *, int,
274 static int re_allocmem(device_t);
275 static void re_freemem(device_t);
276 static void re_freebufmem(struct re_softc *, int, int);
277 static int re_encap(struct re_softc *, struct mbuf **, int *);
278 static int re_newbuf_std(struct re_softc *, int, int);
279 static int re_newbuf_jumbo(struct re_softc *, int, int);
280 static void re_setup_rxdesc(struct re_softc *, int);
281 static int re_rx_list_init(struct re_softc *);
282 static int re_tx_list_init(struct re_softc *);
283 static int re_rxeof(struct re_softc *);
284 static int re_txeof(struct re_softc *);
285 static int re_tx_collect(struct re_softc *);
286 static void re_intr(void *);
287 static void re_tick(void *);
288 static void re_tick_serialized(void *);
290 static void re_start(struct ifnet *);
291 static int re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
292 static void re_init(void *);
293 static void re_stop(struct re_softc *);
294 static void re_watchdog(struct ifnet *);
295 static int re_ifmedia_upd(struct ifnet *);
296 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
298 static void re_eeprom_putbyte(struct re_softc *, int);
299 static void re_eeprom_getword(struct re_softc *, int, u_int16_t *);
300 static void re_read_eeprom(struct re_softc *, caddr_t, int, int);
301 static void re_get_eewidth(struct re_softc *);
303 static int re_gmii_readreg(device_t, int, int);
304 static int re_gmii_writereg(device_t, int, int, int);
306 static int re_miibus_readreg(device_t, int, int);
307 static int re_miibus_writereg(device_t, int, int, int);
308 static void re_miibus_statchg(device_t);
310 static void re_setmulti(struct re_softc *);
311 static void re_reset(struct re_softc *, int);
312 static void re_get_eaddr(struct re_softc *, uint8_t *);
314 static void re_setup_hw_im(struct re_softc *);
315 static void re_setup_sim_im(struct re_softc *);
316 static void re_disable_hw_im(struct re_softc *);
317 static void re_disable_sim_im(struct re_softc *);
318 static void re_config_imtype(struct re_softc *, int);
319 static void re_setup_intr(struct re_softc *, int, int);
321 static int re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
322 static int re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
323 static int re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
324 static int re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
325 static int re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
327 static int re_jpool_alloc(struct re_softc *);
328 static void re_jpool_free(struct re_softc *);
329 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
330 static void re_jbuf_free(void *);
331 static void re_jbuf_ref(void *);
334 static int re_diag(struct re_softc *);
337 #ifdef DEVICE_POLLING
338 static void re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
341 static device_method_t re_methods[] = {
342 /* Device interface */
343 DEVMETHOD(device_probe, re_probe),
344 DEVMETHOD(device_attach, re_attach),
345 DEVMETHOD(device_detach, re_detach),
346 DEVMETHOD(device_suspend, re_suspend),
347 DEVMETHOD(device_resume, re_resume),
348 DEVMETHOD(device_shutdown, re_shutdown),
351 DEVMETHOD(bus_print_child, bus_generic_print_child),
352 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
355 DEVMETHOD(miibus_readreg, re_miibus_readreg),
356 DEVMETHOD(miibus_writereg, re_miibus_writereg),
357 DEVMETHOD(miibus_statchg, re_miibus_statchg),
362 static driver_t re_driver = {
365 sizeof(struct re_softc)
368 static devclass_t re_devclass;
370 DECLARE_DUMMY_MODULE(if_re);
371 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
372 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
373 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
375 static int re_rx_desc_count = RE_RX_DESC_CNT_DEF;
376 static int re_tx_desc_count = RE_TX_DESC_CNT_DEF;
378 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
379 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
382 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
385 CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
388 re_free_rxchain(struct re_softc *sc)
390 if (sc->re_head != NULL) {
391 m_freem(sc->re_head);
392 sc->re_head = sc->re_tail = NULL;
397 * Send a read command and address to the EEPROM, check for ACK.
400 re_eeprom_putbyte(struct re_softc *sc, int addr)
404 d = addr | (RE_9346_READ << sc->re_eewidth);
407 * Feed in each bit and strobe the clock.
409 for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
411 EE_SET(RE_EE_DATAIN);
413 EE_CLR(RE_EE_DATAIN);
423 * Read a word of data stored in the EEPROM at address 'addr.'
426 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
432 * Send address of word we want to read.
434 re_eeprom_putbyte(sc, addr);
437 * Start reading bits from EEPROM.
439 for (i = 0x8000; i != 0; i >>= 1) {
442 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
452 * Read a sequence of words from the EEPROM.
455 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
458 uint16_t word = 0, *ptr;
460 CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
463 for (i = 0; i < cnt; i++) {
464 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
465 re_eeprom_getword(sc, off + i, &word);
466 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
467 ptr = (uint16_t *)(dest + (i * 2));
471 CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
475 re_get_eewidth(struct re_softc *sc)
480 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
481 if (re_did != 0x8129)
486 re_gmii_readreg(device_t dev, int phy, int reg)
488 struct re_softc *sc = device_get_softc(dev);
495 /* Let the rgephy driver read the GMEDIASTAT register */
497 if (reg == RE_GMEDIASTAT)
498 return(CSR_READ_1(sc, RE_GMEDIASTAT));
500 CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
503 for (i = 0; i < RE_TIMEOUT; i++) {
504 rval = CSR_READ_4(sc, RE_PHYAR);
505 if (rval & RE_PHYAR_BUSY)
510 if (i == RE_TIMEOUT) {
511 device_printf(dev, "PHY read failed\n");
515 return(rval & RE_PHYAR_PHYDATA);
519 re_gmii_writereg(device_t dev, int phy, int reg, int data)
521 struct re_softc *sc = device_get_softc(dev);
525 CSR_WRITE_4(sc, RE_PHYAR,
526 (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
529 for (i = 0; i < RE_TIMEOUT; i++) {
530 rval = CSR_READ_4(sc, RE_PHYAR);
531 if ((rval & RE_PHYAR_BUSY) == 0)
537 device_printf(dev, "PHY write failed\n");
543 re_miibus_readreg(device_t dev, int phy, int reg)
545 struct re_softc *sc = device_get_softc(dev);
547 uint16_t re8139_reg = 0;
549 if (!RE_IS_8139CP(sc)) {
550 rval = re_gmii_readreg(dev, phy, reg);
554 /* Pretend the internal PHY is only at address 0 */
560 re8139_reg = RE_BMCR;
563 re8139_reg = RE_BMSR;
566 re8139_reg = RE_ANAR;
569 re8139_reg = RE_ANER;
572 re8139_reg = RE_LPAR;
578 * Allow the rlphy driver to read the media status
579 * register. If we have a link partner which does not
580 * support NWAY, this is the register which will tell
581 * us the results of parallel detection.
584 return(CSR_READ_1(sc, RE_MEDIASTAT));
586 device_printf(dev, "bad phy register\n");
589 rval = CSR_READ_2(sc, re8139_reg);
590 if (re8139_reg == RE_BMCR) {
591 /* 8139C+ has different bit layout. */
592 rval &= ~(BMCR_LOOP | BMCR_ISO);
598 re_miibus_writereg(device_t dev, int phy, int reg, int data)
600 struct re_softc *sc= device_get_softc(dev);
601 u_int16_t re8139_reg = 0;
603 if (!RE_IS_8139CP(sc))
604 return(re_gmii_writereg(dev, phy, reg, data));
606 /* Pretend the internal PHY is only at address 0 */
612 re8139_reg = RE_BMCR;
613 /* 8139C+ has different bit layout. */
614 data &= ~(BMCR_LOOP | BMCR_ISO);
617 re8139_reg = RE_BMSR;
620 re8139_reg = RE_ANAR;
623 re8139_reg = RE_ANER;
626 re8139_reg = RE_LPAR;
632 device_printf(dev, "bad phy register\n");
635 CSR_WRITE_2(sc, re8139_reg, data);
640 re_miibus_statchg(device_t dev)
645 * Program the 64-bit multicast hash filter.
648 re_setmulti(struct re_softc *sc)
650 struct ifnet *ifp = &sc->arpcom.ac_if;
652 uint32_t hashes[2] = { 0, 0 };
653 struct ifmultiaddr *ifma;
657 rxfilt = CSR_READ_4(sc, RE_RXCFG);
659 /* Set the individual bit to receive frames for this host only. */
660 rxfilt |= RE_RXCFG_RX_INDIV;
661 /* Set capture broadcast bit to capture broadcast frames. */
662 rxfilt |= RE_RXCFG_RX_BROAD;
664 rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
665 if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
666 rxfilt |= RE_RXCFG_RX_MULTI;
668 /* If we want promiscuous mode, set the allframes bit. */
669 if (ifp->if_flags & IFF_PROMISC)
670 rxfilt |= RE_RXCFG_RX_ALLPHYS;
672 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
673 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
674 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
678 /* first, zot all the existing hash bits */
679 CSR_WRITE_4(sc, RE_MAR0, 0);
680 CSR_WRITE_4(sc, RE_MAR4, 0);
682 /* now program new ones */
683 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
684 if (ifma->ifma_addr->sa_family != AF_LINK)
686 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
687 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
689 hashes[0] |= (1 << h);
691 hashes[1] |= (1 << (h - 32));
696 rxfilt |= RE_RXCFG_RX_MULTI;
698 rxfilt &= ~RE_RXCFG_RX_MULTI;
700 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
703 * For some unfathomable reason, RealTek decided to reverse
704 * the order of the multicast hash registers in the PCI Express
705 * parts. This means we have to write the hash pattern in reverse
706 * order for those devices.
708 if (sc->re_caps & RE_C_PCIE) {
709 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
710 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
712 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
713 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
718 re_reset(struct re_softc *sc, int running)
722 if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
723 CSR_WRITE_1(sc, RE_COMMAND,
724 RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
728 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
730 for (i = 0; i < RE_TIMEOUT; i++) {
732 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
736 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
741 * The following routine is designed to test for a defect on some
742 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
743 * lines connected to the bus, however for a 32-bit only card, they
744 * should be pulled high. The result of this defect is that the
745 * NIC will not work right if you plug it into a 64-bit slot: DMA
746 * operations will be done with 64-bit transfers, which will fail
747 * because the 64-bit data lines aren't connected.
749 * There's no way to work around this (short of talking a soldering
750 * iron to the board), however we can detect it. The method we use
751 * here is to put the NIC into digital loopback mode, set the receiver
752 * to promiscuous mode, and then try to send a frame. We then compare
753 * the frame data we sent to what was received. If the data matches,
754 * then the NIC is working correctly, otherwise we know the user has
755 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
756 * slot. In the latter case, there's no way the NIC can work correctly,
757 * so we print out a message on the console and abort the device attach.
761 re_diag(struct re_softc *sc)
763 struct ifnet *ifp = &sc->arpcom.ac_if;
765 struct ether_header *eh;
766 struct re_desc *cur_rx;
769 int total_len, i, error = 0, phyaddr;
770 uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
771 uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
773 /* Allocate a single mbuf */
775 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
780 * Initialize the NIC in test mode. This sets the chip up
781 * so that it can send and receive frames, but performs the
782 * following special functions:
783 * - Puts receiver in promiscuous mode
784 * - Enables digital loopback mode
785 * - Leaves interrupts turned off
788 ifp->if_flags |= IFF_PROMISC;
789 sc->re_flags |= RE_F_TESTMODE;
791 sc->re_flags |= RE_F_LINKED;
792 if (!RE_IS_8139CP(sc))
797 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
798 for (i = 0; i < RE_TIMEOUT; i++) {
799 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
800 if (!(status & BMCR_RESET))
804 re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
805 CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
809 /* Put some data in the mbuf */
811 eh = mtod(m0, struct ether_header *);
812 bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
813 bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
814 eh->ether_type = htons(ETHERTYPE_IP);
815 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
818 * Queue the packet, start transmission.
819 * Note: ifq_handoff() ultimately calls re_start() for us.
822 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
823 error = ifq_handoff(ifp, m0, NULL);
830 /* Wait for it to propagate through the chip */
833 for (i = 0; i < RE_TIMEOUT; i++) {
834 status = CSR_READ_2(sc, RE_ISR);
835 CSR_WRITE_2(sc, RE_ISR, status);
836 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
837 (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
842 if (i == RE_TIMEOUT) {
843 if_printf(ifp, "diagnostic failed to receive packet "
844 "in loopback mode\n");
850 * The packet should have been dumped into the first
851 * entry in the RX DMA ring. Grab it from there.
854 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
855 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
856 bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
857 BUS_DMASYNC_POSTWRITE);
858 bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
860 m0 = sc->re_ldata.re_rx_mbuf[0];
861 sc->re_ldata.re_rx_mbuf[0] = NULL;
862 eh = mtod(m0, struct ether_header *);
864 cur_rx = &sc->re_ldata.re_rx_list[0];
865 total_len = RE_RXBYTES(cur_rx);
866 rxstat = le32toh(cur_rx->re_cmdstat);
868 if (total_len != ETHER_MIN_LEN) {
869 if_printf(ifp, "diagnostic failed, received short packet\n");
874 /* Test that the received packet data matches what we sent. */
876 if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
877 bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
878 be16toh(eh->ether_type) != ETHERTYPE_IP) {
879 if_printf(ifp, "WARNING, DMA FAILURE!\n");
880 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
881 dst, ":", src, ":", ETHERTYPE_IP);
882 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
883 eh->ether_dhost, ":", eh->ether_shost, ":",
884 ntohs(eh->ether_type));
885 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
886 "into a 64-bit PCI slot.\n");
887 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
888 "for proper operation.\n");
889 if_printf(ifp, "Read the re(4) man page for more details.\n");
894 /* Turn interface off, release resources */
896 sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
897 ifp->if_flags &= ~IFF_PROMISC;
907 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
908 * IDs against our list and return a device name if we find a match.
911 re_probe(device_t dev)
913 const struct re_type *t;
914 const struct re_hwrev *hw_rev;
917 uint32_t hwrev, macmode, txcfg;
918 uint16_t vendor, product;
920 vendor = pci_get_vendor(dev);
921 product = pci_get_device(dev);
924 * Only attach to rev.3 of the Linksys EG1032 adapter.
925 * Rev.2 is supported by sk(4).
927 if (vendor == PCI_VENDOR_LINKSYS &&
928 product == PCI_PRODUCT_LINKSYS_EG1032 &&
929 pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
932 if (vendor == PCI_VENDOR_REALTEK &&
933 product == PCI_PRODUCT_REALTEK_RT8139 &&
934 pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
939 for (t = re_devs; t->re_name != NULL; t++) {
940 if (product == t->re_did && vendor == t->re_vid)
945 * Check if we found a RealTek device.
947 if (t->re_name == NULL)
951 * Temporarily map the I/O space so we can read the chip ID register.
953 sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
955 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
957 if (sc->re_res == NULL) {
958 device_printf(dev, "couldn't map ports/memory\n");
963 sc->re_btag = rman_get_bustag(sc->re_res);
964 sc->re_bhandle = rman_get_bushandle(sc->re_res);
966 txcfg = CSR_READ_4(sc, RE_TXCFG);
967 hwrev = txcfg & RE_TXCFG_HWREV;
968 macmode = txcfg & RE_TXCFG_MACMODE;
969 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
973 * and continue matching for the specific chip...
975 for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
976 if (hw_rev->re_hwrev == hwrev) {
977 sc = device_get_softc(dev);
979 sc->re_hwrev = hw_rev->re_hwrev;
980 sc->re_macver = hw_rev->re_macver;
981 sc->re_caps = hw_rev->re_caps;
982 sc->re_maxmtu = hw_rev->re_maxmtu;
985 * Apply chip property fixup
987 switch (sc->re_hwrev) {
988 case RE_HWREV_8101E1:
989 case RE_HWREV_8101E2:
991 sc->re_macver = RE_MACVER_11;
992 else if (macmode == 0x200000)
993 sc->re_macver = RE_MACVER_12;
996 case RE_HWREV_8102EL:
998 sc->re_macver = RE_MACVER_13;
999 else if (macmode == 0x100000)
1000 sc->re_macver = RE_MACVER_14;
1002 case RE_HWREV_8168B2:
1003 case RE_HWREV_8168B3:
1005 sc->re_macver = RE_MACVER_22;
1007 case RE_HWREV_8168C:
1009 sc->re_macver = RE_MACVER_24;
1010 else if (macmode == 0x200000)
1011 sc->re_macver = RE_MACVER_25;
1012 else if (macmode == 0x300000)
1013 sc->re_macver = RE_MACVER_27;
1015 case RE_HWREV_8168CP:
1017 sc->re_macver = RE_MACVER_26;
1018 else if (macmode == 0x100000)
1019 sc->re_macver = RE_MACVER_28;
1022 if (pci_is_pcie(dev))
1023 sc->re_caps |= RE_C_PCIE;
1025 device_set_desc(dev, t->re_name);
1031 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1038 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs,
1039 bus_size_t mapsize, int error)
1041 struct re_dmaload_arg *arg = xarg;
1047 if (nsegs > arg->re_nsegs) {
1052 arg->re_nsegs = nsegs;
1053 for (i = 0; i < nsegs; ++i)
1054 arg->re_segs[i] = segs[i];
1058 * Map a single buffer address.
1062 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1069 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1071 *addr = segs->ds_addr;
1075 re_allocmem(device_t dev)
1077 struct re_softc *sc = device_get_softc(dev);
1081 * Allocate list data
1083 sc->re_ldata.re_tx_mbuf =
1084 kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1085 M_DEVBUF, M_ZERO | M_WAITOK);
1087 sc->re_ldata.re_rx_mbuf =
1088 kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1089 M_DEVBUF, M_ZERO | M_WAITOK);
1091 sc->re_ldata.re_rx_paddr =
1092 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1093 M_DEVBUF, M_ZERO | M_WAITOK);
1095 sc->re_ldata.re_tx_dmamap =
1096 kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1097 M_DEVBUF, M_ZERO | M_WAITOK);
1099 sc->re_ldata.re_rx_dmamap =
1100 kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1101 M_DEVBUF, M_ZERO | M_WAITOK);
1104 * Allocate the parent bus DMA tag appropriate for PCI.
1106 error = bus_dma_tag_create(NULL, /* parent */
1107 1, 0, /* alignment, boundary */
1108 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1109 BUS_SPACE_MAXADDR, /* highaddr */
1110 NULL, NULL, /* filter, filterarg */
1111 MAXBSIZE, RE_MAXSEGS, /* maxsize, nsegments */
1112 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1113 BUS_DMA_ALLOCNOW, /* flags */
1114 &sc->re_parent_tag);
1116 device_printf(dev, "could not allocate parent dma tag\n");
1120 /* Allocate tag for TX descriptor list. */
1121 error = bus_dma_tag_create(sc->re_parent_tag,
1123 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1125 RE_TX_LIST_SZ(sc), 1, RE_TX_LIST_SZ(sc),
1127 &sc->re_ldata.re_tx_list_tag);
1129 device_printf(dev, "could not allocate TX ring dma tag\n");
1133 /* Allocate DMA'able memory for the TX ring */
1134 error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
1135 (void **)&sc->re_ldata.re_tx_list,
1136 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1137 &sc->re_ldata.re_tx_list_map);
1139 device_printf(dev, "could not allocate TX ring\n");
1140 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1141 sc->re_ldata.re_tx_list_tag = NULL;
1145 /* Load the map for the TX ring. */
1146 error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
1147 sc->re_ldata.re_tx_list_map,
1148 sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc),
1149 re_dma_map_addr, &sc->re_ldata.re_tx_list_addr,
1152 device_printf(dev, "could not get address of TX ring\n");
1153 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1154 sc->re_ldata.re_tx_list,
1155 sc->re_ldata.re_tx_list_map);
1156 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1157 sc->re_ldata.re_tx_list_tag = NULL;
1161 /* Allocate tag for RX descriptor list. */
1162 error = bus_dma_tag_create(sc->re_parent_tag,
1164 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1166 RE_RX_LIST_SZ(sc), 1, RE_RX_LIST_SZ(sc),
1168 &sc->re_ldata.re_rx_list_tag);
1170 device_printf(dev, "could not allocate RX ring dma tag\n");
1174 /* Allocate DMA'able memory for the RX ring */
1175 error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1176 (void **)&sc->re_ldata.re_rx_list,
1177 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1178 &sc->re_ldata.re_rx_list_map);
1180 device_printf(dev, "could not allocate RX ring\n");
1181 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1182 sc->re_ldata.re_rx_list_tag = NULL;
1186 /* Load the map for the RX ring. */
1187 error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1188 sc->re_ldata.re_rx_list_map,
1189 sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc),
1190 re_dma_map_addr, &sc->re_ldata.re_rx_list_addr,
1193 device_printf(dev, "could not get address of RX ring\n");
1194 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1195 sc->re_ldata.re_rx_list,
1196 sc->re_ldata.re_rx_list_map);
1197 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1198 sc->re_ldata.re_rx_list_tag = NULL;
1202 /* Allocate map for RX/TX mbufs. */
1203 error = bus_dma_tag_create(sc->re_parent_tag,
1205 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1207 RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1209 &sc->re_ldata.re_mtag);
1211 device_printf(dev, "could not allocate buf dma tag\n");
1215 /* Create spare DMA map for RX */
1216 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1217 &sc->re_ldata.re_rx_spare);
1219 device_printf(dev, "can't create spare DMA map for RX\n");
1220 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1221 sc->re_ldata.re_mtag = NULL;
1225 /* Create DMA maps for TX buffers */
1226 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1227 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1228 &sc->re_ldata.re_tx_dmamap[i]);
1230 device_printf(dev, "can't create DMA map for TX buf\n");
1231 re_freebufmem(sc, i, 0);
1236 /* Create DMA maps for RX buffers */
1237 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1238 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1239 &sc->re_ldata.re_rx_dmamap[i]);
1241 device_printf(dev, "can't create DMA map for RX buf\n");
1242 re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1247 /* Create jumbo buffer pool for RX if required */
1248 if (sc->re_caps & RE_C_CONTIGRX) {
1249 error = re_jpool_alloc(sc);
1252 /* Disable jumbo frame support */
1253 sc->re_maxmtu = ETHERMTU;
1260 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1264 /* Destroy all the RX and TX buffer maps */
1265 if (sc->re_ldata.re_mtag) {
1266 for (i = 0; i < tx_cnt; i++) {
1267 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1268 sc->re_ldata.re_tx_dmamap[i]);
1270 for (i = 0; i < rx_cnt; i++) {
1271 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1272 sc->re_ldata.re_rx_dmamap[i]);
1274 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1275 sc->re_ldata.re_rx_spare);
1276 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1277 sc->re_ldata.re_mtag = NULL;
1282 re_freemem(device_t dev)
1284 struct re_softc *sc = device_get_softc(dev);
1286 /* Unload and free the RX DMA ring memory and map */
1287 if (sc->re_ldata.re_rx_list_tag) {
1288 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1289 sc->re_ldata.re_rx_list_map);
1290 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1291 sc->re_ldata.re_rx_list,
1292 sc->re_ldata.re_rx_list_map);
1293 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1296 /* Unload and free the TX DMA ring memory and map */
1297 if (sc->re_ldata.re_tx_list_tag) {
1298 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1299 sc->re_ldata.re_tx_list_map);
1300 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1301 sc->re_ldata.re_tx_list,
1302 sc->re_ldata.re_tx_list_map);
1303 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1306 /* Free RX/TX buf DMA stuffs */
1307 re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1309 /* Unload and free the stats buffer and map */
1310 if (sc->re_ldata.re_stag) {
1311 bus_dmamap_unload(sc->re_ldata.re_stag,
1312 sc->re_ldata.re_rx_list_map);
1313 bus_dmamem_free(sc->re_ldata.re_stag,
1314 sc->re_ldata.re_stats,
1315 sc->re_ldata.re_smap);
1316 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1319 if (sc->re_caps & RE_C_CONTIGRX)
1322 if (sc->re_parent_tag)
1323 bus_dma_tag_destroy(sc->re_parent_tag);
1325 if (sc->re_ldata.re_tx_mbuf != NULL)
1326 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1327 if (sc->re_ldata.re_rx_mbuf != NULL)
1328 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1329 if (sc->re_ldata.re_rx_paddr != NULL)
1330 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1331 if (sc->re_ldata.re_tx_dmamap != NULL)
1332 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1333 if (sc->re_ldata.re_rx_dmamap != NULL)
1334 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1338 * Attach the interface. Allocate softc structures, do ifmedia
1339 * setup and ethernet/BPF attach.
1342 re_attach(device_t dev)
1344 struct re_softc *sc = device_get_softc(dev);
1346 uint8_t eaddr[ETHER_ADDR_LEN];
1347 int error = 0, rid, qlen;
1349 callout_init(&sc->re_timer);
1352 if (RE_IS_8139CP(sc)) {
1353 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1354 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1356 sc->re_rx_desc_cnt = re_rx_desc_count;
1357 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1358 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1360 sc->re_tx_desc_cnt = re_tx_desc_count;
1361 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1362 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1365 qlen = RE_IFQ_MAXLEN;
1366 if (sc->re_tx_desc_cnt > qlen)
1367 qlen = sc->re_tx_desc_cnt;
1369 sc->re_rxbuf_size = MCLBYTES;
1370 sc->re_newbuf = re_newbuf_std;
1372 sc->re_tx_time = 5; /* 125us */
1373 sc->re_rx_time = 2; /* 50us */
1374 if (sc->re_caps & RE_C_PCIE)
1375 sc->re_sim_time = 75; /* 75us */
1377 sc->re_sim_time = 125; /* 125us */
1378 if (!RE_IS_8139CP(sc)) {
1379 /* simulated interrupt moderation */
1380 sc->re_imtype = RE_IMTYPE_SIM;
1382 sc->re_imtype = RE_IMTYPE_NONE;
1384 re_config_imtype(sc, sc->re_imtype);
1386 sysctl_ctx_init(&sc->re_sysctl_ctx);
1387 sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1388 SYSCTL_STATIC_CHILDREN(_hw),
1390 device_get_nameunit(dev),
1392 if (sc->re_sysctl_tree == NULL) {
1393 device_printf(dev, "can't add sysctl node\n");
1397 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1398 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1399 "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1400 0, "RX desc count");
1401 SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1402 SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1403 "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1404 0, "TX desc count");
1405 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1406 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1407 OID_AUTO, "sim_time",
1408 CTLTYPE_INT | CTLFLAG_RW,
1409 sc, 0, re_sysctl_simtime, "I",
1410 "Simulated interrupt moderation time (usec).");
1411 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1412 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1414 CTLTYPE_INT | CTLFLAG_RW,
1415 sc, 0, re_sysctl_imtype, "I",
1416 "Interrupt moderation type -- "
1417 "0:disable, 1:simulated, "
1418 "2:hardware(if supported)");
1419 if (sc->re_caps & RE_C_HWIM) {
1420 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1421 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1422 OID_AUTO, "hw_rxtime",
1423 CTLTYPE_INT | CTLFLAG_RW,
1424 sc, 0, re_sysctl_rxtime, "I",
1425 "Hardware interrupt moderation time "
1427 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1428 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1429 OID_AUTO, "hw_txtime",
1430 CTLTYPE_INT | CTLFLAG_RW,
1431 sc, 0, re_sysctl_txtime, "I",
1432 "Hardware interrupt moderation time "
1436 #ifndef BURN_BRIDGES
1438 * Handle power management nonsense.
1441 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1442 uint32_t membase, irq;
1444 /* Save important PCI config data. */
1445 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1446 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1448 /* Reset the power state. */
1449 device_printf(dev, "chip is in D%d power mode "
1450 "-- setting to D0\n", pci_get_powerstate(dev));
1452 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1454 /* Restore PCI config data. */
1455 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1456 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1460 * Map control/status registers.
1462 pci_enable_busmaster(dev);
1465 sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1468 if (sc->re_res == NULL) {
1469 device_printf(dev, "couldn't map ports\n");
1474 sc->re_btag = rman_get_bustag(sc->re_res);
1475 sc->re_bhandle = rman_get_bushandle(sc->re_res);
1477 /* Allocate interrupt */
1479 sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1480 RF_SHAREABLE | RF_ACTIVE);
1482 if (sc->re_irq == NULL) {
1483 device_printf(dev, "couldn't map interrupt\n");
1488 /* Reset the adapter. */
1491 if (RE_IS_8139CP(sc)) {
1492 sc->re_bus_speed = 33; /* XXX */
1493 } else if (sc->re_caps & RE_C_PCIE) {
1494 sc->re_bus_speed = 125;
1498 cfg2 = CSR_READ_1(sc, RE_CFG2);
1499 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1500 case RE_CFG2_PCICLK_33MHZ:
1501 sc->re_bus_speed = 33;
1503 case RE_CFG2_PCICLK_66MHZ:
1504 sc->re_bus_speed = 66;
1507 device_printf(dev, "unknown bus speed, assume 33MHz\n");
1508 sc->re_bus_speed = 33;
1511 if (cfg2 & RE_CFG2_PCI64)
1512 sc->re_caps |= RE_C_PCI64;
1514 device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1516 sc->re_hwrev, sc->re_macver,
1517 (sc->re_caps & RE_C_PCIE) ?
1518 "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1523 * DO NOT try to adjust config1 and config5 which was spotted in
1524 * Realtek's Linux drivers. It will _permanently_ damage certain
1525 * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1528 re_get_eaddr(sc, eaddr);
1530 if (!RE_IS_8139CP(sc)) {
1531 /* Set RX length mask */
1532 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1533 sc->re_txstart = RE_GTXSTART;
1535 /* Set RX length mask */
1536 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1537 sc->re_txstart = RE_TXSTART;
1540 /* Allocate DMA stuffs */
1541 error = re_allocmem(dev);
1546 * Apply some magic PCI settings from Realtek ...
1548 if (RE_IS_8169(sc)) {
1549 CSR_WRITE_1(sc, 0x82, 1);
1550 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1552 pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1554 if (sc->re_caps & RE_C_MAC2) {
1556 * Following part is extracted from Realtek BSD driver v176.
1557 * However, this does _not_ make much/any sense:
1558 * 8168C's PCI Express device control is located at 0x78,
1559 * so the reading from 0x79 (higher part of 0x78) and setting
1560 * the 4~6bits intend to enlarge the "max read request size"
1561 * (we will do it). The content of the rest part of this
1562 * register is not meaningful to other PCI registers, so
1563 * writing the value to 0x54 could be completely wrong.
1564 * 0x80 is the lower part of PCI Express device status, non-
1565 * reserved bits are RW1C, writing 0 to them will not have
1566 * any effect at all.
1571 val = pci_read_config(dev, 0x79, 1);
1572 val = (val & ~0x70) | 0x50;
1573 pci_write_config(dev, 0x54, val, 1);
1574 pci_write_config(dev, 0x80, 0, 1);
1579 * Apply some PHY fixup from Realtek ...
1581 if (sc->re_hwrev == RE_HWREV_8110S) {
1582 CSR_WRITE_1(sc, 0x82, 1);
1583 re_miibus_writereg(dev, 1, 0xb, 0);
1585 if (sc->re_caps & RE_C_PHYPMGT) {
1587 re_miibus_writereg(dev, 1, 0x1f, 0);
1588 re_miibus_writereg(dev, 1, 0xe, 0);
1592 if (mii_phy_probe(dev, &sc->re_miibus,
1593 re_ifmedia_upd, re_ifmedia_sts)) {
1594 device_printf(dev, "MII without any phy!\n");
1599 ifp = &sc->arpcom.ac_if;
1601 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1602 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1603 ifp->if_ioctl = re_ioctl;
1604 ifp->if_start = re_start;
1605 #ifdef DEVICE_POLLING
1606 ifp->if_poll = re_poll;
1608 ifp->if_watchdog = re_watchdog;
1609 ifp->if_init = re_init;
1610 if (!RE_IS_8139CP(sc)) /* XXX */
1611 ifp->if_baudrate = 1000000000;
1613 ifp->if_baudrate = 100000000;
1614 ifq_set_maxlen(&ifp->if_snd, qlen);
1615 ifq_set_ready(&ifp->if_snd);
1617 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1618 if (sc->re_caps & RE_C_HWCSUM)
1619 ifp->if_capabilities |= IFCAP_HWCSUM;
1621 ifp->if_capenable = ifp->if_capabilities;
1622 if (ifp->if_capabilities & IFCAP_HWCSUM)
1623 ifp->if_hwassist = RE_CSUM_FEATURES;
1625 ifp->if_hwassist = 0;
1628 * Call MI attach routine.
1630 ether_ifattach(ifp, eaddr, NULL);
1634 * Perform hardware diagnostic on the original RTL8169.
1635 * Some 32-bit cards were incorrectly wired and would
1636 * malfunction if plugged into a 64-bit slot.
1638 if (sc->re_hwrev == RE_HWREV_8169) {
1639 lwkt_serialize_enter(ifp->if_serializer);
1640 error = re_diag(sc);
1641 lwkt_serialize_exit(ifp->if_serializer);
1644 device_printf(dev, "hardware diagnostic failure\n");
1645 ether_ifdetach(ifp);
1649 #endif /* RE_DIAG */
1651 /* Hook interrupt last to avoid having to lock softc */
1652 error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1653 &sc->re_intrhand, ifp->if_serializer);
1656 device_printf(dev, "couldn't set up irq\n");
1657 ether_ifdetach(ifp);
1661 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1662 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1672 * Shutdown hardware and free up resources. This can be called any
1673 * time after the mutex has been initialized. It is called in both
1674 * the error case in attach and the normal detach case so it needs
1675 * to be careful about only freeing resources that have actually been
1679 re_detach(device_t dev)
1681 struct re_softc *sc = device_get_softc(dev);
1682 struct ifnet *ifp = &sc->arpcom.ac_if;
1684 /* These should only be active if attach succeeded */
1685 if (device_is_attached(dev)) {
1686 lwkt_serialize_enter(ifp->if_serializer);
1688 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1689 lwkt_serialize_exit(ifp->if_serializer);
1691 ether_ifdetach(ifp);
1694 device_delete_child(dev, sc->re_miibus);
1695 bus_generic_detach(dev);
1697 if (sc->re_sysctl_tree != NULL)
1698 sysctl_ctx_free(&sc->re_sysctl_ctx);
1701 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1703 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1707 /* Free DMA stuffs */
1714 re_setup_rxdesc(struct re_softc *sc, int idx)
1720 paddr = sc->re_ldata.re_rx_paddr[idx];
1721 d = &sc->re_ldata.re_rx_list[idx];
1723 d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1724 d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1726 cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1727 if (idx == (sc->re_rx_desc_cnt - 1))
1728 cmdstat |= RE_RDESC_CMD_EOR;
1729 d->re_cmdstat = htole32(cmdstat);
1733 re_newbuf_std(struct re_softc *sc, int idx, int init)
1735 struct re_dmaload_arg arg;
1736 bus_dma_segment_t seg;
1741 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1746 if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1752 m->m_len = m->m_pkthdr.len = MCLBYTES;
1756 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1757 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1762 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1763 sc->re_ldata.re_rx_spare, m,
1764 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1765 if (error || arg.re_nsegs == 0) {
1767 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
1768 bus_dmamap_unload(sc->re_ldata.re_mtag,
1769 sc->re_ldata.re_rx_spare);
1775 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1783 bus_dmamap_sync(sc->re_ldata.re_mtag,
1784 sc->re_ldata.re_rx_dmamap[idx],
1785 BUS_DMASYNC_POSTREAD);
1786 bus_dmamap_unload(sc->re_ldata.re_mtag,
1787 sc->re_ldata.re_rx_dmamap[idx]);
1789 sc->re_ldata.re_rx_mbuf[idx] = m;
1790 sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1792 map = sc->re_ldata.re_rx_dmamap[idx];
1793 sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1794 sc->re_ldata.re_rx_spare = map;
1796 re_setup_rxdesc(sc, idx);
1801 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1804 struct re_jbuf *jbuf;
1807 MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1811 if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1818 jbuf = re_jbuf_alloc(sc);
1824 if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1831 m->m_ext.ext_arg = jbuf;
1832 m->m_ext.ext_buf = jbuf->re_buf;
1833 m->m_ext.ext_free = re_jbuf_free;
1834 m->m_ext.ext_ref = re_jbuf_ref;
1835 m->m_ext.ext_size = sc->re_rxbuf_size;
1837 m->m_data = m->m_ext.ext_buf;
1838 m->m_flags |= M_EXT;
1839 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1843 * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1844 * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1847 sc->re_ldata.re_rx_mbuf[idx] = m;
1848 sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1850 re_setup_rxdesc(sc, idx);
1855 re_tx_list_init(struct re_softc *sc)
1857 bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1859 /* Flush the TX descriptors */
1860 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1861 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1863 sc->re_ldata.re_tx_prodidx = 0;
1864 sc->re_ldata.re_tx_considx = 0;
1865 sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1871 re_rx_list_init(struct re_softc *sc)
1875 bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1877 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1878 error = sc->re_newbuf(sc, i, 1);
1883 /* Flush the RX descriptors */
1884 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1885 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1887 sc->re_ldata.re_rx_prodidx = 0;
1888 sc->re_head = sc->re_tail = NULL;
1893 #define RE_IP4_PACKET 0x1
1894 #define RE_TCP_PACKET 0x2
1895 #define RE_UDP_PACKET 0x4
1897 static __inline uint8_t
1898 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1900 uint8_t packet_type = 0;
1902 if (sc->re_caps & RE_C_MAC2) {
1903 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1904 packet_type |= RE_IP4_PACKET;
1906 if (rxstat & RE_RDESC_STAT_PROTOID)
1907 packet_type |= RE_IP4_PACKET;
1909 if (RE_TCPPKT(rxstat))
1910 packet_type |= RE_TCP_PACKET;
1911 else if (RE_UDPPKT(rxstat))
1912 packet_type |= RE_UDP_PACKET;
1917 * RX handler for C+ and 8169. For the gigE chips, we support
1918 * the reception of jumbo frames that have been fragmented
1919 * across multiple 2K mbuf cluster buffers.
1922 re_rxeof(struct re_softc *sc)
1924 struct ifnet *ifp = &sc->arpcom.ac_if;
1926 struct re_desc *cur_rx;
1927 uint32_t rxstat, rxctrl;
1928 int i, total_len, rx = 0;
1929 struct mbuf_chain chain[MAXCPU];
1931 /* Invalidate the descriptor memory */
1933 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1934 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1936 ether_input_chain_init(chain);
1938 for (i = sc->re_ldata.re_rx_prodidx;
1939 RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1940 cur_rx = &sc->re_ldata.re_rx_list[i];
1941 m = sc->re_ldata.re_rx_mbuf[i];
1942 total_len = RE_RXBYTES(cur_rx);
1943 rxstat = le32toh(cur_rx->re_cmdstat);
1944 rxctrl = le32toh(cur_rx->re_control);
1949 if (sc->re_flags & RE_F_USE_JPOOL)
1950 KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1953 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1954 if (sc->re_flags & RE_F_DROP_RXFRAG) {
1955 re_setup_rxdesc(sc, i);
1959 if (sc->re_newbuf(sc, i, 0)) {
1960 /* Drop upcoming fragments */
1961 sc->re_flags |= RE_F_DROP_RXFRAG;
1965 m->m_len = MCLBYTES;
1966 if (sc->re_head == NULL) {
1967 sc->re_head = sc->re_tail = m;
1969 sc->re_tail->m_next = m;
1973 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1975 * Last fragment of a multi-fragment packet.
1977 * Since error already happened, this fragment
1978 * must be dropped as well as the fragment chain.
1980 re_setup_rxdesc(sc, i);
1981 re_free_rxchain(sc);
1982 sc->re_flags &= ~RE_F_DROP_RXFRAG;
1987 * NOTE: for the 8139C+, the frame length field
1988 * is always 12 bits in size, but for the gigE chips,
1989 * it is 13 bits (since the max RX frame length is 16K).
1990 * Unfortunately, all 32 bits in the status word
1991 * were already used, so to make room for the extra
1992 * length bit, RealTek took out the 'frame alignment
1993 * error' bit and shifted the other status bits
1994 * over one slot. The OWN, EOR, FS and LS bits are
1995 * still in the same places. We have already extracted
1996 * the frame length and checked the OWN bit, so rather
1997 * than using an alternate bit mapping, we shift the
1998 * status bits one space to the right so we can evaluate
1999 * them using the 8169 status as though it was in the
2000 * same format as that of the 8139C+.
2002 if (!RE_IS_8139CP(sc))
2005 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
2008 * If this is part of a multi-fragment packet,
2009 * discard all the pieces.
2011 re_free_rxchain(sc);
2012 re_setup_rxdesc(sc, i);
2017 * If allocating a replacement mbuf fails,
2018 * reload the current one.
2021 if (sc->re_newbuf(sc, i, 0)) {
2026 if (sc->re_head != NULL) {
2027 m->m_len = total_len % MCLBYTES;
2029 * Special case: if there's 4 bytes or less
2030 * in this buffer, the mbuf can be discarded:
2031 * the last 4 bytes is the CRC, which we don't
2032 * care about anyway.
2034 if (m->m_len <= ETHER_CRC_LEN) {
2035 sc->re_tail->m_len -=
2036 (ETHER_CRC_LEN - m->m_len);
2039 m->m_len -= ETHER_CRC_LEN;
2040 sc->re_tail->m_next = m;
2043 sc->re_head = sc->re_tail = NULL;
2044 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2046 m->m_pkthdr.len = m->m_len =
2047 (total_len - ETHER_CRC_LEN);
2051 m->m_pkthdr.rcvif = ifp;
2053 /* Do RX checksumming if enabled */
2055 if (ifp->if_capenable & IFCAP_RXCSUM) {
2056 uint8_t packet_type;
2058 packet_type = re_packet_type(sc, rxstat, rxctrl);
2060 /* Check IP header checksum */
2061 if (packet_type & RE_IP4_PACKET) {
2062 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2063 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
2064 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2067 /* Check TCP/UDP checksum */
2068 if (((packet_type & RE_TCP_PACKET) &&
2069 (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2070 ((packet_type & RE_UDP_PACKET) &&
2071 (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2072 m->m_pkthdr.csum_flags |=
2073 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2074 CSUM_FRAG_NOT_CHECKED;
2075 m->m_pkthdr.csum_data = 0xffff;
2079 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2080 m->m_flags |= M_VLANTAG;
2081 m->m_pkthdr.ether_vlantag =
2082 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2084 ether_input_chain(ifp, m, chain);
2087 ether_input_dispatch(chain);
2089 /* Flush the RX DMA ring */
2091 bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
2092 sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
2094 sc->re_ldata.re_rx_prodidx = i;
2099 #undef RE_IP4_PACKET
2100 #undef RE_TCP_PACKET
2101 #undef RE_UDP_PACKET
2104 re_tx_collect(struct re_softc *sc)
2106 struct ifnet *ifp = &sc->arpcom.ac_if;
2110 /* Invalidate the TX descriptor list */
2111 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2112 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
2114 for (idx = sc->re_ldata.re_tx_considx;
2115 sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2116 RE_TXDESC_INC(sc, idx)) {
2117 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2118 if (txstat & RE_TDESC_CMD_OWN)
2123 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2126 * We only stash mbufs in the last descriptor
2127 * in a fragment chain, which also happens to
2128 * be the only place where the TX status bits
2131 if (txstat & RE_TDESC_CMD_EOF) {
2132 m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2133 sc->re_ldata.re_tx_mbuf[idx] = NULL;
2134 bus_dmamap_unload(sc->re_ldata.re_mtag,
2135 sc->re_ldata.re_tx_dmamap[idx]);
2136 if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2137 RE_TDESC_STAT_COLCNT))
2138 ifp->if_collisions++;
2139 if (txstat & RE_TDESC_STAT_TXERRSUM)
2144 sc->re_ldata.re_tx_free++;
2146 sc->re_ldata.re_tx_considx = idx;
2152 re_txeof(struct re_softc *sc)
2154 struct ifnet *ifp = &sc->arpcom.ac_if;
2157 tx = re_tx_collect(sc);
2159 /* There is enough free TX descs */
2160 if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2161 ifp->if_flags &= ~IFF_OACTIVE;
2164 * Some chips will ignore a second TX request issued while an
2165 * existing transmission is in progress. If the transmitter goes
2166 * idle but there are still packets waiting to be sent, we need
2167 * to restart the channel here to flush them out. This only seems
2168 * to be required with the PCIe devices.
2170 if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2171 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2181 struct re_softc *sc = xsc;
2183 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2184 re_tick_serialized(xsc);
2185 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2189 re_tick_serialized(void *xsc)
2191 struct re_softc *sc = xsc;
2192 struct ifnet *ifp = &sc->arpcom.ac_if;
2193 struct mii_data *mii;
2195 ASSERT_SERIALIZED(ifp->if_serializer);
2197 mii = device_get_softc(sc->re_miibus);
2199 if (sc->re_flags & RE_F_LINKED) {
2200 if (!(mii->mii_media_status & IFM_ACTIVE))
2201 sc->re_flags &= ~RE_F_LINKED;
2203 if (mii->mii_media_status & IFM_ACTIVE &&
2204 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2205 sc->re_flags |= RE_F_LINKED;
2206 if (!ifq_is_empty(&ifp->if_snd))
2211 callout_reset(&sc->re_timer, hz, re_tick, sc);
2214 #ifdef DEVICE_POLLING
2217 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2219 struct re_softc *sc = ifp->if_softc;
2221 ASSERT_SERIALIZED(ifp->if_serializer);
2225 /* disable interrupts */
2226 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2229 case POLL_DEREGISTER:
2230 /* enable interrupts */
2231 re_setup_intr(sc, 1, sc->re_imtype);
2235 sc->rxcycles = count;
2239 if (!ifq_is_empty(&ifp->if_snd))
2242 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2245 status = CSR_READ_2(sc, RE_ISR);
2246 if (status == 0xffff)
2249 CSR_WRITE_2(sc, RE_ISR, status);
2252 * XXX check behaviour on receiver stalls.
2255 if (status & RE_ISR_SYSTEM_ERR)
2261 #endif /* DEVICE_POLLING */
2266 struct re_softc *sc = arg;
2267 struct ifnet *ifp = &sc->arpcom.ac_if;
2271 ASSERT_SERIALIZED(ifp->if_serializer);
2273 if ((sc->re_flags & RE_F_SUSPENDED) ||
2274 (ifp->if_flags & IFF_RUNNING) == 0)
2279 status = CSR_READ_2(sc, RE_ISR);
2280 /* If the card has gone away the read returns 0xffff. */
2281 if (status == 0xffff)
2284 CSR_WRITE_2(sc, RE_ISR, status);
2286 if ((status & sc->re_intrs) == 0)
2289 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2292 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2295 if (status & RE_ISR_SYSTEM_ERR)
2298 if (status & RE_ISR_LINKCHG) {
2299 callout_stop(&sc->re_timer);
2300 re_tick_serialized(sc);
2304 if (sc->re_imtype == RE_IMTYPE_SIM) {
2305 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2306 if ((tx | rx) == 0) {
2308 * Nothing needs to be processed, fallback
2309 * to use TX/RX interrupts.
2311 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2314 * Recollect, mainly to avoid the possible
2315 * race introduced by changing interrupt
2321 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2323 } else if (tx | rx) {
2325 * Assume that using simulated interrupt moderation
2326 * (hardware timer based) could reduce the interript
2329 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2333 if (tx && !ifq_is_empty(&ifp->if_snd))
2338 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2340 struct ifnet *ifp = &sc->arpcom.ac_if;
2342 struct re_dmaload_arg arg;
2343 bus_dma_segment_t segs[RE_MAXSEGS];
2345 int error, maxsegs, idx, i;
2346 struct re_desc *d, *tx_ring;
2347 uint32_t cmd_csum, ctl_csum, vlantag;
2349 KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2350 ("not enough free TX desc\n"));
2353 map = sc->re_ldata.re_tx_dmamap[*idx0];
2356 * Set up checksum offload. Note: checksum offload bits must
2357 * appear in all descriptors of a multi-descriptor transmit
2358 * attempt. (This is according to testing done with an 8169
2359 * chip. I'm not sure if this is a requirement or a bug.)
2361 cmd_csum = ctl_csum = 0;
2362 if (m->m_pkthdr.csum_flags & CSUM_IP) {
2363 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2364 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2366 if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2367 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2368 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2370 if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2371 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2372 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2375 /* For MAC2 chips, csum flags are set on re_control */
2376 if (sc->re_caps & RE_C_MAC2)
2381 if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2383 * With some of the RealTek chips, using the checksum offload
2384 * support in conjunction with the autopadding feature results
2385 * in the transmission of corrupt frames. For example, if we
2386 * need to send a really small IP fragment that's less than 60
2387 * bytes in size, and IP header checksumming is enabled, the
2388 * resulting ethernet frame that appears on the wire will
2389 * have garbled payload. To work around this, if TX checksum
2390 * offload is enabled, we always manually pad short frames out
2391 * to the minimum ethernet frame size.
2393 * Note: this appears unnecessary for TCP, and doing it for TCP
2394 * with PCIe adapters seems to result in bad checksums.
2396 if ((m->m_pkthdr.csum_flags &
2397 (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2398 (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2399 m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2400 error = m_devpad(m, RE_MIN_FRAMELEN);
2407 if (m->m_flags & M_VLANTAG) {
2408 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2409 RE_TDESC_CTL_INSTAG;
2412 maxsegs = sc->re_ldata.re_tx_free;
2413 if (maxsegs > RE_MAXSEGS)
2414 maxsegs = RE_MAXSEGS;
2416 arg.re_nsegs = maxsegs;
2418 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2419 re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2420 if (error && error != EFBIG) {
2421 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2426 * Too many segments to map, coalesce into a single mbuf
2428 if (!error && arg.re_nsegs == 0) {
2429 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2435 m_new = m_defrag(m, MB_DONTWAIT);
2436 if (m_new == NULL) {
2437 if_printf(ifp, "can't defrag TX mbuf\n");
2441 *m_head = m = m_new;
2444 arg.re_nsegs = maxsegs;
2446 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2447 re_dma_map_desc, &arg,
2449 if (error || arg.re_nsegs == 0) {
2451 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2454 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2458 bus_dmamap_sync(sc->re_ldata.re_mtag, map, BUS_DMASYNC_PREWRITE);
2461 * Map the segment array into descriptors. We also keep track
2462 * of the end of the ring and set the end-of-ring bits as needed,
2463 * and we set the ownership bits in all except the very first
2464 * descriptor, whose ownership bits will be turned on later.
2466 tx_ring = sc->re_ldata.re_tx_list;
2474 cmdstat = segs[i].ds_len;
2475 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2476 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2478 cmdstat |= RE_TDESC_CMD_SOF;
2480 cmdstat |= RE_TDESC_CMD_OWN;
2481 if (idx == (sc->re_tx_desc_cnt - 1))
2482 cmdstat |= RE_TDESC_CMD_EOR;
2483 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2484 d->re_control = htole32(ctl_csum | vlantag);
2487 if (i == arg.re_nsegs)
2489 RE_TXDESC_INC(sc, idx);
2491 d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2493 /* Transfer ownership of packet to the chip. */
2494 d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2496 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2499 * Insure that the map for this transmission
2500 * is placed at the array index of the last descriptor
2503 sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2504 sc->re_ldata.re_tx_dmamap[idx] = map;
2506 sc->re_ldata.re_tx_mbuf[idx] = m;
2507 sc->re_ldata.re_tx_free -= arg.re_nsegs;
2509 RE_TXDESC_INC(sc, idx);
2520 * Main transmit routine for C+ and gigE NICs.
2524 re_start(struct ifnet *ifp)
2526 struct re_softc *sc = ifp->if_softc;
2527 struct mbuf *m_head;
2528 int idx, need_trans, oactive, error;
2530 ASSERT_SERIALIZED(ifp->if_serializer);
2532 if ((sc->re_flags & RE_F_LINKED) == 0) {
2533 ifq_purge(&ifp->if_snd);
2537 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2540 idx = sc->re_ldata.re_tx_prodidx;
2544 while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2545 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2547 if (re_tx_collect(sc)) {
2552 ifp->if_flags |= IFF_OACTIVE;
2556 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2560 error = re_encap(sc, &m_head, &idx);
2562 /* m_head is freed by re_encap(), if we reach here */
2565 if (error == EFBIG && !oactive) {
2566 if (re_tx_collect(sc)) {
2571 ifp->if_flags |= IFF_OACTIVE;
2579 * If there's a BPF listener, bounce a copy of this frame
2582 ETHER_BPF_MTAP(ifp, m_head);
2588 /* Flush the TX descriptors */
2589 bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2590 sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2592 sc->re_ldata.re_tx_prodidx = idx;
2595 * RealTek put the TX poll request register in a different
2596 * location on the 8169 gigE chip. I don't know why.
2598 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2601 * Set a timeout in case the chip goes out to lunch.
2609 struct re_softc *sc = xsc;
2610 struct ifnet *ifp = &sc->arpcom.ac_if;
2611 struct mii_data *mii;
2612 int error, framelen;
2614 ASSERT_SERIALIZED(ifp->if_serializer);
2616 mii = device_get_softc(sc->re_miibus);
2619 * Cancel pending I/O and free all RX/TX buffers.
2623 if (sc->re_caps & RE_C_CONTIGRX) {
2624 if (ifp->if_mtu > ETHERMTU) {
2625 KKASSERT(sc->re_ldata.re_jbuf != NULL);
2626 sc->re_flags |= RE_F_USE_JPOOL;
2627 sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2628 sc->re_newbuf = re_newbuf_jumbo;
2630 sc->re_flags &= ~RE_F_USE_JPOOL;
2631 sc->re_rxbuf_size = MCLBYTES;
2632 sc->re_newbuf = re_newbuf_std;
2637 * Adjust max read request size according to MTU; mainly to
2638 * improve TX performance for common case (ETHERMTU) on GigE
2639 * NICs. However, this could _not_ be done on 10/100 only
2640 * NICs; their DMA engines will malfunction using non-default
2641 * max read request size.
2643 if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2644 if (ifp->if_mtu > ETHERMTU) {
2646 * 512 seems to be the only value that works
2647 * reliably with jumbo frame
2649 pcie_set_max_readrq(sc->re_dev,
2650 PCIEM_DEVCTL_MAX_READRQ_512);
2652 pcie_set_max_readrq(sc->re_dev,
2653 PCIEM_DEVCTL_MAX_READRQ_4096);
2658 * Enable C+ RX and TX mode, as well as VLAN stripping and
2659 * RX checksum offload. We must configure the C+ register
2660 * before all others.
2662 CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2663 RE_CPLUSCMD_PCI_MRW |
2664 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2665 RE_CPLUSCMD_VLANSTRIP : 0) |
2666 (ifp->if_capenable & IFCAP_RXCSUM ?
2667 RE_CPLUSCMD_RXCSUM_ENB : 0));
2670 * Init our MAC address. Even though the chipset
2671 * documentation doesn't mention it, we need to enter "Config
2672 * register write enable" mode to modify the ID registers.
2674 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2675 CSR_WRITE_4(sc, RE_IDR0,
2676 htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2677 CSR_WRITE_2(sc, RE_IDR4,
2678 htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2679 CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2682 * For C+ mode, initialize the RX descriptors and mbufs.
2684 error = re_rx_list_init(sc);
2689 error = re_tx_list_init(sc);
2696 * Load the addresses of the RX and TX lists into the chip.
2698 CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2699 RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2700 CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2701 RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2703 CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2704 RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2705 CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2706 RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2709 * Enable transmit and receive.
2711 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2714 * Set the initial TX and RX configuration.
2716 if (sc->re_flags & RE_F_TESTMODE) {
2717 if (!RE_IS_8139CP(sc))
2718 CSR_WRITE_4(sc, RE_TXCFG,
2719 RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2721 CSR_WRITE_4(sc, RE_TXCFG,
2722 RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2724 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2726 framelen = RE_FRAMELEN(ifp->if_mtu);
2727 if (framelen < MCLBYTES)
2728 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2730 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2732 CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2735 * Program the multicast filter, if necessary.
2739 #ifdef DEVICE_POLLING
2741 * Disable interrupts if we are polling.
2743 if (ifp->if_flags & IFF_POLLING)
2744 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2745 else /* otherwise ... */
2746 #endif /* DEVICE_POLLING */
2748 * Enable interrupts.
2750 if (sc->re_flags & RE_F_TESTMODE)
2751 CSR_WRITE_2(sc, RE_IMR, 0);
2753 re_setup_intr(sc, 1, sc->re_imtype);
2754 CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2756 /* Start RX/TX process. */
2757 CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2760 /* Enable receiver and transmitter. */
2761 CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2765 * For 8169 gigE NICs, set the max allowed RX packet
2766 * size so we can receive jumbo frames.
2768 if (!RE_IS_8139CP(sc)) {
2769 if (sc->re_caps & RE_C_CONTIGRX)
2770 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2772 CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2775 if (sc->re_flags & RE_F_TESTMODE)
2780 CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2782 ifp->if_flags |= IFF_RUNNING;
2783 ifp->if_flags &= ~IFF_OACTIVE;
2785 callout_reset(&sc->re_timer, hz, re_tick, sc);
2789 * Set media options.
2792 re_ifmedia_upd(struct ifnet *ifp)
2794 struct re_softc *sc = ifp->if_softc;
2795 struct mii_data *mii;
2797 ASSERT_SERIALIZED(ifp->if_serializer);
2799 mii = device_get_softc(sc->re_miibus);
2806 * Report current media status.
2809 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2811 struct re_softc *sc = ifp->if_softc;
2812 struct mii_data *mii;
2814 ASSERT_SERIALIZED(ifp->if_serializer);
2816 mii = device_get_softc(sc->re_miibus);
2819 ifmr->ifm_active = mii->mii_media_active;
2820 ifmr->ifm_status = mii->mii_media_status;
2824 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2826 struct re_softc *sc = ifp->if_softc;
2827 struct ifreq *ifr = (struct ifreq *) data;
2828 struct mii_data *mii;
2829 int error = 0, mask;
2831 ASSERT_SERIALIZED(ifp->if_serializer);
2835 if (ifr->ifr_mtu > sc->re_maxmtu) {
2837 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2838 ifp->if_mtu = ifr->ifr_mtu;
2839 if (ifp->if_flags & IFF_RUNNING)
2845 if (ifp->if_flags & IFF_UP) {
2846 if (ifp->if_flags & IFF_RUNNING) {
2847 if ((ifp->if_flags ^ sc->re_if_flags) &
2848 (IFF_PROMISC | IFF_ALLMULTI))
2853 } else if (ifp->if_flags & IFF_RUNNING) {
2856 sc->re_if_flags = ifp->if_flags;
2866 mii = device_get_softc(sc->re_miibus);
2867 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2871 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2872 ifp->if_capabilities;
2873 ifp->if_capenable ^= mask;
2875 if (mask & IFCAP_HWCSUM) {
2876 if (ifp->if_capenable & IFCAP_TXCSUM)
2877 ifp->if_hwassist = RE_CSUM_FEATURES;
2879 ifp->if_hwassist = 0;
2881 if (mask && (ifp->if_flags & IFF_RUNNING))
2886 error = ether_ioctl(ifp, command, data);
2893 re_watchdog(struct ifnet *ifp)
2895 struct re_softc *sc = ifp->if_softc;
2897 ASSERT_SERIALIZED(ifp->if_serializer);
2899 if_printf(ifp, "watchdog timeout\n");
2908 if (!ifq_is_empty(&ifp->if_snd))
2913 * Stop the adapter and free any mbufs allocated to the
2917 re_stop(struct re_softc *sc)
2919 struct ifnet *ifp = &sc->arpcom.ac_if;
2922 ASSERT_SERIALIZED(ifp->if_serializer);
2924 /* Reset the adapter. */
2925 re_reset(sc, ifp->if_flags & IFF_RUNNING);
2928 callout_stop(&sc->re_timer);
2930 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2931 sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2933 CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2934 CSR_WRITE_2(sc, RE_IMR, 0x0000);
2935 CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2937 re_free_rxchain(sc);
2939 /* Free the TX list buffers. */
2940 for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2941 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2942 bus_dmamap_unload(sc->re_ldata.re_mtag,
2943 sc->re_ldata.re_tx_dmamap[i]);
2944 m_freem(sc->re_ldata.re_tx_mbuf[i]);
2945 sc->re_ldata.re_tx_mbuf[i] = NULL;
2949 /* Free the RX list buffers. */
2950 for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2951 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2952 if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2953 bus_dmamap_unload(sc->re_ldata.re_mtag,
2954 sc->re_ldata.re_rx_dmamap[i]);
2956 m_freem(sc->re_ldata.re_rx_mbuf[i]);
2957 sc->re_ldata.re_rx_mbuf[i] = NULL;
2963 * Device suspend routine. Stop the interface and save some PCI
2964 * settings in case the BIOS doesn't restore them properly on
2968 re_suspend(device_t dev)
2970 #ifndef BURN_BRIDGES
2973 struct re_softc *sc = device_get_softc(dev);
2974 struct ifnet *ifp = &sc->arpcom.ac_if;
2976 lwkt_serialize_enter(ifp->if_serializer);
2980 #ifndef BURN_BRIDGES
2981 for (i = 0; i < 5; i++)
2982 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2983 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2984 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2985 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2986 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2989 sc->re_flags |= RE_F_SUSPENDED;
2991 lwkt_serialize_exit(ifp->if_serializer);
2997 * Device resume routine. Restore some PCI settings in case the BIOS
2998 * doesn't, re-enable busmastering, and restart the interface if
3002 re_resume(device_t dev)
3004 struct re_softc *sc = device_get_softc(dev);
3005 struct ifnet *ifp = &sc->arpcom.ac_if;
3006 #ifndef BURN_BRIDGES
3010 lwkt_serialize_enter(ifp->if_serializer);
3012 #ifndef BURN_BRIDGES
3013 /* better way to do this? */
3014 for (i = 0; i < 5; i++)
3015 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
3016 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
3017 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
3018 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
3019 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3021 /* reenable busmastering */
3022 pci_enable_busmaster(dev);
3023 pci_enable_io(dev, SYS_RES_IOPORT);
3026 /* reinitialize interface if necessary */
3027 if (ifp->if_flags & IFF_UP)
3030 sc->re_flags &= ~RE_F_SUSPENDED;
3032 lwkt_serialize_exit(ifp->if_serializer);
3038 * Stop all chip I/O so that the kernel's probe routines don't
3039 * get confused by errant DMAs when rebooting.
3042 re_shutdown(device_t dev)
3044 struct re_softc *sc = device_get_softc(dev);
3045 struct ifnet *ifp = &sc->arpcom.ac_if;
3047 lwkt_serialize_enter(ifp->if_serializer);
3049 lwkt_serialize_exit(ifp->if_serializer);
3053 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
3055 struct re_softc *sc = arg1;
3057 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
3061 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
3063 struct re_softc *sc = arg1;
3065 return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
3069 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
3071 struct re_softc *sc = arg1;
3072 struct ifnet *ifp = &sc->arpcom.ac_if;
3075 lwkt_serialize_enter(ifp->if_serializer);
3078 error = sysctl_handle_int(oidp, &v, 0, req);
3079 if (error || req->newptr == NULL)
3090 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3091 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
3095 lwkt_serialize_exit(ifp->if_serializer);
3100 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
3102 struct re_softc *sc = arg1;
3103 struct ifnet *ifp = &sc->arpcom.ac_if;
3106 lwkt_serialize_enter(ifp->if_serializer);
3108 v = sc->re_sim_time;
3109 error = sysctl_handle_int(oidp, &v, 0, req);
3110 if (error || req->newptr == NULL)
3118 if (v != sc->re_sim_time) {
3119 sc->re_sim_time = v;
3121 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3122 IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3127 * Following code causes various strange
3128 * performance problems. Hmm ...
3130 CSR_WRITE_2(sc, RE_IMR, 0);
3131 if (!RE_IS_8139CP(sc))
3132 reg = RE_TIMERINT_8169;
3135 CSR_WRITE_4(sc, reg, 0);
3136 CSR_READ_4(sc, reg); /* flush */
3138 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3139 re_setup_sim_im(sc);
3141 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3143 re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3148 lwkt_serialize_exit(ifp->if_serializer);
3153 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3155 struct re_softc *sc = arg1;
3156 struct ifnet *ifp = &sc->arpcom.ac_if;
3159 lwkt_serialize_enter(ifp->if_serializer);
3162 error = sysctl_handle_int(oidp, &v, 0, req);
3163 if (error || req->newptr == NULL)
3166 if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3170 if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3171 /* Can't do hardware interrupt moderation */
3176 if (v != sc->re_imtype) {
3178 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3180 re_setup_intr(sc, 1, sc->re_imtype);
3183 lwkt_serialize_exit(ifp->if_serializer);
3188 re_setup_hw_im(struct re_softc *sc)
3190 KKASSERT(sc->re_caps & RE_C_HWIM);
3193 * Interrupt moderation
3196 * A - unknown (maybe TX related)
3197 * B - TX timer (unit: 25us)
3198 * C - unknown (maybe RX related)
3199 * D - RX timer (unit: 25us)
3202 * re(4)'s interrupt moderation is actually controlled by
3203 * two variables, like most other NICs (bge, bce etc.)
3205 * o number of packets [P]
3207 * The logic relationship between these two variables is
3208 * similar to other NICs too:
3209 * if (timer expire || packets > [P])
3210 * Interrupt is delivered
3212 * Currently we only know how to set 'timer', but not
3213 * 'number of packets', which should be ~30, as far as I
3214 * tested (sink ~900Kpps, interrupt rate is 30KHz)
3216 CSR_WRITE_2(sc, RE_IM,
3217 RE_IM_RXTIME(sc->re_rx_time) |
3218 RE_IM_TXTIME(sc->re_tx_time) |
3223 re_disable_hw_im(struct re_softc *sc)
3225 if (sc->re_caps & RE_C_HWIM)
3226 CSR_WRITE_2(sc, RE_IM, 0);
3230 re_setup_sim_im(struct re_softc *sc)
3232 if (!RE_IS_8139CP(sc)) {
3236 * Datasheet says tick decreases at bus speed,
3237 * but it seems the clock runs a little bit
3238 * faster, so we do some compensation here.
3240 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3241 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3243 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3245 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3246 sc->re_flags |= RE_F_TIMER_INTR;
3250 re_disable_sim_im(struct re_softc *sc)
3252 if (!RE_IS_8139CP(sc))
3253 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3255 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3256 sc->re_flags &= ~RE_F_TIMER_INTR;
3260 re_config_imtype(struct re_softc *sc, int imtype)
3264 KKASSERT(sc->re_caps & RE_C_HWIM);
3266 case RE_IMTYPE_NONE:
3267 sc->re_intrs = RE_INTRS;
3268 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3270 sc->re_tx_ack = RE_ISR_TX_OK;
3274 sc->re_intrs = RE_INTRS_TIMER;
3275 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3276 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3280 panic("%s: unknown imtype %d\n",
3281 sc->arpcom.ac_if.if_xname, imtype);
3286 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3288 re_config_imtype(sc, imtype);
3291 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3293 CSR_WRITE_2(sc, RE_IMR, 0);
3296 case RE_IMTYPE_NONE:
3297 re_disable_sim_im(sc);
3298 re_disable_hw_im(sc);
3302 KKASSERT(sc->re_caps & RE_C_HWIM);
3303 re_disable_sim_im(sc);
3308 re_disable_hw_im(sc);
3309 re_setup_sim_im(sc);
3313 panic("%s: unknown imtype %d\n",
3314 sc->arpcom.ac_if.if_xname, imtype);
3319 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3323 if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) {
3327 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3328 if (re_did == 0x8128) {
3329 uint16_t as[ETHER_ADDR_LEN / 2];
3332 * Get station address from the EEPROM.
3334 re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
3335 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3336 as[i] = le16toh(as[i]);
3337 bcopy(as, eaddr, sizeof(eaddr));
3343 * Get station address from IDRx.
3345 for (i = 0; i < ETHER_ADDR_LEN; ++i)
3346 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3350 re_jpool_alloc(struct re_softc *sc)
3352 struct re_list_data *ldata = &sc->re_ldata;
3353 struct re_jbuf *jbuf;
3355 bus_size_t jpool_size;
3359 lwkt_serialize_init(&ldata->re_jbuf_serializer);
3361 ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3362 M_DEVBUF, M_WAITOK | M_ZERO);
3364 jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3366 error = bus_dma_tag_create(sc->re_parent_tag,
3367 RE_BUF_ALIGN, 0, /* alignment, boundary */
3368 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
3369 BUS_SPACE_MAXADDR, /* highaddr */
3370 NULL, NULL, /* filter, filterarg */
3371 jpool_size, 1, /* nsegments, maxsize */
3372 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
3373 BUS_DMA_ALLOCNOW, /* flags */
3374 &ldata->re_jpool_tag);
3376 device_printf(sc->re_dev, "could not allocate jumbo dma tag\n");
3380 error = bus_dmamem_alloc(ldata->re_jpool_tag, (void **)&ldata->re_jpool,
3381 BUS_DMA_WAITOK, &ldata->re_jpool_map);
3383 device_printf(sc->re_dev,
3384 "could not allocate jumbo dma memory\n");
3385 bus_dma_tag_destroy(ldata->re_jpool_tag);
3386 ldata->re_jpool_tag = NULL;
3390 error = bus_dmamap_load(ldata->re_jpool_tag, ldata->re_jpool_map,
3391 ldata->re_jpool, jpool_size,
3392 re_dma_map_addr, &paddr, BUS_DMA_WAITOK);
3394 device_printf(sc->re_dev, "could not load jumbo dma map\n");
3395 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3396 ldata->re_jpool_map);
3397 bus_dma_tag_destroy(ldata->re_jpool_tag);
3398 ldata->re_jpool_tag = NULL;
3402 /* ..and split it into 9KB chunks */
3403 SLIST_INIT(&ldata->re_jbuf_free);
3405 buf = ldata->re_jpool;
3406 for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3407 jbuf = &ldata->re_jbuf[i];
3413 jbuf->re_paddr = paddr;
3415 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3417 buf += RE_JBUF_SIZE;
3418 paddr += RE_JBUF_SIZE;
3424 re_jpool_free(struct re_softc *sc)
3426 struct re_list_data *ldata = &sc->re_ldata;
3428 if (ldata->re_jpool_tag != NULL) {
3429 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3430 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3431 ldata->re_jpool_map);
3432 bus_dma_tag_destroy(ldata->re_jpool_tag);
3433 ldata->re_jpool_tag = NULL;
3436 if (ldata->re_jbuf != NULL) {
3437 kfree(ldata->re_jbuf, M_DEVBUF);
3438 ldata->re_jbuf = NULL;
3442 static struct re_jbuf *
3443 re_jbuf_alloc(struct re_softc *sc)
3445 struct re_list_data *ldata = &sc->re_ldata;
3446 struct re_jbuf *jbuf;
3448 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3450 jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3452 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3456 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3462 re_jbuf_free(void *arg)
3464 struct re_jbuf *jbuf = arg;
3465 struct re_softc *sc = jbuf->re_sc;
3466 struct re_list_data *ldata = &sc->re_ldata;
3468 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3469 panic("%s: free wrong jumbo buffer\n",
3470 sc->arpcom.ac_if.if_xname);
3471 } else if (jbuf->re_inuse == 0) {
3472 panic("%s: jumbo buffer already freed\n",
3473 sc->arpcom.ac_if.if_xname);
3476 lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3477 atomic_subtract_int(&jbuf->re_inuse, 1);
3478 if (jbuf->re_inuse == 0)
3479 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3480 lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3484 re_jbuf_ref(void *arg)
3486 struct re_jbuf *jbuf = arg;
3487 struct re_softc *sc = jbuf->re_sc;
3488 struct re_list_data *ldata = &sc->re_ldata;
3490 if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3491 panic("%s: ref wrong jumbo buffer\n",
3492 sc->arpcom.ac_if.if_xname);
3493 } else if (jbuf->re_inuse == 0) {
3494 panic("%s: jumbo buffer already freed\n",
3495 sc->arpcom.ac_if.if_xname);
3497 atomic_add_int(&jbuf->re_inuse, 1);