2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
39 * $DragonFly: src/sys/platform/pc64/isa/clock.c,v 1.1 2008/08/29 17:07:19 dillon Exp $
43 * Routines to handle clock hardware.
47 * inittodr, settodr and support routines written
48 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
50 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 //#include "use_apm.h"
54 //#include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/eventhandler.h>
60 #include <sys/kernel.h>
65 #include <sys/sysctl.h>
67 #include <sys/systimer.h>
68 #include <sys/globaldata.h>
69 #include <sys/thread2.h>
70 #include <sys/systimer.h>
71 #include <sys/machintr.h>
73 #include <machine/clock.h>
74 #ifdef CLK_CALIBRATION_LOOP
76 #include <machine/cputypes.h>
77 #include <machine/frame.h>
78 #include <machine/ipl.h>
79 #include <machine/limits.h>
80 #include <machine/md_var.h>
81 #include <machine/psl.h>
82 #include <machine/segments.h>
83 #include <machine/smp.h>
84 #include <machine/specialreg.h>
86 #include <machine_base/icu/icu.h>
87 #include <bus/isa/isa.h>
88 #include <bus/isa/rtc.h>
89 #include <machine_base/isa/timerreg.h>
91 #include <machine_base/isa/intr_machdep.h>
94 /* The interrupt triggered by the 8254 (timer) chip */
96 static void setup_8254_mixed_mode (void);
98 static void i8254_restore(void);
99 static void resettodr_on_shutdown(void *arg __unused);
102 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
103 * can use a simple formula for leap years.
105 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
106 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
109 #define TIMER_FREQ 1193182
112 static uint8_t i8254_walltimer_sel;
113 static uint16_t i8254_walltimer_cntr;
115 int adjkerntz; /* local offset from GMT in seconds */
116 int disable_rtc_set; /* disable resettodr() if != 0 */
117 int statclock_disable = 1; /* we don't use the statclock right now */
119 int64_t tsc_frequency;
121 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
123 enum tstate { RELEASED, ACQUIRED };
124 enum tstate timer0_state;
125 enum tstate timer1_state;
126 enum tstate timer2_state;
128 static int beeping = 0;
129 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
130 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
131 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
132 static int rtc_loaded;
134 static int i8254_cputimer_div;
136 static struct callout sysbeepstop_ch;
138 static sysclock_t i8254_cputimer_count(void);
139 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
140 static void i8254_cputimer_destruct(struct cputimer *cputimer);
142 static struct cputimer i8254_cputimer = {
143 SLIST_ENTRY_INITIALIZER,
147 i8254_cputimer_count,
148 cputimer_default_fromhz,
149 cputimer_default_fromus,
150 i8254_cputimer_construct,
151 i8254_cputimer_destruct,
157 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
158 * counting as of this interrupt. We use timer1 in free-running mode (not
159 * generating any interrupts) as our main counter. Each cpu has timeouts
162 * This code is INTR_MPSAFE and may be called without the BGL held.
165 clkintr(void *dummy, void *frame_arg)
167 static sysclock_t sysclock_count; /* NOTE! Must be static */
168 struct globaldata *gd = mycpu;
170 struct globaldata *gscan;
175 * SWSTROBE mode is a one-shot, the timer is no longer running
180 * XXX the dispatcher needs work. right now we call systimer_intr()
181 * directly or via IPI for any cpu with systimers queued, which is
182 * usually *ALL* of them. We need to use the LAPIC timer for this.
184 sysclock_count = sys_cputimer->count();
186 for (n = 0; n < ncpus; ++n) {
187 gscan = globaldata_find(n);
188 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
191 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
194 systimer_intr(&sysclock_count, 0, frame_arg);
198 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
199 systimer_intr(&sysclock_count, 0, frame_arg);
208 acquire_timer2(int mode)
210 if (timer2_state != RELEASED)
212 timer2_state = ACQUIRED;
215 * This access to the timer registers is as atomic as possible
216 * because it is a single instruction. We could do better if we
219 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
226 if (timer2_state != ACQUIRED)
228 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
229 timer2_state = RELEASED;
234 * This routine receives statistical clock interrupts from the RTC.
235 * As explained above, these occur at 128 interrupts per second.
236 * When profiling, we receive interrupts at a rate of 1024 Hz.
238 * This does not actually add as much overhead as it sounds, because
239 * when the statistical clock is active, the hardclock driver no longer
240 * needs to keep (inaccurate) statistics on its own. This decouples
241 * statistics gathering from scheduling interrupts.
243 * The RTC chip requires that we read status register C (RTC_INTR)
244 * to acknowledge an interrupt, before it will generate the next one.
245 * Under high interrupt load, rtcintr() can be indefinitely delayed and
246 * the clock can tick immediately after the read from RTC_INTR. In this
247 * case, the mc146818A interrupt signal will not drop for long enough
248 * to register with the 8259 PIC. If an interrupt is missed, the stat
249 * clock will halt, considerably degrading system performance. This is
250 * why we use 'while' rather than a more straightforward 'if' below.
251 * Stat clock ticks can still be lost, causing minor loss of accuracy
252 * in the statistics, but the stat clock will no longer stop.
255 rtcintr(void *dummy, void *frame)
257 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
259 /* statclock(frame); no longer used */
266 DB_SHOW_COMMAND(rtc, rtc)
268 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
269 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
270 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
271 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
276 * Return the current cpu timer count as a 32 bit integer.
280 i8254_cputimer_count(void)
282 static __uint16_t cputimer_last;
287 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
288 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
289 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
290 count = -count; /* -> countup */
291 if (count < cputimer_last) /* rollover */
292 i8254_cputimer.base += 0x00010000;
293 ret = i8254_cputimer.base | count;
294 cputimer_last = count;
300 * This function is called whenever the system timebase changes, allowing
301 * us to calculate what is needed to convert a system timebase tick
302 * into an 8254 tick for the interrupt timer. If we can convert to a
303 * simple shift, multiplication, or division, we do so. Otherwise 64
304 * bit arithmatic is required every time the interrupt timer is reloaded.
307 cputimer_intr_config(struct cputimer *timer)
313 * Will a simple divide do the trick?
315 div = (timer->freq + (i8254_cputimer.freq / 2)) / i8254_cputimer.freq;
316 freq = i8254_cputimer.freq * div;
318 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
319 i8254_cputimer_div = div;
321 i8254_cputimer_div = 0;
325 * Reload for the next timeout. It is possible for the reload value
326 * to be 0 or negative, indicating that an immediate timer interrupt
327 * is desired. For now make the minimum 2 ticks.
329 * We may have to convert from the system timebase to the 8254 timebase.
332 cputimer_intr_reload(sysclock_t reload)
336 if (i8254_cputimer_div)
337 reload /= i8254_cputimer_div;
339 reload = (int64_t)reload * i8254_cputimer.freq / sys_cputimer->freq;
345 if (timer0_running) {
346 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
347 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
348 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
349 if (reload < count) {
350 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
351 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
352 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
357 reload = 0; /* full count */
358 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
359 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
360 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
366 * DELAY(usec) - Spin for the specified number of microseconds.
367 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
368 * but do a thread switch in the loop
370 * Relies on timer 1 counting down from (cputimer_freq / hz)
371 * Note: timer had better have been programmed before this is first used!
374 DODELAY(int n, int doswitch)
376 int delta, prev_tick, tick, ticks_left;
381 static int state = 0;
385 for (n1 = 1; n1 <= 10000000; n1 *= 10)
390 kprintf("DELAY(%d)...", n);
393 * Guard against the timer being uninitialized if we are called
394 * early for console i/o.
396 if (timer0_state == RELEASED)
400 * Read the counter first, so that the rest of the setup overhead is
401 * counted. Then calculate the number of hardware timer ticks
402 * required, rounding up to be sure we delay at least the requested
403 * number of microseconds.
405 prev_tick = sys_cputimer->count();
406 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
412 while (ticks_left > 0) {
413 tick = sys_cputimer->count();
417 delta = tick - prev_tick;
422 if (doswitch && ticks_left > 0)
427 kprintf(" %d calls to getit() at %d usec each\n",
428 getit_calls, (n + 5) / getit_calls);
439 DRIVERSLEEP(int usec)
441 globaldata_t gd = mycpu;
443 if (gd->gd_intr_nesting_level ||
444 gd->gd_spinlock_rd ||
445 gd->gd_spinlocks_wr) {
453 sysbeepstop(void *chan)
455 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
461 sysbeep(int pitch, int period)
463 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
466 * Nobody else is using timer2, we do not need the clock lock
468 outb(TIMER_CNTR2, pitch);
469 outb(TIMER_CNTR2, (pitch>>8));
471 /* enable counter2 output to speaker */
472 outb(IO_PPI, inb(IO_PPI) | 3);
474 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
480 * RTC support routines
491 val = inb(IO_RTC + 1);
498 writertc(u_char reg, u_char val)
504 outb(IO_RTC + 1, val);
505 inb(0x84); /* XXX work around wrong order in rtcin() */
512 return(bcd2bin(rtcin(port)));
516 calibrate_clocks(void)
519 u_int count, prev_count, tot_count;
520 int sec, start_sec, timeout;
523 kprintf("Calibrating clock(s) ... ");
524 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
528 /* Read the mc146818A seconds counter. */
530 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
531 sec = rtcin(RTC_SEC);
538 /* Wait for the mC146818A seconds counter to change. */
541 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
542 sec = rtcin(RTC_SEC);
543 if (sec != start_sec)
550 /* Start keeping track of the i8254 counter. */
551 prev_count = sys_cputimer->count();
557 old_tsc = 0; /* shut up gcc */
560 * Wait for the mc146818A seconds counter to change. Read the i8254
561 * counter for each iteration since this is convenient and only
562 * costs a few usec of inaccuracy. The timing of the final reads
563 * of the counters almost matches the timing of the initial reads,
564 * so the main cause of inaccuracy is the varying latency from
565 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
566 * rtcin(RTC_SEC) that returns a changed seconds count. The
567 * maximum inaccuracy from this cause is < 10 usec on 486's.
571 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
572 sec = rtcin(RTC_SEC);
573 count = sys_cputimer->count();
574 tot_count += (int)(count - prev_count);
576 if (sec != start_sec)
583 * Read the cpu cycle counter. The timing considerations are
584 * similar to those for the i8254 clock.
587 tsc_frequency = rdtsc() - old_tsc;
591 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
592 kprintf("i8254 clock: %u Hz\n", tot_count);
596 kprintf("failed, using default i8254 clock of %u Hz\n",
597 i8254_cputimer.freq);
598 return (i8254_cputimer.freq);
604 timer0_state = ACQUIRED;
609 * Timer0 is our fine-grained variable clock interrupt
611 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
612 outb(TIMER_CNTR0, 2); /* lsb */
613 outb(TIMER_CNTR0, 0); /* msb */
617 * Timer1 or timer2 is our free-running clock, but only if another
618 * has not been selected.
620 cputimer_register(&i8254_cputimer);
621 cputimer_select(&i8254_cputimer, 0);
625 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
630 * Should we use timer 1 or timer 2 ?
633 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
634 if (which != 1 && which != 2)
639 timer->name = "i8254_timer1";
640 timer->type = CPUTIMER_8254_SEL1;
641 i8254_walltimer_sel = TIMER_SEL1;
642 i8254_walltimer_cntr = TIMER_CNTR1;
643 timer1_state = ACQUIRED;
646 timer->name = "i8254_timer2";
647 timer->type = CPUTIMER_8254_SEL2;
648 i8254_walltimer_sel = TIMER_SEL2;
649 i8254_walltimer_cntr = TIMER_CNTR2;
650 timer2_state = ACQUIRED;
654 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
657 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
658 outb(i8254_walltimer_cntr, 0); /* lsb */
659 outb(i8254_walltimer_cntr, 0); /* msb */
660 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
665 i8254_cputimer_destruct(struct cputimer *timer)
667 switch(timer->type) {
668 case CPUTIMER_8254_SEL1:
669 timer1_state = RELEASED;
671 case CPUTIMER_8254_SEL2:
672 timer2_state = RELEASED;
683 /* Restore all of the RTC's "status" (actually, control) registers. */
684 writertc(RTC_STATUSB, RTCSB_24HR);
685 writertc(RTC_STATUSA, rtc_statusa);
686 writertc(RTC_STATUSB, rtc_statusb);
690 * Restore all the timers.
692 * This function is called to resynchronize our core timekeeping after a
693 * long halt, e.g. from apm_default_resume() and friends. It is also
694 * called if after a BIOS call we have detected munging of the 8254.
695 * It is necessary because cputimer_count() counter's delta may have grown
696 * too large for nanouptime() and friends to handle, or (in the case of 8254
697 * munging) might cause the SYSTIMER code to prematurely trigger.
703 i8254_restore(); /* restore timer_freq and hz */
704 rtc_restore(); /* reenable RTC interrupts */
709 * Initialize 8254 timer 0 early so that it can be used in DELAY().
717 * Can we use the TSC?
719 if (cpu_feature & CPUID_TSC)
725 * Initial RTC state, don't do anything unexpected
727 writertc(RTC_STATUSA, rtc_statusa);
728 writertc(RTC_STATUSB, RTCSB_24HR);
731 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
732 * generate an interrupt, which we will ignore for now.
734 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
735 * (so it counts a full 2^16 and repeats). We will use this timer
739 freq = calibrate_clocks();
740 #ifdef CLK_CALIBRATION_LOOP
743 "Press a key on the console to abort clock calibration\n");
744 while (cncheckc() == -1)
750 * Use the calibrated i8254 frequency if it seems reasonable.
751 * Otherwise use the default, and don't use the calibrated i586
754 delta = freq > i8254_cputimer.freq ?
755 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
756 if (delta < i8254_cputimer.freq / 100) {
757 #ifndef CLK_USE_I8254_CALIBRATION
760 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
761 freq = i8254_cputimer.freq;
763 cputimer_set_frequency(&i8254_cputimer, freq);
767 "%d Hz differs from default of %d Hz by more than 1%%\n",
768 freq, i8254_cputimer.freq);
772 #ifndef CLK_USE_TSC_CALIBRATION
773 if (tsc_frequency != 0) {
776 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
780 if (tsc_present && tsc_frequency == 0) {
782 * Calibration of the i586 clock relative to the mc146818A
783 * clock failed. Do a less accurate calibration relative
784 * to the i8254 clock.
786 u_int64_t old_tsc = rdtsc();
789 tsc_frequency = rdtsc() - old_tsc;
790 #ifdef CLK_USE_TSC_CALIBRATION
792 kprintf("TSC clock: %llu Hz (Method B)\n",
798 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
802 * We can not use the TSC in SMP mode, until we figure out a
803 * cheap (impossible), reliable and precise (yeah right!) way
804 * to synchronize the TSCs of all the CPUs.
805 * Curse Intel for leaving the counter out of the I/O APIC.
810 * We can not use the TSC if we support APM. Precise timekeeping
811 * on an APM'ed machine is at best a fools pursuit, since
812 * any and all of the time spent in various SMM code can't
813 * be reliably accounted for. Reading the RTC is your only
814 * source of reliable time info. The i8254 looses too of course
815 * but we need to have some kind of time...
816 * We don't know at this point whether APM is going to be used
817 * or not, nor when it might be activated. Play it safe.
820 #endif /* NAPM > 0 */
822 #endif /* !defined(SMP) */
826 * Sync the time of day back to the RTC on shutdown, but only if
827 * we have already loaded it and have not crashed.
830 resettodr_on_shutdown(void *arg __unused)
832 if (rtc_loaded && panicstr == NULL) {
838 * Initialize the time of day register, based on the time base which is, e.g.
842 inittodr(time_t base)
844 unsigned long sec, days;
856 /* Look if we have a RTC present and the time is valid */
857 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
860 /* wait for time update to complete */
861 /* If RTCSA_TUP is zero, we have at least 244us before next update */
863 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
869 #ifdef USE_RTC_CENTURY
870 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
872 year = readrtc(RTC_YEAR) + 1900;
880 month = readrtc(RTC_MONTH);
881 for (m = 1; m < month; m++)
882 days += daysinmonth[m-1];
883 if ((month > 2) && LEAPYEAR(year))
885 days += readrtc(RTC_DAY) - 1;
887 for (y = 1970; y < year; y++)
888 days += DAYSPERYEAR + LEAPYEAR(y);
889 sec = ((( days * 24 +
890 readrtc(RTC_HRS)) * 60 +
891 readrtc(RTC_MIN)) * 60 +
893 /* sec now contains the number of seconds, since Jan 1 1970,
894 in the local time zone */
896 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
898 y = time_second - sec;
899 if (y <= -2 || y >= 2) {
900 /* badly off, adjust it */
910 kprintf("Invalid time in real time clock.\n");
911 kprintf("Check and reset the date immediately!\n");
915 * Write system time back to RTC
932 /* Disable RTC updates and interrupts. */
933 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
935 /* Calculate local time to put in RTC */
937 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
939 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
940 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
941 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
943 /* We have now the days since 01-01-1970 in tm */
944 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
945 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
947 y++, m = DAYSPERYEAR + LEAPYEAR(y))
950 /* Now we have the years in y and the day-of-the-year in tm */
951 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
952 #ifdef USE_RTC_CENTURY
953 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
959 if (m == 1 && LEAPYEAR(y))
966 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
967 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
969 /* Reenable RTC updates and interrupts. */
970 writertc(RTC_STATUSB, rtc_statusb);
976 * Start both clocks running. DragonFly note: the stat clock is no longer
977 * used. Instead, 8254 based systimers are used for all major clock
978 * interrupts. statclock_disable is set by default.
981 cpu_initclocks(void *arg __unused)
989 if (statclock_disable) {
991 * The stat interrupt mask is different without the
992 * statistics clock. Also, don't set the interrupt
993 * flag which would normally cause the RTC to generate
996 rtc_statusb = RTCSB_24HR;
998 /* Setting stathz to nonzero early helps avoid races. */
999 stathz = RTC_NOPROFRATE;
1000 profhz = RTC_PROFRATE;
1003 /* Finish initializing 8253 timer 0. */
1006 apic_8254_intr = isa_apic_irq(0);
1007 apic_8254_trial = 0;
1008 if (apic_8254_intr >= 0 ) {
1009 if (apic_int_type(0, 0) == 3)
1010 apic_8254_trial = 1;
1012 /* look for ExtInt on pin 0 */
1013 if (apic_int_type(0, 0) == 3) {
1014 apic_8254_intr = apic_irq(0, 0);
1015 setup_8254_mixed_mode();
1017 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1020 clkdesc = register_int(apic_8254_intr, clkintr, NULL, "clk",
1022 INTR_EXCL | INTR_FAST |
1023 INTR_NOPOLL | INTR_MPSAFE |
1025 machintr_intren(apic_8254_intr);
1029 register_int(0, clkintr, NULL, "clk", NULL,
1030 INTR_EXCL | INTR_FAST |
1031 INTR_NOPOLL | INTR_MPSAFE |
1033 machintr_intren(ICU_IRQ0);
1035 #endif /* APIC_IO */
1037 /* Initialize RTC. */
1038 writertc(RTC_STATUSA, rtc_statusa);
1039 writertc(RTC_STATUSB, RTCSB_24HR);
1041 if (statclock_disable == 0) {
1042 diag = rtcin(RTC_DIAG);
1044 kprintf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1047 if (isa_apic_irq(8) != 8)
1048 panic("APIC RTC != 8");
1049 #endif /* APIC_IO */
1051 register_int(8, (inthand2_t *)rtcintr, NULL, "rtc", NULL,
1052 INTR_EXCL | INTR_FAST | INTR_NOPOLL |
1056 writertc(RTC_STATUSB, rtc_statusb);
1060 if (apic_8254_trial) {
1064 lastcnt = get_interrupt_counter(apic_8254_intr);
1067 * XXX this assumes the 8254 is the cpu timer. Force an
1068 * 8254 Timer0 interrupt and wait 1/100s for it to happen,
1069 * then see if we got it.
1071 kprintf("APIC_IO: Testing 8254 interrupt delivery\n");
1072 cputimer_intr_reload(2); /* XXX assumes 8254 */
1073 base = sys_cputimer->count();
1074 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1076 if (get_interrupt_counter(apic_8254_intr) - lastcnt == 0) {
1078 * The MP table is broken.
1079 * The 8254 was not connected to the specified pin
1081 * Workaround: Limited variant of mixed mode.
1083 machintr_intrdis(apic_8254_intr);
1084 unregister_int(clkdesc);
1085 kprintf("APIC_IO: Broken MP table detected: "
1086 "8254 is not connected to "
1087 "IOAPIC #%d intpin %d\n",
1088 int_to_apicintpin[apic_8254_intr].ioapic,
1089 int_to_apicintpin[apic_8254_intr].int_pin);
1091 * Revoke current ISA IRQ 0 assignment and
1092 * configure a fallback interrupt routing from
1093 * the 8254 Timer via the 8259 PIC to the
1094 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1095 * We reuse the low level interrupt handler number.
1097 if (apic_irq(0, 0) < 0) {
1098 revoke_apic_irq(apic_8254_intr);
1099 assign_apic_irq(0, 0, apic_8254_intr);
1101 apic_8254_intr = apic_irq(0, 0);
1102 setup_8254_mixed_mode();
1103 register_int(apic_8254_intr, clkintr, NULL, "clk",
1105 INTR_EXCL | INTR_FAST |
1106 INTR_NOPOLL | INTR_MPSAFE |
1108 machintr_intren(apic_8254_intr);
1112 if (apic_int_type(0, 0) != 3 ||
1113 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1114 int_to_apicintpin[apic_8254_intr].int_pin != 0) {
1115 kprintf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1116 int_to_apicintpin[apic_8254_intr].ioapic,
1117 int_to_apicintpin[apic_8254_intr].int_pin);
1120 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1123 callout_init(&sysbeepstop_ch);
1125 SYSINIT(clocks8254, SI_BOOT2_CLOCKREG, SI_ORDER_FIRST, cpu_initclocks, NULL)
1130 setup_8254_mixed_mode(void)
1133 * Allow 8254 timer to INTerrupt 8259:
1134 * re-initialize master 8259:
1135 * reset; prog 4 bytes, single ICU, edge triggered
1137 outb(IO_ICU1, 0x13);
1138 outb(IO_ICU1 + 1, IDT_OFFSET); /* start vector (unused) */
1139 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1140 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1141 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1143 /* program IO APIC for type 3 INT on INT0 */
1144 if (ext_int_setup(0, 0) < 0)
1145 panic("8254 redirect via APIC pin0 impossible!");
1150 setstatclockrate(int newhz)
1152 if (newhz == RTC_PROFRATE)
1153 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1155 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1156 writertc(RTC_STATUSA, rtc_statusa);
1161 tsc_get_timecount(struct timecounter *tc)
1167 #ifdef KERN_TIMESTAMP
1168 #define KERN_TIMESTAMP_SIZE 16384
1169 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1170 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1171 sizeof(tsc), "LU", "Kernel timestamps");
1177 tsc[i] = (u_int32_t)rdtsc();
1180 if (i >= KERN_TIMESTAMP_SIZE)
1182 tsc[i] = 0; /* mark last entry */
1184 #endif /* KERN_TIMESTAMP */
1191 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1198 if (sys_cputimer == &i8254_cputimer)
1199 count = sys_cputimer->count();
1207 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1208 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1211 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1212 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1214 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1215 0, 0, hw_i8254_timestamp, "A", "");
1217 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1218 &tsc_present, 0, "TSC Available");
1219 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1220 &tsc_frequency, 0, "TSC Frequency");