MP Implementation 1/2: Get the APIC code working again, sweetly integrate the
[dragonfly.git] / sys / i386 / i386 / identcpu.c
1 /*
2  * Copyright (c) 1992 Terrence R. Lambert.
3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4  * Copyright (c) 1997 KATO Takenori.
5  * Copyright (c) 2001 Tamotsu Hattori.
6  * Copyright (c) 2001 Mitsuru IWASAKI.
7  * All rights reserved.
8  *
9  * This code is derived from software contributed to Berkeley by
10  * William Jolitz.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *      This product includes software developed by the University of
23  *      California, Berkeley and its contributors.
24  * 4. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
41  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.80.2.15 2003/04/11 17:06:41 jhb Exp $
42  * $DragonFly: src/sys/i386/i386/Attic/identcpu.c,v 1.3 2003/07/06 21:23:48 dillon Exp $
43  */
44
45 #include "opt_cpu.h"
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/sysctl.h>
51
52 #include <machine/asmacros.h>
53 #include <machine/clock.h>
54 #include <machine/cputypes.h>
55 #include <machine/segments.h>
56 #include <machine/specialreg.h>
57 #include <machine/md_var.h>
58
59 #include <i386/isa/intr_machdep.h>
60
61 #define IDENTBLUE_CYRIX486      0
62 #define IDENTBLUE_IBMCPU        1
63 #define IDENTBLUE_CYRIXM2       2
64
65 /* XXX - should be in header file: */
66 void printcpuinfo(void);
67 void finishidentcpu(void);
68 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
69 void    enable_K5_wt_alloc(void);
70 void    enable_K6_wt_alloc(void);
71 void    enable_K6_2_wt_alloc(void);
72 #endif
73 void panicifcpuunsupported(void);
74
75 static void identifycyrix(void);
76 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
77 static void print_AMD_features(void);
78 #endif
79 static void print_AMD_info(void);
80 static void print_AMD_assoc(int i);
81 static void print_transmeta_info(void);
82 static void setup_tmx86_longrun(void);
83
84 int     cpu_class = CPUCLASS_386;
85 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
86 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
87 char machine[] = "i386";
88 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
89     machine, 0, "Machine class");
90
91 static char cpu_model[128];
92 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
93     cpu_model, 0, "Machine model");
94
95 static char cpu_brand[48];
96
97 #define MAX_BRAND_INDEX 8
98
99 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
100         NULL,                   /* No brand */
101         "Intel Celeron",
102         "Intel Pentium III",
103         "Intel Pentium III Xeon",
104         NULL,
105         NULL,
106         NULL,
107         NULL,
108         "Intel Pentium 4"
109 };
110
111 static struct cpu_nameclass i386_cpus[] = {
112         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
113         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
114         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
115         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
116         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
117         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
118         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
119         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
120         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
121         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
122         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
123         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
124         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
125         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
126         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
127         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
128         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
129 };
130
131 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
132 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
133 #endif
134
135 void
136 printcpuinfo(void)
137 {
138 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
139         u_int regs[4], i;
140 #endif
141         char *brand;
142
143         cpu_class = i386_cpus[cpu].cpu_class;
144         printf("CPU: ");
145         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
146
147 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
148         /* Check for extended CPUID information and a processor name. */
149         if (cpu_high > 0 &&
150             (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
151             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
152             strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
153             strcmp(cpu_vendor, "TransmetaCPU") == 0)) {
154                 do_cpuid(0x80000000, regs);
155                 if (regs[0] >= 0x80000000) {
156                         cpu_exthigh = regs[0];
157                         if (cpu_exthigh >= 0x80000004) {
158                                 brand = cpu_brand;
159                                 for (i = 0x80000002; i < 0x80000005; i++) {
160                                         do_cpuid(i, regs);
161                                         memcpy(brand, regs, sizeof(regs));
162                                         brand += sizeof(regs);
163                                 }
164                         }
165                 }
166         }
167
168         if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
169                 if ((cpu_id & 0xf00) > 0x300) {
170                         u_int brand_index;
171
172                         cpu_model[0] = '\0';
173
174                         switch (cpu_id & 0x3000) {
175                         case 0x1000:
176                                 strcpy(cpu_model, "Overdrive ");
177                                 break;
178                         case 0x2000:
179                                 strcpy(cpu_model, "Dual ");
180                                 break;
181                         }
182
183                         switch (cpu_id & 0xf00) {
184                         case 0x400:
185                                 strcat(cpu_model, "i486 ");
186                                 /* Check the particular flavor of 486 */
187                                 switch (cpu_id & 0xf0) {
188                                 case 0x00:
189                                 case 0x10:
190                                         strcat(cpu_model, "DX");
191                                         break;
192                                 case 0x20:
193                                         strcat(cpu_model, "SX");
194                                         break;
195                                 case 0x30:
196                                         strcat(cpu_model, "DX2");
197                                         break;
198                                 case 0x40:
199                                         strcat(cpu_model, "SL");
200                                         break;
201                                 case 0x50:
202                                         strcat(cpu_model, "SX2");
203                                         break;
204                                 case 0x70:
205                                         strcat(cpu_model,
206                                             "DX2 Write-Back Enhanced");
207                                         break;
208                                 case 0x80:
209                                         strcat(cpu_model, "DX4");
210                                         break;
211                                 }
212                                 break;
213                         case 0x500:
214                                 /* Check the particular flavor of 586 */
215                                 strcat(cpu_model, "Pentium");
216                                 switch (cpu_id & 0xf0) {
217                                 case 0x00:
218                                         strcat(cpu_model, " A-step");
219                                         break;
220                                 case 0x10:
221                                         strcat(cpu_model, "/P5");
222                                         break;
223                                 case 0x20:
224                                         strcat(cpu_model, "/P54C");
225                                         break;
226                                 case 0x30:
227                                         strcat(cpu_model, "/P54T Overdrive");
228                                         break;
229                                 case 0x40:
230                                         strcat(cpu_model, "/P55C");
231                                         break;
232                                 case 0x70:
233                                         strcat(cpu_model, "/P54C");
234                                         break;
235                                 case 0x80:
236                                         strcat(cpu_model, "/P55C (quarter-micron)");
237                                         break;
238                                 default:
239                                         /* nothing */
240                                         break;
241                                 }
242 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
243                                 /*
244                                  * XXX - If/when Intel fixes the bug, this
245                                  * should also check the version of the
246                                  * CPU, not just that it's a Pentium.
247                                  */
248                                 has_f00f_bug = 1;
249 #endif
250                                 break;
251                         case 0x600:
252                                 /* Check the particular flavor of 686 */
253                                 switch (cpu_id & 0xf0) {
254                                 case 0x00:
255                                         strcat(cpu_model, "Pentium Pro A-step");
256                                         break;
257                                 case 0x10:
258                                         strcat(cpu_model, "Pentium Pro");
259                                         break;
260                                 case 0x30:
261                                 case 0x50:
262                                 case 0x60:
263                                         strcat(cpu_model,
264                                 "Pentium II/Pentium II Xeon/Celeron");
265                                         cpu = CPU_PII;
266                                         break;
267                                 case 0x70:
268                                 case 0x80:
269                                 case 0xa0:
270                                 case 0xb0:
271                                         strcat(cpu_model,
272                                         "Pentium III/Pentium III Xeon/Celeron");
273                                         cpu = CPU_PIII;
274                                         break;
275                                 default:
276                                         strcat(cpu_model, "Unknown 80686");
277                                         break;
278                                 }
279                                 break;
280                         case 0xf00:
281                                 strcat(cpu_model, "Pentium 4");
282                                 cpu = CPU_P4;
283                                 break;
284                         default:
285                                 strcat(cpu_model, "unknown");
286                                 break;
287                         }
288
289                         /*
290                          * If we didn't get a brand name from the extended
291                          * CPUID, try to look it up in the brand table.
292                          */
293                         if (cpu_high > 0 && *cpu_brand == '\0') {
294                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
295                                 if (brand_index <= MAX_BRAND_INDEX &&
296                                     cpu_brandtable[brand_index] != NULL)
297                                         strcpy(cpu_brand,
298                                             cpu_brandtable[brand_index]);
299                         }
300                 }
301         } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
302                 /*
303                  * Values taken from AMD Processor Recognition
304                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
305                  * (also describes ``Features'' encodings.
306                  */
307                 strcpy(cpu_model, "AMD ");
308                 switch (cpu_id & 0xFF0) {
309                 case 0x410:
310                         strcat(cpu_model, "Standard Am486DX");
311                         break;
312                 case 0x430:
313                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
314                         break;
315                 case 0x470:
316                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
317                         break;
318                 case 0x480:
319                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
320                         break;
321                 case 0x490:
322                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
323                         break;
324                 case 0x4E0:
325                         strcat(cpu_model, "Am5x86 Write-Through");
326                         break;
327                 case 0x4F0:
328                         strcat(cpu_model, "Am5x86 Write-Back");
329                         break;
330                 case 0x500:
331                         strcat(cpu_model, "K5 model 0");
332                         tsc_is_broken = 1;
333                         break;
334                 case 0x510:
335                         strcat(cpu_model, "K5 model 1");
336                         break;
337                 case 0x520:
338                         strcat(cpu_model, "K5 PR166 (model 2)");
339                         break;
340                 case 0x530:
341                         strcat(cpu_model, "K5 PR200 (model 3)");
342                         break;
343                 case 0x560:
344                         strcat(cpu_model, "K6");
345                         break;
346                 case 0x570:
347                         strcat(cpu_model, "K6 266 (model 1)");
348                         break;
349                 case 0x580:
350                         strcat(cpu_model, "K6-2");
351                         break;
352                 case 0x590:
353                         strcat(cpu_model, "K6-III");
354                         break;
355                 default:
356                         strcat(cpu_model, "Unknown");
357                         break;
358                 }
359 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
360                 if ((cpu_id & 0xf00) == 0x500) {
361                         if (((cpu_id & 0x0f0) > 0)
362                             && ((cpu_id & 0x0f0) < 0x60)
363                             && ((cpu_id & 0x00f) > 3))
364                                 enable_K5_wt_alloc();
365                         else if (((cpu_id & 0x0f0) > 0x80)
366                                  || (((cpu_id & 0x0f0) == 0x80)
367                                      && (cpu_id & 0x00f) > 0x07))
368                                 enable_K6_2_wt_alloc();
369                         else if ((cpu_id & 0x0f0) > 0x50)
370                                 enable_K6_wt_alloc();
371                 }
372 #endif
373         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
374                 strcpy(cpu_model, "Cyrix ");
375                 switch (cpu_id & 0xff0) {
376                 case 0x440:
377                         strcat(cpu_model, "MediaGX");
378                         break;
379                 case 0x520:
380                         strcat(cpu_model, "6x86");
381                         break;
382                 case 0x540:
383                         cpu_class = CPUCLASS_586;
384                         strcat(cpu_model, "GXm");
385                         break;
386                 case 0x600:
387                         strcat(cpu_model, "6x86MX");
388                         break;
389                 default:
390                         /*
391                          * Even though CPU supports the cpuid
392                          * instruction, it can be disabled.
393                          * Therefore, this routine supports all Cyrix
394                          * CPUs.
395                          */
396                         switch (cyrix_did & 0xf0) {
397                         case 0x00:
398                                 switch (cyrix_did & 0x0f) {
399                                 case 0x00:
400                                         strcat(cpu_model, "486SLC");
401                                         break;
402                                 case 0x01:
403                                         strcat(cpu_model, "486DLC");
404                                         break;
405                                 case 0x02:
406                                         strcat(cpu_model, "486SLC2");
407                                         break;
408                                 case 0x03:
409                                         strcat(cpu_model, "486DLC2");
410                                         break;
411                                 case 0x04:
412                                         strcat(cpu_model, "486SRx");
413                                         break;
414                                 case 0x05:
415                                         strcat(cpu_model, "486DRx");
416                                         break;
417                                 case 0x06:
418                                         strcat(cpu_model, "486SRx2");
419                                         break;
420                                 case 0x07:
421                                         strcat(cpu_model, "486DRx2");
422                                         break;
423                                 case 0x08:
424                                         strcat(cpu_model, "486SRu");
425                                         break;
426                                 case 0x09:
427                                         strcat(cpu_model, "486DRu");
428                                         break;
429                                 case 0x0a:
430                                         strcat(cpu_model, "486SRu2");
431                                         break;
432                                 case 0x0b:
433                                         strcat(cpu_model, "486DRu2");
434                                         break;
435                                 default:
436                                         strcat(cpu_model, "Unknown");
437                                         break;
438                                 }
439                                 break;
440                         case 0x10:
441                                 switch (cyrix_did & 0x0f) {
442                                 case 0x00:
443                                         strcat(cpu_model, "486S");
444                                         break;
445                                 case 0x01:
446                                         strcat(cpu_model, "486S2");
447                                         break;
448                                 case 0x02:
449                                         strcat(cpu_model, "486Se");
450                                         break;
451                                 case 0x03:
452                                         strcat(cpu_model, "486S2e");
453                                         break;
454                                 case 0x0a:
455                                         strcat(cpu_model, "486DX");
456                                         break;
457                                 case 0x0b:
458                                         strcat(cpu_model, "486DX2");
459                                         break;
460                                 case 0x0f:
461                                         strcat(cpu_model, "486DX4");
462                                         break;
463                                 default:
464                                         strcat(cpu_model, "Unknown");
465                                         break;
466                                 }
467                                 break;
468                         case 0x20:
469                                 if ((cyrix_did & 0x0f) < 8)
470                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
471                                 else
472                                         strcat(cpu_model, "5x86");
473                                 break;
474                         case 0x30:
475                                 strcat(cpu_model, "6x86");
476                                 break;
477                         case 0x40:
478                                 if ((cyrix_did & 0xf000) == 0x3000) {
479                                         cpu_class = CPUCLASS_586;
480                                         strcat(cpu_model, "GXm");
481                                 } else
482                                         strcat(cpu_model, "MediaGX");
483                                 break;
484                         case 0x50:
485                                 strcat(cpu_model, "6x86MX");
486                                 break;
487                         case 0xf0:
488                                 switch (cyrix_did & 0x0f) {
489                                 case 0x0d:
490                                         strcat(cpu_model, "Overdrive CPU");
491                                 case 0x0e:
492                                         strcpy(cpu_model, "Texas Instruments 486SXL");
493                                         break;
494                                 case 0x0f:
495                                         strcat(cpu_model, "486SLC/DLC");
496                                         break;
497                                 default:
498                                         strcat(cpu_model, "Unknown");
499                                         break;
500                                 }
501                                 break;
502                         default:
503                                 strcat(cpu_model, "Unknown");
504                                 break;
505                         }
506                         break;
507                 }
508         } else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
509                 strcpy(cpu_model, "Rise ");
510                 switch (cpu_id & 0xff0) {
511                 case 0x500:
512                         strcat(cpu_model, "mP6");
513                         break;
514                 default:
515                         strcat(cpu_model, "Unknown");
516                 }
517         } else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
518                 switch (cpu_id & 0xff0) {
519                 case 0x540:
520                         strcpy(cpu_model, "IDT WinChip C6");
521                         tsc_is_broken = 1;
522                         break;
523                 case 0x580:
524                         strcpy(cpu_model, "IDT WinChip 2");
525                         break;
526                 case 0x670:
527                         strcpy(cpu_model, "VIA C3 Samuel 2");
528                         break;
529                 default:
530                         strcpy(cpu_model, "VIA/IDT Unknown");
531                 }
532         } else if (strcmp(cpu_vendor, "IBM") == 0) {
533                 strcpy(cpu_model, "Blue Lightning CPU");
534         }
535
536         /*
537          * Replace cpu_model with cpu_brand minus leading spaces if
538          * we have one.
539          */
540         brand = cpu_brand;
541         while (*brand == ' ')
542                 ++brand;
543         if (*brand != '\0')
544                 strcpy(cpu_model, brand);
545
546 #endif
547
548         printf("%s (", cpu_model);
549         switch(cpu_class) {
550         case CPUCLASS_286:
551                 printf("286");
552                 break;
553 #if defined(I386_CPU)
554         case CPUCLASS_386:
555                 printf("386");
556                 break;
557 #endif
558 #if defined(I486_CPU)
559         case CPUCLASS_486:
560                 printf("486");
561                 bzero = i486_bzero;
562                 break;
563 #endif
564 #if defined(I586_CPU)
565         case CPUCLASS_586:
566                 printf("%d.%02d-MHz ",
567                        (tsc_freq + 4999) / 1000000,
568                        ((tsc_freq + 4999) / 10000) % 100);
569                 printf("586");
570                 break;
571 #endif
572 #if defined(I686_CPU)
573         case CPUCLASS_686:
574                 printf("%d.%02d-MHz ",
575                        (tsc_freq + 4999) / 1000000,
576                        ((tsc_freq + 4999) / 10000) % 100);
577                 printf("686");
578                 break;
579 #endif
580         default:
581                 printf("Unknown");      /* will panic below... */
582         }
583         printf("-class CPU)\n");
584 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
585         if(*cpu_vendor)
586                 printf("  Origin = \"%s\"",cpu_vendor);
587         if(cpu_id)
588                 printf("  Id = 0x%x", cpu_id);
589
590         if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
591             strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
592             strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
593             strcmp(cpu_vendor, "CentaurHauls") == 0 ||
594                 ((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
595                  ((cpu_id & 0xf00) > 0x500))) {
596                 printf("  Stepping = %u", cpu_id & 0xf);
597                 if (strcmp(cpu_vendor, "CyrixInstead") == 0)
598                         printf("  DIR=0x%04x", cyrix_did);
599                 if (cpu_high > 0) {
600                         /*
601                          * Here we should probably set up flags indicating
602                          * whether or not various features are available.
603                          * The interesting ones are probably VME, PSE, PAE,
604                          * and PGE.  The code already assumes without bothering
605                          * to check that all CPUs >= Pentium have a TSC and
606                          * MSRs.
607                          */
608                         printf("\n  Features=0x%b", cpu_feature,
609                         "\020"
610                         "\001FPU"       /* Integral FPU */
611                         "\002VME"       /* Extended VM86 mode support */
612                         "\003DE"        /* Debugging Extensions (CR4.DE) */
613                         "\004PSE"       /* 4MByte page tables */
614                         "\005TSC"       /* Timestamp counter */
615                         "\006MSR"       /* Machine specific registers */
616                         "\007PAE"       /* Physical address extension */
617                         "\010MCE"       /* Machine Check support */
618                         "\011CX8"       /* CMPEXCH8 instruction */
619                         "\012APIC"      /* SMP local APIC */
620                         "\013oldMTRR"   /* Previous implementation of MTRR */
621                         "\014SEP"       /* Fast System Call */
622                         "\015MTRR"      /* Memory Type Range Registers */
623                         "\016PGE"       /* PG_G (global bit) support */
624                         "\017MCA"       /* Machine Check Architecture */
625                         "\020CMOV"      /* CMOV instruction */
626                         "\021PAT"       /* Page attributes table */
627                         "\022PSE36"     /* 36 bit address space support */
628                         "\023PN"        /* Processor Serial number */
629                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
630                         "\025<b20>"
631                         "\026DTS"       /* Debug Trace Store */
632                         "\027ACPI"      /* ACPI support */
633                         "\030MMX"       /* MMX instructions */
634                         "\031FXSR"      /* FXSAVE/FXRSTOR */
635                         "\032SSE"       /* Streaming SIMD Extensions */
636                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
637                         "\034SS"        /* Self snoop */
638                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
639                         "\036TM"        /* Thermal Monitor clock slowdown */
640                         "\037IA64"      /* CPU can execute IA64 instructions */
641                         "\040PBE"       /* Pending Break Enable */
642                         );
643
644                         /*
645                          * If this CPU supports hyperthreading then mention
646                          * the number of logical CPU's it contains.
647                          */
648                         if (cpu_feature & CPUID_HTT &&
649                             (cpu_procinfo & CPUID_HTT_CORES) >> 16 > 1)
650                                 printf("\n  Hyperthreading: %d logical CPUs",
651                                     (cpu_procinfo & CPUID_HTT_CORES) >> 16);
652                 }
653                 if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
654                     cpu_exthigh >= 0x80000001)
655                         print_AMD_features();
656         } else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
657                 printf("  DIR=0x%04x", cyrix_did);
658                 printf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
659                 printf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
660 #ifndef CYRIX_CACHE_REALLY_WORKS
661                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
662                         printf("\n  CPU cache: write-through mode");
663 #endif
664         }
665         /* Avoid ugly blank lines: only print newline when we have to. */
666         if (*cpu_vendor || cpu_id)
667                 printf("\n");
668
669 #endif
670         if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
671             strcmp(cpu_vendor, "TransmetaCPU") == 0) {
672                 setup_tmx86_longrun();
673         }
674
675         if (!bootverbose)
676                 return;
677
678         if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
679                 print_AMD_info();
680         else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
681                  strcmp(cpu_vendor, "TransmetaCPU") == 0)
682                 print_transmeta_info();
683
684 #ifdef I686_CPU
685         /*
686          * XXX - Do PPro CPUID level=2 stuff here?
687          *
688          * No, but maybe in a print_Intel_info() function called from here.
689          */
690 #endif
691 }
692
693 void
694 panicifcpuunsupported(void)
695 {
696
697 #if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
698 #error This kernel is not configured for one of the supported CPUs
699 #endif
700         /*
701          * Now that we have told the user what they have,
702          * let them know if that machine type isn't configured.
703          */
704         switch (cpu_class) {
705         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
706 #if !defined(I386_CPU)
707         case CPUCLASS_386:
708 #endif
709 #if !defined(I486_CPU)
710         case CPUCLASS_486:
711 #endif
712 #if !defined(I586_CPU)
713         case CPUCLASS_586:
714 #endif
715 #if !defined(I686_CPU)
716         case CPUCLASS_686:
717 #endif
718                 panic("CPU class not configured");
719         default:
720                 break;
721         }
722 }
723
724
725 static  volatile u_int trap_by_rdmsr;
726
727 /*
728  * Special exception 6 handler.
729  * The rdmsr instruction generates invalid opcodes fault on 486-class
730  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
731  * function identblue() when this handler is called.  Stacked eip should
732  * be advanced.
733  */
734 inthand_t       bluetrap6;
735 __asm
736 ("
737         .text
738         .p2align 2,0x90
739         .type   " __XSTRING(CNAME(bluetrap6)) ",@function
740 " __XSTRING(CNAME(bluetrap6)) ":
741         ss
742         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "
743         addl    $2, (%esp)                # I know rdmsr is a 2-bytes instruction.
744         iret
745 ");
746
747 /*
748  * Special exception 13 handler.
749  * Accessing non-existent MSR generates general protection fault.
750  */
751 inthand_t       bluetrap13;
752 __asm
753 ("
754         .text
755         .p2align 2,0x90
756         .type " __XSTRING(CNAME(bluetrap13)) ",@function
757 " __XSTRING(CNAME(bluetrap13)) ":
758         ss
759         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "
760         popl    %eax                            # discard errorcode.
761         addl    $2, (%esp)                      # I know rdmsr is a 2-bytes instruction.
762         iret
763 ");
764
765 /*
766  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
767  * support cpuid instruction.  This function should be called after
768  * loading interrupt descriptor table register.
769  *
770  * I don't like this method that handles fault, but I couldn't get
771  * information for any other methods.  Does blue giant know?
772  */
773 static int
774 identblue(void)
775 {
776
777         trap_by_rdmsr = 0;
778
779         /*
780          * Cyrix 486-class CPU does not support rdmsr instruction.
781          * The rdmsr instruction generates invalid opcode fault, and exception
782          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
783          * bluetrap6() set the magic number to trap_by_rdmsr.
784          */
785         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
786
787         /*
788          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
789          * In this case, rdmsr generates general protection fault, and
790          * exception will be trapped by bluetrap13().
791          */
792         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
793
794         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
795
796         if (trap_by_rdmsr == 0xa8c1d)
797                 return IDENTBLUE_CYRIX486;
798         else if (trap_by_rdmsr == 0xa89c4)
799                 return IDENTBLUE_CYRIXM2;
800         return IDENTBLUE_IBMCPU;
801 }
802
803
804 /*
805  * identifycyrix() set lower 16 bits of cyrix_did as follows:
806  *
807  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
808  * +-------+-------+---------------+
809  * |  SID  |  RID  |   Device ID   |
810  * |    (DIR 1)    |    (DIR 0)    |
811  * +-------+-------+---------------+
812  */
813 static void
814 identifycyrix(void)
815 {
816         int     ccr2_test = 0, dir_test = 0;
817         u_char  ccr2, ccr3;
818
819         mpintr_lock();
820
821         ccr2 = read_cyrix_reg(CCR2);
822         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
823         read_cyrix_reg(CCR2);
824         if (read_cyrix_reg(CCR2) != ccr2)
825                 ccr2_test = 1;
826         write_cyrix_reg(CCR2, ccr2);
827
828         ccr3 = read_cyrix_reg(CCR3);
829         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
830         read_cyrix_reg(CCR3);
831         if (read_cyrix_reg(CCR3) != ccr3)
832                 dir_test = 1;                                   /* CPU supports DIRs. */
833         write_cyrix_reg(CCR3, ccr3);
834
835         if (dir_test) {
836                 /* Device ID registers are available. */
837                 cyrix_did = read_cyrix_reg(DIR1) << 8;
838                 cyrix_did += read_cyrix_reg(DIR0);
839         } else if (ccr2_test)
840                 cyrix_did = 0x0010;             /* 486S A-step */
841         else
842                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
843
844         mpintr_unlock();
845 }
846
847 /*
848  * Final stage of CPU identification. -- Should I check TI?
849  */
850 void
851 finishidentcpu(void)
852 {
853         int     isblue = 0;
854         u_char  ccr3;
855         u_int   regs[4];
856
857         if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
858                 if (cpu == CPU_486) {
859                         /*
860                          * These conditions are equivalent to:
861                          *     - CPU does not support cpuid instruction.
862                          *     - Cyrix/IBM CPU is detected.
863                          */
864                         isblue = identblue();
865                         if (isblue == IDENTBLUE_IBMCPU) {
866                                 strcpy(cpu_vendor, "IBM");
867                                 cpu = CPU_BLUE;
868                                 return;
869                         }
870                 }
871                 switch (cpu_id & 0xf00) {
872                 case 0x600:
873                         /*
874                          * Cyrix's datasheet does not describe DIRs.
875                          * Therefor, I assume it does not have them
876                          * and use the result of the cpuid instruction.
877                          * XXX they seem to have it for now at least. -Peter
878                          */
879                         identifycyrix();
880                         cpu = CPU_M2;
881                         break;
882                 default:
883                         identifycyrix();
884                         /*
885                          * This routine contains a trick.
886                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
887                          */
888                         switch (cyrix_did & 0x00f0) {
889                         case 0x00:
890                         case 0xf0:
891                                 cpu = CPU_486DLC;
892                                 break;
893                         case 0x10:
894                                 cpu = CPU_CY486DX;
895                                 break;
896                         case 0x20:
897                                 if ((cyrix_did & 0x000f) < 8)
898                                         cpu = CPU_M1;
899                                 else
900                                         cpu = CPU_M1SC;
901                                 break;
902                         case 0x30:
903                                 cpu = CPU_M1;
904                                 break;
905                         case 0x40:
906                                 /* MediaGX CPU */
907                                 cpu = CPU_M1SC;
908                                 break;
909                         default:
910                                 /* M2 and later CPUs are treated as M2. */
911                                 cpu = CPU_M2;
912
913                                 /*
914                                  * enable cpuid instruction.
915                                  */
916                                 ccr3 = read_cyrix_reg(CCR3);
917                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
918                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
919                                 write_cyrix_reg(CCR3, ccr3);
920
921                                 do_cpuid(0, regs);
922                                 cpu_high = regs[0];     /* eax */
923                                 do_cpuid(1, regs);
924                                 cpu_id = regs[0];       /* eax */
925                                 cpu_feature = regs[3];  /* edx */
926                                 break;
927                         }
928                 }
929         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
930                 /*
931                  * There are BlueLightning CPUs that do not change
932                  * undefined flags by dividing 5 by 2.  In this case,
933                  * the CPU identification routine in locore.s leaves
934                  * cpu_vendor null string and puts CPU_486 into the
935                  * cpu.
936                  */
937                 isblue = identblue();
938                 if (isblue == IDENTBLUE_IBMCPU) {
939                         strcpy(cpu_vendor, "IBM");
940                         cpu = CPU_BLUE;
941                         return;
942                 }
943         }
944 }
945
946 static void
947 print_AMD_assoc(int i)
948 {
949         if (i == 255)
950                 printf(", fully associative\n");
951         else
952                 printf(", %d-way associative\n", i);
953 }
954
955 static void
956 print_AMD_info(void)
957 {
958         quad_t amd_whcr;
959
960         if (cpu_exthigh >= 0x80000005) {
961                 u_int regs[4];
962
963                 do_cpuid(0x80000005, regs);
964                 printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
965                 print_AMD_assoc(regs[1] >> 24);
966                 printf("Instruction TLB: %d entries", regs[1] & 0xff);
967                 print_AMD_assoc((regs[1] >> 8) & 0xff);
968                 printf("L1 data cache: %d kbytes", regs[2] >> 24);
969                 printf(", %d bytes/line", regs[2] & 0xff);
970                 printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
971                 print_AMD_assoc((regs[2] >> 16) & 0xff);
972                 printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
973                 printf(", %d bytes/line", regs[3] & 0xff);
974                 printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
975                 print_AMD_assoc((regs[3] >> 16) & 0xff);
976                 if (cpu_exthigh >= 0x80000006) {        /* K6-III only */
977                         do_cpuid(0x80000006, regs);
978                         printf("L2 internal cache: %d kbytes", regs[2] >> 16);
979                         printf(", %d bytes/line", regs[2] & 0xff);
980                         printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
981                         print_AMD_assoc((regs[2] >> 12) & 0x0f);        
982                 }
983         }
984         if (((cpu_id & 0xf00) == 0x500)
985             && (((cpu_id & 0x0f0) > 0x80)
986                 || (((cpu_id & 0x0f0) == 0x80)
987                     && (cpu_id & 0x00f) > 0x07))) {
988                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
989                 amd_whcr = rdmsr(0xc0000082);
990                 if (!(amd_whcr & (0x3ff << 22))) {
991                         printf("Write Allocate Disable\n");
992                 } else {
993                         printf("Write Allocate Enable Limit: %dM bytes\n",
994                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
995                         printf("Write Allocate 15-16M bytes: %s\n",
996                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
997                 }
998         } else if (((cpu_id & 0xf00) == 0x500)
999                    && ((cpu_id & 0x0f0) > 0x50)) {
1000                 /* K6, K6-2(old core) */
1001                 amd_whcr = rdmsr(0xc0000082);
1002                 if (!(amd_whcr & (0x7f << 1))) {
1003                         printf("Write Allocate Disable\n");
1004                 } else {
1005                         printf("Write Allocate Enable Limit: %dM bytes\n",
1006                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1007                         printf("Write Allocate 15-16M bytes: %s\n",
1008                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1009                         printf("Hardware Write Allocate Control: %s\n",
1010                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1011                 }
1012         }
1013 }
1014
1015 #if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
1016 static void
1017 print_AMD_features(void)
1018 {
1019         u_int regs[4];
1020
1021         /*
1022          * Values taken from AMD Processor Recognition
1023          * http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
1024          */
1025         do_cpuid(0x80000001, regs);
1026         printf("\n  AMD Features=0x%b", regs[3] &~ cpu_feature,
1027                 "\020"          /* in hex */
1028                 "\001FPU"       /* Integral FPU */
1029                 "\002VME"       /* Extended VM86 mode support */
1030                 "\003DE"        /* Debug extensions */
1031                 "\004PSE"       /* 4MByte page tables */
1032                 "\005TSC"       /* Timestamp counter */
1033                 "\006MSR"       /* Machine specific registers */
1034                 "\007PAE"       /* Physical address extension */
1035                 "\010MCE"       /* Machine Check support */
1036                 "\011CX8"       /* CMPEXCH8 instruction */
1037                 "\012APIC"      /* SMP local APIC */
1038                 "\013<b10>"
1039                 "\014SYSCALL"   /* SYSENTER/SYSEXIT instructions */
1040                 "\015MTRR"      /* Memory Type Range Registers */
1041                 "\016PGE"       /* PG_G (global bit) support */
1042                 "\017MCA"       /* Machine Check Architecture */
1043                 "\020ICMOV"     /* CMOV instruction */
1044                 "\021PAT"       /* Page attributes table */
1045                 "\022PGE36"     /* 36 bit address space support */
1046                 "\023RSVD"      /* Reserved, unknown */
1047                 "\024MP"        /* Multiprocessor Capable */
1048                 "\025<b20>"
1049                 "\026<b21>"
1050                 "\027AMIE"      /* AMD MMX Instruction Extensions */
1051                 "\030MMX"
1052                 "\031FXSAVE"    /* FXSAVE/FXRSTOR */
1053                 "\032<b25>"
1054                 "\033<b26>"
1055                 "\034<b27>"
1056                 "\035<b28>"
1057                 "\036<b29>"
1058                 "\037DSP"       /* AMD 3DNow! Instruction Extensions */
1059                 "\0403DNow!"
1060                 );
1061 }
1062 #endif
1063
1064 /*
1065  * Transmeta Crusoe LongRun Support by Tamotsu Hattori. 
1066  */
1067
1068 #define MSR_TMx86_LONGRUN               0x80868010
1069 #define MSR_TMx86_LONGRUN_FLAGS         0x80868011
1070
1071 #define LONGRUN_MODE_MASK(x)            ((x) & 0x000000007f)
1072 #define LONGRUN_MODE_RESERVED(x)        ((x) & 0xffffff80)
1073 #define LONGRUN_MODE_WRITE(x, y)        (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
1074
1075 #define LONGRUN_MODE_MINFREQUENCY       0x00
1076 #define LONGRUN_MODE_ECONOMY            0x01
1077 #define LONGRUN_MODE_PERFORMANCE        0x02
1078 #define LONGRUN_MODE_MAXFREQUENCY       0x03
1079 #define LONGRUN_MODE_UNKNOWN            0x04
1080 #define LONGRUN_MODE_MAX                0x04
1081
1082 union msrinfo {
1083         u_int64_t       msr;
1084         u_int32_t       regs[2];
1085 };
1086
1087 u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
1088         /*  MSR low, MSR high, flags bit0 */
1089         {         0,      0,            0},     /* LONGRUN_MODE_MINFREQUENCY */
1090         {         0,    100,            0},     /* LONGRUN_MODE_ECONOMY */
1091         {         0,    100,            1},     /* LONGRUN_MODE_PERFORMANCE */
1092         {       100,    100,            1},     /* LONGRUN_MODE_MAXFREQUENCY */
1093 };
1094
1095 static u_int 
1096 tmx86_get_longrun_mode(void)
1097 {
1098         union msrinfo   msrinfo;
1099         u_int           low, high, flags, mode;
1100
1101         mpintr_lock();
1102
1103         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1104         low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
1105         high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
1106         flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
1107
1108         for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
1109                 if (low   == longrun_modes[mode][0] &&
1110                     high  == longrun_modes[mode][1] &&
1111                     flags == longrun_modes[mode][2]) {
1112                         goto out;
1113                 }
1114         }
1115         mode = LONGRUN_MODE_UNKNOWN;
1116 out:
1117         mpintr_unlock();
1118         return (mode);
1119 }
1120
1121 static u_int 
1122 tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
1123 {
1124         u_int           regs[4];
1125
1126         mpintr_lock();
1127
1128         do_cpuid(0x80860007, regs);
1129         *frequency = regs[0];
1130         *voltage = regs[1];
1131         *percentage = regs[2];
1132
1133         mpintr_unlock();
1134         return (1);
1135 }
1136
1137 static u_int 
1138 tmx86_set_longrun_mode(u_int mode)
1139 {
1140         union msrinfo   msrinfo;
1141
1142         if (mode >= LONGRUN_MODE_UNKNOWN) {
1143                 return (0);
1144         }
1145
1146         mpintr_lock();
1147
1148         /* Write LongRun mode values to Model Specific Register. */
1149         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
1150         msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
1151                                              longrun_modes[mode][0]);
1152         msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
1153                                              longrun_modes[mode][1]);
1154         wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
1155
1156         /* Write LongRun mode flags to Model Specific Register. */
1157         msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
1158         msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
1159         wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
1160
1161         mpintr_unlock();
1162         return (1);
1163 }
1164
1165 static u_int                     crusoe_longrun;
1166 static u_int                     crusoe_frequency;
1167 static u_int                     crusoe_voltage;
1168 static u_int                     crusoe_percentage;
1169 static struct sysctl_ctx_list    crusoe_sysctl_ctx;
1170 static struct sysctl_oid        *crusoe_sysctl_tree;
1171
1172 static int
1173 tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
1174 {
1175         u_int   mode;
1176         int     error;
1177
1178         crusoe_longrun = tmx86_get_longrun_mode();
1179         mode = crusoe_longrun;
1180         error = sysctl_handle_int(oidp, &mode, 0, req);
1181         if (error || !req->newptr) {
1182                 return (error);
1183         }
1184         if (mode >= LONGRUN_MODE_UNKNOWN) {
1185                 error = EINVAL;
1186                 return (error);
1187         }
1188         if (crusoe_longrun != mode) {
1189                 crusoe_longrun = mode;
1190                 tmx86_set_longrun_mode(crusoe_longrun);
1191         }
1192
1193         return (error);
1194 }
1195
1196 static int
1197 tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
1198 {
1199         u_int   val;
1200         int     error;
1201
1202         tmx86_get_longrun_status(&crusoe_frequency,
1203                                  &crusoe_voltage, &crusoe_percentage);
1204         val = *(u_int *)oidp->oid_arg1;
1205         error = sysctl_handle_int(oidp, &val, 0, req);
1206         return (error);
1207 }
1208
1209 static void
1210 setup_tmx86_longrun(void)
1211 {
1212         static int      done = 0;
1213
1214         if (done)
1215                 return;
1216         done++;
1217
1218         sysctl_ctx_init(&crusoe_sysctl_ctx);
1219         crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
1220                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1221                                 "crusoe", CTLFLAG_RD, 0,
1222                                 "Transmeta Crusoe LongRun support");
1223         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1224                 OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
1225                 &crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
1226                 "LongRun mode [0-3]");
1227         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1228                 OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
1229                 &crusoe_frequency, 0, tmx86_status_sysctl, "I",
1230                 "Current frequency (MHz)");
1231         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1232                 OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
1233                 &crusoe_voltage, 0, tmx86_status_sysctl, "I",
1234                 "Current voltage (mV)");
1235         SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
1236                 OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
1237                 &crusoe_percentage, 0, tmx86_status_sysctl, "I",
1238                 "Processing performance (%)");
1239 }
1240
1241 static void
1242 print_transmeta_info()
1243 {
1244         u_int regs[4], nreg = 0;
1245
1246         do_cpuid(0x80860000, regs);
1247         nreg = regs[0];
1248         if (nreg >= 0x80860001) {
1249                 do_cpuid(0x80860001, regs);
1250                 printf("  Processor revision %u.%u.%u.%u\n",
1251                        (regs[1] >> 24) & 0xff,
1252                        (regs[1] >> 16) & 0xff,
1253                        (regs[1] >> 8) & 0xff,
1254                        regs[1] & 0xff);
1255         }
1256         if (nreg >= 0x80860002) {
1257                 do_cpuid(0x80860002, regs);
1258                 printf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1259                        (regs[1] >> 24) & 0xff,
1260                        (regs[1] >> 16) & 0xff,
1261                        (regs[1] >> 8) & 0xff,
1262                        regs[1] & 0xff,
1263                        regs[2]);
1264         }
1265         if (nreg >= 0x80860006) {
1266                 char info[65];
1267                 do_cpuid(0x80860003, (u_int*) &info[0]);
1268                 do_cpuid(0x80860004, (u_int*) &info[16]);
1269                 do_cpuid(0x80860005, (u_int*) &info[32]);
1270                 do_cpuid(0x80860006, (u_int*) &info[48]);
1271                 info[64] = 0;
1272                 printf("  %s\n", info);
1273         }
1274
1275         crusoe_longrun = tmx86_get_longrun_mode();
1276         tmx86_get_longrun_status(&crusoe_frequency,
1277                                  &crusoe_voltage, &crusoe_percentage);
1278         printf("  LongRun mode: %d  <%dMHz %dmV %d%%>\n", crusoe_longrun,
1279                crusoe_frequency, crusoe_voltage, crusoe_percentage);
1280 }
1281