2 * Copyright 1996 Massachusetts Institute of Technology
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5 * its documentation for any purpose and without fee is hereby
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29 * $FreeBSD: src/sys/i386/i386/perfmon.c,v 1.21 1999/09/25 18:24:04 phk Exp $
30 * $DragonFly: src/sys/i386/i386/Attic/perfmon.c,v 1.4 2003/07/06 21:23:48 dillon Exp $
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/fcntl.h>
39 #include <machine/cputypes.h>
41 #include <machine/clock.h>
42 #include <machine/perfmon.h>
44 static int perfmon_inuse;
45 static int perfmon_cpuok;
47 static int msr_ctl[NPMC];
49 static int msr_pmc[NPMC];
50 static unsigned int ctl_shadow[NPMC];
51 static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
52 static int (*writectl)(int);
54 static int writectl5(int);
55 static int writectl6(int);
58 static d_close_t perfmon_close;
59 static d_open_t perfmon_open;
60 static d_ioctl_t perfmon_ioctl;
62 #define CDEV_MAJOR 2 /* We're really a minor of mem.c */
63 static struct cdevsw perfmon_cdevsw = {
64 /* open */ perfmon_open,
65 /* close */ perfmon_close,
68 /* ioctl */ perfmon_ioctl,
71 /* strategy */ nostrategy,
81 * Must be called after cpu_class is set up.
102 writectl = writectl6;
110 make_dev(&perfmon_cdevsw, 32, UID_ROOT, GID_KMEM, 0640, "perfmon");
116 return perfmon_cpuok;
120 perfmon_setup(int pmc, unsigned int control)
122 if (pmc < 0 || pmc >= NPMC)
125 perfmon_inuse |= (1 << pmc);
126 control &= ~(PMCF_SYS_FLAGS << 16);
127 mpintr_lock(); /* doesn't have to be mpintr_lock YYY */
128 ctl_shadow[pmc] = control;
130 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
136 perfmon_get(int pmc, unsigned int *control)
138 if (pmc < 0 || pmc >= NPMC)
141 if (perfmon_inuse & (1 << pmc)) {
142 *control = ctl_shadow[pmc];
145 return EBUSY; /* XXX reversed sense */
149 perfmon_fini(int pmc)
151 if (pmc < 0 || pmc >= NPMC)
154 if (perfmon_inuse & (1 << pmc)) {
157 perfmon_inuse &= ~(1 << pmc);
160 return EBUSY; /* XXX reversed sense */
164 perfmon_start(int pmc)
166 if (pmc < 0 || pmc >= NPMC)
169 if (perfmon_inuse & (1 << pmc)) {
170 mpintr_lock(); /* doesn't have to be mpintr YYY */
171 ctl_shadow[pmc] |= (PMCF_EN << 16);
172 wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
181 perfmon_stop(int pmc)
183 if (pmc < 0 || pmc >= NPMC)
186 if (perfmon_inuse & (1 << pmc)) {
188 pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
189 ctl_shadow[pmc] &= ~(PMCF_EN << 16);
198 perfmon_read(int pmc, quad_t *val)
200 if (pmc < 0 || pmc >= NPMC)
203 if (perfmon_inuse & (1 << pmc)) {
204 if (ctl_shadow[pmc] & (PMCF_EN << 16))
205 *val = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
207 *val = pmc_shadow[pmc];
215 perfmon_reset(int pmc)
217 if (pmc < 0 || pmc >= NPMC)
220 if (perfmon_inuse & (1 << pmc)) {
221 wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
229 * Unfortunately, the performance-monitoring registers are laid out
230 * differently in the P5 and P6. We keep everything in P6 format
231 * internally (except for the event code), and convert to P5
232 * format as needed on those CPUs. The writectl function pointer
233 * is set up to point to one of these functions by perfmon_init().
238 if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
239 wrmsr(msr_ctl[pmc], 0);
241 wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
246 #define P5FLAG_P 0x200
247 #define P5FLAG_E 0x100
248 #define P5FLAG_USR 0x80
249 #define P5FLAG_OS 0x40
256 if (ctl_shadow[1] & (PMCF_EN << 16)) {
257 if (ctl_shadow[1] & (PMCF_USR << 16))
258 newval |= P5FLAG_USR << 16;
259 if (ctl_shadow[1] & (PMCF_OS << 16))
260 newval |= P5FLAG_OS << 16;
261 if (!(ctl_shadow[1] & (PMCF_E << 16)))
262 newval |= P5FLAG_E << 16;
263 newval |= (ctl_shadow[1] & 0x3f) << 16;
265 if (ctl_shadow[0] & (PMCF_EN << 16)) {
266 if (ctl_shadow[0] & (PMCF_USR << 16))
267 newval |= P5FLAG_USR;
268 if (ctl_shadow[0] & (PMCF_OS << 16))
270 if (!(ctl_shadow[0] & (PMCF_E << 16)))
272 newval |= ctl_shadow[0] & 0x3f;
275 wrmsr(msr_ctl[0], newval);
276 return 0; /* XXX should check for unimplemented bits */
281 * Now the user-mode interface, called from a subdevice of mem.c.
284 static int writerpmc;
287 perfmon_open(dev_t dev, int flags, int fmt, struct thread *td)
292 if (flags & FWRITE) {
304 perfmon_close(dev_t dev, int flags, int fmt, struct thread *td)
306 if (flags & FWRITE) {
309 for (i = 0; i < NPMC; i++) {
310 if (writerpmc & (1 << i))
319 perfmon_ioctl(dev_t dev, u_long cmd, caddr_t param, int flags, struct thread *td)
322 struct pmc_data *pmcd;
323 struct pmc_tstamp *pmct;
329 if (!(flags & FWRITE))
331 pmc = (struct pmc *)param;
333 rv = perfmon_setup(pmc->pmc_num, pmc->pmc_val);
335 writerpmc |= (1 << pmc->pmc_num);
340 pmc = (struct pmc *)param;
341 rv = perfmon_get(pmc->pmc_num, &pmc->pmc_val);
345 if (!(flags & FWRITE))
349 rv = perfmon_start(*ip);
353 if (!(flags & FWRITE))
357 rv = perfmon_stop(*ip);
361 if (!(flags & FWRITE))
365 rv = perfmon_reset(*ip);
369 pmcd = (struct pmc_data *)param;
370 rv = perfmon_read(pmcd->pmcd_num, &pmcd->pmcd_value);
378 pmct = (struct pmc_tstamp *)param;
379 /* XXX interface loses precision. */
380 pmct->pmct_rate = tsc_freq / 1000000;
381 pmct->pmct_value = rdtsc();