2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $FreeBSD: src/sys/i386/i386/initcpu.c,v 1.19.2.9 2003/04/05 13:47:19 dwmalone Exp $
30 * $DragonFly: src/sys/platform/pc32/i386/initcpu.c,v 1.3 2003/07/06 21:23:48 dillon Exp $
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
44 void initializecpu(void);
45 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
46 void enable_K5_wt_alloc(void);
47 void enable_K6_wt_alloc(void);
48 void enable_K6_2_wt_alloc(void);
52 static void init_5x86(void);
53 static void init_bluelightning(void);
54 static void init_486dlc(void);
55 static void init_cy486dx(void);
56 #ifdef CPU_I486_ON_386
57 static void init_i486_on_386(void);
59 static void init_6x86(void);
63 static void init_6x86MX(void);
64 static void init_ppro(void);
65 static void init_mendocino(void);
68 static int hw_instruction_sse;
69 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
70 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
73 u_int cpu_fxsr; /* SSE enabled */
81 init_bluelightning(void)
85 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
86 need_post_dma_flush = 1;
89 eflags = read_eflags();
92 load_cr0(rcr0() | CR0_CD | CR0_NW);
95 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
96 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
98 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
100 /* Enables 13MB and 0-640KB cache. */
101 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
102 #ifdef CPU_BLUELIGHTNING_3X
103 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
105 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
108 /* Enable caching in CR0. */
109 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
111 write_eflags(eflags);
115 * Cyrix 486SLC/DLC/SR/DR series
123 eflags = read_eflags();
127 ccr0 = read_cyrix_reg(CCR0);
128 #ifndef CYRIX_CACHE_WORKS
129 ccr0 |= CCR0_NC1 | CCR0_BARB;
130 write_cyrix_reg(CCR0, ccr0);
134 #ifndef CYRIX_CACHE_REALLY_WORKS
135 ccr0 |= CCR0_NC1 | CCR0_BARB;
139 #ifdef CPU_DIRECT_MAPPED_CACHE
140 ccr0 |= CCR0_CO; /* Direct mapped mode. */
142 write_cyrix_reg(CCR0, ccr0);
144 /* Clear non-cacheable region. */
145 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
146 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
147 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
148 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
150 write_cyrix_reg(0, 0); /* dummy write */
152 /* Enable caching in CR0. */
153 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
155 #endif /* !CYRIX_CACHE_WORKS */
156 write_eflags(eflags);
161 * Cyrix 486S/DX series
169 eflags = read_eflags();
173 ccr2 = read_cyrix_reg(CCR2);
175 ccr2 |= CCR2_SUSP_HLT;
179 /* Enables WB cache interface pin and Lock NW bit in CR0. */
180 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
181 /* Unlock NW bit in CR0. */
182 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
183 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
186 write_cyrix_reg(CCR2, ccr2);
187 write_eflags(eflags);
198 u_char ccr2, ccr3, ccr4, pcr0;
200 eflags = read_eflags();
203 load_cr0(rcr0() | CR0_CD | CR0_NW);
206 (void)read_cyrix_reg(CCR3); /* dummy */
208 /* Initialize CCR2. */
209 ccr2 = read_cyrix_reg(CCR2);
212 ccr2 |= CCR2_SUSP_HLT;
214 ccr2 &= ~CCR2_SUSP_HLT;
217 write_cyrix_reg(CCR2, ccr2);
219 /* Initialize CCR4. */
220 ccr3 = read_cyrix_reg(CCR3);
221 write_cyrix_reg(CCR3, CCR3_MAPEN0);
223 ccr4 = read_cyrix_reg(CCR4);
226 #ifdef CPU_FASTER_5X86_FPU
227 ccr4 |= CCR4_FASTFPE;
229 ccr4 &= ~CCR4_FASTFPE;
231 ccr4 &= ~CCR4_IOMASK;
232 /********************************************************************
233 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
234 * should be 0 for errata fix.
235 ********************************************************************/
237 ccr4 |= CPU_IORT & CCR4_IOMASK;
239 write_cyrix_reg(CCR4, ccr4);
241 /* Initialize PCR0. */
242 /****************************************************************
243 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
244 * BTB_EN might make your system unstable.
245 ****************************************************************/
246 pcr0 = read_cyrix_reg(PCR0);
263 /****************************************************************
264 * WARNING: if you use a memory mapped I/O device, don't use
265 * DISABLE_5X86_LSSER option, which may reorder memory mapped
267 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
268 ****************************************************************/
269 #ifdef CPU_DISABLE_5X86_LSSER
274 write_cyrix_reg(PCR0, pcr0);
277 write_cyrix_reg(CCR3, ccr3);
279 (void)read_cyrix_reg(0x80); /* dummy */
281 /* Unlock NW bit in CR0. */
282 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
283 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
284 /* Lock NW bit in CR0. */
285 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
287 write_eflags(eflags);
290 #ifdef CPU_I486_ON_386
292 * There are i486 based upgrade products for i386 machines.
293 * In this case, BIOS doesn't enables CPU cache.
296 init_i486_on_386(void)
300 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
301 need_post_dma_flush = 1;
304 eflags = read_eflags();
307 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
309 write_eflags(eflags);
316 * XXX - What should I do here? Please let me know.
324 eflags = read_eflags();
327 load_cr0(rcr0() | CR0_CD | CR0_NW);
330 /* Initialize CCR0. */
331 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
333 /* Initialize CCR1. */
334 #ifdef CPU_CYRIX_NO_LOCK
335 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
337 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
340 /* Initialize CCR2. */
342 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
344 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
347 ccr3 = read_cyrix_reg(CCR3);
348 write_cyrix_reg(CCR3, CCR3_MAPEN0);
350 /* Initialize CCR4. */
351 ccr4 = read_cyrix_reg(CCR4);
353 ccr4 &= ~CCR4_IOMASK;
355 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
357 write_cyrix_reg(CCR4, ccr4 | 7);
360 /* Initialize CCR5. */
362 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
366 write_cyrix_reg(CCR3, ccr3);
368 /* Unlock NW bit in CR0. */
369 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
372 * Earlier revision of the 6x86 CPU could crash the system if
373 * L1 cache is in write-back mode.
375 if ((cyrix_did & 0xff00) > 0x1600)
376 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
378 /* Revision 2.6 and lower. */
379 #ifdef CYRIX_CACHE_REALLY_WORKS
380 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
382 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
386 /* Lock NW bit in CR0. */
387 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
389 write_eflags(eflags);
391 #endif /* I486_CPU */
395 * Cyrix 6x86MX (code-named M2)
397 * XXX - What should I do here? Please let me know.
405 eflags = read_eflags();
408 load_cr0(rcr0() | CR0_CD | CR0_NW);
411 /* Initialize CCR0. */
412 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
414 /* Initialize CCR1. */
415 #ifdef CPU_CYRIX_NO_LOCK
416 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
418 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
421 /* Initialize CCR2. */
423 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
425 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
428 ccr3 = read_cyrix_reg(CCR3);
429 write_cyrix_reg(CCR3, CCR3_MAPEN0);
431 /* Initialize CCR4. */
432 ccr4 = read_cyrix_reg(CCR4);
433 ccr4 &= ~CCR4_IOMASK;
435 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
437 write_cyrix_reg(CCR4, ccr4 | 7);
440 /* Initialize CCR5. */
442 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
446 write_cyrix_reg(CCR3, ccr3);
448 /* Unlock NW bit in CR0. */
449 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
451 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
453 /* Lock NW bit in CR0. */
454 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
456 write_eflags(eflags);
466 * Local APIC should be diabled in UP kernel.
468 apicbase = rdmsr(0x1b);
469 apicbase &= ~0x800LL;
470 wrmsr(0x1b, apicbase);
475 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
481 #ifdef CPU_PPRO2CELERON
483 u_int64_t bbl_cr_ctl3;
485 eflags = read_eflags();
488 load_cr0(rcr0() | CR0_CD | CR0_NW);
491 bbl_cr_ctl3 = rdmsr(0x11e);
493 /* If the L2 cache is configured, do nothing. */
494 if (!(bbl_cr_ctl3 & 1)) {
495 bbl_cr_ctl3 = 0x134052bLL;
497 /* Set L2 Cache Latency (Default: 5). */
498 #ifdef CPU_CELERON_L2_LATENCY
499 #if CPU_L2_LATENCY > 15
500 #error invalid CPU_L2_LATENCY.
502 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
504 bbl_cr_ctl3 |= 5 << 1;
506 wrmsr(0x11e, bbl_cr_ctl3);
509 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
510 write_eflags(eflags);
511 #endif /* CPU_PPRO2CELERON */
514 #endif /* I686_CPU */
517 * Initialize CR4 (Control register 4) to enable SSE instructions.
522 #if defined(CPU_ENABLE_SSE)
523 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
524 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
525 cpu_fxsr = hw_instruction_sse = 1;
537 init_bluelightning();
548 #ifdef CPU_I486_ON_386
556 #endif /* I486_CPU */
562 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
563 switch (cpu_id & 0xff0) {
571 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
572 #if defined(I686_CPU) && defined(CPU_ATHLON_SSE_HACK)
574 * Sometimes the BIOS doesn't enable SSE instructions.
575 * According to AMD document 20734, the mobile
576 * Duron, the (mobile) Athlon 4 and the Athlon MP
577 * support SSE. These correspond to cpu_id 0x66X
580 if ((cpu_feature & CPUID_XMM) == 0 &&
581 ((cpu_id & ~0xf) == 0x660 ||
582 (cpu_id & ~0xf) == 0x670 ||
583 (cpu_id & ~0xf) == 0x680)) {
585 wrmsr(0xC0010015, rdmsr(0xC0010015) & ~0x08000);
587 cpu_feature = regs[3];
598 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
600 * OS should flush L1 cache by itself because no PC-98 supports
601 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
602 * when need_pre_dma_flush = 1, use invd instruction after DMA
603 * transfer when need_post_dma_flush = 1. If your CPU upgrade
604 * product supports hardware cache control, you can add the
605 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
606 * This option eliminates unneeded cache flush instruction(s).
608 if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
612 need_post_dma_flush = 1;
615 need_pre_dma_flush = 1;
618 need_pre_dma_flush = 1;
619 #ifdef CPU_I486_ON_386
620 need_post_dma_flush = 1;
627 } else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
628 switch (cpu_id & 0xFF0) {
629 case 0x470: /* Enhanced Am486DX2 WB */
630 case 0x490: /* Enhanced Am486DX4 WB */
631 case 0x4F0: /* Am5x86 WB */
632 need_pre_dma_flush = 1;
635 } else if (strcmp(cpu_vendor, "IBM") == 0) {
636 need_post_dma_flush = 1;
638 #ifdef CPU_I486_ON_386
639 need_pre_dma_flush = 1;
642 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
645 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
647 * Enable write allocate feature of AMD processors.
648 * Following two functions require the Maxmem variable being set.
651 enable_K5_wt_alloc(void)
656 * Write allocate is supported only on models 1, 2, and 3, with
657 * a stepping of 4 or greater.
659 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
661 msr = rdmsr(0x83); /* HWCR */
662 wrmsr(0x83, msr & !(0x10));
665 * We have to tell the chip where the top of memory is,
666 * since video cards could have frame bufferes there,
667 * memory-mapped I/O could be there, etc.
673 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
675 if (!(inb(0x43b) & 4)) {
676 wrmsr(0x86, 0x0ff00f0);
677 msr |= AMD_WT_ALLOC_PRE;
681 * There is no way to know wheter 15-16M hole exists or not.
682 * Therefore, we disable write allocate for this range.
684 wrmsr(0x86, 0x0ff00f0);
685 msr |= AMD_WT_ALLOC_PRE;
690 wrmsr(0x83, msr|0x10); /* enable write allocate */
697 enable_K6_wt_alloc(void)
703 eflags = read_eflags();
707 #ifdef CPU_DISABLE_CACHE
709 * Certain K6-2 box becomes unstable when write allocation is
713 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
714 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
715 * All other bits in TR12 have no effect on the processer's operation.
716 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
719 wrmsr(0x0000000e, (u_int64_t)0x0008);
721 /* Don't assume that memory size is aligned with 4M. */
723 size = ((Maxmem >> 8) + 3) >> 2;
727 /* Limit is 508M bytes. */
730 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
732 #if defined(PC98) || defined(NO_MEMORY_HOLE)
733 if (whcr & (0x7fLL << 1)) {
736 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
739 if (!(inb(0x43b) & 4))
747 * There is no way to know wheter 15-16M hole exists or not.
748 * Therefore, we disable write allocate for this range.
752 wrmsr(0x0c0000082, whcr);
754 write_eflags(eflags);
759 enable_K6_2_wt_alloc(void)
765 eflags = read_eflags();
769 #ifdef CPU_DISABLE_CACHE
771 * Certain K6-2 box becomes unstable when write allocation is
775 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
776 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
777 * All other bits in TR12 have no effect on the processer's operation.
778 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
781 wrmsr(0x0000000e, (u_int64_t)0x0008);
783 /* Don't assume that memory size is aligned with 4M. */
785 size = ((Maxmem >> 8) + 3) >> 2;
789 /* Limit is 4092M bytes. */
792 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
794 #if defined(PC98) || defined(NO_MEMORY_HOLE)
795 if (whcr & (0x3ffLL << 22)) {
798 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
801 if (!(inb(0x43b) & 4))
802 whcr &= ~(1LL << 16);
809 * There is no way to know wheter 15-16M hole exists or not.
810 * Therefore, we disable write allocate for this range.
812 whcr &= ~(1LL << 16);
814 wrmsr(0x0c0000082, whcr);
816 write_eflags(eflags);
819 #endif /* I585_CPU && CPU_WT_ALLOC */
825 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
829 u_char ccr1, ccr2, ccr3;
830 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
833 if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
834 eflags = read_eflags();
838 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
839 ccr0 = read_cyrix_reg(CCR0);
841 ccr1 = read_cyrix_reg(CCR1);
842 ccr2 = read_cyrix_reg(CCR2);
843 ccr3 = read_cyrix_reg(CCR3);
844 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
845 write_cyrix_reg(CCR3, CCR3_MAPEN0);
846 ccr4 = read_cyrix_reg(CCR4);
847 if ((cpu == CPU_M1) || (cpu == CPU_M2))
848 ccr5 = read_cyrix_reg(CCR5);
850 pcr0 = read_cyrix_reg(PCR0);
851 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
853 write_eflags(eflags);
855 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
856 printf("CCR0=%x, ", (u_int)ccr0);
858 printf("CCR1=%x, CCR2=%x, CCR3=%x",
859 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
860 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
861 printf(", CCR4=%x, ", (u_int)ccr4);
863 printf("PCR0=%x\n", pcr0);
865 printf("CCR5=%x\n", ccr5);
868 printf("CR0=%x\n", cr0);