bnx: Properly setup TX ring prod index position
[dragonfly.git] / sys / dev / netif / bnx / if_bnx.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 #include "opt_bnx.h"
37 #include "opt_ifpoll.h"
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
44 #include <sys/mbuf.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
47 #include <sys/rman.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
52
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/vlan/if_vlan_var.h>
66 #include <net/vlan/if_vlan_ether.h>
67
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/mii_layer/brgphyreg.h>
71
72 #include <bus/pci/pcidevs.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75
76 #include <dev/netif/bge/if_bgereg.h>
77 #include <dev/netif/bnx/if_bnxvar.h>
78
79 /* "device miibus" required.  See GENERIC if you get errors here. */
80 #include "miibus_if.h"
81
82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
83
84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
85
86 static const struct bnx_type {
87         uint16_t                bnx_vid;
88         uint16_t                bnx_did;
89         char                    *bnx_name;
90 } bnx_devs[] = {
91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
92                 "Broadcom BCM5717 Gigabit Ethernet" },
93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
94                 "Broadcom BCM5717C Gigabit Ethernet" },
95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
96                 "Broadcom BCM5718 Gigabit Ethernet" },
97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
98                 "Broadcom BCM5719 Gigabit Ethernet" },
99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
100                 "Broadcom BCM5720 Gigabit Ethernet" },
101
102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
103                 "Broadcom BCM5725 Gigabit Ethernet" },
104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
105                 "Broadcom BCM5727 Gigabit Ethernet" },
106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
107                 "Broadcom BCM5762 Gigabit Ethernet" },
108
109         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
110                 "Broadcom BCM57761 Gigabit Ethernet" },
111         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
112                 "Broadcom BCM57762 Gigabit Ethernet" },
113         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
114                 "Broadcom BCM57765 Gigabit Ethernet" },
115         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
116                 "Broadcom BCM57766 Gigabit Ethernet" },
117         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
118                 "Broadcom BCM57781 Gigabit Ethernet" },
119         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
120                 "Broadcom BCM57782 Gigabit Ethernet" },
121         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
122                 "Broadcom BCM57785 Gigabit Ethernet" },
123         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
124                 "Broadcom BCM57786 Gigabit Ethernet" },
125         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
126                 "Broadcom BCM57791 Fast Ethernet" },
127         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
128                 "Broadcom BCM57795 Fast Ethernet" },
129
130         { 0, 0, NULL }
131 };
132
133 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
134 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
135 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
136 #define BNX_IS_57765_FAMILY(sc)  \
137         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
138
139 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
140
141 static int      bnx_probe(device_t);
142 static int      bnx_attach(device_t);
143 static int      bnx_detach(device_t);
144 static void     bnx_shutdown(device_t);
145 static int      bnx_suspend(device_t);
146 static int      bnx_resume(device_t);
147 static int      bnx_miibus_readreg(device_t, int, int);
148 static int      bnx_miibus_writereg(device_t, int, int, int);
149 static void     bnx_miibus_statchg(device_t);
150
151 #ifdef IFPOLL_ENABLE
152 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
153 static void     bnx_npoll_compat(struct ifnet *, void *, int);
154 #endif
155 static void     bnx_intr_legacy(void *);
156 static void     bnx_msi(void *);
157 static void     bnx_msi_oneshot(void *);
158 static void     bnx_intr(struct bnx_softc *);
159 static void     bnx_enable_intr(struct bnx_softc *);
160 static void     bnx_disable_intr(struct bnx_softc *);
161 static void     bnx_txeof(struct bnx_tx_ring *, uint16_t);
162 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
163
164 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
165 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
166 static void     bnx_init(void *);
167 static void     bnx_stop(struct bnx_softc *);
168 static void     bnx_watchdog(struct ifnet *);
169 static int      bnx_ifmedia_upd(struct ifnet *);
170 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
171 static void     bnx_tick(void *);
172
173 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
174 static void     bnx_free_jumbo_mem(struct bnx_softc *);
175 static struct bnx_jslot
176                 *bnx_jalloc(struct bnx_softc *);
177 static void     bnx_jfree(void *);
178 static void     bnx_jref(void *);
179 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
180 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
181 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
182 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
183 static int      bnx_init_rx_ring_std(struct bnx_softc *);
184 static void     bnx_free_rx_ring_std(struct bnx_softc *);
185 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
186 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
187 static void     bnx_free_tx_ring(struct bnx_tx_ring *);
188 static int      bnx_init_tx_ring(struct bnx_tx_ring *);
189 static int      bnx_create_tx_ring(struct bnx_tx_ring *);
190 static void     bnx_destroy_tx_ring(struct bnx_tx_ring *);
191 static int      bnx_dma_alloc(struct bnx_softc *);
192 static void     bnx_dma_free(struct bnx_softc *);
193 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
194                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
195 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
196 static struct mbuf *
197                 bnx_defrag_shortdma(struct mbuf *);
198 static int      bnx_encap(struct bnx_tx_ring *, struct mbuf **,
199                     uint32_t *, int *);
200 static int      bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
201                     uint16_t *, uint16_t *);
202
203 static void     bnx_reset(struct bnx_softc *);
204 static int      bnx_chipinit(struct bnx_softc *);
205 static int      bnx_blockinit(struct bnx_softc *);
206 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
207 static void     bnx_enable_msi(struct bnx_softc *sc);
208 static void     bnx_setmulti(struct bnx_softc *);
209 static void     bnx_setpromisc(struct bnx_softc *);
210 static void     bnx_stats_update_regs(struct bnx_softc *);
211 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
212
213 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
214 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
215 #ifdef notdef
216 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
217 #endif
218 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
219 static void     bnx_writembx(struct bnx_softc *, int, int);
220 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
221 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
222 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
223
224 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
225 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
226 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
227 static void     bnx_link_poll(struct bnx_softc *);
228
229 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
230 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
231 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
232 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
233
234 static void     bnx_coal_change(struct bnx_softc *);
235 static int      bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
236 static int      bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
237 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
238 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
239 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
240 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
241 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
242 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
243 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
244                     int, int, uint32_t);
245
246 static int      bnx_msi_enable = 1;
247 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
248
249 static device_method_t bnx_methods[] = {
250         /* Device interface */
251         DEVMETHOD(device_probe,         bnx_probe),
252         DEVMETHOD(device_attach,        bnx_attach),
253         DEVMETHOD(device_detach,        bnx_detach),
254         DEVMETHOD(device_shutdown,      bnx_shutdown),
255         DEVMETHOD(device_suspend,       bnx_suspend),
256         DEVMETHOD(device_resume,        bnx_resume),
257
258         /* bus interface */
259         DEVMETHOD(bus_print_child,      bus_generic_print_child),
260         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
261
262         /* MII interface */
263         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
264         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
265         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
266
267         DEVMETHOD_END
268 };
269
270 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
271 static devclass_t bnx_devclass;
272
273 DECLARE_DUMMY_MODULE(if_bnx);
274 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
275 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
276
277 static uint32_t
278 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
279 {
280         device_t dev = sc->bnx_dev;
281         uint32_t val;
282
283         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
284         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
285         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
286         return (val);
287 }
288
289 static void
290 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
291 {
292         device_t dev = sc->bnx_dev;
293
294         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
295         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
296         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
297 }
298
299 static void
300 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
301 {
302         CSR_WRITE_4(sc, off, val);
303 }
304
305 static void
306 bnx_writembx(struct bnx_softc *sc, int off, int val)
307 {
308         CSR_WRITE_4(sc, off, val);
309 }
310
311 /*
312  * Read a sequence of bytes from NVRAM.
313  */
314 static int
315 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
316 {
317         return (1);
318 }
319
320 /*
321  * Read a byte of data stored in the EEPROM at address 'addr.' The
322  * BCM570x supports both the traditional bitbang interface and an
323  * auto access interface for reading the EEPROM. We use the auto
324  * access method.
325  */
326 static uint8_t
327 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
328 {
329         int i;
330         uint32_t byte = 0;
331
332         /*
333          * Enable use of auto EEPROM access so we can avoid
334          * having to use the bitbang method.
335          */
336         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
337
338         /* Reset the EEPROM, load the clock period. */
339         CSR_WRITE_4(sc, BGE_EE_ADDR,
340             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
341         DELAY(20);
342
343         /* Issue the read EEPROM command. */
344         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
345
346         /* Wait for completion */
347         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
348                 DELAY(10);
349                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
350                         break;
351         }
352
353         if (i == BNX_TIMEOUT) {
354                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
355                 return(1);
356         }
357
358         /* Get result. */
359         byte = CSR_READ_4(sc, BGE_EE_DATA);
360
361         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
362
363         return(0);
364 }
365
366 /*
367  * Read a sequence of bytes from the EEPROM.
368  */
369 static int
370 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
371 {
372         size_t i;
373         int err;
374         uint8_t byte;
375
376         for (byte = 0, err = 0, i = 0; i < len; i++) {
377                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
378                 if (err)
379                         break;
380                 *(dest + i) = byte;
381         }
382
383         return(err ? 1 : 0);
384 }
385
386 static int
387 bnx_miibus_readreg(device_t dev, int phy, int reg)
388 {
389         struct bnx_softc *sc = device_get_softc(dev);
390         uint32_t val;
391         int i;
392
393         KASSERT(phy == sc->bnx_phyno,
394             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
395
396         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
397         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
398                 CSR_WRITE_4(sc, BGE_MI_MODE,
399                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
400                 DELAY(80);
401         }
402
403         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
404             BGE_MIPHY(phy) | BGE_MIREG(reg));
405
406         /* Poll for the PHY register access to complete. */
407         for (i = 0; i < BNX_TIMEOUT; i++) {
408                 DELAY(10);
409                 val = CSR_READ_4(sc, BGE_MI_COMM);
410                 if ((val & BGE_MICOMM_BUSY) == 0) {
411                         DELAY(5);
412                         val = CSR_READ_4(sc, BGE_MI_COMM);
413                         break;
414                 }
415         }
416         if (i == BNX_TIMEOUT) {
417                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
418                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
419                 val = 0;
420         }
421
422         /* Restore the autopoll bit if necessary. */
423         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
424                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
425                 DELAY(80);
426         }
427
428         if (val & BGE_MICOMM_READFAIL)
429                 return 0;
430
431         return (val & 0xFFFF);
432 }
433
434 static int
435 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
436 {
437         struct bnx_softc *sc = device_get_softc(dev);
438         int i;
439
440         KASSERT(phy == sc->bnx_phyno,
441             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
442
443         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
444         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
445                 CSR_WRITE_4(sc, BGE_MI_MODE,
446                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
447                 DELAY(80);
448         }
449
450         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
451             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
452
453         for (i = 0; i < BNX_TIMEOUT; i++) {
454                 DELAY(10);
455                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
456                         DELAY(5);
457                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
458                         break;
459                 }
460         }
461         if (i == BNX_TIMEOUT) {
462                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
463                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
464         }
465
466         /* Restore the autopoll bit if necessary. */
467         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
468                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
469                 DELAY(80);
470         }
471
472         return 0;
473 }
474
475 static void
476 bnx_miibus_statchg(device_t dev)
477 {
478         struct bnx_softc *sc;
479         struct mii_data *mii;
480
481         sc = device_get_softc(dev);
482         mii = device_get_softc(sc->bnx_miibus);
483
484         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
485             (IFM_ACTIVE | IFM_AVALID)) {
486                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
487                 case IFM_10_T:
488                 case IFM_100_TX:
489                         sc->bnx_link = 1;
490                         break;
491                 case IFM_1000_T:
492                 case IFM_1000_SX:
493                 case IFM_2500_SX:
494                         sc->bnx_link = 1;
495                         break;
496                 default:
497                         sc->bnx_link = 0;
498                         break;
499                 }
500         } else {
501                 sc->bnx_link = 0;
502         }
503         if (sc->bnx_link == 0)
504                 return;
505
506         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
507         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
508             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
509                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
510         } else {
511                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
512         }
513
514         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
515                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
516         } else {
517                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
518         }
519 }
520
521 /*
522  * Memory management for jumbo frames.
523  */
524 static int
525 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
526 {
527         struct ifnet *ifp = &sc->arpcom.ac_if;
528         struct bnx_jslot *entry;
529         uint8_t *ptr;
530         bus_addr_t paddr;
531         int i, error;
532
533         /*
534          * Create tag for jumbo mbufs.
535          * This is really a bit of a kludge. We allocate a special
536          * jumbo buffer pool which (thanks to the way our DMA
537          * memory allocation works) will consist of contiguous
538          * pages. This means that even though a jumbo buffer might
539          * be larger than a page size, we don't really need to
540          * map it into more than one DMA segment. However, the
541          * default mbuf tag will result in multi-segment mappings,
542          * so we have to create a special jumbo mbuf tag that
543          * lets us get away with mapping the jumbo buffers as
544          * a single segment. I think eventually the driver should
545          * be changed so that it uses ordinary mbufs and cluster
546          * buffers, i.e. jumbo frames can span multiple DMA
547          * descriptors. But that's a project for another day.
548          */
549
550         /*
551          * Create DMA stuffs for jumbo RX ring.
552          */
553         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
554                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
555                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
556                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
557                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
558         if (error) {
559                 if_printf(ifp, "could not create jumbo RX ring\n");
560                 return error;
561         }
562
563         /*
564          * Create DMA stuffs for jumbo buffer block.
565          */
566         error = bnx_dma_block_alloc(sc, BNX_JMEM,
567                                     &sc->bnx_cdata.bnx_jumbo_tag,
568                                     &sc->bnx_cdata.bnx_jumbo_map,
569                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
570                                     &paddr);
571         if (error) {
572                 if_printf(ifp, "could not create jumbo buffer\n");
573                 return error;
574         }
575
576         SLIST_INIT(&sc->bnx_jfree_listhead);
577
578         /*
579          * Now divide it up into 9K pieces and save the addresses
580          * in an array. Note that we play an evil trick here by using
581          * the first few bytes in the buffer to hold the the address
582          * of the softc structure for this interface. This is because
583          * bnx_jfree() needs it, but it is called by the mbuf management
584          * code which will not pass it to us explicitly.
585          */
586         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
587                 entry = &sc->bnx_cdata.bnx_jslots[i];
588                 entry->bnx_sc = sc;
589                 entry->bnx_buf = ptr;
590                 entry->bnx_paddr = paddr;
591                 entry->bnx_inuse = 0;
592                 entry->bnx_slot = i;
593                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
594
595                 ptr += BNX_JLEN;
596                 paddr += BNX_JLEN;
597         }
598         return 0;
599 }
600
601 static void
602 bnx_free_jumbo_mem(struct bnx_softc *sc)
603 {
604         /* Destroy jumbo RX ring. */
605         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
606                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
607                            sc->bnx_ldata.bnx_rx_jumbo_ring);
608
609         /* Destroy jumbo buffer block. */
610         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
611                            sc->bnx_cdata.bnx_jumbo_map,
612                            sc->bnx_ldata.bnx_jumbo_buf);
613 }
614
615 /*
616  * Allocate a jumbo buffer.
617  */
618 static struct bnx_jslot *
619 bnx_jalloc(struct bnx_softc *sc)
620 {
621         struct bnx_jslot *entry;
622
623         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
624         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
625         if (entry) {
626                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
627                 entry->bnx_inuse = 1;
628         } else {
629                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
630         }
631         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
632         return(entry);
633 }
634
635 /*
636  * Adjust usage count on a jumbo buffer.
637  */
638 static void
639 bnx_jref(void *arg)
640 {
641         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
642         struct bnx_softc *sc = entry->bnx_sc;
643
644         if (sc == NULL)
645                 panic("bnx_jref: can't find softc pointer!");
646
647         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
648                 panic("bnx_jref: asked to reference buffer "
649                     "that we don't manage!");
650         } else if (entry->bnx_inuse == 0) {
651                 panic("bnx_jref: buffer already free!");
652         } else {
653                 atomic_add_int(&entry->bnx_inuse, 1);
654         }
655 }
656
657 /*
658  * Release a jumbo buffer.
659  */
660 static void
661 bnx_jfree(void *arg)
662 {
663         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
664         struct bnx_softc *sc = entry->bnx_sc;
665
666         if (sc == NULL)
667                 panic("bnx_jfree: can't find softc pointer!");
668
669         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
670                 panic("bnx_jfree: asked to free buffer that we don't manage!");
671         } else if (entry->bnx_inuse == 0) {
672                 panic("bnx_jfree: buffer already free!");
673         } else {
674                 /*
675                  * Possible MP race to 0, use the serializer.  The atomic insn
676                  * is still needed for races against bnx_jref().
677                  */
678                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
679                 atomic_subtract_int(&entry->bnx_inuse, 1);
680                 if (entry->bnx_inuse == 0) {
681                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, 
682                                           entry, jslot_link);
683                 }
684                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
685         }
686 }
687
688
689 /*
690  * Intialize a standard receive ring descriptor.
691  */
692 static int
693 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
694 {
695         struct mbuf *m_new = NULL;
696         bus_dma_segment_t seg;
697         bus_dmamap_t map;
698         int error, nsegs;
699
700         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
701         if (m_new == NULL)
702                 return ENOBUFS;
703         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
704         m_adj(m_new, ETHER_ALIGN);
705
706         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
707                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
708                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
709         if (error) {
710                 m_freem(m_new);
711                 return error;
712         }
713
714         if (!init) {
715                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
716                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
717                                 BUS_DMASYNC_POSTREAD);
718                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
719                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
720         }
721
722         map = sc->bnx_cdata.bnx_rx_tmpmap;
723         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
724         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
725
726         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
727         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
728
729         bnx_setup_rxdesc_std(sc, i);
730         return 0;
731 }
732
733 static void
734 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
735 {
736         struct bnx_rxchain *rc;
737         struct bge_rx_bd *r;
738
739         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
740         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
741
742         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
743         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
744         r->bge_len = rc->bnx_mbuf->m_len;
745         r->bge_idx = i;
746         r->bge_flags = BGE_RXBDFLAG_END;
747 }
748
749 /*
750  * Initialize a jumbo receive ring descriptor. This allocates
751  * a jumbo buffer from the pool managed internally by the driver.
752  */
753 static int
754 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
755 {
756         struct mbuf *m_new = NULL;
757         struct bnx_jslot *buf;
758         bus_addr_t paddr;
759
760         /* Allocate the mbuf. */
761         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
762         if (m_new == NULL)
763                 return ENOBUFS;
764
765         /* Allocate the jumbo buffer */
766         buf = bnx_jalloc(sc);
767         if (buf == NULL) {
768                 m_freem(m_new);
769                 return ENOBUFS;
770         }
771
772         /* Attach the buffer to the mbuf. */
773         m_new->m_ext.ext_arg = buf;
774         m_new->m_ext.ext_buf = buf->bnx_buf;
775         m_new->m_ext.ext_free = bnx_jfree;
776         m_new->m_ext.ext_ref = bnx_jref;
777         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
778
779         m_new->m_flags |= M_EXT;
780
781         m_new->m_data = m_new->m_ext.ext_buf;
782         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
783
784         paddr = buf->bnx_paddr;
785         m_adj(m_new, ETHER_ALIGN);
786         paddr += ETHER_ALIGN;
787
788         /* Save necessary information */
789         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
790         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
791
792         /* Set up the descriptor. */
793         bnx_setup_rxdesc_jumbo(sc, i);
794         return 0;
795 }
796
797 static void
798 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
799 {
800         struct bge_rx_bd *r;
801         struct bnx_rxchain *rc;
802
803         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
804         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
805
806         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
807         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
808         r->bge_len = rc->bnx_mbuf->m_len;
809         r->bge_idx = i;
810         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
811 }
812
813 static int
814 bnx_init_rx_ring_std(struct bnx_softc *sc)
815 {
816         int i, error;
817
818         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
819                 error = bnx_newbuf_std(sc, i, 1);
820                 if (error)
821                         return error;
822         }
823
824         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
825         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
826
827         return(0);
828 }
829
830 static void
831 bnx_free_rx_ring_std(struct bnx_softc *sc)
832 {
833         int i;
834
835         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
836                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
837
838                 if (rc->bnx_mbuf != NULL) {
839                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
840                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
841                         m_freem(rc->bnx_mbuf);
842                         rc->bnx_mbuf = NULL;
843                 }
844                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
845                     sizeof(struct bge_rx_bd));
846         }
847 }
848
849 static int
850 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
851 {
852         struct bge_rcb *rcb;
853         int i, error;
854
855         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
856                 error = bnx_newbuf_jumbo(sc, i, 1);
857                 if (error)
858                         return error;
859         }
860
861         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
862
863         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
864         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
865         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
866
867         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
868
869         return(0);
870 }
871
872 static void
873 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
874 {
875         int i;
876
877         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
878                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
879
880                 if (rc->bnx_mbuf != NULL) {
881                         m_freem(rc->bnx_mbuf);
882                         rc->bnx_mbuf = NULL;
883                 }
884                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
885                     sizeof(struct bge_rx_bd));
886         }
887 }
888
889 static void
890 bnx_free_tx_ring(struct bnx_tx_ring *txr)
891 {
892         int i;
893
894         for (i = 0; i < BGE_TX_RING_CNT; i++) {
895                 if (txr->bnx_tx_chain[i] != NULL) {
896                         bus_dmamap_unload(txr->bnx_tx_mtag,
897                             txr->bnx_tx_dmamap[i]);
898                         m_freem(txr->bnx_tx_chain[i]);
899                         txr->bnx_tx_chain[i] = NULL;
900                 }
901                 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
902         }
903         txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
904 }
905
906 static int
907 bnx_init_tx_ring(struct bnx_tx_ring *txr)
908 {
909         txr->bnx_txcnt = 0;
910         txr->bnx_tx_saved_considx = 0;
911         txr->bnx_tx_prodidx = 0;
912
913         /* Initialize transmit producer index for host-memory send ring. */
914         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
915
916         return(0);
917 }
918
919 static void
920 bnx_setmulti(struct bnx_softc *sc)
921 {
922         struct ifnet *ifp;
923         struct ifmultiaddr *ifma;
924         uint32_t hashes[4] = { 0, 0, 0, 0 };
925         int h, i;
926
927         ifp = &sc->arpcom.ac_if;
928
929         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
930                 for (i = 0; i < 4; i++)
931                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
932                 return;
933         }
934
935         /* First, zot all the existing filters. */
936         for (i = 0; i < 4; i++)
937                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
938
939         /* Now program new ones. */
940         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
941                 if (ifma->ifma_addr->sa_family != AF_LINK)
942                         continue;
943                 h = ether_crc32_le(
944                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
945                     ETHER_ADDR_LEN) & 0x7f;
946                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
947         }
948
949         for (i = 0; i < 4; i++)
950                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
951 }
952
953 /*
954  * Do endian, PCI and DMA initialization. Also check the on-board ROM
955  * self-test results.
956  */
957 static int
958 bnx_chipinit(struct bnx_softc *sc)
959 {
960         uint32_t dma_rw_ctl, mode_ctl;
961         int i;
962
963         /* Set endian type before we access any non-PCI registers. */
964         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
965             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
966
967         /* Clear the MAC control register */
968         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
969
970         /*
971          * Clear the MAC statistics block in the NIC's
972          * internal memory.
973          */
974         for (i = BGE_STATS_BLOCK;
975             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
976                 BNX_MEMWIN_WRITE(sc, i, 0);
977
978         for (i = BGE_STATUS_BLOCK;
979             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
980                 BNX_MEMWIN_WRITE(sc, i, 0);
981
982         if (BNX_IS_57765_FAMILY(sc)) {
983                 uint32_t val;
984
985                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
986                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
987                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
988
989                         /* Access the lower 1K of PL PCI-E block registers. */
990                         CSR_WRITE_4(sc, BGE_MODE_CTL,
991                             val | BGE_MODECTL_PCIE_PL_SEL);
992
993                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
994                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
995                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
996
997                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
998                 }
999                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1000                         /* Fix transmit hangs */
1001                         val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1002                         val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1003                         CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1004
1005                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1006                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1007
1008                         /* Access the lower 1K of DL PCI-E block registers. */
1009                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1010                             val | BGE_MODECTL_PCIE_DL_SEL);
1011
1012                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1013                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1014                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1015                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1016
1017                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1018                 }
1019
1020                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1021                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1022                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1023                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1024         }
1025
1026         /*
1027          * Set up the PCI DMA control register.
1028          */
1029         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1030         /*
1031          * Disable 32bytes cache alignment for DMA write to host memory
1032          *
1033          * NOTE:
1034          * 64bytes cache alignment for DMA write to host memory is still
1035          * enabled.
1036          */
1037         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1038         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1039                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1040         /*
1041          * Enable HW workaround for controllers that misinterpret
1042          * a status tag update and leave interrupts permanently
1043          * disabled.
1044          */
1045         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1046             sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1047             !BNX_IS_57765_FAMILY(sc))
1048                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1049         if (bootverbose) {
1050                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1051                     dma_rw_ctl);
1052         }
1053         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1054
1055         /*
1056          * Set up general mode register.
1057          */
1058         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1059             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1060         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1061
1062         /*
1063          * Disable memory write invalidate.  Apparently it is not supported
1064          * properly by these devices.  Also ensure that INTx isn't disabled,
1065          * as these chips need it even when using MSI.
1066          */
1067         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1068             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1069
1070         /* Set the timer prescaler (always 66Mhz) */
1071         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1072
1073         return(0);
1074 }
1075
1076 static int
1077 bnx_blockinit(struct bnx_softc *sc)
1078 {
1079         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
1080         struct bge_rcb *rcb;
1081         bus_size_t vrcb;
1082         bge_hostaddr taddr;
1083         uint32_t val;
1084         int i, limit;
1085
1086         /*
1087          * Initialize the memory window pointer register so that
1088          * we can access the first 32K of internal NIC RAM. This will
1089          * allow us to set up the TX send ring RCBs and the RX return
1090          * ring RCBs, plus other things which live in NIC memory.
1091          */
1092         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1093
1094         /* Configure mbuf pool watermarks */
1095         if (BNX_IS_57765_PLUS(sc)) {
1096                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1097                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1098                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1099                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1100                 } else {
1101                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1102                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1103                 }
1104         } else {
1105                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1106                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1107                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1108         }
1109
1110         /* Configure DMA resource watermarks */
1111         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1112         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1113
1114         /* Enable buffer manager */
1115         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1116         /*
1117          * Change the arbitration algorithm of TXMBUF read request to
1118          * round-robin instead of priority based for BCM5719.  When
1119          * TXFIFO is almost empty, RDMA will hold its request until
1120          * TXFIFO is not almost empty.
1121          */
1122         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1123                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1124         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1125             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1126             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1127                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1128         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1129
1130         /* Poll for buffer manager start indication */
1131         for (i = 0; i < BNX_TIMEOUT; i++) {
1132                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1133                         break;
1134                 DELAY(10);
1135         }
1136
1137         if (i == BNX_TIMEOUT) {
1138                 if_printf(&sc->arpcom.ac_if,
1139                           "buffer manager failed to start\n");
1140                 return(ENXIO);
1141         }
1142
1143         /* Enable flow-through queues */
1144         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1145         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1146
1147         /* Wait until queue initialization is complete */
1148         for (i = 0; i < BNX_TIMEOUT; i++) {
1149                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1150                         break;
1151                 DELAY(10);
1152         }
1153
1154         if (i == BNX_TIMEOUT) {
1155                 if_printf(&sc->arpcom.ac_if,
1156                           "flow-through queue init failed\n");
1157                 return(ENXIO);
1158         }
1159
1160         /*
1161          * Summary of rings supported by the controller:
1162          *
1163          * Standard Receive Producer Ring
1164          * - This ring is used to feed receive buffers for "standard"
1165          *   sized frames (typically 1536 bytes) to the controller.
1166          *
1167          * Jumbo Receive Producer Ring
1168          * - This ring is used to feed receive buffers for jumbo sized
1169          *   frames (i.e. anything bigger than the "standard" frames)
1170          *   to the controller.
1171          *
1172          * Mini Receive Producer Ring
1173          * - This ring is used to feed receive buffers for "mini"
1174          *   sized frames to the controller.
1175          * - This feature required external memory for the controller
1176          *   but was never used in a production system.  Should always
1177          *   be disabled.
1178          *
1179          * Receive Return Ring
1180          * - After the controller has placed an incoming frame into a
1181          *   receive buffer that buffer is moved into a receive return
1182          *   ring.  The driver is then responsible to passing the
1183          *   buffer up to the stack.  Many versions of the controller
1184          *   support multiple RR rings.
1185          *
1186          * Send Ring
1187          * - This ring is used for outgoing frames.  Many versions of
1188          *   the controller support multiple send rings.
1189          */
1190
1191         /* Initialize the standard receive producer ring control block. */
1192         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1193         rcb->bge_hostaddr.bge_addr_lo =
1194             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1195         rcb->bge_hostaddr.bge_addr_hi =
1196             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1197         if (BNX_IS_57765_PLUS(sc)) {
1198                 /*
1199                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1200                  * Bits 15-2 : Maximum RX frame size
1201                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1202                  * Bit 0     : Reserved
1203                  */
1204                 rcb->bge_maxlen_flags =
1205                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1206         } else {
1207                 /*
1208                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1209                  * Bits 15-2 : Reserved (should be 0)
1210                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1211                  * Bit 0     : Reserved
1212                  */
1213                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1214         }
1215         if (BNX_IS_5717_PLUS(sc))
1216                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1217         else
1218                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1219         /* Write the standard receive producer ring control block. */
1220         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1221         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1222         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1223         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1224         /* Reset the standard receive producer ring producer index. */
1225         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1226
1227         /*
1228          * Initialize the jumbo RX producer ring control
1229          * block.  We set the 'ring disabled' bit in the
1230          * flags field until we're actually ready to start
1231          * using this ring (i.e. once we set the MTU
1232          * high enough to require it).
1233          */
1234         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1235                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1236                 /* Get the jumbo receive producer ring RCB parameters. */
1237                 rcb->bge_hostaddr.bge_addr_lo =
1238                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1239                 rcb->bge_hostaddr.bge_addr_hi =
1240                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1241                 rcb->bge_maxlen_flags =
1242                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1243                     BGE_RCB_FLAG_RING_DISABLED);
1244                 if (BNX_IS_5717_PLUS(sc))
1245                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1246                 else
1247                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1248                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1249                     rcb->bge_hostaddr.bge_addr_hi);
1250                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1251                     rcb->bge_hostaddr.bge_addr_lo);
1252                 /* Program the jumbo receive producer ring RCB parameters. */
1253                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1254                     rcb->bge_maxlen_flags);
1255                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1256                 /* Reset the jumbo receive producer ring producer index. */
1257                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1258         }
1259
1260         /*
1261          * The BD ring replenish thresholds control how often the
1262          * hardware fetches new BD's from the producer rings in host
1263          * memory.  Setting the value too low on a busy system can
1264          * starve the hardware and recue the throughpout.
1265          *
1266          * Set the BD ring replentish thresholds. The recommended
1267          * values are 1/8th the number of descriptors allocated to
1268          * each ring.
1269          */
1270         val = 8;
1271         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1272         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1273                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1274                     BGE_JUMBO_RX_RING_CNT/8);
1275         }
1276         if (BNX_IS_57765_PLUS(sc)) {
1277                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1278                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1279         }
1280
1281         /*
1282          * Disable all send rings by setting the 'ring disabled' bit
1283          * in the flags field of all the TX send ring control blocks,
1284          * located in NIC memory.
1285          */
1286         if (BNX_IS_5717_PLUS(sc))
1287                 limit = 4;
1288         else if (BNX_IS_57765_FAMILY(sc) ||
1289             sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1290                 limit = 2;
1291         else
1292                 limit = 1;
1293         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1294         for (i = 0; i < limit; i++) {
1295                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1296                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1297                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1298                 vrcb += sizeof(struct bge_rcb);
1299         }
1300
1301         /* Configure send ring RCB 0 (we use only the first ring) */
1302         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1303         BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1304         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1305         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1306         if (BNX_IS_5717_PLUS(sc)) {
1307                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1308         } else {
1309                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1310                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1311         }
1312         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1313             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1314
1315         /*
1316          * Disable all receive return rings by setting the
1317          * 'ring disabled' bit in the flags field of all the receive
1318          * return ring control blocks, located in NIC memory.
1319          */
1320         if (BNX_IS_5717_PLUS(sc)) {
1321                 /* Should be 17, use 16 until we get an SRAM map. */
1322                 limit = 16;
1323         } else if (BNX_IS_57765_FAMILY(sc) ||
1324             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1325                 limit = 4;
1326         } else {
1327                 limit = 1;
1328         }
1329         /* Disable all receive return rings. */
1330         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1331         for (i = 0; i < limit; i++) {
1332                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1333                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1334                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1335                     BGE_RCB_FLAG_RING_DISABLED);
1336                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1337                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1338                     (i * (sizeof(uint64_t))), 0);
1339                 vrcb += sizeof(struct bge_rcb);
1340         }
1341
1342         /*
1343          * Set up receive return ring 0.  Note that the NIC address
1344          * for RX return rings is 0x0.  The return rings live entirely
1345          * within the host, so the nicaddr field in the RCB isn't used.
1346          */
1347         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1348         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1349         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1350         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1351         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1352         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1353             BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1354
1355         /* Set random backoff seed for TX */
1356         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1357             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1358             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1359             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1360             BGE_TX_BACKOFF_SEED_MASK);
1361
1362         /* Set inter-packet gap */
1363         val = 0x2620;
1364         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1365             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1366                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1367                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1368         }
1369         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1370
1371         /*
1372          * Specify which ring to use for packets that don't match
1373          * any RX rules.
1374          */
1375         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1376
1377         /*
1378          * Configure number of RX lists. One interrupt distribution
1379          * list, sixteen active lists, one bad frames class.
1380          */
1381         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1382
1383         /* Inialize RX list placement stats mask. */
1384         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1385         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1386
1387         /* Disable host coalescing until we get it set up */
1388         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1389
1390         /* Poll to make sure it's shut down. */
1391         for (i = 0; i < BNX_TIMEOUT; i++) {
1392                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1393                         break;
1394                 DELAY(10);
1395         }
1396
1397         if (i == BNX_TIMEOUT) {
1398                 if_printf(&sc->arpcom.ac_if,
1399                           "host coalescing engine failed to idle\n");
1400                 return(ENXIO);
1401         }
1402
1403         /* Set up host coalescing defaults */
1404         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1405         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1406         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1407         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1408         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1409         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1410
1411         /* Set up address of status block */
1412         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1413         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1414             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1415         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1416             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1417
1418         /* Set up status block partail update size. */
1419         val = BGE_STATBLKSZ_32BYTE;
1420 #if 0
1421         /*
1422          * Does not seem to have visible effect in both
1423          * bulk data (1472B UDP datagram) and tiny data
1424          * (18B UDP datagram) TX tests.
1425          */
1426         val |= BGE_HCCMODE_CLRTICK_TX;
1427 #endif
1428         /* Turn on host coalescing state machine */
1429         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1430
1431         /* Turn on RX BD completion state machine and enable attentions */
1432         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1433             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1434
1435         /* Turn on RX list placement state machine */
1436         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1437
1438         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1439             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1440             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1441             BGE_MACMODE_FRMHDR_DMA_ENB;
1442
1443         if (sc->bnx_flags & BNX_FLAG_TBI)
1444                 val |= BGE_PORTMODE_TBI;
1445         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1446                 val |= BGE_PORTMODE_GMII;
1447         else
1448                 val |= BGE_PORTMODE_MII;
1449
1450         /* Turn on DMA, clear stats */
1451         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1452
1453         /* Set misc. local control, enable interrupts on attentions */
1454         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1455
1456 #ifdef notdef
1457         /* Assert GPIO pins for PHY reset */
1458         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1459             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1460         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1461             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1462 #endif
1463
1464         /* Turn on write DMA state machine */
1465         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1466         /* Enable host coalescing bug fix. */
1467         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1468         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1469                 /* Request larger DMA burst size to get better performance. */
1470                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1471         }
1472         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1473         DELAY(40);
1474
1475         if (BNX_IS_57765_PLUS(sc)) {
1476                 uint32_t dmactl, dmactl_reg;
1477
1478                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1479                         dmactl_reg = BGE_RDMA_RSRVCTRL2;
1480                 else
1481                         dmactl_reg = BGE_RDMA_RSRVCTRL;
1482
1483                 dmactl = CSR_READ_4(sc, dmactl_reg);
1484                 /*
1485                  * Adjust tx margin to prevent TX data corruption and
1486                  * fix internal FIFO overflow.
1487                  */
1488                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1489                     sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1490                     sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1491                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1492                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1493                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1494                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1495                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1496                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1497                 }
1498                 /*
1499                  * Enable fix for read DMA FIFO overruns.
1500                  * The fix is to limit the number of RX BDs
1501                  * the hardware would fetch at a fime.
1502                  */
1503                 CSR_WRITE_4(sc, dmactl_reg,
1504                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1505         }
1506
1507         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1508                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1509                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1510                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1511                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1512         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1513             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1514                 uint32_t ctrl_reg;
1515
1516                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1517                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1518                 else
1519                         ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1520
1521                 /*
1522                  * Allow 4KB burst length reads for non-LSO frames.
1523                  * Enable 512B burst length reads for buffer descriptors.
1524                  */
1525                 CSR_WRITE_4(sc, ctrl_reg,
1526                     CSR_READ_4(sc, ctrl_reg) |
1527                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1528                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1529         }
1530
1531         /* Turn on read DMA state machine */
1532         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1533         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1534                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1535         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1536             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1537             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1538                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1539                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1540                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1541         }
1542         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1543             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1544                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1545                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1546                 /*
1547                  * Allow multiple outstanding read requests from
1548                  * non-LSO read DMA engine.
1549                  */
1550                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1551         }
1552         if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1553                 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1554         if (sc->bnx_flags & BNX_FLAG_TSO)
1555                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1556         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1557         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1558         DELAY(40);
1559
1560         /* Turn on RX data completion state machine */
1561         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1562
1563         /* Turn on RX BD initiator state machine */
1564         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1565
1566         /* Turn on RX data and RX BD initiator state machine */
1567         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1568
1569         /* Turn on send BD completion state machine */
1570         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1571
1572         /* Turn on send data completion state machine */
1573         val = BGE_SDCMODE_ENABLE;
1574         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1575                 val |= BGE_SDCMODE_CDELAY; 
1576         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1577
1578         /* Turn on send data initiator state machine */
1579         if (sc->bnx_flags & BNX_FLAG_TSO) {
1580                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1581                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1582         } else {
1583                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1584         }
1585
1586         /* Turn on send BD initiator state machine */
1587         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1588
1589         /* Turn on send BD selector state machine */
1590         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1591
1592         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1593         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1594             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1595
1596         /* ack/clear link change events */
1597         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1598             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1599             BGE_MACSTAT_LINK_CHANGED);
1600         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1601
1602         /*
1603          * Enable attention when the link has changed state for
1604          * devices that use auto polling.
1605          */
1606         if (sc->bnx_flags & BNX_FLAG_TBI) {
1607                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1608         } else {
1609                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1610                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1611                         DELAY(80);
1612                 }
1613         }
1614
1615         /*
1616          * Clear any pending link state attention.
1617          * Otherwise some link state change events may be lost until attention
1618          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1619          * It's not necessary on newer BCM chips - perhaps enabling link
1620          * state change attentions implies clearing pending attention.
1621          */
1622         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1623             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1624             BGE_MACSTAT_LINK_CHANGED);
1625
1626         /* Enable link state change attentions. */
1627         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1628
1629         return(0);
1630 }
1631
1632 /*
1633  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1634  * against our list and return its name if we find a match. Note
1635  * that since the Broadcom controller contains VPD support, we
1636  * can get the device name string from the controller itself instead
1637  * of the compiled-in string. This is a little slow, but it guarantees
1638  * we'll always announce the right product name.
1639  */
1640 static int
1641 bnx_probe(device_t dev)
1642 {
1643         const struct bnx_type *t;
1644         uint16_t product, vendor;
1645
1646         if (!pci_is_pcie(dev))
1647                 return ENXIO;
1648
1649         product = pci_get_device(dev);
1650         vendor = pci_get_vendor(dev);
1651
1652         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1653                 if (vendor == t->bnx_vid && product == t->bnx_did)
1654                         break;
1655         }
1656         if (t->bnx_name == NULL)
1657                 return ENXIO;
1658
1659         device_set_desc(dev, t->bnx_name);
1660         return 0;
1661 }
1662
1663 static int
1664 bnx_attach(device_t dev)
1665 {
1666         struct ifnet *ifp;
1667         struct bnx_softc *sc;
1668         uint32_t hwcfg = 0;
1669         int error = 0, rid, capmask;
1670         uint8_t ether_addr[ETHER_ADDR_LEN];
1671         uint16_t product;
1672         driver_intr_t *intr_func;
1673         uintptr_t mii_priv = 0;
1674         u_int intr_flags;
1675 #ifdef BNX_TSO_DEBUG
1676         char desc[32];
1677         int i;
1678 #endif
1679
1680         sc = device_get_softc(dev);
1681         sc->bnx_dev = dev;
1682         callout_init_mp(&sc->bnx_stat_timer);
1683         callout_init_mp(&sc->bnx_intr_timer);
1684         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1685
1686         product = pci_get_device(dev);
1687
1688 #ifndef BURN_BRIDGES
1689         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1690                 uint32_t irq, mem;
1691
1692                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1693                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1694
1695                 device_printf(dev, "chip is in D%d power mode "
1696                     "-- setting to D0\n", pci_get_powerstate(dev));
1697
1698                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1699
1700                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1701                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1702         }
1703 #endif  /* !BURN_BRIDGE */
1704
1705         /*
1706          * Map control/status registers.
1707          */
1708         pci_enable_busmaster(dev);
1709
1710         rid = BGE_PCI_BAR0;
1711         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1712             RF_ACTIVE);
1713
1714         if (sc->bnx_res == NULL) {
1715                 device_printf(dev, "couldn't map memory\n");
1716                 return ENXIO;
1717         }
1718
1719         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1720         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1721
1722         /* Save various chip information */
1723         sc->bnx_chipid =
1724             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1725             BGE_PCIMISCCTL_ASICREV_SHIFT;
1726         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1727                 /* All chips having dedicated ASICREV register have CPMU */
1728                 sc->bnx_flags |= BNX_FLAG_CPMU;
1729
1730                 switch (product) {
1731                 case PCI_PRODUCT_BROADCOM_BCM5717:
1732                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1733                 case PCI_PRODUCT_BROADCOM_BCM5718:
1734                 case PCI_PRODUCT_BROADCOM_BCM5719:
1735                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1736                 case PCI_PRODUCT_BROADCOM_BCM5725:
1737                 case PCI_PRODUCT_BROADCOM_BCM5727:
1738                 case PCI_PRODUCT_BROADCOM_BCM5762:
1739                         sc->bnx_chipid = pci_read_config(dev,
1740                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1741                         break;
1742
1743                 case PCI_PRODUCT_BROADCOM_BCM57761:
1744                 case PCI_PRODUCT_BROADCOM_BCM57762:
1745                 case PCI_PRODUCT_BROADCOM_BCM57765:
1746                 case PCI_PRODUCT_BROADCOM_BCM57766:
1747                 case PCI_PRODUCT_BROADCOM_BCM57781:
1748                 case PCI_PRODUCT_BROADCOM_BCM57782:
1749                 case PCI_PRODUCT_BROADCOM_BCM57785:
1750                 case PCI_PRODUCT_BROADCOM_BCM57786:
1751                 case PCI_PRODUCT_BROADCOM_BCM57791:
1752                 case PCI_PRODUCT_BROADCOM_BCM57795:
1753                         sc->bnx_chipid = pci_read_config(dev,
1754                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1755                         break;
1756
1757                 default:
1758                         sc->bnx_chipid = pci_read_config(dev,
1759                             BGE_PCI_PRODID_ASICREV, 4);
1760                         break;
1761                 }
1762         }
1763         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1764                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1765
1766         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1767         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1768
1769         switch (sc->bnx_asicrev) {
1770         case BGE_ASICREV_BCM5717:
1771         case BGE_ASICREV_BCM5719:
1772         case BGE_ASICREV_BCM5720:
1773                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1774                 break;
1775
1776         case BGE_ASICREV_BCM5762:
1777                 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1778                 break;
1779
1780         case BGE_ASICREV_BCM57765:
1781         case BGE_ASICREV_BCM57766:
1782                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1783                 break;
1784         }
1785
1786         sc->bnx_flags |= BNX_FLAG_TSO;
1787         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1788             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1789                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1790
1791         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1792             BNX_IS_57765_FAMILY(sc)) {
1793                 /*
1794                  * All BCM57785 and BCM5718 families chips have a bug that
1795                  * under certain situation interrupt will not be enabled
1796                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1797                  *
1798                  * While BCM5719 and BCM5720 have a hardware workaround
1799                  * which could fix the above bug.
1800                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1801                  * bnx_chipinit().
1802                  *
1803                  * For the rest of the chips in these two families, we will
1804                  * have to poll the status block at high rate (10ms currently)
1805                  * to check whether the interrupt is hosed or not.
1806                  * See bnx_intr_check() for details.
1807                  */
1808                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1809         }
1810
1811         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1812         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1813             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1814                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1815         else
1816                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1817         device_printf(dev, "CHIP ID 0x%08x; "
1818                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1819                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1820
1821         /*
1822          * Set various PHY quirk flags.
1823          */
1824
1825         capmask = MII_CAPMASK_DEFAULT;
1826         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1827             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1828                 /* 10/100 only */
1829                 capmask &= ~BMSR_EXTSTAT;
1830         }
1831
1832         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1833         if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1834                 mii_priv |= BRGPHY_FLAG_5762_A0;
1835
1836         /* Initialize if_name earlier, so if_printf could be used */
1837         ifp = &sc->arpcom.ac_if;
1838         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1839
1840         /* Try to reset the chip. */
1841         bnx_reset(sc);
1842
1843         if (bnx_chipinit(sc)) {
1844                 device_printf(dev, "chip initialization failed\n");
1845                 error = ENXIO;
1846                 goto fail;
1847         }
1848
1849         /*
1850          * Get station address
1851          */
1852         error = bnx_get_eaddr(sc, ether_addr);
1853         if (error) {
1854                 device_printf(dev, "failed to read station address\n");
1855                 goto fail;
1856         }
1857
1858         /* XXX */
1859         sc->bnx_tx_ringcnt = 1;
1860
1861         error = bnx_dma_alloc(sc);
1862         if (error)
1863                 goto fail;
1864
1865         /*
1866          * Allocate interrupt
1867          */
1868         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1869             &intr_flags);
1870
1871         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1872             intr_flags);
1873         if (sc->bnx_irq == NULL) {
1874                 device_printf(dev, "couldn't map interrupt\n");
1875                 error = ENXIO;
1876                 goto fail;
1877         }
1878
1879         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1880                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1881                 bnx_enable_msi(sc);
1882         }
1883
1884         /* Set default tuneable values. */
1885         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1886         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1887         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1888         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1889         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1890         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1891
1892         /* Set up ifnet structure */
1893         ifp->if_softc = sc;
1894         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1895         ifp->if_ioctl = bnx_ioctl;
1896         ifp->if_start = bnx_start;
1897 #ifdef IFPOLL_ENABLE
1898         ifp->if_npoll = bnx_npoll;
1899 #endif
1900         ifp->if_watchdog = bnx_watchdog;
1901         ifp->if_init = bnx_init;
1902         ifp->if_mtu = ETHERMTU;
1903         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1904         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1905         ifq_set_ready(&ifp->if_snd);
1906
1907         ifp->if_capabilities |= IFCAP_HWCSUM;
1908         ifp->if_hwassist = BNX_CSUM_FEATURES;
1909         if (sc->bnx_flags & BNX_FLAG_TSO) {
1910                 ifp->if_capabilities |= IFCAP_TSO;
1911                 ifp->if_hwassist |= CSUM_TSO;
1912         }
1913         ifp->if_capenable = ifp->if_capabilities;
1914
1915         /*
1916          * Figure out what sort of media we have by checking the
1917          * hardware config word in the first 32k of NIC internal memory,
1918          * or fall back to examining the EEPROM if necessary.
1919          * Note: on some BCM5700 cards, this value appears to be unset.
1920          * If that's the case, we have to rely on identifying the NIC
1921          * by its PCI subsystem ID, as we do below for the SysKonnect
1922          * SK-9D41.
1923          */
1924         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
1925                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1926         } else {
1927                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1928                                     sizeof(hwcfg))) {
1929                         device_printf(dev, "failed to read EEPROM\n");
1930                         error = ENXIO;
1931                         goto fail;
1932                 }
1933                 hwcfg = ntohl(hwcfg);
1934         }
1935
1936         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1937         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
1938             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1939                 sc->bnx_flags |= BNX_FLAG_TBI;
1940
1941         /* Setup MI MODE */
1942         if (sc->bnx_flags & BNX_FLAG_CPMU)
1943                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
1944         else
1945                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
1946
1947         /* Setup link status update stuffs */
1948         if (sc->bnx_flags & BNX_FLAG_TBI) {
1949                 sc->bnx_link_upd = bnx_tbi_link_upd;
1950                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1951         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1952                 sc->bnx_link_upd = bnx_autopoll_link_upd;
1953                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1954         } else {
1955                 sc->bnx_link_upd = bnx_copper_link_upd;
1956                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
1957         }
1958
1959         /* Set default PHY address */
1960         sc->bnx_phyno = 1;
1961
1962         /*
1963          * PHY address mapping for various devices.
1964          *
1965          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
1966          * ---------+-------+-------+-------+-------+
1967          * BCM57XX  |   1   |   X   |   X   |   X   |
1968          * BCM5704  |   1   |   X   |   1   |   X   |
1969          * BCM5717  |   1   |   8   |   2   |   9   |
1970          * BCM5719  |   1   |   8   |   2   |   9   |
1971          * BCM5720  |   1   |   8   |   2   |   9   |
1972          *
1973          * Other addresses may respond but they are not
1974          * IEEE compliant PHYs and should be ignored.
1975          */
1976         if (BNX_IS_5717_PLUS(sc)) {
1977                 int f;
1978
1979                 f = pci_get_function(dev);
1980                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
1981                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
1982                             BGE_SGDIGSTS_IS_SERDES)
1983                                 sc->bnx_phyno = f + 8;
1984                         else
1985                                 sc->bnx_phyno = f + 1;
1986                 } else {
1987                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
1988                             BGE_CPMU_PHY_STRAP_IS_SERDES)
1989                                 sc->bnx_phyno = f + 8;
1990                         else
1991                                 sc->bnx_phyno = f + 1;
1992                 }
1993         }
1994
1995         if (sc->bnx_flags & BNX_FLAG_TBI) {
1996                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
1997                     bnx_ifmedia_upd, bnx_ifmedia_sts);
1998                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1999                 ifmedia_add(&sc->bnx_ifmedia,
2000                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2001                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2002                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2003                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2004         } else {
2005                 struct mii_probe_args mii_args;
2006
2007                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2008                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2009                 mii_args.mii_capmask = capmask;
2010                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2011                 mii_args.mii_priv = mii_priv;
2012
2013                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2014                 if (error) {
2015                         device_printf(dev, "MII without any PHY!\n");
2016                         goto fail;
2017                 }
2018         }
2019
2020         /*
2021          * Create sysctl nodes.
2022          */
2023         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2024         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2025                                               SYSCTL_STATIC_CHILDREN(_hw),
2026                                               OID_AUTO,
2027                                               device_get_nameunit(dev),
2028                                               CTLFLAG_RD, 0, "");
2029         if (sc->bnx_sysctl_tree == NULL) {
2030                 device_printf(dev, "can't add sysctl node\n");
2031                 error = ENXIO;
2032                 goto fail;
2033         }
2034
2035         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2036                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2037                         OID_AUTO, "rx_coal_ticks",
2038                         CTLTYPE_INT | CTLFLAG_RW,
2039                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2040                         "Receive coalescing ticks (usec).");
2041         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2042                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2043                         OID_AUTO, "tx_coal_ticks",
2044                         CTLTYPE_INT | CTLFLAG_RW,
2045                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2046                         "Transmit coalescing ticks (usec).");
2047         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2048                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2049                         OID_AUTO, "rx_coal_bds",
2050                         CTLTYPE_INT | CTLFLAG_RW,
2051                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2052                         "Receive max coalesced BD count.");
2053         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2054                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2055                         OID_AUTO, "tx_coal_bds",
2056                         CTLTYPE_INT | CTLFLAG_RW,
2057                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2058                         "Transmit max coalesced BD count.");
2059         /*
2060          * A common design characteristic for many Broadcom
2061          * client controllers is that they only support a
2062          * single outstanding DMA read operation on the PCIe
2063          * bus. This means that it will take twice as long to
2064          * fetch a TX frame that is split into header and
2065          * payload buffers as it does to fetch a single,
2066          * contiguous TX frame (2 reads vs. 1 read). For these
2067          * controllers, coalescing buffers to reduce the number
2068          * of memory reads is effective way to get maximum
2069          * performance(about 940Mbps).  Without collapsing TX
2070          * buffers the maximum TCP bulk transfer performance
2071          * is about 850Mbps. However forcing coalescing mbufs
2072          * consumes a lot of CPU cycles, so leave it off by
2073          * default.
2074          */
2075         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2076             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2077             "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2078             sc, 0, bnx_sysctl_force_defrag, "I",
2079             "Force defragment on TX path");
2080
2081         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2082             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2083             "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2084             sc, 0, bnx_sysctl_tx_wreg, "I",
2085             "# of segments before writing to hardware register");
2086
2087         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2088             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2089             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2090             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2091             "Receive max coalesced BD count during interrupt.");
2092         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2093             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2094             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2095             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2096             "Transmit max coalesced BD count during interrupt.");
2097
2098 #ifdef BNX_TSO_DEBUG
2099         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2100                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2101                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2102                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2103                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2104         }
2105 #endif
2106
2107         /*
2108          * Call MI attach routine.
2109          */
2110         ether_ifattach(ifp, ether_addr, NULL);
2111
2112         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2113
2114 #ifdef IFPOLL_ENABLE
2115         ifpoll_compat_setup(&sc->bnx_npoll,
2116             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2117             device_get_unit(dev), ifp->if_serializer);
2118 #endif
2119
2120         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2121                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2122                         intr_func = bnx_msi_oneshot;
2123                         if (bootverbose)
2124                                 device_printf(dev, "oneshot MSI\n");
2125                 } else {
2126                         intr_func = bnx_msi;
2127                 }
2128         } else {
2129                 intr_func = bnx_intr_legacy;
2130         }
2131         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2132             &sc->bnx_intrhand, ifp->if_serializer);
2133         if (error) {
2134                 ether_ifdetach(ifp);
2135                 device_printf(dev, "couldn't set up irq\n");
2136                 goto fail;
2137         }
2138
2139         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2140         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2141
2142         return(0);
2143 fail:
2144         bnx_detach(dev);
2145         return(error);
2146 }
2147
2148 static int
2149 bnx_detach(device_t dev)
2150 {
2151         struct bnx_softc *sc = device_get_softc(dev);
2152
2153         if (device_is_attached(dev)) {
2154                 struct ifnet *ifp = &sc->arpcom.ac_if;
2155
2156                 lwkt_serialize_enter(ifp->if_serializer);
2157                 bnx_stop(sc);
2158                 bnx_reset(sc);
2159                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2160                 lwkt_serialize_exit(ifp->if_serializer);
2161
2162                 ether_ifdetach(ifp);
2163         }
2164
2165         if (sc->bnx_flags & BNX_FLAG_TBI)
2166                 ifmedia_removeall(&sc->bnx_ifmedia);
2167         if (sc->bnx_miibus)
2168                 device_delete_child(dev, sc->bnx_miibus);
2169         bus_generic_detach(dev);
2170
2171         if (sc->bnx_irq != NULL) {
2172                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2173                     sc->bnx_irq);
2174         }
2175         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2176                 pci_release_msi(dev);
2177
2178         if (sc->bnx_res != NULL) {
2179                 bus_release_resource(dev, SYS_RES_MEMORY,
2180                     BGE_PCI_BAR0, sc->bnx_res);
2181         }
2182
2183         if (sc->bnx_sysctl_tree != NULL)
2184                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2185
2186         bnx_dma_free(sc);
2187
2188         return 0;
2189 }
2190
2191 static void
2192 bnx_reset(struct bnx_softc *sc)
2193 {
2194         device_t dev;
2195         uint32_t cachesize, command, pcistate, reset;
2196         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2197         int i, val = 0;
2198         uint16_t devctl;
2199
2200         dev = sc->bnx_dev;
2201
2202         write_op = bnx_writemem_direct;
2203
2204         /* Save some important PCI state. */
2205         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2206         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2207         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2208
2209         pci_write_config(dev, BGE_PCI_MISC_CTL,
2210             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2211             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2212             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2213
2214         /* Disable fastboot on controllers that support it. */
2215         if (bootverbose)
2216                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2217         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2218
2219         /*
2220          * Write the magic number to SRAM at offset 0xB50.
2221          * When firmware finishes its initialization it will
2222          * write ~BGE_MAGIC_NUMBER to the same location.
2223          */
2224         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2225
2226         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2227
2228         /* XXX: Broadcom Linux driver. */
2229         /* Force PCI-E 1.0a mode */
2230         if (!BNX_IS_57765_PLUS(sc) &&
2231             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2232             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2233              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2234                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2235                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2236         }
2237         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2238                 /* Prevent PCIE link training during global reset */
2239                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2240                 reset |= (1<<29);
2241         }
2242
2243         /* 
2244          * Set GPHY Power Down Override to leave GPHY
2245          * powered up in D0 uninitialized.
2246          */
2247         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2248                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2249
2250         /* Issue global reset */
2251         write_op(sc, BGE_MISC_CFG, reset);
2252
2253         DELAY(1000);
2254
2255         /* XXX: Broadcom Linux driver. */
2256         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2257                 uint32_t v;
2258
2259                 DELAY(500000); /* wait for link training to complete */
2260                 v = pci_read_config(dev, 0xc4, 4);
2261                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2262         }
2263
2264         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2265
2266         /* Disable no snoop and disable relaxed ordering. */
2267         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2268
2269         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2270         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2271                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2272                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2273         }
2274
2275         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2276             devctl, 2);
2277
2278         /* Clear error status. */
2279         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2280             PCIEM_DEVSTS_CORR_ERR |
2281             PCIEM_DEVSTS_NFATAL_ERR |
2282             PCIEM_DEVSTS_FATAL_ERR |
2283             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2284
2285         /* Reset some of the PCI state that got zapped by reset */
2286         pci_write_config(dev, BGE_PCI_MISC_CTL,
2287             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2288             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2289             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2290         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2291         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2292         write_op(sc, BGE_MISC_CFG, (65 << 1));
2293
2294         /* Enable memory arbiter */
2295         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2296
2297         /*
2298          * Poll until we see the 1's complement of the magic number.
2299          * This indicates that the firmware initialization is complete.
2300          */
2301         for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2302                 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2303                 if (val == ~BGE_MAGIC_NUMBER)
2304                         break;
2305                 DELAY(10);
2306         }
2307         if (i == BNX_FIRMWARE_TIMEOUT) {
2308                 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2309                           "timed out, found 0x%08x\n", val);
2310         }
2311
2312         /* BCM57765 A0 needs additional time before accessing. */
2313         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2314                 DELAY(10 * 1000);
2315
2316         /*
2317          * XXX Wait for the value of the PCISTATE register to
2318          * return to its original pre-reset state. This is a
2319          * fairly good indicator of reset completion. If we don't
2320          * wait for the reset to fully complete, trying to read
2321          * from the device's non-PCI registers may yield garbage
2322          * results.
2323          */
2324         for (i = 0; i < BNX_TIMEOUT; i++) {
2325                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2326                         break;
2327                 DELAY(10);
2328         }
2329
2330         /* Fix up byte swapping */
2331         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2332
2333         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2334
2335         /*
2336          * The 5704 in TBI mode apparently needs some special
2337          * adjustment to insure the SERDES drive level is set
2338          * to 1.2V.
2339          */
2340         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2341             (sc->bnx_flags & BNX_FLAG_TBI)) {
2342                 uint32_t serdescfg;
2343
2344                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2345                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2346                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2347         }
2348
2349         CSR_WRITE_4(sc, BGE_MI_MODE,
2350             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2351         DELAY(80);
2352
2353         /* XXX: Broadcom Linux driver. */
2354         if (!BNX_IS_57765_PLUS(sc)) {
2355                 uint32_t v;
2356
2357                 /* Enable Data FIFO protection. */
2358                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2359                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2360         }
2361
2362         DELAY(10000);
2363
2364         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2365                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2366                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2367         }
2368 }
2369
2370 /*
2371  * Frame reception handling. This is called if there's a frame
2372  * on the receive return list.
2373  *
2374  * Note: we have to be able to handle two possibilities here:
2375  * 1) the frame is from the jumbo recieve ring
2376  * 2) the frame is from the standard receive ring
2377  */
2378
2379 static void
2380 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2381 {
2382         struct ifnet *ifp;
2383         int stdcnt = 0, jumbocnt = 0;
2384
2385         ifp = &sc->arpcom.ac_if;
2386
2387         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2388                 struct bge_rx_bd        *cur_rx;
2389                 uint32_t                rxidx;
2390                 struct mbuf             *m = NULL;
2391                 uint16_t                vlan_tag = 0;
2392                 int                     have_tag = 0;
2393
2394                 --count;
2395
2396                 cur_rx =
2397             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2398
2399                 rxidx = cur_rx->bge_idx;
2400                 BNX_INC(sc->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2401
2402                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2403                         have_tag = 1;
2404                         vlan_tag = cur_rx->bge_vlan_tag;
2405                 }
2406
2407                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2408                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2409                         jumbocnt++;
2410
2411                         if (rxidx != sc->bnx_jumbo) {
2412                                 IFNET_STAT_INC(ifp, ierrors, 1);
2413                                 if_printf(ifp, "sw jumbo index(%d) "
2414                                     "and hw jumbo index(%d) mismatch, drop!\n",
2415                                     sc->bnx_jumbo, rxidx);
2416                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2417                                 continue;
2418                         }
2419
2420                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2421                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2422                                 IFNET_STAT_INC(ifp, ierrors, 1);
2423                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2424                                 continue;
2425                         }
2426                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2427                                 IFNET_STAT_INC(ifp, ierrors, 1);
2428                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2429                                 continue;
2430                         }
2431                 } else {
2432                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2433                         stdcnt++;
2434
2435                         if (rxidx != sc->bnx_std) {
2436                                 IFNET_STAT_INC(ifp, ierrors, 1);
2437                                 if_printf(ifp, "sw std index(%d) "
2438                                     "and hw std index(%d) mismatch, drop!\n",
2439                                     sc->bnx_std, rxidx);
2440                                 bnx_setup_rxdesc_std(sc, rxidx);
2441                                 continue;
2442                         }
2443
2444                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2445                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2446                                 IFNET_STAT_INC(ifp, ierrors, 1);
2447                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2448                                 continue;
2449                         }
2450                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2451                                 IFNET_STAT_INC(ifp, ierrors, 1);
2452                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2453                                 continue;
2454                         }
2455                 }
2456
2457                 IFNET_STAT_INC(ifp, ipackets, 1);
2458                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2459                 m->m_pkthdr.rcvif = ifp;
2460
2461                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2462                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2463                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2464                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2465                                 if ((cur_rx->bge_error_flag &
2466                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2467                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2468                         }
2469                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2470                                 m->m_pkthdr.csum_data =
2471                                     cur_rx->bge_tcp_udp_csum;
2472                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2473                                     CSUM_PSEUDO_HDR;
2474                         }
2475                 }
2476
2477                 /*
2478                  * If we received a packet with a vlan tag, pass it
2479                  * to vlan_input() instead of ether_input().
2480                  */
2481                 if (have_tag) {
2482                         m->m_flags |= M_VLANTAG;
2483                         m->m_pkthdr.ether_vlantag = vlan_tag;
2484                 }
2485                 ifp->if_input(ifp, m);
2486         }
2487
2488         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2489         if (stdcnt)
2490                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2491         if (jumbocnt)
2492                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2493 }
2494
2495 static void
2496 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2497 {
2498         struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2499
2500         /*
2501          * Go through our tx ring and free mbufs for those
2502          * frames that have been sent.
2503          */
2504         while (txr->bnx_tx_saved_considx != tx_cons) {
2505                 uint32_t idx = 0;
2506
2507                 idx = txr->bnx_tx_saved_considx;
2508                 if (txr->bnx_tx_chain[idx] != NULL) {
2509                         IFNET_STAT_INC(ifp, opackets, 1);
2510                         bus_dmamap_unload(txr->bnx_tx_mtag,
2511                             txr->bnx_tx_dmamap[idx]);
2512                         m_freem(txr->bnx_tx_chain[idx]);
2513                         txr->bnx_tx_chain[idx] = NULL;
2514                 }
2515                 txr->bnx_txcnt--;
2516                 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2517         }
2518
2519         if ((BGE_TX_RING_CNT - txr->bnx_txcnt) >=
2520             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2521                 ifq_clr_oactive(&ifp->if_snd);
2522
2523         if (txr->bnx_txcnt == 0)
2524                 ifp->if_timer = 0;
2525
2526         if (!ifq_is_empty(&ifp->if_snd))
2527                 if_devstart(ifp);
2528 }
2529
2530 #ifdef IFPOLL_ENABLE
2531
2532 static void
2533 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2534 {
2535         struct bnx_softc *sc = ifp->if_softc;
2536
2537         ASSERT_SERIALIZED(ifp->if_serializer);
2538
2539         if (info != NULL) {
2540                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2541
2542                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2543                 info->ifpi_rx[cpuid].arg = NULL;
2544                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2545
2546                 if (ifp->if_flags & IFF_RUNNING)
2547                         bnx_disable_intr(sc);
2548                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2549         } else {
2550                 if (ifp->if_flags & IFF_RUNNING)
2551                         bnx_enable_intr(sc);
2552                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2553         }
2554 }
2555
2556 static void
2557 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2558 {
2559         struct bnx_softc *sc = ifp->if_softc;
2560         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2561         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2562         uint16_t rx_prod, tx_cons;
2563
2564         ASSERT_SERIALIZED(ifp->if_serializer);
2565
2566         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2567                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2568                 /*
2569                  * Process link state changes.
2570                  */
2571                 bnx_link_poll(sc);
2572         }
2573
2574         sc->bnx_status_tag = sblk->bge_status_tag;
2575
2576         /*
2577          * Use a load fence to ensure that status_tag is saved
2578          * before rx_prod and tx_cons.
2579          */
2580         cpu_lfence();
2581
2582         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2583         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2584
2585         if (sc->bnx_rx_saved_considx != rx_prod)
2586                 bnx_rxeof(sc, rx_prod, cycle);
2587
2588         if (txr->bnx_tx_saved_considx != tx_cons)
2589                 bnx_txeof(txr, tx_cons);
2590
2591         if (sc->bnx_coal_chg)
2592                 bnx_coal_change(sc);
2593 }
2594
2595 #endif  /* IFPOLL_ENABLE */
2596
2597 static void
2598 bnx_intr_legacy(void *xsc)
2599 {
2600         struct bnx_softc *sc = xsc;
2601         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2602
2603         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2604                 uint32_t val;
2605
2606                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2607                 if (val & BGE_PCISTAT_INTR_NOTACT)
2608                         return;
2609         }
2610
2611         /*
2612          * NOTE:
2613          * Interrupt will have to be disabled if tagged status
2614          * is used, else interrupt will always be asserted on
2615          * certain chips (at least on BCM5750 AX/BX).
2616          */
2617         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2618
2619         bnx_intr(sc);
2620 }
2621
2622 static void
2623 bnx_msi(void *xsc)
2624 {
2625         struct bnx_softc *sc = xsc;
2626
2627         /* Disable interrupt first */
2628         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2629         bnx_intr(sc);
2630 }
2631
2632 static void
2633 bnx_msi_oneshot(void *xsc)
2634 {
2635         bnx_intr(xsc);
2636 }
2637
2638 static void
2639 bnx_intr(struct bnx_softc *sc)
2640 {
2641         struct ifnet *ifp = &sc->arpcom.ac_if;
2642         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2643         uint16_t rx_prod, tx_cons;
2644         uint32_t status;
2645
2646         sc->bnx_status_tag = sblk->bge_status_tag;
2647         /*
2648          * Use a load fence to ensure that status_tag is saved 
2649          * before rx_prod, tx_cons and status.
2650          */
2651         cpu_lfence();
2652
2653         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2654         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2655         status = sblk->bge_status;
2656
2657         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2658                 bnx_link_poll(sc);
2659
2660         if (ifp->if_flags & IFF_RUNNING) {
2661                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2662
2663                 if (sc->bnx_rx_saved_considx != rx_prod)
2664                         bnx_rxeof(sc, rx_prod, -1);
2665
2666                 if (txr->bnx_tx_saved_considx != tx_cons)
2667                         bnx_txeof(txr, tx_cons);
2668         }
2669
2670         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2671
2672         if (sc->bnx_coal_chg)
2673                 bnx_coal_change(sc);
2674 }
2675
2676 static void
2677 bnx_tick(void *xsc)
2678 {
2679         struct bnx_softc *sc = xsc;
2680         struct ifnet *ifp = &sc->arpcom.ac_if;
2681
2682         lwkt_serialize_enter(ifp->if_serializer);
2683
2684         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2685
2686         bnx_stats_update_regs(sc);
2687
2688         if (sc->bnx_flags & BNX_FLAG_TBI) {
2689                 /*
2690                  * Since in TBI mode auto-polling can't be used we should poll
2691                  * link status manually. Here we register pending link event
2692                  * and trigger interrupt.
2693                  */
2694                 sc->bnx_link_evt++;
2695                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2696         } else if (!sc->bnx_link) {
2697                 mii_tick(device_get_softc(sc->bnx_miibus));
2698         }
2699
2700         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2701
2702         lwkt_serialize_exit(ifp->if_serializer);
2703 }
2704
2705 static void
2706 bnx_stats_update_regs(struct bnx_softc *sc)
2707 {
2708         struct ifnet *ifp = &sc->arpcom.ac_if;
2709         struct bge_mac_stats_regs stats;
2710         uint32_t *s;
2711         int i;
2712
2713         s = (uint32_t *)&stats;
2714         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2715                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2716                 s++;
2717         }
2718
2719         IFNET_STAT_SET(ifp, collisions,
2720            (stats.dot3StatsSingleCollisionFrames +
2721            stats.dot3StatsMultipleCollisionFrames +
2722            stats.dot3StatsExcessiveCollisions +
2723            stats.dot3StatsLateCollisions));
2724 }
2725
2726 /*
2727  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2728  * pointers to descriptors.
2729  */
2730 static int
2731 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
2732     int *segs_used)
2733 {
2734         struct bge_tx_bd *d = NULL;
2735         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2736         bus_dma_segment_t segs[BNX_NSEG_NEW];
2737         bus_dmamap_t map;
2738         int error, maxsegs, nsegs, idx, i;
2739         struct mbuf *m_head = *m_head0, *m_new;
2740
2741         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2742 #ifdef BNX_TSO_DEBUG
2743                 int tso_nsegs;
2744 #endif
2745
2746                 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
2747                 if (error)
2748                         return error;
2749                 m_head = *m_head0;
2750
2751 #ifdef BNX_TSO_DEBUG
2752                 tso_nsegs = (m_head->m_pkthdr.len /
2753                     m_head->m_pkthdr.tso_segsz) - 1;
2754                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2755                         tso_nsegs = BNX_TSO_NSTATS - 1;
2756                 else if (tso_nsegs < 0)
2757                         tso_nsegs = 0;
2758                 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
2759 #endif
2760         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2761                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2762                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2763                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2764                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2765                 if (m_head->m_flags & M_LASTFRAG)
2766                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2767                 else if (m_head->m_flags & M_FRAG)
2768                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2769         }
2770         if (m_head->m_flags & M_VLANTAG) {
2771                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2772                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2773         }
2774
2775         idx = *txidx;
2776         map = txr->bnx_tx_dmamap[idx];
2777
2778         maxsegs = (BGE_TX_RING_CNT - txr->bnx_txcnt) - BNX_NSEG_RSVD;
2779         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2780                 ("not enough segments %d", maxsegs));
2781
2782         if (maxsegs > BNX_NSEG_NEW)
2783                 maxsegs = BNX_NSEG_NEW;
2784
2785         /*
2786          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2787          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2788          * but when such padded frames employ the bge IP/TCP checksum
2789          * offload, the hardware checksum assist gives incorrect results
2790          * (possibly from incorporating its own padding into the UDP/TCP
2791          * checksum; who knows).  If we pad such runts with zeros, the
2792          * onboard checksum comes out correct.
2793          */
2794         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2795             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2796                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2797                 if (error)
2798                         goto back;
2799         }
2800
2801         if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
2802             m_head->m_next != NULL) {
2803                 m_new = bnx_defrag_shortdma(m_head);
2804                 if (m_new == NULL) {
2805                         error = ENOBUFS;
2806                         goto back;
2807                 }
2808                 *m_head0 = m_head = m_new;
2809         }
2810         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2811             (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
2812             m_head->m_next != NULL) {
2813                 /*
2814                  * Forcefully defragment mbuf chain to overcome hardware
2815                  * limitation which only support a single outstanding
2816                  * DMA read operation.  If it fails, keep moving on using
2817                  * the original mbuf chain.
2818                  */
2819                 m_new = m_defrag(m_head, MB_DONTWAIT);
2820                 if (m_new != NULL)
2821                         *m_head0 = m_head = m_new;
2822         }
2823
2824         error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
2825             m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2826         if (error)
2827                 goto back;
2828         *segs_used += nsegs;
2829
2830         m_head = *m_head0;
2831         bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2832
2833         for (i = 0; ; i++) {
2834                 d = &txr->bnx_tx_ring[idx];
2835
2836                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2837                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2838                 d->bge_len = segs[i].ds_len;
2839                 d->bge_flags = csum_flags;
2840                 d->bge_vlan_tag = vlan_tag;
2841                 d->bge_mss = mss;
2842
2843                 if (i == nsegs - 1)
2844                         break;
2845                 BNX_INC(idx, BGE_TX_RING_CNT);
2846         }
2847         /* Mark the last segment as end of packet... */
2848         d->bge_flags |= BGE_TXBDFLAG_END;
2849
2850         /*
2851          * Insure that the map for this transmission is placed at
2852          * the array index of the last descriptor in this chain.
2853          */
2854         txr->bnx_tx_dmamap[*txidx] = txr->bnx_tx_dmamap[idx];
2855         txr->bnx_tx_dmamap[idx] = map;
2856         txr->bnx_tx_chain[idx] = m_head;
2857         txr->bnx_txcnt += nsegs;
2858
2859         BNX_INC(idx, BGE_TX_RING_CNT);
2860         *txidx = idx;
2861 back:
2862         if (error) {
2863                 m_freem(*m_head0);
2864                 *m_head0 = NULL;
2865         }
2866         return error;
2867 }
2868
2869 /*
2870  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2871  * to the mbuf data regions directly in the transmit descriptors.
2872  */
2873 static void
2874 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2875 {
2876         struct bnx_softc *sc = ifp->if_softc;
2877         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
2878         struct mbuf *m_head = NULL;
2879         uint32_t prodidx;
2880         int nsegs = 0;
2881
2882         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2883
2884         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2885                 return;
2886
2887         prodidx = txr->bnx_tx_prodidx;
2888
2889         while (txr->bnx_tx_chain[prodidx] == NULL) {
2890                 /*
2891                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2892                  * descriptors of the end of the ring.  Also make
2893                  * sure there are BGE_NSEG_SPARE descriptors for
2894                  * jumbo buffers' or TSO segments' defragmentation.
2895                  */
2896                 if ((BGE_TX_RING_CNT - txr->bnx_txcnt) <
2897                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2898                         ifq_set_oactive(&ifp->if_snd);
2899                         break;
2900                 }
2901
2902                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2903                 if (m_head == NULL)
2904                         break;
2905
2906                 /*
2907                  * Pack the data into the transmit ring. If we
2908                  * don't have room, set the OACTIVE flag and wait
2909                  * for the NIC to drain the ring.
2910                  */
2911                 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
2912                         ifq_set_oactive(&ifp->if_snd);
2913                         IFNET_STAT_INC(ifp, oerrors, 1);
2914                         break;
2915                 }
2916
2917                 if (nsegs >= txr->bnx_tx_wreg) {
2918                         /* Transmit */
2919                         bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2920                         nsegs = 0;
2921                 }
2922
2923                 ETHER_BPF_MTAP(ifp, m_head);
2924
2925                 /*
2926                  * Set a timeout in case the chip goes out to lunch.
2927                  */
2928                 ifp->if_timer = 5;
2929         }
2930
2931         if (nsegs > 0) {
2932                 /* Transmit */
2933                 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
2934         }
2935         txr->bnx_tx_prodidx = prodidx;
2936 }
2937
2938 static void
2939 bnx_init(void *xsc)
2940 {
2941         struct bnx_softc *sc = xsc;
2942         struct ifnet *ifp = &sc->arpcom.ac_if;
2943         uint16_t *m;
2944         uint32_t mode;
2945         int i;
2946
2947         ASSERT_SERIALIZED(ifp->if_serializer);
2948
2949         /* Cancel pending I/O and flush buffers. */
2950         bnx_stop(sc);
2951         bnx_reset(sc);
2952         bnx_chipinit(sc);
2953
2954         /*
2955          * Init the various state machines, ring
2956          * control blocks and firmware.
2957          */
2958         if (bnx_blockinit(sc)) {
2959                 if_printf(ifp, "initialization failure\n");
2960                 bnx_stop(sc);
2961                 return;
2962         }
2963
2964         /* Specify MTU. */
2965         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2966             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2967
2968         /* Load our MAC address. */
2969         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2970         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2971         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2972
2973         /* Enable or disable promiscuous mode as needed. */
2974         bnx_setpromisc(sc);
2975
2976         /* Program multicast filter. */
2977         bnx_setmulti(sc);
2978
2979         /* Init RX ring. */
2980         if (bnx_init_rx_ring_std(sc)) {
2981                 if_printf(ifp, "RX ring initialization failed\n");
2982                 bnx_stop(sc);
2983                 return;
2984         }
2985
2986         /* Init jumbo RX ring. */
2987         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
2988                 if (bnx_init_rx_ring_jumbo(sc)) {
2989                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
2990                         bnx_stop(sc);
2991                         return;
2992                 }
2993         }
2994
2995         /* Init our RX return ring index */
2996         sc->bnx_rx_saved_considx = 0;
2997
2998         /* Init TX ring. */
2999         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3000                 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3001
3002         /* Enable TX MAC state machine lockup fix. */
3003         mode = CSR_READ_4(sc, BGE_TX_MODE);
3004         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3005         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3006             sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3007                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3008                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3009                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3010         }
3011         /* Turn on transmitter */
3012         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3013
3014         /* Turn on receiver */
3015         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3016
3017         /*
3018          * Set the number of good frames to receive after RX MBUF
3019          * Low Watermark has been reached.  After the RX MAC receives
3020          * this number of frames, it will drop subsequent incoming
3021          * frames until the MBUF High Watermark is reached.
3022          */
3023         if (BNX_IS_57765_FAMILY(sc))
3024                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3025         else
3026                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3027
3028         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3029                 if (bootverbose) {
3030                         if_printf(ifp, "MSI_MODE: %#x\n",
3031                             CSR_READ_4(sc, BGE_MSI_MODE));
3032                 }
3033         }
3034
3035         /* Tell firmware we're alive. */
3036         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3037
3038         /* Enable host interrupts if polling(4) is not enabled. */
3039         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3040 #ifdef IFPOLL_ENABLE
3041         if (ifp->if_flags & IFF_NPOLLING)
3042                 bnx_disable_intr(sc);
3043         else
3044 #endif
3045         bnx_enable_intr(sc);
3046
3047         bnx_ifmedia_upd(ifp);
3048
3049         ifp->if_flags |= IFF_RUNNING;
3050         ifq_clr_oactive(&ifp->if_snd);
3051
3052         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3053             sc->bnx_stat_cpuid);
3054 }
3055
3056 /*
3057  * Set media options.
3058  */
3059 static int
3060 bnx_ifmedia_upd(struct ifnet *ifp)
3061 {
3062         struct bnx_softc *sc = ifp->if_softc;
3063
3064         /* If this is a 1000baseX NIC, enable the TBI port. */
3065         if (sc->bnx_flags & BNX_FLAG_TBI) {
3066                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3067
3068                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3069                         return(EINVAL);
3070
3071                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3072                 case IFM_AUTO:
3073                         break;
3074
3075                 case IFM_1000_SX:
3076                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3077                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3078                                     BGE_MACMODE_HALF_DUPLEX);
3079                         } else {
3080                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3081                                     BGE_MACMODE_HALF_DUPLEX);
3082                         }
3083                         break;
3084                 default:
3085                         return(EINVAL);
3086                 }
3087         } else {
3088                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3089
3090                 sc->bnx_link_evt++;
3091                 sc->bnx_link = 0;
3092                 if (mii->mii_instance) {
3093                         struct mii_softc *miisc;
3094
3095                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3096                                 mii_phy_reset(miisc);
3097                 }
3098                 mii_mediachg(mii);
3099
3100                 /*
3101                  * Force an interrupt so that we will call bnx_link_upd
3102                  * if needed and clear any pending link state attention.
3103                  * Without this we are not getting any further interrupts
3104                  * for link state changes and thus will not UP the link and
3105                  * not be able to send in bnx_start.  The only way to get
3106                  * things working was to receive a packet and get an RX
3107                  * intr.
3108                  *
3109                  * bnx_tick should help for fiber cards and we might not
3110                  * need to do this here if BNX_FLAG_TBI is set but as
3111                  * we poll for fiber anyway it should not harm.
3112                  */
3113                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3114         }
3115         return(0);
3116 }
3117
3118 /*
3119  * Report current media status.
3120  */
3121 static void
3122 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3123 {
3124         struct bnx_softc *sc = ifp->if_softc;
3125
3126         if (sc->bnx_flags & BNX_FLAG_TBI) {
3127                 ifmr->ifm_status = IFM_AVALID;
3128                 ifmr->ifm_active = IFM_ETHER;
3129                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3130                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3131                         ifmr->ifm_status |= IFM_ACTIVE;
3132                 } else {
3133                         ifmr->ifm_active |= IFM_NONE;
3134                         return;
3135                 }
3136
3137                 ifmr->ifm_active |= IFM_1000_SX;
3138                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3139                         ifmr->ifm_active |= IFM_HDX;    
3140                 else
3141                         ifmr->ifm_active |= IFM_FDX;
3142         } else {
3143                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3144
3145                 mii_pollstat(mii);
3146                 ifmr->ifm_active = mii->mii_media_active;
3147                 ifmr->ifm_status = mii->mii_media_status;
3148         }
3149 }
3150
3151 static int
3152 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3153 {
3154         struct bnx_softc *sc = ifp->if_softc;
3155         struct ifreq *ifr = (struct ifreq *)data;
3156         int mask, error = 0;
3157
3158         ASSERT_SERIALIZED(ifp->if_serializer);
3159
3160         switch (command) {
3161         case SIOCSIFMTU:
3162                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3163                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3164                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3165                         error = EINVAL;
3166                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3167                         ifp->if_mtu = ifr->ifr_mtu;
3168                         if (ifp->if_flags & IFF_RUNNING)
3169                                 bnx_init(sc);
3170                 }
3171                 break;
3172         case SIOCSIFFLAGS:
3173                 if (ifp->if_flags & IFF_UP) {
3174                         if (ifp->if_flags & IFF_RUNNING) {
3175                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3176
3177                                 /*
3178                                  * If only the state of the PROMISC flag
3179                                  * changed, then just use the 'set promisc
3180                                  * mode' command instead of reinitializing
3181                                  * the entire NIC. Doing a full re-init
3182                                  * means reloading the firmware and waiting
3183                                  * for it to start up, which may take a
3184                                  * second or two.  Similarly for ALLMULTI.
3185                                  */
3186                                 if (mask & IFF_PROMISC)
3187                                         bnx_setpromisc(sc);
3188                                 if (mask & IFF_ALLMULTI)
3189                                         bnx_setmulti(sc);
3190                         } else {
3191                                 bnx_init(sc);
3192                         }
3193                 } else if (ifp->if_flags & IFF_RUNNING) {
3194                         bnx_stop(sc);
3195                 }
3196                 sc->bnx_if_flags = ifp->if_flags;
3197                 break;
3198         case SIOCADDMULTI:
3199         case SIOCDELMULTI:
3200                 if (ifp->if_flags & IFF_RUNNING)
3201                         bnx_setmulti(sc);
3202                 break;
3203         case SIOCSIFMEDIA:
3204         case SIOCGIFMEDIA:
3205                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3206                         error = ifmedia_ioctl(ifp, ifr,
3207                             &sc->bnx_ifmedia, command);
3208                 } else {
3209                         struct mii_data *mii;
3210
3211                         mii = device_get_softc(sc->bnx_miibus);
3212                         error = ifmedia_ioctl(ifp, ifr,
3213                                               &mii->mii_media, command);
3214                 }
3215                 break;
3216         case SIOCSIFCAP:
3217                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3218                 if (mask & IFCAP_HWCSUM) {
3219                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3220                         if (ifp->if_capenable & IFCAP_TXCSUM)
3221                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3222                         else
3223                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3224                 }
3225                 if (mask & IFCAP_TSO) {
3226                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3227                         if (ifp->if_capenable & IFCAP_TSO)
3228                                 ifp->if_hwassist |= CSUM_TSO;
3229                         else
3230                                 ifp->if_hwassist &= ~CSUM_TSO;
3231                 }
3232                 break;
3233         default:
3234                 error = ether_ioctl(ifp, command, data);
3235                 break;
3236         }
3237         return error;
3238 }
3239
3240 static void
3241 bnx_watchdog(struct ifnet *ifp)
3242 {
3243         struct bnx_softc *sc = ifp->if_softc;
3244
3245         if_printf(ifp, "watchdog timeout -- resetting\n");
3246
3247         bnx_init(sc);
3248
3249         IFNET_STAT_INC(ifp, oerrors, 1);
3250
3251         if (!ifq_is_empty(&ifp->if_snd))
3252                 if_devstart(ifp);
3253 }
3254
3255 /*
3256  * Stop the adapter and free any mbufs allocated to the
3257  * RX and TX lists.
3258  */
3259 static void
3260 bnx_stop(struct bnx_softc *sc)
3261 {
3262         struct ifnet *ifp = &sc->arpcom.ac_if;
3263         int i;
3264
3265         ASSERT_SERIALIZED(ifp->if_serializer);
3266
3267         callout_stop(&sc->bnx_stat_timer);
3268
3269         /*
3270          * Disable all of the receiver blocks
3271          */
3272         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3273         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3274         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3275         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3276         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3277         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3278
3279         /*
3280          * Disable all of the transmit blocks
3281          */
3282         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3283         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3284         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3285         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3286         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3287         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3288
3289         /*
3290          * Shut down all of the memory managers and related
3291          * state machines.
3292          */
3293         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3294         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3295         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3296         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3297
3298         /* Disable host interrupts. */
3299         bnx_disable_intr(sc);
3300
3301         /*
3302          * Tell firmware we're shutting down.
3303          */
3304         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3305
3306         /* Free the RX lists. */
3307         bnx_free_rx_ring_std(sc);
3308
3309         /* Free jumbo RX list. */
3310         if (BNX_IS_JUMBO_CAPABLE(sc))
3311                 bnx_free_rx_ring_jumbo(sc);
3312
3313         /* Free TX buffers. */
3314         for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3315                 bnx_free_tx_ring(&sc->bnx_tx_ring[i]);
3316
3317         sc->bnx_status_tag = 0;
3318         sc->bnx_link = 0;
3319         sc->bnx_coal_chg = 0;
3320
3321         ifp->if_flags &= ~IFF_RUNNING;
3322         ifq_clr_oactive(&ifp->if_snd);
3323         ifp->if_timer = 0;
3324 }
3325
3326 /*
3327  * Stop all chip I/O so that the kernel's probe routines don't
3328  * get confused by errant DMAs when rebooting.
3329  */
3330 static void
3331 bnx_shutdown(device_t dev)
3332 {
3333         struct bnx_softc *sc = device_get_softc(dev);
3334         struct ifnet *ifp = &sc->arpcom.ac_if;
3335
3336         lwkt_serialize_enter(ifp->if_serializer);
3337         bnx_stop(sc);
3338         bnx_reset(sc);
3339         lwkt_serialize_exit(ifp->if_serializer);
3340 }
3341
3342 static int
3343 bnx_suspend(device_t dev)
3344 {
3345         struct bnx_softc *sc = device_get_softc(dev);
3346         struct ifnet *ifp = &sc->arpcom.ac_if;
3347
3348         lwkt_serialize_enter(ifp->if_serializer);
3349         bnx_stop(sc);
3350         lwkt_serialize_exit(ifp->if_serializer);
3351
3352         return 0;
3353 }
3354
3355 static int
3356 bnx_resume(device_t dev)
3357 {
3358         struct bnx_softc *sc = device_get_softc(dev);
3359         struct ifnet *ifp = &sc->arpcom.ac_if;
3360
3361         lwkt_serialize_enter(ifp->if_serializer);
3362
3363         if (ifp->if_flags & IFF_UP) {
3364                 bnx_init(sc);
3365
3366                 if (!ifq_is_empty(&ifp->if_snd))
3367                         if_devstart(ifp);
3368         }
3369
3370         lwkt_serialize_exit(ifp->if_serializer);
3371
3372         return 0;
3373 }
3374
3375 static void
3376 bnx_setpromisc(struct bnx_softc *sc)
3377 {
3378         struct ifnet *ifp = &sc->arpcom.ac_if;
3379
3380         if (ifp->if_flags & IFF_PROMISC)
3381                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3382         else
3383                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3384 }
3385
3386 static void
3387 bnx_dma_free(struct bnx_softc *sc)
3388 {
3389         int i;
3390
3391         /* Destroy RX mbuf DMA stuffs. */
3392         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3393                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3394                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3395                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3396                 }
3397                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3398                                    sc->bnx_cdata.bnx_rx_tmpmap);
3399                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3400         }
3401
3402         /* Destroy TX rings */
3403         if (sc->bnx_tx_ring != NULL) {
3404                 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3405                         bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3406                 kfree(sc->bnx_tx_ring, M_DEVBUF);
3407         }
3408
3409         /* Destroy standard RX ring */
3410         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3411                            sc->bnx_cdata.bnx_rx_std_ring_map,
3412                            sc->bnx_ldata.bnx_rx_std_ring);
3413
3414         if (BNX_IS_JUMBO_CAPABLE(sc))
3415                 bnx_free_jumbo_mem(sc);
3416
3417         /* Destroy RX return ring */
3418         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3419                            sc->bnx_cdata.bnx_rx_return_ring_map,
3420                            sc->bnx_ldata.bnx_rx_return_ring);
3421
3422         /* Destroy status block */
3423         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3424                            sc->bnx_cdata.bnx_status_map,
3425                            sc->bnx_ldata.bnx_status_block);
3426
3427         /* Destroy the parent tag */
3428         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3429                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3430 }
3431
3432 static int
3433 bnx_dma_alloc(struct bnx_softc *sc)
3434 {
3435         struct ifnet *ifp = &sc->arpcom.ac_if;
3436         int i, error, mbx;
3437
3438         /*
3439          * Allocate the parent bus DMA tag appropriate for PCI.
3440          *
3441          * All of the NetExtreme/NetLink controllers have 4GB boundary
3442          * DMA bug.
3443          * Whenever an address crosses a multiple of the 4GB boundary
3444          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3445          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3446          * state machine will lockup and cause the device to hang.
3447          */
3448         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3449                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3450                                    NULL, NULL,
3451                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3452                                    BUS_SPACE_MAXSIZE_32BIT,
3453                                    0, &sc->bnx_cdata.bnx_parent_tag);
3454         if (error) {
3455                 if_printf(ifp, "could not allocate parent dma tag\n");
3456                 return error;
3457         }
3458
3459         /*
3460          * Create DMA tag and maps for RX mbufs.
3461          */
3462         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3463                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3464                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3465                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3466                                    &sc->bnx_cdata.bnx_rx_mtag);
3467         if (error) {
3468                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3469                 return error;
3470         }
3471
3472         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3473                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3474         if (error) {
3475                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3476                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3477                 return error;
3478         }
3479
3480         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3481                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3482                                           BUS_DMA_WAITOK,
3483                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3484                 if (error) {
3485                         int j;
3486
3487                         for (j = 0; j < i; ++j) {
3488                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3489                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3490                         }
3491                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3492                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3493
3494                         if_printf(ifp, "could not create DMA map for RX\n");
3495                         return error;
3496                 }
3497         }
3498
3499         /*
3500          * Create DMA stuffs for standard RX ring.
3501          */
3502         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3503                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3504                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3505                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3506                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3507         if (error) {
3508                 if_printf(ifp, "could not create std RX ring\n");
3509                 return error;
3510         }
3511
3512         /*
3513          * Create jumbo buffer pool.
3514          */
3515         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3516                 error = bnx_alloc_jumbo_mem(sc);
3517                 if (error) {
3518                         if_printf(ifp, "could not create jumbo buffer pool\n");
3519                         return error;
3520                 }
3521         }
3522
3523         /*
3524          * Create DMA stuffs for RX return ring.
3525          */
3526         error = bnx_dma_block_alloc(sc,
3527             BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
3528             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3529             &sc->bnx_cdata.bnx_rx_return_ring_map,
3530             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3531             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3532         if (error) {
3533                 if_printf(ifp, "could not create RX ret ring\n");
3534                 return error;
3535         }
3536
3537         /*
3538          * Create DMA stuffs for status block.
3539          */
3540         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3541                                     &sc->bnx_cdata.bnx_status_tag,
3542                                     &sc->bnx_cdata.bnx_status_map,
3543                                     (void *)&sc->bnx_ldata.bnx_status_block,
3544                                     &sc->bnx_ldata.bnx_status_block_paddr);
3545         if (error) {
3546                 if_printf(ifp, "could not create status block\n");
3547                 return error;
3548         }
3549
3550         mbx = BGE_MBX_TX_HOST_PROD0_LO;
3551         sc->bnx_tx_ring = kmalloc_cachealign(
3552             sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
3553             M_WAITOK | M_ZERO);
3554         for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3555                 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3556
3557                 txr->bnx_sc = sc;
3558                 txr->bnx_tx_mbx = mbx;
3559
3560                 if (mbx & 0x4)
3561                         mbx -= 0x4;
3562                 else
3563                         mbx += 0xc;
3564
3565                 error = bnx_create_tx_ring(txr);
3566                 if (error) {
3567                         device_printf(sc->bnx_dev,
3568                             "can't create %dth tx ring\n", i);
3569                         return error;
3570                 }
3571         }
3572
3573         return 0;
3574 }
3575
3576 static int
3577 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3578                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3579 {
3580         bus_dmamem_t dmem;
3581         int error;
3582
3583         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3584                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3585                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3586         if (error)
3587                 return error;
3588
3589         *tag = dmem.dmem_tag;
3590         *map = dmem.dmem_map;
3591         *addr = dmem.dmem_addr;
3592         *paddr = dmem.dmem_busaddr;
3593
3594         return 0;
3595 }
3596
3597 static void
3598 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3599 {
3600         if (tag != NULL) {
3601                 bus_dmamap_unload(tag, map);
3602                 bus_dmamem_free(tag, addr, map);
3603                 bus_dma_tag_destroy(tag);
3604         }
3605 }
3606
3607 static void
3608 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3609 {
3610         struct ifnet *ifp = &sc->arpcom.ac_if;
3611
3612 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3613
3614         /*
3615          * Sometimes PCS encoding errors are detected in
3616          * TBI mode (on fiber NICs), and for some reason
3617          * the chip will signal them as link changes.
3618          * If we get a link change event, but the 'PCS
3619          * encoding error' bit in the MAC status register
3620          * is set, don't bother doing a link check.
3621          * This avoids spurious "gigabit link up" messages
3622          * that sometimes appear on fiber NICs during
3623          * periods of heavy traffic.
3624          */
3625         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3626                 if (!sc->bnx_link) {
3627                         sc->bnx_link++;
3628                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3629                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3630                                     BGE_MACMODE_TBI_SEND_CFGS);
3631                         }
3632                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3633
3634                         if (bootverbose)
3635                                 if_printf(ifp, "link UP\n");
3636
3637                         ifp->if_link_state = LINK_STATE_UP;
3638                         if_link_state_change(ifp);
3639                 }
3640         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3641                 if (sc->bnx_link) {
3642                         sc->bnx_link = 0;
3643
3644                         if (bootverbose)
3645                                 if_printf(ifp, "link DOWN\n");
3646
3647                         ifp->if_link_state = LINK_STATE_DOWN;
3648                         if_link_state_change(ifp);
3649                 }
3650         }
3651
3652 #undef PCS_ENCODE_ERR
3653
3654         /* Clear the attention. */
3655         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3656             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3657             BGE_MACSTAT_LINK_CHANGED);
3658 }
3659
3660 static void
3661 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3662 {
3663         struct ifnet *ifp = &sc->arpcom.ac_if;
3664         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3665
3666         mii_pollstat(mii);
3667         bnx_miibus_statchg(sc->bnx_dev);
3668
3669         if (bootverbose) {
3670                 if (sc->bnx_link)
3671                         if_printf(ifp, "link UP\n");
3672                 else
3673                         if_printf(ifp, "link DOWN\n");
3674         }
3675
3676         /* Clear the attention. */
3677         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3678             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3679             BGE_MACSTAT_LINK_CHANGED);
3680 }
3681
3682 static void
3683 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3684 {
3685         struct ifnet *ifp = &sc->arpcom.ac_if;
3686         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3687
3688         mii_pollstat(mii);
3689
3690         if (!sc->bnx_link &&
3691             (mii->mii_media_status & IFM_ACTIVE) &&
3692             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3693                 sc->bnx_link++;
3694                 if (bootverbose)
3695                         if_printf(ifp, "link UP\n");
3696         } else if (sc->bnx_link &&
3697             (!(mii->mii_media_status & IFM_ACTIVE) ||
3698             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3699                 sc->bnx_link = 0;
3700                 if (bootverbose)
3701                         if_printf(ifp, "link DOWN\n");
3702         }
3703
3704         /* Clear the attention. */
3705         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3706             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3707             BGE_MACSTAT_LINK_CHANGED);
3708 }
3709
3710 static int
3711 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3712 {
3713         struct bnx_softc *sc = arg1;
3714
3715         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3716             &sc->bnx_rx_coal_ticks,
3717             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3718             BNX_RX_COAL_TICKS_CHG);
3719 }
3720
3721 static int
3722 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3723 {
3724         struct bnx_softc *sc = arg1;
3725
3726         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3727             &sc->bnx_tx_coal_ticks,
3728             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3729             BNX_TX_COAL_TICKS_CHG);
3730 }
3731
3732 static int
3733 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3734 {
3735         struct bnx_softc *sc = arg1;
3736
3737         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3738             &sc->bnx_rx_coal_bds,
3739             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3740             BNX_RX_COAL_BDS_CHG);
3741 }
3742
3743 static int
3744 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3745 {
3746         struct bnx_softc *sc = arg1;
3747
3748         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3749             &sc->bnx_tx_coal_bds,
3750             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3751             BNX_TX_COAL_BDS_CHG);
3752 }
3753
3754 static int
3755 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3756 {
3757         struct bnx_softc *sc = arg1;
3758
3759         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3760             &sc->bnx_rx_coal_bds_int,
3761             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3762             BNX_RX_COAL_BDS_INT_CHG);
3763 }
3764
3765 static int
3766 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3767 {
3768         struct bnx_softc *sc = arg1;
3769
3770         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3771             &sc->bnx_tx_coal_bds_int,
3772             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3773             BNX_TX_COAL_BDS_INT_CHG);
3774 }
3775
3776 static int
3777 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3778     int coal_min, int coal_max, uint32_t coal_chg_mask)
3779 {
3780         struct bnx_softc *sc = arg1;
3781         struct ifnet *ifp = &sc->arpcom.ac_if;
3782         int error = 0, v;
3783
3784         lwkt_serialize_enter(ifp->if_serializer);
3785
3786         v = *coal;
3787         error = sysctl_handle_int(oidp, &v, 0, req);
3788         if (!error && req->newptr != NULL) {
3789                 if (v < coal_min || v > coal_max) {
3790                         error = EINVAL;
3791                 } else {
3792                         *coal = v;
3793                         sc->bnx_coal_chg |= coal_chg_mask;
3794                 }
3795         }
3796
3797         lwkt_serialize_exit(ifp->if_serializer);
3798         return error;
3799 }
3800
3801 static void
3802 bnx_coal_change(struct bnx_softc *sc)
3803 {
3804         struct ifnet *ifp = &sc->arpcom.ac_if;
3805
3806         ASSERT_SERIALIZED(ifp->if_serializer);
3807
3808         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3809                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3810                             sc->bnx_rx_coal_ticks);
3811                 DELAY(10);
3812                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3813
3814                 if (bootverbose) {
3815                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3816                                   sc->bnx_rx_coal_ticks);
3817                 }
3818         }
3819
3820         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3821                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3822                             sc->bnx_tx_coal_ticks);
3823                 DELAY(10);
3824                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3825
3826                 if (bootverbose) {
3827                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3828                                   sc->bnx_tx_coal_ticks);
3829                 }
3830         }
3831
3832         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3833                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3834                             sc->bnx_rx_coal_bds);
3835                 DELAY(10);
3836                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3837
3838                 if (bootverbose) {
3839                         if_printf(ifp, "rx_coal_bds -> %u\n",
3840                                   sc->bnx_rx_coal_bds);
3841                 }
3842         }
3843
3844         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3845                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3846                             sc->bnx_tx_coal_bds);
3847                 DELAY(10);
3848                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3849
3850                 if (bootverbose) {
3851                         if_printf(ifp, "tx_coal_bds -> %u\n",
3852                                   sc->bnx_tx_coal_bds);
3853                 }
3854         }
3855
3856         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3857                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3858                     sc->bnx_rx_coal_bds_int);
3859                 DELAY(10);
3860                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3861
3862                 if (bootverbose) {
3863                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3864                             sc->bnx_rx_coal_bds_int);
3865                 }
3866         }
3867
3868         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
3869                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
3870                     sc->bnx_tx_coal_bds_int);
3871                 DELAY(10);
3872                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
3873
3874                 if (bootverbose) {
3875                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
3876                             sc->bnx_tx_coal_bds_int);
3877                 }
3878         }
3879
3880         sc->bnx_coal_chg = 0;
3881 }
3882
3883 static void
3884 bnx_intr_check(void *xsc)
3885 {
3886         struct bnx_softc *sc = xsc;
3887         struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0]; /* XXX */
3888         struct ifnet *ifp = &sc->arpcom.ac_if;
3889         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
3890
3891         lwkt_serialize_enter(ifp->if_serializer);
3892
3893         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
3894
3895         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
3896                 lwkt_serialize_exit(ifp->if_serializer);
3897                 return;
3898         }
3899
3900         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
3901             sblk->bge_idx[0].bge_tx_cons_idx != txr->bnx_tx_saved_considx) {
3902                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
3903                     sc->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
3904                         if (!sc->bnx_intr_maylose) {
3905                                 sc->bnx_intr_maylose = TRUE;
3906                                 goto done;
3907                         }
3908                         if (bootverbose)
3909                                 if_printf(ifp, "lost interrupt\n");
3910                         bnx_msi(sc);
3911                 }
3912         }
3913         sc->bnx_intr_maylose = FALSE;
3914         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
3915         sc->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
3916
3917 done:
3918         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3919             bnx_intr_check, sc);
3920         lwkt_serialize_exit(ifp->if_serializer);
3921 }
3922
3923 static void
3924 bnx_enable_intr(struct bnx_softc *sc)
3925 {
3926         struct ifnet *ifp = &sc->arpcom.ac_if;
3927
3928         lwkt_serialize_handler_enable(ifp->if_serializer);
3929
3930         /*
3931          * Enable interrupt.
3932          */
3933         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3934         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
3935                 /* XXX Linux driver */
3936                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
3937         }
3938
3939         /*
3940          * Unmask the interrupt when we stop polling.
3941          */
3942         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3943             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3944
3945         /*
3946          * Trigger another interrupt, since above writing
3947          * to interrupt mailbox0 may acknowledge pending
3948          * interrupt.
3949          */
3950         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3951
3952         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
3953                 sc->bnx_intr_maylose = FALSE;
3954                 sc->bnx_rx_check_considx = 0;
3955                 sc->bnx_tx_check_considx = 0;
3956
3957                 if (bootverbose)
3958                         if_printf(ifp, "status tag bug workaround\n");
3959
3960                 /* 10ms check interval */
3961                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
3962                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
3963         }
3964 }
3965
3966 static void
3967 bnx_disable_intr(struct bnx_softc *sc)
3968 {
3969         struct ifnet *ifp = &sc->arpcom.ac_if;
3970
3971         /*
3972          * Mask the interrupt when we start polling.
3973          */
3974         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
3975             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
3976
3977         /*
3978          * Acknowledge possible asserted interrupt.
3979          */
3980         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3981
3982         callout_stop(&sc->bnx_intr_timer);
3983         sc->bnx_intr_maylose = FALSE;
3984         sc->bnx_rx_check_considx = 0;
3985         sc->bnx_tx_check_considx = 0;
3986
3987         sc->bnx_npoll.ifpc_stcount = 0;
3988
3989         lwkt_serialize_handler_disable(ifp->if_serializer);
3990 }
3991
3992 static int
3993 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
3994 {
3995         uint32_t mac_addr;
3996         int ret = 1;
3997
3998         mac_addr = bnx_readmem_ind(sc, 0x0c14);
3999         if ((mac_addr >> 16) == 0x484b) {
4000                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4001                 ether_addr[1] = (uint8_t)mac_addr;
4002                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4003                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4004                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4005                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4006                 ether_addr[5] = (uint8_t)mac_addr;
4007                 ret = 0;
4008         }
4009         return ret;
4010 }
4011
4012 static int
4013 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4014 {
4015         int mac_offset = BGE_EE_MAC_OFFSET;
4016
4017         if (BNX_IS_5717_PLUS(sc)) {
4018                 int f;
4019
4020                 f = pci_get_function(sc->bnx_dev);
4021                 if (f & 1)
4022                         ma