2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
32 #include <sys/machintr.h>
33 #include <sys/thread2.h>
35 #include <machine/pmap.h>
36 #include <machine_base/icu/icu_var.h>
37 #include <machine_base/apic/lapic.h>
38 #include <machine_base/apic/ioapic.h>
39 #include <machine_base/apic/ioapic_abi.h>
41 #define IOAPIC_COUNT_MAX 16
42 #define IOAPIC_ID_MASK (IOAPIC_COUNT_MAX - 1)
45 extern pt_entry_t *SMPpt;
54 TAILQ_ENTRY(ioapic_info) io_link;
56 TAILQ_HEAD(ioapic_info_list, ioapic_info);
58 struct ioapic_intsrc {
60 enum intr_trigger int_trig;
61 enum intr_polarity int_pola;
65 struct ioapic_info_list ioc_list;
66 struct ioapic_intsrc ioc_intsrc[16]; /* XXX magic number */
69 static void ioapic_setup(const struct ioapic_info *);
70 static int ioapic_alloc_apic_id(int);
71 static void ioapic_set_apic_id(const struct ioapic_info *);
72 static void ioapic_gsi_setup(int);
73 static const struct ioapic_info *
74 ioapic_gsi_search(int);
75 static void ioapic_pin_prog(void *, int, int,
76 enum intr_trigger, enum intr_polarity, uint32_t);
78 static struct ioapic_conf ioapic_conf;
80 static TAILQ_HEAD(, ioapic_enumerator) ioapic_enumerators =
81 TAILQ_HEAD_INITIALIZER(ioapic_enumerators);
83 int ioapic_enable = 1; /* I/O APIC is enabled by default */
88 struct ioapic_info *info;
89 int start_apic_id = 0;
90 struct ioapic_enumerator *e;
94 TAILQ_INIT(&ioapic_conf.ioc_list);
95 /* XXX magic number */
96 for (i = 0; i < 16; ++i)
97 ioapic_conf.ioc_intsrc[i].int_gsi = -1;
100 TUNABLE_INT_FETCH("hw.ioapic_probe", &probe);
102 kprintf("IOAPIC: warning I/O APIC will not be probed\n");
106 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
107 error = e->ioapic_probe(e);
112 kprintf("IOAPIC: can't find I/O APIC\n");
122 * Switch to I/O APIC MachIntrABI and reconfigure
123 * the default IDT entries.
125 MachIntrABI = MachIntrABI_IOAPIC;
126 MachIntrABI.setdefault();
128 e->ioapic_enumerate(e);
134 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
137 if (i > IOAPIC_COUNT_MAX) /* XXX magic number */
138 panic("ioapic_config: more than 16 I/O APIC\n");
143 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
146 apic_id = ioapic_alloc_apic_id(start_apic_id);
147 if (apic_id == NAPICID) {
148 kprintf("IOAPIC: can't alloc APIC ID for "
149 "%dth I/O APIC\n", info->io_idx);
152 info->io_apic_id = apic_id;
154 start_apic_id = apic_id + 1;
158 * xAPIC allows I/O APIC's APIC ID to be same
159 * as the LAPIC's APIC ID
161 kprintf("IOAPIC: use xAPIC model to alloc APIC ID "
164 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
165 info->io_apic_id = info->io_idx;
169 * Warning about any GSI holes
171 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
172 const struct ioapic_info *prev_info;
174 prev_info = TAILQ_PREV(info, ioapic_info_list, io_link);
175 if (prev_info != NULL) {
176 if (info->io_gsi_base !=
177 prev_info->io_gsi_base + prev_info->io_npin) {
178 kprintf("IOAPIC: warning gsi hole "
180 prev_info->io_gsi_base +
182 info->io_gsi_base - 1);
188 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
189 kprintf("IOAPIC: idx %d, apic id %d, "
190 "gsi base %d, npin %d\n",
201 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link)
203 ioapic_abi_fixup_irqmap();
207 MachIntrABI.cleanup();
215 ioapic_enumerator_register(struct ioapic_enumerator *ne)
217 struct ioapic_enumerator *e;
219 TAILQ_FOREACH(e, &ioapic_enumerators, ioapic_link) {
220 if (e->ioapic_prio < ne->ioapic_prio) {
221 TAILQ_INSERT_BEFORE(e, ne, ioapic_link);
225 TAILQ_INSERT_TAIL(&ioapic_enumerators, ne, ioapic_link);
229 ioapic_add(void *addr, int gsi_base, int npin)
231 struct ioapic_info *info, *ninfo;
234 gsi_end = gsi_base + npin - 1;
235 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
236 if ((gsi_base >= info->io_gsi_base &&
237 gsi_base < info->io_gsi_base + info->io_npin) ||
238 (gsi_end >= info->io_gsi_base &&
239 gsi_end < info->io_gsi_base + info->io_npin)) {
240 panic("ioapic_add: overlapped gsi, base %d npin %d, "
241 "hit base %d, npin %d\n", gsi_base, npin,
242 info->io_gsi_base, info->io_npin);
244 if (info->io_addr == addr)
245 panic("ioapic_add: duplicated addr %p\n", addr);
248 ninfo = kmalloc(sizeof(*ninfo), M_DEVBUF, M_WAITOK | M_ZERO);
249 ninfo->io_addr = addr;
250 ninfo->io_npin = npin;
251 ninfo->io_gsi_base = gsi_base;
252 ninfo->io_apic_id = -1;
255 * Create IOAPIC list in ascending order of GSI base
257 TAILQ_FOREACH_REVERSE(info, &ioapic_conf.ioc_list,
258 ioapic_info_list, io_link) {
259 if (ninfo->io_gsi_base > info->io_gsi_base) {
260 TAILQ_INSERT_AFTER(&ioapic_conf.ioc_list,
261 info, ninfo, io_link);
266 TAILQ_INSERT_HEAD(&ioapic_conf.ioc_list, ninfo, io_link);
270 ioapic_intsrc(int irq, int gsi, enum intr_trigger trig, enum intr_polarity pola)
272 struct ioapic_intsrc *int_src;
275 int_src = &ioapic_conf.ioc_intsrc[irq];
278 /* Don't allow mixed mode */
279 kprintf("IOAPIC: warning intsrc irq %d -> gsi 0\n", irq);
283 if (int_src->int_gsi != -1) {
284 if (int_src->int_gsi != gsi) {
285 kprintf("IOAPIC: warning intsrc irq %d, gsi "
286 "%d -> %d\n", irq, int_src->int_gsi, gsi);
288 if (int_src->int_trig != trig) {
289 kprintf("IOAPIC: warning intsrc irq %d, trig "
291 intr_str_trigger(int_src->int_trig),
292 intr_str_trigger(trig));
294 if (int_src->int_pola != pola) {
295 kprintf("IOAPIC: warning intsrc irq %d, pola "
297 intr_str_polarity(int_src->int_pola),
298 intr_str_polarity(pola));
301 int_src->int_gsi = gsi;
302 int_src->int_trig = trig;
303 int_src->int_pola = pola;
307 ioapic_set_apic_id(const struct ioapic_info *info)
312 id = ioapic_read(info->io_addr, IOAPIC_ID);
315 id |= (info->io_apic_id << 24);
317 ioapic_write(info->io_addr, IOAPIC_ID, id);
322 id = ioapic_read(info->io_addr, IOAPIC_ID);
323 apic_id = (id & APIC_ID_MASK) >> 24;
326 * I/O APIC ID is a 4bits field
328 if ((apic_id & IOAPIC_ID_MASK) !=
329 (info->io_apic_id & IOAPIC_ID_MASK)) {
330 panic("ioapic_set_apic_id: can't set apic id to %d, "
331 "currently set to %d\n", info->io_apic_id, apic_id);
336 ioapic_gsi_setup(int gsi)
338 enum intr_trigger trig;
339 enum intr_polarity pola;
345 ioapic_extpin_setup(ioapic_gsi_ioaddr(gsi),
346 ioapic_gsi_pin(gsi), 0);
351 trig = 0; /* silence older gcc's */
352 pola = 0; /* silence older gcc's */
354 for (irq = 0; irq < 16; ++irq) {
355 const struct ioapic_intsrc *int_src =
356 &ioapic_conf.ioc_intsrc[irq];
358 if (gsi == int_src->int_gsi) {
359 trig = int_src->int_trig;
360 pola = int_src->int_pola;
367 trig = INTR_TRIGGER_EDGE;
368 pola = INTR_POLARITY_HIGH;
370 trig = INTR_TRIGGER_LEVEL;
371 pola = INTR_POLARITY_LOW;
376 ioapic_abi_set_irqmap(irq, gsi, trig, pola);
380 ioapic_gsi_ioaddr(int gsi)
382 const struct ioapic_info *info;
384 info = ioapic_gsi_search(gsi);
385 return info->io_addr;
389 ioapic_gsi_pin(int gsi)
391 const struct ioapic_info *info;
393 info = ioapic_gsi_search(gsi);
394 return gsi - info->io_gsi_base;
397 static const struct ioapic_info *
398 ioapic_gsi_search(int gsi)
400 const struct ioapic_info *info;
402 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
403 if (gsi >= info->io_gsi_base &&
404 gsi < info->io_gsi_base + info->io_npin)
407 panic("ioapic_gsi_search: no I/O APIC\n");
411 ioapic_gsi(int idx, int pin)
413 const struct ioapic_info *info;
415 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
416 if (info->io_idx == idx)
421 if (pin >= info->io_npin)
423 return info->io_gsi_base + pin;
427 ioapic_extpin_setup(void *addr, int pin, int vec)
429 ioapic_pin_prog(addr, pin, vec,
430 INTR_TRIGGER_CONFORM, INTR_POLARITY_CONFORM, IOART_DELEXINT);
434 ioapic_extpin_gsi(void)
440 ioapic_pin_setup(void *addr, int pin, int vec,
441 enum intr_trigger trig, enum intr_polarity pola)
444 * Always clear an I/O APIC pin before [re]programming it. This is
445 * particularly important if the pin is set up for a level interrupt
446 * as the IOART_REM_IRR bit might be set. When we reprogram the
447 * vector any EOI from pending ints on this pin could be lost and
448 * IRR might never get reset.
450 * To fix this problem, clear the vector and make sure it is
451 * programmed as an edge interrupt. This should theoretically
452 * clear IRR so we can later, safely program it as a level
455 ioapic_pin_prog(addr, pin, vec, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH,
457 ioapic_pin_prog(addr, pin, vec, trig, pola, IOART_DELFIXED);
461 ioapic_pin_prog(void *addr, int pin, int vec,
462 enum intr_trigger trig, enum intr_polarity pola, uint32_t del_mode)
464 uint32_t flags, target;
467 KKASSERT(del_mode == IOART_DELEXINT || del_mode == IOART_DELFIXED);
469 select = IOAPIC_REDTBL0 + (2 * pin);
471 flags = ioapic_read(addr, select) & IOART_RESV;
472 flags |= IOART_INTMSET | IOART_DESTPHY;
477 * We only support limited I/O APIC mixed mode,
478 * so even for ExtINT, we still use "fixed"
481 flags |= IOART_DELFIXED;
484 if (del_mode == IOART_DELEXINT) {
485 KKASSERT(trig == INTR_TRIGGER_CONFORM &&
486 pola == INTR_POLARITY_CONFORM);
487 flags |= IOART_TRGREDG | IOART_INTAHI;
490 case INTR_TRIGGER_EDGE:
491 flags |= IOART_TRGREDG;
494 case INTR_TRIGGER_LEVEL:
495 flags |= IOART_TRGRLVL;
498 case INTR_TRIGGER_CONFORM:
499 panic("ioapic_pin_prog: trig conform is not "
503 case INTR_POLARITY_HIGH:
504 flags |= IOART_INTAHI;
507 case INTR_POLARITY_LOW:
508 flags |= IOART_INTALO;
511 case INTR_POLARITY_CONFORM:
512 panic("ioapic_pin_prog: pola conform is not "
517 target = ioapic_read(addr, select + 1) & IOART_HI_DEST_RESV;
518 target |= (CPUID_TO_APICID(0) << IOART_HI_DEST_SHIFT) &
521 ioapic_write(addr, select, flags | vec);
522 ioapic_write(addr, select + 1, target);
526 ioapic_setup(const struct ioapic_info *info)
530 ioapic_set_apic_id(info);
532 for (i = 0; i < info->io_npin; ++i)
533 ioapic_gsi_setup(info->io_gsi_base + i);
537 ioapic_alloc_apic_id(int start)
540 const struct ioapic_info *info;
541 int apic_id, apic_id16;
543 apic_id = lapic_unused_apic_id(start);
544 if (apic_id == NAPICID) {
545 kprintf("IOAPIC: can't find unused APIC ID\n");
548 apic_id16 = apic_id & IOAPIC_ID_MASK;
551 * Check against other I/O APIC's APIC ID's lower 4bits.
553 * The new APIC ID will have to be different from others
554 * in the lower 4bits, no matter whether xAPIC is used
557 TAILQ_FOREACH(info, &ioapic_conf.ioc_list, io_link) {
558 if (info->io_apic_id == -1) {
562 if ((info->io_apic_id & IOAPIC_ID_MASK) == apic_id16)
568 kprintf("IOAPIC: APIC ID %d has same lower 4bits as "
569 "%dth I/O APIC, keep searching...\n",
570 apic_id, info->io_idx);
574 panic("ioapic_unused_apic_id: never reached\n");
578 ioapic_map(vm_paddr_t pa)
580 KKASSERT(pa < 0x100000000LL);
581 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
585 ioapic_sysinit(void *dummy __unused)
592 KASSERT(lapic_enable, ("I/O APIC is enabled, but LAPIC is disabled\n"));
593 error = ioapic_config();
596 icu_reinit_noioapic();
597 lapic_fixup_noioapic();
600 SYSINIT(ioapic, SI_BOOT2_IOAPIC, SI_ORDER_FIRST, ioapic_sysinit, NULL)