sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/async.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/drm_legacy.h>
  34 #include "intel_drv.h"
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_vgpu.h"
  38
  39
  40 static int i915_getparam(struct drm_device *dev, void *data,
  41                          struct drm_file *file_priv)
  42 {
  43         struct drm_i915_private *dev_priv = dev->dev_private;
  44         drm_i915_getparam_t *param = data;
  45         int value;
  46
  47         switch (param->param) {
  48         case I915_PARAM_IRQ_ACTIVE:
  49         case I915_PARAM_ALLOW_BATCHBUFFER:
  50         case I915_PARAM_LAST_DISPATCH:
  51                 /* Reject all old ums/dri params. */
  52                 return -ENODEV;
  53         case I915_PARAM_CHIPSET_ID:
  54                 value = dev->pdev->device;
  55                 break;
  56         case I915_PARAM_REVISION:
  57                 value = dev->pdev->revision;
  58                 break;
  59         case I915_PARAM_HAS_GEM:
  60                 value = 1;
  61                 break;
  62         case I915_PARAM_NUM_FENCES_AVAIL:
  63                 value = dev_priv->num_fence_regs;
  64                 break;
  65         case I915_PARAM_HAS_OVERLAY:
  66                 value = dev_priv->overlay ? 1 : 0;
  67                 break;
  68         case I915_PARAM_HAS_PAGEFLIPPING:
  69                 value = 1;
  70                 break;
  71         case I915_PARAM_HAS_EXECBUF2:
  72                 /* depends on GEM */
  73                 value = 1;
  74                 break;
  75         case I915_PARAM_HAS_BSD:
  76                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  77                 break;
  78         case I915_PARAM_HAS_BLT:
  79                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  80                 break;
  81         case I915_PARAM_HAS_VEBOX:
  82                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  83                 break;
  84         case I915_PARAM_HAS_BSD2:
  85                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  86                 break;
  87         case I915_PARAM_HAS_RELAXED_FENCING:
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_COHERENT_RINGS:
  91                 value = 1;
  92                 break;
  93         case I915_PARAM_HAS_EXEC_CONSTANTS:
  94                 value = INTEL_INFO(dev)->gen >= 4;
  95                 break;
  96         case I915_PARAM_HAS_RELAXED_DELTA:
  97                 value = 1;
  98                 break;
  99         case I915_PARAM_HAS_GEN7_SOL_RESET:
 100                 value = 1;
 101                 break;
 102         case I915_PARAM_HAS_LLC:
 103                 value = HAS_LLC(dev);
 104                 break;
 105         case I915_PARAM_HAS_WT:
 106                 value = HAS_WT(dev);
 107                 break;
 108         case I915_PARAM_HAS_ALIASING_PPGTT:
 109                 value = USES_PPGTT(dev);
 110                 break;
 111         case I915_PARAM_HAS_WAIT_TIMEOUT:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_SEMAPHORES:
 115                 value = i915_semaphore_is_enabled(dev);
 116                 break;
 117         case I915_PARAM_HAS_PINNED_BATCHES:
 118                 value = 1;
 119                 break;
 120         case I915_PARAM_HAS_EXEC_NO_RELOC:
 121                 value = 1;
 122                 break;
 123         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 124                 value = 1;
 125                 break;
 126         case I915_PARAM_CMD_PARSER_VERSION:
 127                 value = i915_cmd_parser_get_version();
 128                 break;
 129         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 130                 value = 1;
 131                 break;
 132         case I915_PARAM_SUBSLICE_TOTAL:
 133                 value = INTEL_INFO(dev)->subslice_total;
 134                 if (!value)
 135                         return -ENODEV;
 136                 break;
 137         case I915_PARAM_EU_TOTAL:
 138                 value = INTEL_INFO(dev)->eu_total;
 139                 if (!value)
 140                         return -ENODEV;
 141                 break;
 142         case I915_PARAM_HAS_GPU_RESET:
 143                 value = i915.enable_hangcheck &&
 144                         intel_has_gpu_reset(dev);
 145                 break;
 146         case I915_PARAM_HAS_RESOURCE_STREAMER:
 147                 value = HAS_RESOURCE_STREAMER(dev);
 148                 break;
 149         default:
 150                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 151                 return -EINVAL;
 152         }
 153
 154         if (copy_to_user(param->value, &value, sizeof(int))) {
 155                 DRM_ERROR("copy_to_user failed\n");
 156                 return -EFAULT;
 157         }
 158
 159         return 0;
 160 }
 161
 162 static int i915_get_bridge_dev(struct drm_device *dev)
 163 {
 164         struct drm_i915_private *dev_priv = dev->dev_private;
 165         static struct pci_dev i915_bridge_dev;
 166
 167         i915_bridge_dev.dev.bsddev = pci_find_dbsf(0, 0, 0, 0);
 168         if (!i915_bridge_dev.dev.bsddev) {
 169                 DRM_ERROR("bridge device not found\n");
 170                 return -1;
 171         }
 172
 173         dev_priv->bridge_dev = &i915_bridge_dev;
 174         return 0;
 175 }
 176
 177 #define MCHBAR_I915 0x44
 178 #define MCHBAR_I965 0x48
 179 #define MCHBAR_SIZE (4*4096)
 180
 181 #define DEVEN_REG 0x54
 182 #define   DEVEN_MCHBAR_EN (1 << 28)
 183
 184 /* Allocate space for the MCH regs if needed, return nonzero on error */
 185 static int
 186 intel_alloc_mchbar_resource(struct drm_device *dev)
 187 {
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 190         device_t vga;
 191         u32 temp_lo, temp_hi = 0;
 192         u64 mchbar_addr;
 193
 194         if (INTEL_INFO(dev)->gen >= 4)
 195                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 196         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 197         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 198
 199         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 200 #ifdef CONFIG_PNP
 201         if (mchbar_addr &&
 202             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 203                 return 0;
 204 #endif
 205
 206         /* Get some space for it */
 207         vga = device_get_parent(dev->dev->bsddev);
 208         dev_priv->mch_res_rid = 0x100;
 209         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
 210             dev->dev->bsddev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
 211             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
 212         if (dev_priv->mch_res == NULL) {
 213                 DRM_ERROR("failed mchbar resource alloc\n");
 214                 return (-ENOMEM);
 215         }
 216
 217         if (INTEL_INFO(dev)->gen >= 4)
 218                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 219                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
 220
 221         pci_write_config_dword(dev_priv->bridge_dev, reg,
 222                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
 223         return 0;
 224 }
 225
 226 /* Setup MCHBAR if possible, return true if we should disable it again */
 227 static void
 228 intel_setup_mchbar(struct drm_device *dev)
 229 {
 230         struct drm_i915_private *dev_priv = dev->dev_private;
 231         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 232         u32 temp;
 233         bool enabled;
 234
 235         if (IS_VALLEYVIEW(dev))
 236                 return;
 237
 238         dev_priv->mchbar_need_disable = false;
 239
 240         if (IS_I915G(dev) || IS_I915GM(dev)) {
 241                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 242                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 243         } else {
 244                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 245                 enabled = temp & 1;
 246         }
 247
 248         /* If it's already enabled, don't have to do anything */
 249         if (enabled)
 250                 return;
 251
 252         if (intel_alloc_mchbar_resource(dev))
 253                 return;
 254
 255         dev_priv->mchbar_need_disable = true;
 256
 257         /* Space is allocated or reserved, so enable it. */
 258         if (IS_I915G(dev) || IS_I915GM(dev)) {
 259                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 260                                        temp | DEVEN_MCHBAR_EN);
 261         } else {
 262                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 263                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 264         }
 265 }
 266
 267 static void
 268 intel_teardown_mchbar(struct drm_device *dev)
 269 {
 270         struct drm_i915_private *dev_priv = dev->dev_private;
 271         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 272         device_t vga;
 273         u32 temp;
 274
 275         if (dev_priv->mchbar_need_disable) {
 276                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 277                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 278                         temp &= ~DEVEN_MCHBAR_EN;
 279                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 280                 } else {
 281                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 282                         temp &= ~1;
 283                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 284                 }
 285         }
 286
 287         if (dev_priv->mch_res != NULL) {
 288                 vga = device_get_parent(dev->dev->bsddev);
 289                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
 290                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 291                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev->bsddev,
 292                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 293                 dev_priv->mch_res = NULL;
 294         }
 295 }
 296
 297 #if 0
 298 /* true = enable decode, false = disable decoder */
 299 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 300 {
 301         struct drm_device *dev = cookie;
 302
 303         intel_modeset_vga_set_state(dev, state);
 304         if (state)
 305                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 306                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 307         else
 308                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 309 }
 310
 311 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 312 {
 313         struct drm_device *dev = pci_get_drvdata(pdev);
 314         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 315
 316         if (state == VGA_SWITCHEROO_ON) {
 317                 pr_info("switched on\n");
 318                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 319                 /* i915 resume handler doesn't set to D0 */
 320                 pci_set_power_state(dev->pdev, PCI_D0);
 321                 i915_resume_switcheroo(dev);
 322                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 323         } else {
 324                 pr_err("switched off\n");
 325                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 326                 i915_suspend_switcheroo(dev, pmm);
 327                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 328         }
 329 }
 330
 331 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 332 {
 333         struct drm_device *dev = pci_get_drvdata(pdev);
 334
 335         /*
 336          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 337          * locking inversion with the driver load path. And the access here is
 338          * completely racy anyway. So don't bother with locking for now.
 339          */
 340         return dev->open_count == 0;
 341 }
 342
 343 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 344         .set_gpu_state = i915_switcheroo_set_state,
 345         .reprobe = NULL,
 346         .can_switch = i915_switcheroo_can_switch,
 347 };
 348 #endif
 349
 350 static int i915_load_modeset_init(struct drm_device *dev)
 351 {
 352         struct drm_i915_private *dev_priv = dev->dev_private;
 353         int ret;
 354
 355         ret = intel_parse_bios(dev);
 356         if (ret)
 357                 DRM_INFO("failed to find VBIOS tables\n");
 358
 359 #if 0
 360         /* If we have > 1 VGA cards, then we need to arbitrate access
 361          * to the common VGA resources.
 362          *
 363          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 364          * then we do not take part in VGA arbitration and the
 365          * vga_client_register() fails with -ENODEV.
 366          */
 367         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 368         if (ret && ret != -ENODEV)
 369                 goto out;
 370
 371         intel_register_dsm_handler();
 372
 373         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 374         if (ret)
 375                 goto cleanup_vga_client;
 376
 377         /* Initialise stolen first so that we may reserve preallocated
 378          * objects for the BIOS to KMS transition.
 379          */
 380         ret = i915_gem_init_stolen(dev);
 381         if (ret)
 382                 goto cleanup_vga_switcheroo;
 383 #endif
 384
 385         intel_power_domains_init_hw(dev_priv);
 386
 387         ret = intel_irq_install(dev_priv);
 388         if (ret)
 389                 goto cleanup_gem_stolen;
 390
 391         /* Important: The output setup functions called by modeset_init need
 392          * working irqs for e.g. gmbus and dp aux transfers. */
 393         intel_modeset_init(dev);
 394
 395         intel_guc_ucode_init(dev);
 396
 397         ret = i915_gem_init(dev);
 398         if (ret)
 399                 goto cleanup_irq;
 400
 401         intel_modeset_gem_init(dev);
 402
 403         /* Always safe in the mode setting case. */
 404         /* FIXME: do pre/post-mode set stuff in core KMS code */
 405         dev->vblank_disable_allowed = 1;
 406         if (INTEL_INFO(dev)->num_pipes == 0)
 407                 return 0;
 408
 409         ret = intel_fbdev_init(dev);
 410         if (ret)
 411                 goto cleanup_gem;
 412
 413         /* Only enable hotplug handling once the fbdev is fully set up. */
 414         intel_hpd_init(dev_priv);
 415
 416         /*
 417          * Some ports require correctly set-up hpd registers for detection to
 418          * work properly (leading to ghost connected connector status), e.g. VGA
 419          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 420          * irqs are fully enabled. Now we should scan for the initial config
 421          * only once hotplug handling is enabled, but due to screwed-up locking
 422          * around kms/fbdev init we can't protect the fdbev initial config
 423          * scanning against hotplug events. Hence do this first and ignore the
 424          * tiny window where we will loose hotplug notifactions.
 425          */
 426         async_schedule(intel_fbdev_initial_config, dev_priv);
 427
 428         drm_kms_helper_poll_init(dev);
 429
 430         return 0;
 431
 432 cleanup_gem:
 433         mutex_lock(&dev->struct_mutex);
 434         i915_gem_cleanup_ringbuffer(dev);
 435         i915_gem_context_fini(dev);
 436         mutex_unlock(&dev->struct_mutex);
 437 cleanup_irq:
 438         intel_guc_ucode_fini(dev);
 439         drm_irq_uninstall(dev);
 440 cleanup_gem_stolen:
 441         i915_gem_cleanup_stolen(dev);
 442 #if 0
 443 cleanup_vga_switcheroo:
 444         vga_switcheroo_unregister_client(dev->pdev);
 445 cleanup_vga_client:
 446         vga_client_register(dev->pdev, NULL, NULL, NULL);
 447 out:
 448 #endif
 449         return ret;
 450 }
 451
 452 #if IS_ENABLED(CONFIG_FB)
 453 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 454 {
 455         struct apertures_struct *ap;
 456         struct pci_dev *pdev = dev_priv->dev->pdev;
 457         bool primary;
 458         int ret;
 459
 460         ap = alloc_apertures(1);
 461         if (!ap)
 462                 return -ENOMEM;
 463
 464         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 465         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 466
 467         primary =
 468                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 469
 470         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 471
 472         kfree(ap);
 473
 474         return ret;
 475 }
 476 #else
 477 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 478 {
 479         return 0;
 480 }
 481 #endif
 482
 483 #if !defined(CONFIG_VGA_CONSOLE)
 484 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 485 {
 486         return 0;
 487 }
 488 #elif !defined(CONFIG_DUMMY_CONSOLE)
 489 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 490 {
 491         return -ENODEV;
 492 }
 493 #else
 494 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 495 {
 496         int ret = 0;
 497
 498         DRM_INFO("Replacing VGA console driver\n");
 499
 500         console_lock();
 501         if (con_is_bound(&vga_con))
 502                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 503         if (ret == 0) {
 504                 ret = do_unregister_con_driver(&vga_con);
 505
 506                 /* Ignore "already unregistered". */
 507                 if (ret == -ENODEV)
 508                         ret = 0;
 509         }
 510         console_unlock();
 511
 512         return ret;
 513 }
 514 #endif
 515
 516 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 517 {
 518 #if 0
 519         const struct intel_device_info *info = &dev_priv->info;
 520
 521 #define PRINT_S(name) "%s"
 522 #define SEP_EMPTY
 523 #define PRINT_FLAG(name) info->name ? #name "," : ""
 524 #define SEP_COMMA ,
 525         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 526                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 527                          info->gen,
 528                          dev_priv->dev->pdev->device,
 529                          dev_priv->dev->pdev->revision,
 530                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 531 #undef PRINT_S
 532 #undef SEP_EMPTY
 533 #undef PRINT_FLAG
 534 #undef SEP_COMMA
 535 #endif
 536 }
 537
 538 static void cherryview_sseu_info_init(struct drm_device *dev)
 539 {
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_device_info *info;
 542         u32 fuse, eu_dis;
 543
 544         info = (struct intel_device_info *)&dev_priv->info;
 545         fuse = I915_READ(CHV_FUSE_GT);
 546
 547         info->slice_total = 1;
 548
 549         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 550                 info->subslice_per_slice++;
 551                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 552                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 553                 info->eu_total += 8 - hweight32(eu_dis);
 554         }
 555
 556         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 557                 info->subslice_per_slice++;
 558                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 559                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 560                 info->eu_total += 8 - hweight32(eu_dis);
 561         }
 562
 563         info->subslice_total = info->subslice_per_slice;
 564         /*
 565          * CHV expected to always have a uniform distribution of EU
 566          * across subslices.
 567         */
 568         info->eu_per_subslice = info->subslice_total ?
 569                                 info->eu_total / info->subslice_total :
 570                                 0;
 571         /*
 572          * CHV supports subslice power gating on devices with more than
 573          * one subslice, and supports EU power gating on devices with
 574          * more than one EU pair per subslice.
 575         */
 576         info->has_slice_pg = 0;
 577         info->has_subslice_pg = (info->subslice_total > 1);
 578         info->has_eu_pg = (info->eu_per_subslice > 2);
 579 }
 580
 581 static void gen9_sseu_info_init(struct drm_device *dev)
 582 {
 583         struct drm_i915_private *dev_priv = dev->dev_private;
 584         struct intel_device_info *info;
 585         int s_max = 3, ss_max = 4, eu_max = 8;
 586         int s, ss;
 587         u32 fuse2, s_enable, ss_disable, eu_disable;
 588         u8 eu_mask = 0xff;
 589
 590         info = (struct intel_device_info *)&dev_priv->info;
 591         fuse2 = I915_READ(GEN8_FUSE2);
 592         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 593                    GEN8_F2_S_ENA_SHIFT;
 594         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 595                      GEN9_F2_SS_DIS_SHIFT;
 596
 597         info->slice_total = hweight32(s_enable);
 598         /*
 599          * The subslice disable field is global, i.e. it applies
 600          * to each of the enabled slices.
 601         */
 602         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 603         info->subslice_total = info->slice_total *
 604                                info->subslice_per_slice;
 605
 606         /*
 607          * Iterate through enabled slices and subslices to
 608          * count the total enabled EU.
 609         */
 610         for (s = 0; s < s_max; s++) {
 611                 if (!(s_enable & (0x1 << s)))
 612                         /* skip disabled slice */
 613                         continue;
 614
 615                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 616                 for (ss = 0; ss < ss_max; ss++) {
 617                         int eu_per_ss;
 618
 619                         if (ss_disable & (0x1 << ss))
 620                                 /* skip disabled subslice */
 621                                 continue;
 622
 623                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 624                                                       eu_mask);
 625
 626                         /*
 627                          * Record which subslice(s) has(have) 7 EUs. we
 628                          * can tune the hash used to spread work among
 629                          * subslices if they are unbalanced.
 630                          */
 631                         if (eu_per_ss == 7)
 632                                 info->subslice_7eu[s] |= 1 << ss;
 633
 634                         info->eu_total += eu_per_ss;
 635                 }
 636         }
 637
 638         /*
 639          * SKL is expected to always have a uniform distribution
 640          * of EU across subslices with the exception that any one
 641          * EU in any one subslice may be fused off for die
 642          * recovery. BXT is expected to be perfectly uniform in EU
 643          * distribution.
 644         */
 645         info->eu_per_subslice = info->subslice_total ?
 646                                 DIV_ROUND_UP(info->eu_total,
 647                                              info->subslice_total) : 0;
 648         /*
 649          * SKL supports slice power gating on devices with more than
 650          * one slice, and supports EU power gating on devices with
 651          * more than one EU pair per subslice. BXT supports subslice
 652          * power gating on devices with more than one subslice, and
 653          * supports EU power gating on devices with more than one EU
 654          * pair per subslice.
 655         */
 656         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 657         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 658         info->has_eu_pg = (info->eu_per_subslice > 2);
 659 }
 660
 661 static void broadwell_sseu_info_init(struct drm_device *dev)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         struct intel_device_info *info;
 665         const int s_max = 3, ss_max = 3, eu_max = 8;
 666         int s, ss;
 667         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 668
 669         fuse2 = I915_READ(GEN8_FUSE2);
 670         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 671         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 672
 673         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 674         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 675                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 676                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 677         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 678                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 679                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 680
 681
 682         info = (struct intel_device_info *)&dev_priv->info;
 683         info->slice_total = hweight32(s_enable);
 684
 685         /*
 686          * The subslice disable field is global, i.e. it applies
 687          * to each of the enabled slices.
 688          */
 689         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 690         info->subslice_total = info->slice_total * info->subslice_per_slice;
 691
 692         /*
 693          * Iterate through enabled slices and subslices to
 694          * count the total enabled EU.
 695          */
 696         for (s = 0; s < s_max; s++) {
 697                 if (!(s_enable & (0x1 << s)))
 698                         /* skip disabled slice */
 699                         continue;
 700
 701                 for (ss = 0; ss < ss_max; ss++) {
 702                         u32 n_disabled;
 703
 704                         if (ss_disable & (0x1 << ss))
 705                                 /* skip disabled subslice */
 706                                 continue;
 707
 708                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 709
 710                         /*
 711                          * Record which subslices have 7 EUs.
 712                          */
 713                         if (eu_max - n_disabled == 7)
 714                                 info->subslice_7eu[s] |= 1 << ss;
 715
 716                         info->eu_total += eu_max - n_disabled;
 717                 }
 718         }
 719
 720         /*
 721          * BDW is expected to always have a uniform distribution of EU across
 722          * subslices with the exception that any one EU in any one subslice may
 723          * be fused off for die recovery.
 724          */
 725         info->eu_per_subslice = info->subslice_total ?
 726                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 727
 728         /*
 729          * BDW supports slice power gating on devices with more than
 730          * one slice.
 731          */
 732         info->has_slice_pg = (info->slice_total > 1);
 733         info->has_subslice_pg = 0;
 734         info->has_eu_pg = 0;
 735 }
 736
 737 /*
 738  * Determine various intel_device_info fields at runtime.
 739  *
 740  * Use it when either:
 741  *   - it's judged too laborious to fill n static structures with the limit
 742  *     when a simple if statement does the job,
 743  *   - run-time checks (eg read fuse/strap registers) are needed.
 744  *
 745  * This function needs to be called:
 746  *   - after the MMIO has been setup as we are reading registers,
 747  *   - after the PCH has been detected,
 748  *   - before the first usage of the fields it can tweak.
 749  */
 750 static void intel_device_info_runtime_init(struct drm_device *dev)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         struct intel_device_info *info;
 754         enum i915_pipe pipe;
 755
 756         info = (struct intel_device_info *)&dev_priv->info;
 757
 758         /*
 759          * Skylake and Broxton currently don't expose the topmost plane as its
 760          * use is exclusive with the legacy cursor and we only want to expose
 761          * one of those, not both. Until we can safely expose the topmost plane
 762          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 763          * we don't expose the topmost plane at all to prevent ABI breakage
 764          * down the line.
 765          */
 766         if (IS_BROXTON(dev)) {
 767                 info->num_sprites[PIPE_A] = 2;
 768                 info->num_sprites[PIPE_B] = 2;
 769                 info->num_sprites[PIPE_C] = 1;
 770         } else if (IS_VALLEYVIEW(dev))
 771                 for_each_pipe(dev_priv, pipe)
 772                         info->num_sprites[pipe] = 2;
 773         else
 774                 for_each_pipe(dev_priv, pipe)
 775                         info->num_sprites[pipe] = 1;
 776
 777         if (i915.disable_display) {
 778                 DRM_INFO("Display disabled (module parameter)\n");
 779                 info->num_pipes = 0;
 780         } else if (info->num_pipes > 0 &&
 781                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 782                    !IS_VALLEYVIEW(dev)) {
 783                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 784                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 785
 786                 /*
 787                  * SFUSE_STRAP is supposed to have a bit signalling the display
 788                  * is fused off. Unfortunately it seems that, at least in
 789                  * certain cases, fused off display means that PCH display
 790                  * reads don't land anywhere. In that case, we read 0s.
 791                  *
 792                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 793                  * should be set when taking over after the firmware.
 794                  */
 795                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 796                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 797                     (dev_priv->pch_type == PCH_CPT &&
 798                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 799                         DRM_INFO("Display fused off, disabling\n");
 800                         info->num_pipes = 0;
 801                 }
 802         }
 803
 804         /* Initialize slice/subslice/EU info */
 805         if (IS_CHERRYVIEW(dev))
 806                 cherryview_sseu_info_init(dev);
 807         else if (IS_BROADWELL(dev))
 808                 broadwell_sseu_info_init(dev);
 809         else if (INTEL_INFO(dev)->gen >= 9)
 810                 gen9_sseu_info_init(dev);
 811
 812         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 813         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 814         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 815         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 816         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 817         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 818                          info->has_slice_pg ? "y" : "n");
 819         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 820                          info->has_subslice_pg ? "y" : "n");
 821         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 822                          info->has_eu_pg ? "y" : "n");
 823 }
 824
 825 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 826 {
 827         if (!IS_VALLEYVIEW(dev_priv))
 828                 return;
 829
 830         /*
 831          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 832          * CHV x1 PHY (DP/HDMI D)
 833          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 834          */
 835         if (IS_CHERRYVIEW(dev_priv)) {
 836                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 837                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 838         } else {
 839                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 840         }
 841 }
 842
 843 /**
 844  * i915_driver_load - setup chip and create an initial config
 845  * @dev: DRM device
 846  * @flags: startup flags
 847  *
 848  * The driver load routine has to do several things:
 849  *   - drive output discovery via intel_modeset_init()
 850  *   - initialize the memory manager
 851  *   - allocate initial config memory
 852  *   - setup the DRM framebuffer with the allocated memory
 853  */
 854 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 855 {
 856         struct drm_i915_private *dev_priv;
 857         struct intel_device_info *info, *device_info;
 858         int ret = 0, mmio_bar, mmio_size;
 859         uint32_t aperture_size;
 860
 861         /* XXX: struct pci_dev */
 862         info = i915_get_device_id(dev->pdev->device);
 863
 864         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 865         if (dev_priv == NULL)
 866                 return -ENOMEM;
 867
 868         dev->dev_private = dev_priv;
 869         dev_priv->dev = dev;
 870
 871         /* Setup the write-once "constant" device info */
 872         device_info = (struct intel_device_info *)&dev_priv->info;
 873         memcpy(device_info, info, sizeof(dev_priv->info));
 874         device_info->device_id = dev->pdev->device;
 875
 876         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
 877         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
 878         lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
 879         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
 880         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
 881         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
 882         lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
 883         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
 884         lockinit(&dev_priv->csr_lock, "i915csr", 0, LK_CANRECURSE);
 885         lockinit(&dev_priv->av_mutex, "i915am", 0, LK_CANRECURSE);
 886
 887         intel_pm_setup(dev);
 888
 889         intel_display_crc_init(dev);
 890
 891         i915_dump_device_info(dev_priv);
 892
 893         /* Not all pre-production machines fall into this category, only the
 894          * very first ones. Almost everything should work, except for maybe
 895          * suspend/resume. And we don't implement workarounds that affect only
 896          * pre-production machines. */
 897         if (IS_HSW_EARLY_SDV(dev))
 898                 DRM_INFO("This is an early pre-production Haswell machine. "
 899                          "It may not be fully functional.\n");
 900
 901         if (i915_get_bridge_dev(dev)) {
 902                 ret = -EIO;
 903                 goto free_priv;
 904         }
 905
 906         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 907         /* Before gen4, the registers and the GTT are behind different BARs.
 908          * However, from gen4 onwards, the registers and the GTT are shared
 909          * in the same BAR, so we want to restrict this ioremap from
 910          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 911          * the register BAR remains the same size for all the earlier
 912          * generations up to Ironlake.
 913          */
 914         if (info->gen < 5)
 915                 mmio_size = 512*1024;
 916         else
 917                 mmio_size = 2*1024*1024;
 918
 919         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 920         if (!dev_priv->regs) {
 921                 DRM_ERROR("failed to map registers\n");
 922                 ret = -EIO;
 923                 goto put_bridge;
 924         }
 925
 926         /* This must be called before any calls to HAS_PCH_* */
 927         intel_detect_pch(dev);
 928
 929         intel_uncore_init(dev);
 930
 931         /* Load CSR Firmware for SKL */
 932         intel_csr_ucode_init(dev);
 933
 934         ret = i915_gem_gtt_init(dev);
 935         if (ret)
 936                 goto out_freecsr;
 937
 938         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 939          * otherwise the vga fbdev driver falls over. */
 940         ret = i915_kick_out_firmware_fb(dev_priv);
 941         if (ret) {
 942                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 943                 goto out_gtt;
 944         }
 945
 946         ret = i915_kick_out_vgacon(dev_priv);
 947         if (ret) {
 948                 DRM_ERROR("failed to remove conflicting VGA console\n");
 949                 goto out_gtt;
 950         }
 951
 952 #if 0
 953         pci_set_master(dev->pdev);
 954
 955         /* overlay on gen2 is broken and can't address above 1G */
 956         if (IS_GEN2(dev))
 957                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 958
 959         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 960          * using 32bit addressing, overwriting memory if HWS is located
 961          * above 4GB.
 962          *
 963          * The documentation also mentions an issue with undefined
 964          * behaviour if any general state is accessed within a page above 4GB,
 965          * which also needs to be handled carefully.
 966          */
 967         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 968                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 969 #endif
 970
 971         aperture_size = dev_priv->gtt.mappable_end;
 972
 973         dev_priv->gtt.mappable =
 974                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 975                                      aperture_size);
 976         if (dev_priv->gtt.mappable == NULL) {
 977                 ret = -EIO;
 978                 goto out_gtt;
 979         }
 980
 981         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 982                                               aperture_size);
 983
 984         /* The i915 workqueue is primarily used for batched retirement of
 985          * requests (and thus managing bo) once the task has been completed
 986          * by the GPU. i915_gem_retire_requests() is called directly when we
 987          * need high-priority retirement, such as waiting for an explicit
 988          * bo.
 989          *
 990          * It is also used for periodic low-priority events, such as
 991          * idle-timers and recording error state.
 992          *
 993          * All tasks on the workqueue are expected to acquire the dev mutex
 994          * so there is no point in running more than one instance of the
 995          * workqueue at any time.  Use an ordered one.
 996          */
 997         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 998         if (dev_priv->wq == NULL) {
 999                 DRM_ERROR("Failed to create our workqueue.\n");
1000                 ret = -ENOMEM;
1001                 goto out_mtrrfree;
1002         }
1003
1004         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1005         if (dev_priv->hotplug.dp_wq == NULL) {
1006                 DRM_ERROR("Failed to create our dp workqueue.\n");
1007                 ret = -ENOMEM;
1008                 goto out_freewq;
1009         }
1010
1011         dev_priv->gpu_error.hangcheck_wq =
1012                 alloc_ordered_workqueue("i915-hangcheck", 0);
1013         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
1014                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
1015                 ret = -ENOMEM;
1016                 goto out_freedpwq;
1017         }
1018
1019         intel_irq_init(dev_priv);
1020         intel_uncore_sanitize(dev);
1021
1022         /* Try to make sure MCHBAR is enabled before poking at it */
1023         intel_setup_mchbar(dev);
1024         intel_setup_gmbus(dev);
1025         intel_opregion_setup(dev);
1026
1027         i915_gem_load(dev);
1028
1029         /* On the 945G/GM, the chipset reports the MSI capability on the
1030          * integrated graphics even though the support isn't actually there
1031          * according to the published specs.  It doesn't appear to function
1032          * correctly in testing on 945G.
1033          * This may be a side effect of MSI having been made available for PEG
1034          * and the registers being closely associated.
1035          *
1036          * According to chipset errata, on the 965GM, MSI interrupts may
1037          * be lost or delayed, but we use them anyways to avoid
1038          * stuck interrupts on some machines.
1039          */
1040 #if 0
1041         if (!IS_I945G(dev) && !IS_I945GM(dev))
1042                 pci_enable_msi(dev->pdev);
1043 #endif
1044
1045         intel_device_info_runtime_init(dev);
1046
1047         intel_init_dpio(dev_priv);
1048
1049         if (INTEL_INFO(dev)->num_pipes) {
1050                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1051                 if (ret)
1052                         goto out_gem_unload;
1053         }
1054
1055         intel_power_domains_init(dev_priv);
1056
1057         ret = i915_load_modeset_init(dev);
1058         if (ret < 0) {
1059                 DRM_ERROR("failed to init modeset\n");
1060                 goto out_power_well;
1061         }
1062
1063         /*
1064          * Notify a valid surface after modesetting,
1065          * when running inside a VM.
1066          */
1067         if (intel_vgpu_active(dev))
1068                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1069
1070         i915_setup_sysfs(dev);
1071
1072         if (INTEL_INFO(dev)->num_pipes) {
1073                 /* Must be done after probing outputs */
1074                 intel_opregion_init(dev);
1075 #if 0
1076                 acpi_video_register();
1077 #endif
1078         }
1079
1080         if (IS_GEN5(dev))
1081                 intel_gpu_ips_init(dev_priv);
1082
1083         intel_runtime_pm_enable(dev_priv);
1084
1085         i915_audio_component_init(dev_priv);
1086
1087         return 0;
1088
1089 out_power_well:
1090         intel_power_domains_fini(dev_priv);
1091         drm_vblank_cleanup(dev);
1092 out_gem_unload:
1093
1094         intel_teardown_gmbus(dev);
1095         intel_teardown_mchbar(dev);
1096         pm_qos_remove_request(&dev_priv->pm_qos);
1097         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1098 out_freedpwq:
1099         destroy_workqueue(dev_priv->hotplug.dp_wq);
1100 out_freewq:
1101         destroy_workqueue(dev_priv->wq);
1102 out_mtrrfree:
1103         arch_phys_wc_del(dev_priv->gtt.mtrr);
1104 #if 0
1105         io_mapping_free(dev_priv->gtt.mappable);
1106 #endif
1107 out_gtt:
1108         i915_global_gtt_cleanup(dev);
1109 out_freecsr:
1110         intel_csr_ucode_fini(dev);
1111         intel_uncore_fini(dev);
1112 #if 0
1113         pci_iounmap(dev->pdev, dev_priv->regs);
1114 #endif
1115 put_bridge:
1116         pci_dev_put(dev_priv->bridge_dev);
1117 free_priv:
1118         kfree(dev_priv);
1119         return ret;
1120 }
1121
1122 int i915_driver_unload(struct drm_device *dev)
1123 {
1124         struct drm_i915_private *dev_priv = dev->dev_private;
1125         int ret;
1126
1127         i915_audio_component_cleanup(dev_priv);
1128
1129         ret = i915_gem_suspend(dev);
1130         if (ret) {
1131                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1132                 return ret;
1133         }
1134
1135         intel_power_domains_fini(dev_priv);
1136
1137         intel_gpu_ips_teardown();
1138
1139         i915_teardown_sysfs(dev);
1140
1141 #if 0
1142         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1143         unregister_shrinker(&dev_priv->mm.shrinker);
1144
1145         io_mapping_free(dev_priv->gtt.mappable);
1146 #endif
1147         arch_phys_wc_del(dev_priv->gtt.mtrr);
1148
1149 #if 0
1150         acpi_video_unregister();
1151 #endif
1152
1153         intel_fbdev_fini(dev);
1154
1155         drm_vblank_cleanup(dev);
1156
1157         intel_modeset_cleanup(dev);
1158
1159         /*
1160          * free the memory space allocated for the child device
1161          * config parsed from VBT
1162          */
1163         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1164                 kfree(dev_priv->vbt.child_dev);
1165                 dev_priv->vbt.child_dev = NULL;
1166                 dev_priv->vbt.child_dev_num = 0;
1167         }
1168         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1169         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1170         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1171         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1172
1173 #if 0
1174         vga_switcheroo_unregister_client(dev->pdev);
1175         vga_client_register(dev->pdev, NULL, NULL, NULL);
1176 #endif
1177
1178         /* Free error state after interrupts are fully disabled. */
1179         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1180 #if 0
1181         i915_destroy_error_state(dev);
1182
1183         if (dev->pdev->msi_enabled)
1184                 pci_disable_msi(dev->pdev);
1185 #endif
1186
1187         intel_opregion_fini(dev);
1188
1189         /* Flush any outstanding unpin_work. */
1190         flush_workqueue(dev_priv->wq);
1191
1192         intel_guc_ucode_fini(dev);
1193         mutex_lock(&dev->struct_mutex);
1194         i915_gem_cleanup_ringbuffer(dev);
1195         i915_gem_context_fini(dev);
1196         mutex_unlock(&dev->struct_mutex);
1197         intel_fbc_cleanup_cfb(dev_priv);
1198         i915_gem_cleanup_stolen(dev);
1199
1200         intel_csr_ucode_fini(dev);
1201
1202         intel_teardown_gmbus(dev);
1203         intel_teardown_mchbar(dev);
1204
1205         destroy_workqueue(dev_priv->hotplug.dp_wq);
1206         destroy_workqueue(dev_priv->wq);
1207         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1208         pm_qos_remove_request(&dev_priv->pm_qos);
1209
1210         i915_global_gtt_cleanup(dev);
1211
1212         intel_uncore_fini(dev);
1213 #if 0
1214         if (dev_priv->regs != NULL)
1215                 pci_iounmap(dev->pdev, dev_priv->regs);
1216 #endif
1217
1218         pci_dev_put(dev_priv->bridge_dev);
1219         kfree(dev_priv);
1220
1221         return 0;
1222 }
1223
1224 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1225 {
1226         int ret;
1227
1228         ret = i915_gem_open(dev, file);
1229         if (ret)
1230                 return ret;
1231
1232         return 0;
1233 }
1234
1235 /**
1236  * i915_driver_lastclose - clean up after all DRM clients have exited
1237  * @dev: DRM device
1238  *
1239  * Take care of cleaning up after all DRM clients have exited.  In the
1240  * mode setting case, we want to restore the kernel's initial mode (just
1241  * in case the last client left us in a bad state).
1242  *
1243  * Additionally, in the non-mode setting case, we'll tear down the GTT
1244  * and DMA structures, since the kernel won't be using them, and clea
1245  * up any GEM state.
1246  */
1247 void i915_driver_lastclose(struct drm_device *dev)
1248 {
1249         intel_fbdev_restore_mode(dev);
1250 #if 0
1251         vga_switcheroo_process_delayed_switch();
1252 #endif
1253 }
1254
1255 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1256 {
1257         mutex_lock(&dev->struct_mutex);
1258         i915_gem_context_close(dev, file);
1259         i915_gem_release(dev, file);
1260         mutex_unlock(&dev->struct_mutex);
1261
1262         intel_modeset_preclose(dev, file);
1263 }
1264
1265 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1266 {
1267         struct drm_i915_file_private *file_priv = file->driver_priv;
1268
1269         if (file_priv && file_priv->bsd_ring)
1270                 file_priv->bsd_ring = NULL;
1271         kfree(file_priv);
1272 }
1273
1274 static int
1275 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1276                           struct drm_file *file)
1277 {
1278         return -ENODEV;
1279 }
1280
1281 const struct drm_ioctl_desc i915_ioctls[] = {
1282         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1283         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1284         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1285         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1286         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1287         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1288         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW|DRM_UNLOCKED),
1289         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1290         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1291         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1292         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1293         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1294         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1295         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1296         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1297         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1298         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1299         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1300         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1301         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1302         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1303         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1304         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1305         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1306         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1307         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1308         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1309         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1310         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1311         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1312         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1313         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1314         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1315         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1316         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1317         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1318         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1319         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1320         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1321         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1322         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1323         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1324         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1325         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1326         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1327         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1328         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1329         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1330         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1331 #if 0
1332         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1333 #endif
1334         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1335         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1336 };
1337
1338 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);