2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
164 * this code MUST be enabled here and in mpboot.s.
165 * it follows the very early stages of AP boot by placing values in CMOS ram.
166 * it NORMALLY will never be needed and thus the primitive method for enabling.
169 #if defined(CHECK_POINTS)
170 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
171 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
173 #define CHECK_INIT(D); \
174 CHECK_WRITE(0x34, (D)); \
175 CHECK_WRITE(0x35, (D)); \
176 CHECK_WRITE(0x36, (D)); \
177 CHECK_WRITE(0x37, (D)); \
178 CHECK_WRITE(0x38, (D)); \
179 CHECK_WRITE(0x39, (D));
181 #define CHECK_PRINT(S); \
182 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
191 #else /* CHECK_POINTS */
193 #define CHECK_INIT(D)
194 #define CHECK_PRINT(S)
196 #endif /* CHECK_POINTS */
199 * Values to send to the POST hardware.
201 #define MP_BOOTADDRESS_POST 0x10
202 #define MP_PROBE_POST 0x11
203 #define MPTABLE_PASS1_POST 0x12
205 #define MP_START_POST 0x13
206 #define MP_ENABLE_POST 0x14
207 #define MPTABLE_PASS2_POST 0x15
209 #define START_ALL_APS_POST 0x16
210 #define INSTALL_AP_TRAMP_POST 0x17
211 #define START_AP_POST 0x18
213 #define MP_ANNOUNCE_POST 0x19
215 static int need_hyperthreading_fixup;
216 static u_int logical_cpus;
217 u_int logical_cpus_mask;
219 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
220 int current_postcode;
222 /** XXX FIXME: what system files declare these??? */
223 extern struct region_descriptor r_gdt, r_idt;
225 int bsp_apic_ready = 0; /* flags useability of BSP apic */
226 int mp_naps; /* # of Applications processors */
227 int mp_nbusses; /* # of busses */
229 int mp_napics; /* # of IO APICs */
231 int boot_cpu_id; /* designated BSP */
232 vm_offset_t cpu_apic_address;
234 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
235 u_int32_t *io_apic_versions;
239 u_int32_t cpu_apic_versions[MAXCPU];
241 extern int64_t tsc_offsets[];
244 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
248 * APIC ID logical/physical mapping structures.
249 * We oversize these to simplify boot-time config.
251 int cpu_num_to_apic_id[NAPICID];
253 int io_num_to_apic_id[NAPICID];
255 int apic_id_to_logical[NAPICID];
257 /* AP uses this during bootstrap. Do not staticize. */
262 * SMP page table page. Setup by locore to point to a page table
263 * page from which we allocate per-cpu privatespace areas io_apics,
267 #define IO_MAPPING_START_INDEX \
268 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
270 extern pt_entry_t *SMPpt;
272 struct pcb stoppcbs[MAXCPU];
274 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
277 * Local data and functions.
280 static int mp_capable;
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static mpfps_t mpfps;
286 static long search_for_sig(u_int32_t target, int count);
287 static void mp_enable(u_int boot_addr);
289 static void mptable_hyperthread_fixup(u_int id_mask);
290 static void mptable_pass1(void);
291 static int mptable_pass2(void);
292 static void default_mp_table(int type);
293 static void fix_mp_table(void);
295 static void setup_apic_irq_mapping(void);
296 static int apic_int_is_bus_type(int intr, int bus_type);
298 static int start_all_aps(u_int boot_addr);
300 static void install_ap_tramp(u_int boot_addr);
302 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
303 static int smitest(void);
305 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
306 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
307 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
308 static u_int bootMP_size;
311 * Calculate usable address in base memory for AP trampoline code.
314 mp_bootaddress(u_int basemem)
316 POSTCODE(MP_BOOTADDRESS_POST);
318 base_memory = basemem;
320 bootMP_size = mptramp_end - mptramp_start;
321 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
322 if (((basemem * 1024) - boot_address) < bootMP_size)
323 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
324 /* 3 levels of page table pages */
325 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
327 return mptramp_pagetables;
332 * Look for an Intel MP spec table (ie, SMP capable hardware).
342 * Make sure our SMPpt[] page table is big enough to hold all the
345 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
347 POSTCODE(MP_PROBE_POST);
349 /* see if EBDA exists */
350 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
351 /* search first 1K of EBDA */
352 target = (u_int32_t) (segment << 4);
353 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
356 /* last 1K of base memory, effective 'top of base' passed in */
357 target = (u_int32_t) (base_memory - 0x400);
358 if ((x = search_for_sig(target, 1024 / 4)) != -1L)
362 /* search the BIOS */
363 target = (u_int32_t) BIOS_BASE;
364 if ((x = search_for_sig(target, BIOS_COUNT)) != -1L)
374 * Calculate needed resources. We can safely map physical
375 * memory into SMPpt after mptable_pass1() completes.
380 /* flag fact that we are running multiple processors */
387 * Startup the SMP processors.
392 POSTCODE(MP_START_POST);
394 /* look for MP capable motherboard */
396 mp_enable(boot_address);
398 panic("MP hardware not found!");
403 * Print various information about the SMP system hardware and setup.
410 POSTCODE(MP_ANNOUNCE_POST);
412 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
413 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
414 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
415 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
416 for (x = 1; x <= mp_naps; ++x) {
417 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
418 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
419 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
423 for (x = 0; x < mp_napics; ++x) {
424 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
425 kprintf(", version: 0x%08x", io_apic_versions[x]);
426 kprintf(", at 0x%08lx\n", io_apic_address[x]);
429 kprintf(" Warning: APIC I/O disabled\n");
434 * AP cpu's call this to sync up protected mode.
436 * WARNING! %gs is not set up on entry. This routine sets up %gs.
442 int x, myid = bootAP;
444 struct mdglobaldata *md;
445 struct privatespace *ps;
447 ps = &CPU_prvspace[myid];
449 gdt_segs[GPROC0_SEL].ssd_base =
450 (long) &ps->mdglobaldata.gd_common_tss;
451 ps->mdglobaldata.mi.gd_prvspace = ps;
453 /* We fill the 32-bit segment descriptors */
454 for (x = 0; x < NGDT; x++) {
455 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
456 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
458 /* And now a 64-bit one */
459 ssdtosyssd(&gdt_segs[GPROC0_SEL],
460 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
462 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
463 r_gdt.rd_base = (long) &gdt[myid * NGDT];
464 lgdt(&r_gdt); /* does magic intra-segment return */
466 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
467 wrmsr(MSR_FSBASE, 0); /* User value */
468 wrmsr(MSR_GSBASE, (u_int64_t)ps);
469 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
475 mdcpu->gd_currentldt = _default_ldt;
478 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
479 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
481 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
483 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
485 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
487 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
488 md->gd_common_tssd = *md->gd_tss_gdt;
490 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
495 * Set to a known state:
496 * Set by mpboot.s: CR0_PG, CR0_PE
497 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
500 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
503 /* Set up the fast syscall stuff */
504 msr = rdmsr(MSR_EFER) | EFER_SCE;
505 wrmsr(MSR_EFER, msr);
506 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
507 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
508 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
509 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
510 wrmsr(MSR_STAR, msr);
511 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
513 pmap_set_opt(); /* PSE/4MB pages, etc */
515 /* Initialize the PAT MSR. */
519 /* set up CPU registers and state */
522 /* set up SSE/NX registers */
525 /* set up FPU state on the AP */
526 npxinit(__INITIAL_NPXCW__);
528 /* disable the APIC, just to be SURE */
529 lapic->svr &= ~APIC_SVR_ENABLE;
531 /* data returned to BSP */
532 cpu_apic_versions[0] = lapic->version;
535 /*******************************************************************
536 * local functions and data
540 * start the SMP system
543 mp_enable(u_int boot_addr)
551 POSTCODE(MP_ENABLE_POST);
553 if (cpu_apic_address == 0)
554 panic("pmap_bootstrap: no local apic!");
557 /* turn on 4MB of V == P addressing so we can get to MP table */
558 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
562 /* examine the MP table for needed info, uses physical addresses */
570 /* can't process default configs till the CPU APIC is pmapped */
574 /* post scan cleanup */
579 setup_apic_irq_mapping();
581 /* fill the LOGICAL io_apic_versions table */
582 for (apic = 0; apic < mp_napics; ++apic) {
583 ux = io_apic_read(apic, IOAPIC_VER);
584 io_apic_versions[apic] = ux;
585 io_apic_set_id(apic, IO_TO_ID(apic));
588 /* program each IO APIC in the system */
589 for (apic = 0; apic < mp_napics; ++apic)
590 if (io_apic_setup(apic) < 0)
591 panic("IO APIC setup failure");
596 * These are required for SMP operation
599 /* install a 'Spurious INTerrupt' vector */
600 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
601 SDT_SYSIGT, SEL_KPL, 0);
603 /* install an inter-CPU IPI for TLB invalidation */
604 setidt(XINVLTLB_OFFSET, Xinvltlb,
605 SDT_SYSIGT, SEL_KPL, 0);
607 /* install an inter-CPU IPI for IPIQ messaging */
608 setidt(XIPIQ_OFFSET, Xipiq,
609 SDT_SYSIGT, SEL_KPL, 0);
611 /* install a timer vector */
612 setidt(XTIMER_OFFSET, Xtimer,
613 SDT_SYSIGT, SEL_KPL, 0);
615 /* install an inter-CPU IPI for CPU stop/restart */
616 setidt(XCPUSTOP_OFFSET, Xcpustop,
617 SDT_SYSIGT, SEL_KPL, 0);
619 /* start each Application Processor */
620 start_all_aps(boot_addr);
625 * look for the MP spec signature
628 /* string defined by the Intel MP Spec as identifying the MP table */
629 #define MP_SIG 0x5f504d5f /* _MP_ */
630 #define NEXT(X) ((X) += 4)
632 search_for_sig(u_int32_t target, int count)
635 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
637 for (x = 0; x < count; NEXT(x))
638 if (addr[x] == MP_SIG)
639 /* make array index a byte index */
640 return (long)(&addr[x]);
646 static basetable_entry basetable_entry_types[] =
648 {0, 20, "Processor"},
655 typedef struct BUSDATA {
657 enum busTypes bus_type;
660 typedef struct INTDATA {
670 typedef struct BUSTYPENAME {
675 static bus_type_name bus_type_table[] =
681 {UNKNOWN_BUSTYPE, "---"},
684 {UNKNOWN_BUSTYPE, "---"},
685 {UNKNOWN_BUSTYPE, "---"},
686 {UNKNOWN_BUSTYPE, "---"},
687 {UNKNOWN_BUSTYPE, "---"},
688 {UNKNOWN_BUSTYPE, "---"},
690 {UNKNOWN_BUSTYPE, "---"},
691 {UNKNOWN_BUSTYPE, "---"},
692 {UNKNOWN_BUSTYPE, "---"},
693 {UNKNOWN_BUSTYPE, "---"},
695 {UNKNOWN_BUSTYPE, "---"}
697 /* from MP spec v1.4, table 5-1 */
698 static int default_data[7][5] =
700 /* nbus, id0, type0, id1, type1 */
701 {1, 0, ISA, 255, 255},
702 {1, 0, EISA, 255, 255},
703 {1, 0, EISA, 255, 255},
704 {1, 0, MCA, 255, 255},
706 {2, 0, EISA, 1, PCI},
712 static bus_datum *bus_data;
715 /* the IO INT data, one entry per possible APIC INTerrupt */
716 static io_int *io_apic_ints;
720 static int processor_entry (proc_entry_ptr entry, int cpu);
721 static int bus_entry (bus_entry_ptr entry, int bus);
723 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
724 static int int_entry (int_entry_ptr entry, int intr);
726 static int lookup_bus_type (char *name);
730 * 1st pass on motherboard's Intel MP specification table.
736 * cpu_apic_address (common to all CPUs)
756 POSTCODE(MPTABLE_PASS1_POST);
759 /* clear various tables */
760 for (x = 0; x < NAPICID; ++x) {
761 io_apic_address[x] = ~0; /* IO APIC address table */
765 /* init everything to empty */
774 /* check for use of 'default' configuration */
775 if (mpfps->mpfb1 != 0) {
776 /* use default addresses */
777 cpu_apic_address = DEFAULT_APIC_BASE;
779 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
782 /* fill in with defaults */
783 mp_naps = 2; /* includes BSP */
784 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
792 panic("MP Configuration Table Header MISSING!");
793 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
795 cpu_apic_address = (vm_offset_t) cth->apic_address;
797 /* walk the table, recording info of interest */
798 totalSize = cth->base_table_length - sizeof(struct MPCTH);
799 position = (u_char *) cth + sizeof(struct MPCTH);
800 count = cth->entry_count;
803 switch (type = *(u_char *) position) {
804 case 0: /* processor_entry */
805 if (((proc_entry_ptr)position)->cpu_flags
806 & PROCENTRY_FLAG_EN) {
809 ((proc_entry_ptr)position)->apic_id;
812 case 1: /* bus_entry */
815 case 2: /* io_apic_entry */
817 if (((io_apic_entry_ptr)position)->apic_flags
818 & IOAPICENTRY_FLAG_EN)
819 io_apic_address[mp_napics++] =
820 (vm_offset_t)((io_apic_entry_ptr)
821 position)->apic_address;
824 case 3: /* int_entry */
829 case 4: /* int_entry */
832 panic("mpfps Base Table HOSED!");
836 totalSize -= basetable_entry_types[type].length;
837 position = (uint8_t *)position +
838 basetable_entry_types[type].length;
842 /* qualify the numbers */
843 if (mp_naps > MAXCPU) {
844 kprintf("Warning: only using %d of %d available CPUs!\n",
849 /* See if we need to fixup HT logical CPUs. */
850 mptable_hyperthread_fixup(id_mask);
854 * This is also used as a counter while starting the APs.
858 --mp_naps; /* subtract the BSP */
863 * 2nd pass on motherboard's Intel MP specification table.
867 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
868 * CPU_TO_ID(N), logical CPU to APIC ID table
869 * IO_TO_ID(N), logical IO to APIC ID table
876 struct PROCENTRY proc;
883 int apic, bus, cpu, intr;
886 POSTCODE(MPTABLE_PASS2_POST);
888 /* Initialize fake proc entry for use with HT fixup. */
889 bzero(&proc, sizeof(proc));
891 proc.cpu_flags = PROCENTRY_FLAG_EN;
894 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
896 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
897 M_DEVBUF, M_WAITOK | M_ZERO);
898 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
901 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
905 for (i = 0; i < mp_napics; i++) {
906 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
910 /* clear various tables */
911 for (x = 0; x < NAPICID; ++x) {
912 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
914 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
915 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
919 /* clear bus data table */
920 for (x = 0; x < mp_nbusses; ++x)
921 bus_data[x].bus_id = 0xff;
924 /* clear IO APIC INT table */
925 for (x = 0; x < (nintrs + 1); ++x) {
926 io_apic_ints[x].int_type = 0xff;
927 io_apic_ints[x].int_vector = 0xff;
931 /* setup the cpu/apic mapping arrays */
934 /* record whether PIC or virtual-wire mode */
935 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
937 /* check for use of 'default' configuration */
938 if (mpfps->mpfb1 != 0)
939 return mpfps->mpfb1; /* return default configuration type */
942 panic("MP Configuration Table Header MISSING!");
944 cth = (void *)PHYS_TO_DMAP(mpfps->pap);
945 /* walk the table, recording info of interest */
946 totalSize = cth->base_table_length - sizeof(struct MPCTH);
947 position = (u_char *) cth + sizeof(struct MPCTH);
948 count = cth->entry_count;
949 apic = bus = intr = 0;
950 cpu = 1; /* pre-count the BSP */
953 switch (type = *(u_char *) position) {
955 if (processor_entry(position, cpu))
958 if (need_hyperthreading_fixup) {
960 * Create fake mptable processor entries
961 * and feed them to processor_entry() to
962 * enumerate the logical CPUs.
964 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
965 for (i = 1; i < logical_cpus; i++) {
967 processor_entry(&proc, cpu);
968 logical_cpus_mask |= (1 << cpu);
974 if (bus_entry(position, bus))
979 if (io_apic_entry(position, apic))
985 if (int_entry(position, intr))
990 /* int_entry(position); */
993 panic("mpfps Base Table HOSED!");
997 totalSize -= basetable_entry_types[type].length;
998 position = (uint8_t *)position + basetable_entry_types[type].length;
1001 if (boot_cpu_id == -1)
1002 panic("NO BSP found!");
1004 /* report fact that its NOT a default configuration */
1009 * Check if we should perform a hyperthreading "fix-up" to
1010 * enumerate any logical CPU's that aren't already listed
1013 * XXX: We assume that all of the physical CPUs in the
1014 * system have the same number of logical CPUs.
1016 * XXX: We assume that APIC ID's are allocated such that
1017 * the APIC ID's for a physical processor are aligned
1018 * with the number of logical CPU's in the processor.
1021 mptable_hyperthread_fixup(u_int id_mask)
1025 /* Nothing to do if there is no HTT support. */
1026 if ((cpu_feature & CPUID_HTT) == 0)
1028 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1029 if (logical_cpus <= 1)
1033 * For each APIC ID of a CPU that is set in the mask,
1034 * scan the other candidate APIC ID's for this
1035 * physical processor. If any of those ID's are
1036 * already in the table, then kill the fixup.
1038 for (id = 0; id <= MAXCPU; id++) {
1039 if ((id_mask & 1 << id) == 0)
1041 /* First, make sure we are on a logical_cpus boundary. */
1042 if (id % logical_cpus != 0)
1044 for (i = id + 1; i < id + logical_cpus; i++)
1045 if ((id_mask & 1 << i) != 0)
1050 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1051 * mp_naps right now.
1053 need_hyperthreading_fixup = 1;
1054 mp_naps *= logical_cpus;
1060 assign_apic_irq(int apic, int intpin, int irq)
1064 if (int_to_apicintpin[irq].ioapic != -1)
1065 panic("assign_apic_irq: inconsistent table");
1067 int_to_apicintpin[irq].ioapic = apic;
1068 int_to_apicintpin[irq].int_pin = intpin;
1069 int_to_apicintpin[irq].apic_address = ioapic[apic];
1070 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1072 for (x = 0; x < nintrs; x++) {
1073 if ((io_apic_ints[x].int_type == 0 ||
1074 io_apic_ints[x].int_type == 3) &&
1075 io_apic_ints[x].int_vector == 0xff &&
1076 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1077 io_apic_ints[x].dst_apic_int == intpin)
1078 io_apic_ints[x].int_vector = irq;
1083 revoke_apic_irq(int irq)
1089 if (int_to_apicintpin[irq].ioapic == -1)
1090 panic("revoke_apic_irq: inconsistent table");
1092 oldapic = int_to_apicintpin[irq].ioapic;
1093 oldintpin = int_to_apicintpin[irq].int_pin;
1095 int_to_apicintpin[irq].ioapic = -1;
1096 int_to_apicintpin[irq].int_pin = 0;
1097 int_to_apicintpin[irq].apic_address = NULL;
1098 int_to_apicintpin[irq].redirindex = 0;
1100 for (x = 0; x < nintrs; x++) {
1101 if ((io_apic_ints[x].int_type == 0 ||
1102 io_apic_ints[x].int_type == 3) &&
1103 io_apic_ints[x].int_vector != 0xff &&
1104 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1105 io_apic_ints[x].dst_apic_int == oldintpin)
1106 io_apic_ints[x].int_vector = 0xff;
1114 allocate_apic_irq(int intr)
1120 if (io_apic_ints[intr].int_vector != 0xff)
1121 return; /* Interrupt handler already assigned */
1123 if (io_apic_ints[intr].int_type != 0 &&
1124 (io_apic_ints[intr].int_type != 3 ||
1125 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1126 io_apic_ints[intr].dst_apic_int == 0)))
1127 return; /* Not INT or ExtInt on != (0, 0) */
1130 while (irq < APIC_INTMAPSIZE &&
1131 int_to_apicintpin[irq].ioapic != -1)
1134 if (irq >= APIC_INTMAPSIZE)
1135 return; /* No free interrupt handlers */
1137 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1138 intpin = io_apic_ints[intr].dst_apic_int;
1140 assign_apic_irq(apic, intpin, irq);
1145 swap_apic_id(int apic, int oldid, int newid)
1152 return; /* Nothing to do */
1154 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1155 apic, oldid, newid);
1157 /* Swap physical APIC IDs in interrupt entries */
1158 for (x = 0; x < nintrs; x++) {
1159 if (io_apic_ints[x].dst_apic_id == oldid)
1160 io_apic_ints[x].dst_apic_id = newid;
1161 else if (io_apic_ints[x].dst_apic_id == newid)
1162 io_apic_ints[x].dst_apic_id = oldid;
1165 /* Swap physical APIC IDs in IO_TO_ID mappings */
1166 for (oapic = 0; oapic < mp_napics; oapic++)
1167 if (IO_TO_ID(oapic) == newid)
1170 if (oapic < mp_napics) {
1171 kprintf("Changing APIC ID for IO APIC #%d from "
1172 "%d to %d in MP table\n",
1173 oapic, newid, oldid);
1174 IO_TO_ID(oapic) = oldid;
1176 IO_TO_ID(apic) = newid;
1181 fix_id_to_io_mapping(void)
1185 for (x = 0; x < NAPICID; x++)
1188 for (x = 0; x <= mp_naps; x++)
1189 if (CPU_TO_ID(x) < NAPICID)
1190 ID_TO_IO(CPU_TO_ID(x)) = x;
1192 for (x = 0; x < mp_napics; x++)
1193 if (IO_TO_ID(x) < NAPICID)
1194 ID_TO_IO(IO_TO_ID(x)) = x;
1199 first_free_apic_id(void)
1203 for (freeid = 0; freeid < NAPICID; freeid++) {
1204 for (x = 0; x <= mp_naps; x++)
1205 if (CPU_TO_ID(x) == freeid)
1209 for (x = 0; x < mp_napics; x++)
1210 if (IO_TO_ID(x) == freeid)
1221 io_apic_id_acceptable(int apic, int id)
1223 int cpu; /* Logical CPU number */
1224 int oapic; /* Logical IO APIC number for other IO APIC */
1227 return 0; /* Out of range */
1229 for (cpu = 0; cpu <= mp_naps; cpu++)
1230 if (CPU_TO_ID(cpu) == id)
1231 return 0; /* Conflict with CPU */
1233 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1234 if (IO_TO_ID(oapic) == id)
1235 return 0; /* Conflict with other APIC */
1237 return 1; /* ID is acceptable for IO APIC */
1242 io_apic_find_int_entry(int apic, int pin)
1246 /* search each of the possible INTerrupt sources */
1247 for (x = 0; x < nintrs; ++x) {
1248 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1249 (pin == io_apic_ints[x].dst_apic_int))
1250 return (&io_apic_ints[x]);
1258 * parse an Intel MP specification table
1266 int apic; /* IO APIC unit number */
1267 int freeid; /* Free physical APIC ID */
1268 int physid; /* Current physical IO APIC ID */
1271 int bus_0 = 0; /* Stop GCC warning */
1272 int bus_pci = 0; /* Stop GCC warning */
1276 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1277 * did it wrong. The MP spec says that when more than 1 PCI bus
1278 * exists the BIOS must begin with bus entries for the PCI bus and use
1279 * actual PCI bus numbering. This implies that when only 1 PCI bus
1280 * exists the BIOS can choose to ignore this ordering, and indeed many
1281 * MP motherboards do ignore it. This causes a problem when the PCI
1282 * sub-system makes requests of the MP sub-system based on PCI bus
1283 * numbers. So here we look for the situation and renumber the
1284 * busses and associated INTs in an effort to "make it right".
1287 /* find bus 0, PCI bus, count the number of PCI busses */
1288 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1289 if (bus_data[x].bus_id == 0) {
1292 if (bus_data[x].bus_type == PCI) {
1298 * bus_0 == slot of bus with ID of 0
1299 * bus_pci == slot of last PCI bus encountered
1302 /* check the 1 PCI bus case for sanity */
1303 /* if it is number 0 all is well */
1304 if (num_pci_bus == 1 &&
1305 bus_data[bus_pci].bus_id != 0) {
1307 /* mis-numbered, swap with whichever bus uses slot 0 */
1309 /* swap the bus entry types */
1310 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1311 bus_data[bus_0].bus_type = PCI;
1314 /* swap each relavant INTerrupt entry */
1315 id = bus_data[bus_pci].bus_id;
1316 for (x = 0; x < nintrs; ++x) {
1317 if (io_apic_ints[x].src_bus_id == id) {
1318 io_apic_ints[x].src_bus_id = 0;
1320 else if (io_apic_ints[x].src_bus_id == 0) {
1321 io_apic_ints[x].src_bus_id = id;
1328 /* Assign IO APIC IDs.
1330 * First try the existing ID. If a conflict is detected, try
1331 * the ID in the MP table. If a conflict is still detected, find
1334 * We cannot use the ID_TO_IO table before all conflicts has been
1335 * resolved and the table has been corrected.
1337 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1339 /* First try to use the value set by the BIOS */
1340 physid = io_apic_get_id(apic);
1341 if (io_apic_id_acceptable(apic, physid)) {
1342 if (IO_TO_ID(apic) != physid)
1343 swap_apic_id(apic, IO_TO_ID(apic), physid);
1347 /* Then check if the value in the MP table is acceptable */
1348 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1351 /* Last resort, find a free APIC ID and use it */
1352 freeid = first_free_apic_id();
1353 if (freeid >= NAPICID)
1354 panic("No free physical APIC IDs found");
1356 if (io_apic_id_acceptable(apic, freeid)) {
1357 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1360 panic("Free physical APIC ID not usable");
1362 fix_id_to_io_mapping();
1366 /* detect and fix broken Compaq MP table */
1367 if (apic_int_type(0, 0) == -1) {
1368 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1369 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1370 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1371 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1372 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1373 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1375 } else if (apic_int_type(0, 0) == 0) {
1376 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1377 for (x = 0; x < nintrs; ++x)
1378 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1379 (0 == io_apic_ints[x].dst_apic_int)) {
1380 io_apic_ints[x].int_type = 3;
1381 io_apic_ints[x].int_vector = 0xff;
1387 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1388 * controllers universally come in pairs. If IRQ 14 is specified
1389 * as an ISA interrupt, then IRQ 15 had better be too.
1391 * [ Shuttle XPC / AMD Athlon X2 ]
1392 * The MPTable is missing an entry for IRQ 15. Note that the
1393 * ACPI table has an entry for both 14 and 15.
1395 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1396 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1397 io14 = io_apic_find_int_entry(0, 14);
1398 io_apic_ints[nintrs] = *io14;
1399 io_apic_ints[nintrs].src_bus_irq = 15;
1400 io_apic_ints[nintrs].dst_apic_int = 15;
1408 /* Assign low level interrupt handlers */
1410 setup_apic_irq_mapping(void)
1416 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1417 int_to_apicintpin[x].ioapic = -1;
1418 int_to_apicintpin[x].int_pin = 0;
1419 int_to_apicintpin[x].apic_address = NULL;
1420 int_to_apicintpin[x].redirindex = 0;
1423 /* First assign ISA/EISA interrupts */
1424 for (x = 0; x < nintrs; x++) {
1425 int_vector = io_apic_ints[x].src_bus_irq;
1426 if (int_vector < APIC_INTMAPSIZE &&
1427 io_apic_ints[x].int_vector == 0xff &&
1428 int_to_apicintpin[int_vector].ioapic == -1 &&
1429 (apic_int_is_bus_type(x, ISA) ||
1430 apic_int_is_bus_type(x, EISA)) &&
1431 io_apic_ints[x].int_type == 0) {
1432 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1433 io_apic_ints[x].dst_apic_int,
1438 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1439 for (x = 0; x < nintrs; x++) {
1440 if (io_apic_ints[x].dst_apic_int == 0 &&
1441 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1442 io_apic_ints[x].int_vector == 0xff &&
1443 int_to_apicintpin[0].ioapic == -1 &&
1444 io_apic_ints[x].int_type == 3) {
1445 assign_apic_irq(0, 0, 0);
1450 /* Assign PCI interrupts */
1451 for (x = 0; x < nintrs; ++x) {
1452 if (io_apic_ints[x].int_type == 0 &&
1453 io_apic_ints[x].int_vector == 0xff &&
1454 apic_int_is_bus_type(x, PCI))
1455 allocate_apic_irq(x);
1462 processor_entry(proc_entry_ptr entry, int cpu)
1464 /* check for usability */
1465 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1468 if(entry->apic_id >= NAPICID)
1469 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1470 /* check for BSP flag */
1471 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1472 boot_cpu_id = entry->apic_id;
1473 CPU_TO_ID(0) = entry->apic_id;
1474 ID_TO_CPU(entry->apic_id) = 0;
1475 return 0; /* its already been counted */
1478 /* add another AP to list, if less than max number of CPUs */
1479 else if (cpu < MAXCPU) {
1480 CPU_TO_ID(cpu) = entry->apic_id;
1481 ID_TO_CPU(entry->apic_id) = cpu;
1490 bus_entry(bus_entry_ptr entry, int bus)
1495 /* encode the name into an index */
1496 for (x = 0; x < 6; ++x) {
1497 if ((c = entry->bus_type[x]) == ' ')
1503 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1504 panic("unknown bus type: '%s'", name);
1506 bus_data[bus].bus_id = entry->bus_id;
1507 bus_data[bus].bus_type = x;
1515 io_apic_entry(io_apic_entry_ptr entry, int apic)
1517 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1520 IO_TO_ID(apic) = entry->apic_id;
1521 if (entry->apic_id < NAPICID)
1522 ID_TO_IO(entry->apic_id) = apic;
1530 lookup_bus_type(char *name)
1534 for (x = 0; x < MAX_BUSTYPE; ++x)
1535 if (strcmp(bus_type_table[x].name, name) == 0)
1536 return bus_type_table[x].type;
1538 return UNKNOWN_BUSTYPE;
1544 int_entry(int_entry_ptr entry, int intr)
1548 io_apic_ints[intr].int_type = entry->int_type;
1549 io_apic_ints[intr].int_flags = entry->int_flags;
1550 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1551 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1552 if (entry->dst_apic_id == 255) {
1553 /* This signal goes to all IO APICS. Select an IO APIC
1554 with sufficient number of interrupt pins */
1555 for (apic = 0; apic < mp_napics; apic++)
1556 if (((io_apic_read(apic, IOAPIC_VER) &
1557 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1558 entry->dst_apic_int)
1560 if (apic < mp_napics)
1561 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1563 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1565 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1566 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1572 apic_int_is_bus_type(int intr, int bus_type)
1576 for (bus = 0; bus < mp_nbusses; ++bus)
1577 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1578 && ((int) bus_data[bus].bus_type == bus_type))
1585 * Given a traditional ISA INT mask, return an APIC mask.
1588 isa_apic_mask(u_int isa_mask)
1593 #if defined(SKIP_IRQ15_REDIRECT)
1594 if (isa_mask == (1 << 15)) {
1595 kprintf("skipping ISA IRQ15 redirect\n");
1598 #endif /* SKIP_IRQ15_REDIRECT */
1600 isa_irq = ffs(isa_mask); /* find its bit position */
1601 if (isa_irq == 0) /* doesn't exist */
1603 --isa_irq; /* make it zero based */
1605 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1609 return (1 << apic_pin); /* convert pin# to a mask */
1613 * Determine which APIC pin an ISA/EISA INT is attached to.
1615 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1616 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1617 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1618 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1620 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1622 isa_apic_irq(int isa_irq)
1626 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1627 if (INTTYPE(intr) == 0) { /* standard INT */
1628 if (SRCBUSIRQ(intr) == isa_irq) {
1629 if (apic_int_is_bus_type(intr, ISA) ||
1630 apic_int_is_bus_type(intr, EISA)) {
1631 if (INTIRQ(intr) == 0xff)
1632 return -1; /* unassigned */
1633 return INTIRQ(intr); /* found */
1638 return -1; /* NOT found */
1643 * Determine which APIC pin a PCI INT is attached to.
1645 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1646 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1647 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1649 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1653 --pciInt; /* zero based */
1655 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1656 if ((INTTYPE(intr) == 0) /* standard INT */
1657 && (SRCBUSID(intr) == pciBus)
1658 && (SRCBUSDEVICE(intr) == pciDevice)
1659 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1660 if (apic_int_is_bus_type(intr, PCI)) {
1661 if (INTIRQ(intr) == 0xff) {
1662 kprintf("IOAPIC: pci_apic_irq() "
1664 return -1; /* unassigned */
1666 return INTIRQ(intr); /* exact match */
1671 return -1; /* NOT found */
1675 next_apic_irq(int irq)
1682 for (intr = 0; intr < nintrs; intr++) {
1683 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1685 bus = SRCBUSID(intr);
1686 bustype = apic_bus_type(bus);
1687 if (bustype != ISA &&
1693 if (intr >= nintrs) {
1696 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1697 if (INTTYPE(ointr) != 0)
1699 if (bus != SRCBUSID(ointr))
1701 if (bustype == PCI) {
1702 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1704 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1707 if (bustype == ISA || bustype == EISA) {
1708 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1711 if (INTPIN(intr) == INTPIN(ointr))
1715 if (ointr >= nintrs) {
1718 return INTIRQ(ointr);
1733 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1736 * Exactly what this means is unclear at this point. It is a solution
1737 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1738 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1739 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1743 undirect_isa_irq(int rirq)
1747 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1748 /** FIXME: tickle the MB redirector chip */
1752 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1759 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1762 undirect_pci_irq(int rirq)
1766 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1768 /** FIXME: tickle the MB redirector chip */
1772 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1780 * given a bus ID, return:
1781 * the bus type if found
1785 apic_bus_type(int id)
1789 for (x = 0; x < mp_nbusses; ++x)
1790 if (bus_data[x].bus_id == id)
1791 return bus_data[x].bus_type;
1799 * given a LOGICAL APIC# and pin#, return:
1800 * the associated src bus ID if found
1804 apic_src_bus_id(int apic, int pin)
1808 /* search each of the possible INTerrupt sources */
1809 for (x = 0; x < nintrs; ++x)
1810 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1811 (pin == io_apic_ints[x].dst_apic_int))
1812 return (io_apic_ints[x].src_bus_id);
1814 return -1; /* NOT found */
1818 * given a LOGICAL APIC# and pin#, return:
1819 * the associated src bus IRQ if found
1823 apic_src_bus_irq(int apic, int pin)
1827 for (x = 0; x < nintrs; x++)
1828 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1829 (pin == io_apic_ints[x].dst_apic_int))
1830 return (io_apic_ints[x].src_bus_irq);
1832 return -1; /* NOT found */
1837 * given a LOGICAL APIC# and pin#, return:
1838 * the associated INTerrupt type if found
1842 apic_int_type(int apic, int pin)
1846 /* search each of the possible INTerrupt sources */
1847 for (x = 0; x < nintrs; ++x) {
1848 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1849 (pin == io_apic_ints[x].dst_apic_int))
1850 return (io_apic_ints[x].int_type);
1852 return -1; /* NOT found */
1856 * Return the IRQ associated with an APIC pin
1859 apic_irq(int apic, int pin)
1864 for (x = 0; x < nintrs; ++x) {
1865 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1866 (pin == io_apic_ints[x].dst_apic_int)) {
1867 res = io_apic_ints[x].int_vector;
1870 if (apic != int_to_apicintpin[res].ioapic)
1871 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1872 if (pin != int_to_apicintpin[res].int_pin)
1873 panic("apic_irq inconsistent table (2)");
1882 * given a LOGICAL APIC# and pin#, return:
1883 * the associated trigger mode if found
1887 apic_trigger(int apic, int pin)
1891 /* search each of the possible INTerrupt sources */
1892 for (x = 0; x < nintrs; ++x)
1893 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1894 (pin == io_apic_ints[x].dst_apic_int))
1895 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1897 return -1; /* NOT found */
1902 * given a LOGICAL APIC# and pin#, return:
1903 * the associated 'active' level if found
1907 apic_polarity(int apic, int pin)
1911 /* search each of the possible INTerrupt sources */
1912 for (x = 0; x < nintrs; ++x)
1913 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1914 (pin == io_apic_ints[x].dst_apic_int))
1915 return (io_apic_ints[x].int_flags & 0x03);
1917 return -1; /* NOT found */
1923 * set data according to MP defaults
1924 * FIXME: probably not complete yet...
1927 default_mp_table(int type)
1930 #if defined(APIC_IO)
1933 #endif /* APIC_IO */
1936 kprintf(" MP default config type: %d\n", type);
1939 kprintf(" bus: ISA, APIC: 82489DX\n");
1942 kprintf(" bus: EISA, APIC: 82489DX\n");
1945 kprintf(" bus: EISA, APIC: 82489DX\n");
1948 kprintf(" bus: MCA, APIC: 82489DX\n");
1951 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1954 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1957 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1960 kprintf(" future type\n");
1966 boot_cpu_id = (lapic->id & APIC_ID_MASK) >> 24;
1967 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1970 CPU_TO_ID(0) = boot_cpu_id;
1971 ID_TO_CPU(boot_cpu_id) = 0;
1973 /* one and only AP */
1974 CPU_TO_ID(1) = ap_cpu_id;
1975 ID_TO_CPU(ap_cpu_id) = 1;
1977 #if defined(APIC_IO)
1978 /* one and only IO APIC */
1979 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1982 * sanity check, refer to MP spec section 3.6.6, last paragraph
1983 * necessary as some hardware isn't properly setting up the IO APIC
1985 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1986 if (io_apic_id != 2) {
1988 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1989 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1990 io_apic_set_id(0, 2);
1993 IO_TO_ID(0) = io_apic_id;
1994 ID_TO_IO(io_apic_id) = 0;
1995 #endif /* APIC_IO */
1997 /* fill out bus entries */
2006 bus_data[0].bus_id = default_data[type - 1][1];
2007 bus_data[0].bus_type = default_data[type - 1][2];
2008 bus_data[1].bus_id = default_data[type - 1][3];
2009 bus_data[1].bus_type = default_data[type - 1][4];
2012 /* case 4: case 7: MCA NOT supported */
2013 default: /* illegal/reserved */
2014 panic("BAD default MP config: %d", type);
2018 #if defined(APIC_IO)
2019 /* general cases from MP v1.4, table 5-2 */
2020 for (pin = 0; pin < 16; ++pin) {
2021 io_apic_ints[pin].int_type = 0;
2022 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2023 io_apic_ints[pin].src_bus_id = 0;
2024 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2025 io_apic_ints[pin].dst_apic_id = io_apic_id;
2026 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2029 /* special cases from MP v1.4, table 5-2 */
2031 io_apic_ints[2].int_type = 0xff; /* N/C */
2032 io_apic_ints[13].int_type = 0xff; /* N/C */
2033 #if !defined(APIC_MIXED_MODE)
2035 panic("sorry, can't support type 2 default yet");
2036 #endif /* APIC_MIXED_MODE */
2039 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2042 io_apic_ints[0].int_type = 0xff; /* N/C */
2044 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2045 #endif /* APIC_IO */
2049 * Map a physical memory address representing I/O into KVA. The I/O
2050 * block is assumed not to cross a page boundary.
2053 permanent_io_mapping(vm_paddr_t pa)
2055 KKASSERT(pa < 0x100000000LL);
2057 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2061 * start each AP in our list
2064 start_all_aps(u_int boot_addr)
2066 vm_offset_t va = boot_address + KERNBASE;
2067 u_int64_t *pt4, *pt3, *pt2;
2073 u_char mpbiosreason;
2074 u_long mpbioswarmvec;
2075 struct mdglobaldata *gd;
2076 struct privatespace *ps;
2078 POSTCODE(START_ALL_APS_POST);
2080 /* Initialize BSP's local APIC */
2081 apic_initialize(TRUE);
2084 /* install the AP 1st level boot code */
2085 pmap_kenter(va, boot_address);
2086 cpu_invlpg((void *)va); /* JG XXX */
2087 bcopy(mptramp_start, (void *)va, bootMP_size);
2089 /* Locate the page tables, they'll be below the trampoline */
2090 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2091 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2092 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2094 /* Create the initial 1GB replicated page tables */
2095 for (i = 0; i < 512; i++) {
2096 /* Each slot of the level 4 pages points to the same level 3 page */
2097 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2098 pt4[i] |= PG_V | PG_RW | PG_U;
2100 /* Each slot of the level 3 pages points to the same level 2 page */
2101 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2102 pt3[i] |= PG_V | PG_RW | PG_U;
2104 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2105 pt2[i] = i * (2 * 1024 * 1024);
2106 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2109 /* save the current value of the warm-start vector */
2110 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2111 outb(CMOS_REG, BIOS_RESET);
2112 mpbiosreason = inb(CMOS_DATA);
2114 /* setup a vector to our boot code */
2115 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2116 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2117 outb(CMOS_REG, BIOS_RESET);
2118 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2121 * If we have a TSC we can figure out the SMI interrupt rate.
2122 * The SMI does not necessarily use a constant rate. Spend
2123 * up to 250ms trying to figure it out.
2126 if (cpu_feature & CPUID_TSC) {
2127 set_apic_timer(275000);
2128 smilast = read_apic_timer();
2129 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2130 smicount = smitest();
2131 if (smibest == 0 || smilast - smicount < smibest)
2132 smibest = smilast - smicount;
2135 if (smibest > 250000)
2138 smibest = smibest * (int64_t)1000000 /
2139 get_apic_timer_frequency();
2143 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2144 1000000 / smibest, smibest);
2147 for (x = 1; x <= mp_naps; ++x) {
2149 /* This is a bit verbose, it will go away soon. */
2151 /* first page of AP's private space */
2152 pg = x * x86_64_btop(sizeof(struct privatespace));
2154 /* allocate new private data page(s) */
2155 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2156 MDGLOBALDATA_BASEALLOC_SIZE);
2158 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2159 bzero(gd, sizeof(*gd));
2160 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2162 /* prime data page for it to use */
2163 mi_gdinit(&gd->mi, x);
2165 gd->gd_CMAP1 = &SMPpt[pg + 0];
2166 gd->gd_CMAP2 = &SMPpt[pg + 1];
2167 gd->gd_CMAP3 = &SMPpt[pg + 2];
2168 gd->gd_PMAP1 = &SMPpt[pg + 3];
2169 gd->gd_CADDR1 = ps->CPAGE1;
2170 gd->gd_CADDR2 = ps->CPAGE2;
2171 gd->gd_CADDR3 = ps->CPAGE3;
2172 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2173 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2174 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2176 /* setup a vector to our boot code */
2177 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2178 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2179 outb(CMOS_REG, BIOS_RESET);
2180 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2183 * Setup the AP boot stack
2185 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2188 /* attempt to start the Application Processor */
2189 CHECK_INIT(99); /* setup checkpoints */
2190 if (!start_ap(gd, boot_addr, smibest)) {
2191 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2192 CHECK_PRINT("trace"); /* show checkpoints */
2193 /* better panic as the AP may be running loose */
2194 kprintf("panic y/n? [y] ");
2195 if (cngetc() != 'n')
2198 CHECK_PRINT("trace"); /* show checkpoints */
2200 /* record its version info */
2201 cpu_apic_versions[x] = cpu_apic_versions[0];
2204 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2207 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2208 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2211 ncpus2_shift = shift;
2212 ncpus2 = 1 << shift;
2213 ncpus2_mask = ncpus2 - 1;
2215 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2216 if ((1 << shift) < ncpus)
2218 ncpus_fit = 1 << shift;
2219 ncpus_fit_mask = ncpus_fit - 1;
2221 /* build our map of 'other' CPUs */
2222 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2223 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2224 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2226 /* fill in our (BSP) APIC version */
2227 cpu_apic_versions[0] = lapic->version;
2229 /* restore the warmstart vector */
2230 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2231 outb(CMOS_REG, BIOS_RESET);
2232 outb(CMOS_DATA, mpbiosreason);
2235 * NOTE! The idlestack for the BSP was setup by locore. Finish
2236 * up, clean out the P==V mapping we did earlier.
2240 /* number of APs actually started */
2246 * load the 1st level AP boot code into base memory.
2249 /* targets for relocation */
2250 extern void bigJump(void);
2251 extern void bootCodeSeg(void);
2252 extern void bootDataSeg(void);
2253 extern void MPentry(void);
2254 extern u_int MP_GDT;
2255 extern u_int mp_gdtbase;
2260 install_ap_tramp(u_int boot_addr)
2263 int size = *(int *) ((u_long) & bootMP_size);
2264 u_char *src = (u_char *) ((u_long) bootMP);
2265 u_char *dst = (u_char *) boot_addr + KERNBASE;
2266 u_int boot_base = (u_int) bootMP;
2271 POSTCODE(INSTALL_AP_TRAMP_POST);
2273 for (x = 0; x < size; ++x)
2277 * modify addresses in code we just moved to basemem. unfortunately we
2278 * need fairly detailed info about mpboot.s for this to work. changes
2279 * to mpboot.s might require changes here.
2282 /* boot code is located in KERNEL space */
2283 dst = (u_char *) boot_addr + KERNBASE;
2285 /* modify the lgdt arg */
2286 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2287 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2289 /* modify the ljmp target for MPentry() */
2290 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2291 *dst32 = ((u_int) MPentry - KERNBASE);
2293 /* modify the target for boot code segment */
2294 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2295 dst8 = (u_int8_t *) (dst16 + 1);
2296 *dst16 = (u_int) boot_addr & 0xffff;
2297 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2299 /* modify the target for boot data segment */
2300 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2301 dst8 = (u_int8_t *) (dst16 + 1);
2302 *dst16 = (u_int) boot_addr & 0xffff;
2303 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2309 * This function starts the AP (application processor) identified
2310 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2311 * to accomplish this. This is necessary because of the nuances
2312 * of the different hardware we might encounter. It ain't pretty,
2313 * but it seems to work.
2315 * NOTE: eventually an AP gets to ap_init(), which is called just
2316 * before the AP goes into the LWKT scheduler's idle loop.
2319 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2323 u_long icr_lo, icr_hi;
2325 POSTCODE(START_AP_POST);
2327 /* get the PHYSICAL APIC ID# */
2328 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2330 /* calculate the vector */
2331 vector = (boot_addr >> 12) & 0xff;
2333 /* We don't want anything interfering */
2336 /* Make sure the target cpu sees everything */
2340 * Try to detect when a SMI has occurred, wait up to 200ms.
2342 * If a SMI occurs during an AP reset but before we issue
2343 * the STARTUP command, the AP may brick. To work around
2344 * this problem we hold off doing the AP startup until
2345 * after we have detected the SMI. Hopefully another SMI
2346 * will not occur before we finish the AP startup.
2348 * Retries don't seem to help. SMIs have a window of opportunity
2349 * and if USB->legacy keyboard emulation is enabled in the BIOS
2350 * the interrupt rate can be quite high.
2352 * NOTE: Don't worry about the L1 cache load, it might bloat
2353 * ldelta a little but ndelta will be so huge when the SMI
2354 * occurs the detection logic will still work fine.
2357 set_apic_timer(200000);
2362 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2363 * and running the target CPU. OR this INIT IPI might be latched (P5
2364 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2367 * see apic/apicreg.h for icr bit definitions.
2369 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2373 * Setup the address for the target AP. We can setup
2374 * icr_hi once and then just trigger operations with
2377 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2378 icr_hi |= (physical_cpu << 24);
2379 icr_lo = lapic->icr_lo & 0xfff00000;
2380 lapic->icr_hi = icr_hi;
2383 * Do an INIT IPI: assert RESET
2385 * Use edge triggered mode to assert INIT
2387 lapic->icr_lo = icr_lo | 0x00004500;
2388 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2392 * The spec calls for a 10ms delay but we may have to use a
2393 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2394 * interrupt. We have other loops here too and dividing by 2
2395 * doesn't seem to be enough even after subtracting 350us,
2396 * so we divide by 4.
2398 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2399 * interrupt was detected we use the full 10ms.
2403 else if (smibest < 150 * 4 + 350)
2405 else if ((smibest - 350) / 4 < 10000)
2406 u_sleep((smibest - 350) / 4);
2411 * Do an INIT IPI: deassert RESET
2413 * Use level triggered mode to deassert. It is unclear
2414 * why we need to do this.
2416 lapic->icr_lo = icr_lo | 0x00008500;
2417 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2419 u_sleep(150); /* wait 150us */
2422 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2423 * latched, (P5 bug) this 1st STARTUP would then terminate
2424 * immediately, and the previously started INIT IPI would continue. OR
2425 * the previous INIT IPI has already run. and this STARTUP IPI will
2426 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2429 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2430 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2432 u_sleep(200); /* wait ~200uS */
2435 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2436 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2437 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2438 * recognized after hardware RESET or INIT IPI.
2440 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2441 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2444 /* Resume normal operation */
2447 /* wait for it to start, see ap_init() */
2448 set_apic_timer(5000000);/* == 5 seconds */
2449 while (read_apic_timer()) {
2450 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2451 return 1; /* return SUCCESS */
2454 return 0; /* return FAILURE */
2469 while (read_apic_timer()) {
2471 for (count = 0; count < 100; ++count)
2472 ntsc = rdtsc(); /* force loop to occur */
2474 ndelta = ntsc - ltsc;
2475 if (ldelta > ndelta)
2477 if (ndelta > ldelta * 2)
2480 ldelta = ntsc - ltsc;
2483 return(read_apic_timer());
2487 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2489 * If for some reason we were unable to start all cpus we cannot safely
2490 * use broadcast IPIs.
2496 if (smp_startup_mask == smp_active_mask) {
2497 all_but_self_ipi(XINVLTLB_OFFSET);
2499 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2500 APIC_DELMODE_FIXED);
2506 * When called the executing CPU will send an IPI to all other CPUs
2507 * requesting that they halt execution.
2509 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2511 * - Signals all CPUs in map to stop.
2512 * - Waits for each to stop.
2519 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2520 * from executing at same time.
2523 stop_cpus(u_int map)
2525 map &= smp_active_mask;
2527 /* send the Xcpustop IPI to all CPUs in map */
2528 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2530 while ((stopped_cpus & map) != map)
2538 * Called by a CPU to restart stopped CPUs.
2540 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2542 * - Signals all CPUs in map to restart.
2543 * - Waits for each to restart.
2551 restart_cpus(u_int map)
2553 /* signal other cpus to restart */
2554 started_cpus = map & smp_active_mask;
2556 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2563 * This is called once the mpboot code has gotten us properly relocated
2564 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2565 * and when it returns the scheduler will call the real cpu_idle() main
2566 * loop for the idlethread. Interrupts are disabled on entry and should
2567 * remain disabled at return.
2575 * Adjust smp_startup_mask to signal the BSP that we have started
2576 * up successfully. Note that we do not yet hold the BGL. The BSP
2577 * is waiting for our signal.
2579 * We can't set our bit in smp_active_mask yet because we are holding
2580 * interrupts physically disabled and remote cpus could deadlock
2581 * trying to send us an IPI.
2583 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2587 * Interlock for finalization. Wait until mp_finish is non-zero,
2588 * then get the MP lock.
2590 * Note: We are in a critical section.
2592 * Note: We have to synchronize td_mpcount to our desired MP state
2593 * before calling cpu_try_mplock().
2595 * Note: we are the idle thread, we can only spin.
2597 * Note: The load fence is memory volatile and prevents the compiler
2598 * from improperly caching mp_finish, and the cpu from improperly
2601 while (mp_finish == 0)
2603 ++curthread->td_mpcount;
2604 while (cpu_try_mplock() == 0)
2607 if (cpu_feature & CPUID_TSC) {
2609 * The BSP is constantly updating tsc0_offset, figure out the
2610 * relative difference to synchronize ktrdump.
2612 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2615 /* BSP may have changed PTD while we're waiting for the lock */
2618 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2622 /* Build our map of 'other' CPUs. */
2623 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2625 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2627 /* A quick check from sanity claus */
2628 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2629 if (mycpu->gd_cpuid != apic_id) {
2630 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2631 kprintf("SMP: apic_id = %d\n", apic_id);
2633 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2635 panic("cpuid mismatch! boom!!");
2638 /* Initialize AP's local APIC for irq's */
2639 apic_initialize(FALSE);
2641 /* Set memory range attributes for this CPU to match the BSP */
2642 mem_range_AP_init();
2645 * Once we go active we must process any IPIQ messages that may
2646 * have been queued, because no actual IPI will occur until we
2647 * set our bit in the smp_active_mask. If we don't the IPI
2648 * message interlock could be left set which would also prevent
2651 * The idle loop doesn't expect the BGL to be held and while
2652 * lwkt_switch() normally cleans things up this is a special case
2653 * because we returning almost directly into the idle loop.
2655 * The idle thread is never placed on the runq, make sure
2656 * nothing we've done put it there.
2658 KKASSERT(curthread->td_mpcount == 1);
2659 smp_active_mask |= 1 << mycpu->gd_cpuid;
2662 * Enable interrupts here. idle_restore will also do it, but
2663 * doing it here lets us clean up any strays that got posted to
2664 * the CPU during the AP boot while we are still in a critical
2667 __asm __volatile("sti; pause; pause"::);
2668 mdcpu->gd_fpending = 0;
2670 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2671 lwkt_process_ipiq();
2674 * Releasing the mp lock lets the BSP finish up the SMP init
2677 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2681 * Get SMP fully working before we start initializing devices.
2689 kprintf("Finish MP startup\n");
2690 if (cpu_feature & CPUID_TSC)
2691 tsc0_offset = rdtsc();
2694 while (smp_active_mask != smp_startup_mask) {
2696 if (cpu_feature & CPUID_TSC)
2697 tsc0_offset = rdtsc();
2699 while (try_mplock() == 0)
2702 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2705 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2708 cpu_send_ipiq(int dcpu)
2710 if ((1 << dcpu) & smp_active_mask)
2711 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2714 #if 0 /* single_apic_ipi_passive() not working yet */
2716 * Returns 0 on failure, 1 on success
2719 cpu_send_ipiq_passive(int dcpu)
2722 if ((1 << dcpu) & smp_active_mask) {
2723 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2724 APIC_DELMODE_FIXED);