2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.40 2008/09/17 08:51:29 sephe Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/interrupt.h>
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/queue.h>
46 #include <sys/thread2.h>
49 #include <net/ifq_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/vlan/if_vlan_var.h>
60 #include <netinet/in_systm.h>
61 #include <netinet/in.h>
62 #include <netinet/ip.h>
64 #include <bus/pci/pcireg.h>
65 #include <bus/pci/pcivar.h>
66 #include <bus/pci/pcidevs.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
71 #include <dev/netif/bfe/if_bfereg.h>
73 MODULE_DEPEND(bfe, pci, 1, 1, 1);
74 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
76 /* "controller miibus0" required. See GENERIC if you get errors here. */
77 #include "miibus_if.h"
79 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
81 struct bfe_dmamap_ctx {
83 bus_dma_segment_t *segs;
86 static struct bfe_type bfe_devs[] = {
87 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
88 "Broadcom BCM4401 Fast Ethernet" },
89 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
90 "Broadcom BCM4401-B0 Fast Ethernet" },
91 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
92 "Broadcom BCM4402 Fast Ethernet" },
96 static int bfe_probe(device_t);
97 static int bfe_attach(device_t);
98 static int bfe_detach(device_t);
99 static void bfe_intr(void *);
100 static void bfe_start(struct ifnet *);
101 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void bfe_init(void *);
103 static void bfe_stop(struct bfe_softc *);
104 static void bfe_watchdog(struct ifnet *);
105 static void bfe_shutdown(device_t);
106 static void bfe_tick(void *);
107 static void bfe_txeof(struct bfe_softc *);
108 static void bfe_rxeof(struct bfe_softc *);
109 static void bfe_set_rx_mode(struct bfe_softc *);
110 static int bfe_list_rx_init(struct bfe_softc *);
111 static int bfe_newbuf(struct bfe_softc *, int, int);
112 static void bfe_setup_rxdesc(struct bfe_softc *, int);
113 static void bfe_rx_ring_free(struct bfe_softc *);
115 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
116 static int bfe_ifmedia_upd(struct ifnet *);
117 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
118 static int bfe_miibus_readreg(device_t, int, int);
119 static int bfe_miibus_writereg(device_t, int, int, int);
120 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
122 static void bfe_get_config(struct bfe_softc *sc);
123 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
124 static void bfe_stats_update(struct bfe_softc *);
125 static void bfe_clear_stats (struct bfe_softc *);
126 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
127 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
128 static int bfe_resetphy(struct bfe_softc *);
129 static int bfe_setupphy(struct bfe_softc *);
130 static void bfe_chip_reset(struct bfe_softc *);
131 static void bfe_chip_halt(struct bfe_softc *);
132 static void bfe_core_reset(struct bfe_softc *);
133 static void bfe_core_disable(struct bfe_softc *);
134 static int bfe_dma_alloc(device_t);
135 static void bfe_dma_free(struct bfe_softc *);
136 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
137 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
138 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
139 static void bfe_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
142 static device_method_t bfe_methods[] = {
143 /* Device interface */
144 DEVMETHOD(device_probe, bfe_probe),
145 DEVMETHOD(device_attach, bfe_attach),
146 DEVMETHOD(device_detach, bfe_detach),
147 DEVMETHOD(device_shutdown, bfe_shutdown),
150 DEVMETHOD(bus_print_child, bus_generic_print_child),
151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
154 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
155 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
160 static driver_t bfe_driver = {
163 sizeof(struct bfe_softc)
166 static devclass_t bfe_devclass;
168 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
169 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
172 * Probe for a Broadcom 4401 chip.
175 bfe_probe(device_t dev)
178 uint16_t vendor, product;
180 vendor = pci_get_vendor(dev);
181 product = pci_get_device(dev);
183 for (t = bfe_devs; t->bfe_name != NULL; t++) {
184 if (vendor == t->bfe_vid && product == t->bfe_did) {
185 device_set_desc(dev, t->bfe_name);
194 bfe_dma_alloc(device_t dev)
196 struct bfe_softc *sc = device_get_softc(dev);
197 int error, i, tx_pos = 0, rx_pos = 0;
200 * Parent tag. Apparently the chip cannot handle any DMA address
201 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
203 error = bus_dma_tag_create(NULL, /* parent */
204 1, 0, /* alignment, boundary */
205 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
206 BUS_SPACE_MAXADDR, /* highaddr */
207 NULL, NULL, /* filter, filterarg */
208 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
209 0, /* num of segments */
210 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
212 &sc->bfe_parent_tag);
214 device_printf(dev, "could not allocate parent dma tag\n");
218 /* tag for TX ring */
219 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
220 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
222 BFE_TX_LIST_SIZE, 1, BFE_TX_LIST_SIZE,
225 device_printf(dev, "could not allocate dma tag for TX list\n");
229 /* tag for RX ring */
230 error = bus_dma_tag_create(sc->bfe_parent_tag, PAGE_SIZE, 0,
231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
233 BFE_RX_LIST_SIZE, 1, BFE_RX_LIST_SIZE,
236 device_printf(dev, "could not allocate dma tag for RX list\n");
240 /* Tag for RX mbufs */
241 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
244 MCLBYTES, 1, MCLBYTES,
245 BUS_DMA_ALLOCNOW, &sc->bfe_rxbuf_tag);
247 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
251 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0, &sc->bfe_rx_tmpmap);
253 device_printf(dev, "could not create RX mbuf tmp map\n");
254 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
255 sc->bfe_rxbuf_tag = NULL;
259 /* Allocate dma maps for RX list */
260 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_rxbuf_tag, 0,
262 &sc->bfe_rx_ring[i].bfe_map);
265 device_printf(dev, "cannot create DMA map for RX\n");
269 rx_pos = BFE_RX_LIST_CNT;
271 /* Tag for TX mbufs */
272 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
273 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
275 MCLBYTES, 1, MCLBYTES,
276 BUS_DMA_ALLOCNOW, &sc->bfe_txbuf_tag);
278 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
282 /* Allocate dmamaps for TX list */
283 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
284 error = bus_dmamap_create(sc->bfe_txbuf_tag, 0,
285 &sc->bfe_tx_ring[i].bfe_map);
288 device_printf(dev, "cannot create DMA map for TX\n");
293 /* Alloc dma for rx ring */
294 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
295 BUS_DMA_WAITOK | BUS_DMA_ZERO,
298 device_printf(dev, "cannot allocate DMA mem for RX\n");
302 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
303 sc->bfe_rx_list, sizeof(struct bfe_desc),
304 bfe_dma_map, &sc->bfe_rx_dma, BUS_DMA_WAITOK);
306 device_printf(dev, "cannot load DMA map for RX\n");
310 /* Alloc dma for tx ring */
311 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
312 BUS_DMA_WAITOK | BUS_DMA_ZERO,
315 device_printf(dev, "cannot allocate DMA mem for TX\n");
319 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
320 sc->bfe_tx_list, sizeof(struct bfe_desc),
321 bfe_dma_map, &sc->bfe_tx_dma, BUS_DMA_WAITOK);
323 device_printf(dev, "cannot load DMA map for TX\n");
330 if (sc->bfe_rxbuf_tag != NULL) {
331 for (i = 0; i < rx_pos; ++i) {
332 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
333 sc->bfe_rx_ring[i].bfe_map);
335 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
336 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
337 sc->bfe_rxbuf_tag = NULL;
340 if (sc->bfe_txbuf_tag != NULL) {
341 for (i = 0; i < tx_pos; ++i) {
342 bus_dmamap_destroy(sc->bfe_txbuf_tag,
343 sc->bfe_tx_ring[i].bfe_map);
345 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
346 sc->bfe_txbuf_tag = NULL;
352 bfe_attach(device_t dev)
355 struct bfe_softc *sc;
358 sc = device_get_softc(dev);
361 callout_init(&sc->bfe_stat_timer);
365 * Handle power management nonsense.
367 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
368 uint32_t membase, irq;
370 /* Save important PCI config data. */
371 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
372 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
374 /* Reset the power state. */
375 device_printf(dev, "chip is in D%d power mode"
376 " -- setting to D0\n", pci_get_powerstate(dev));
378 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
380 /* Restore PCI config data. */
381 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
382 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
384 #endif /* !BURN_BRIDGE */
387 * Map control/status registers.
389 pci_enable_busmaster(dev);
392 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
394 if (sc->bfe_res == NULL) {
395 device_printf(dev, "couldn't map memory\n");
399 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
400 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
402 /* Allocate interrupt */
405 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
406 RF_SHAREABLE | RF_ACTIVE);
407 if (sc->bfe_irq == NULL) {
408 device_printf(dev, "couldn't map interrupt\n");
413 error = bfe_dma_alloc(dev);
415 device_printf(dev, "failed to allocate DMA resources\n");
419 /* Set up ifnet structure */
420 ifp = &sc->arpcom.ac_if;
422 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
423 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
424 ifp->if_ioctl = bfe_ioctl;
425 ifp->if_start = bfe_start;
426 ifp->if_watchdog = bfe_watchdog;
427 ifp->if_init = bfe_init;
428 ifp->if_mtu = ETHERMTU;
429 ifp->if_baudrate = 100000000;
430 ifp->if_capabilities |= IFCAP_VLAN_MTU;
431 ifp->if_capenable |= IFCAP_VLAN_MTU;
432 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
433 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
434 ifq_set_ready(&ifp->if_snd);
438 /* Reset the chip and turn on the PHY */
441 if (mii_phy_probe(dev, &sc->bfe_miibus,
442 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
443 device_printf(dev, "MII without any PHY!\n");
448 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
451 * Hook interrupt last to avoid having to lock softc
453 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
454 bfe_intr, sc, &sc->bfe_intrhand,
455 sc->arpcom.ac_if.if_serializer);
459 device_printf(dev, "couldn't set up irq\n");
463 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bfe_irq));
464 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
472 bfe_detach(device_t dev)
474 struct bfe_softc *sc = device_get_softc(dev);
475 struct ifnet *ifp = &sc->arpcom.ac_if;
477 if (device_is_attached(dev)) {
478 lwkt_serialize_enter(ifp->if_serializer);
481 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
482 lwkt_serialize_exit(ifp->if_serializer);
486 if (sc->bfe_miibus != NULL)
487 device_delete_child(dev, sc->bfe_miibus);
488 bus_generic_detach(dev);
490 if (sc->bfe_irq != NULL)
491 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
493 if (sc->bfe_res != NULL) {
494 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
503 * Stop all chip I/O so that the kernel's probe routines don't
504 * get confused by errant DMAs when rebooting.
507 bfe_shutdown(device_t dev)
509 struct bfe_softc *sc = device_get_softc(dev);
510 struct ifnet *ifp = &sc->arpcom.ac_if;
512 lwkt_serialize_enter(ifp->if_serializer);
514 lwkt_serialize_exit(ifp->if_serializer);
518 bfe_miibus_readreg(device_t dev, int phy, int reg)
520 struct bfe_softc *sc;
523 sc = device_get_softc(dev);
524 if (phy != sc->bfe_phyaddr)
526 bfe_readphy(sc, reg, &ret);
532 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
534 struct bfe_softc *sc;
536 sc = device_get_softc(dev);
537 if (phy != sc->bfe_phyaddr)
539 bfe_writephy(sc, reg, val);
545 bfe_tx_ring_free(struct bfe_softc *sc)
549 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
550 bus_dmamap_unload(sc->bfe_txbuf_tag,
551 sc->bfe_tx_ring[i].bfe_map);
552 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
553 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
554 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
557 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
558 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
562 bfe_rx_ring_free(struct bfe_softc *sc)
566 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
567 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
568 bus_dmamap_unload(sc->bfe_rxbuf_tag,
569 sc->bfe_rx_ring[i].bfe_map);
570 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
571 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
574 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
575 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
579 bfe_list_rx_init(struct bfe_softc *sc)
583 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
584 error = bfe_newbuf(sc, i, 1);
589 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
590 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
598 bfe_newbuf(struct bfe_softc *sc, int c, int init)
602 bus_dma_segment_t seg;
603 struct bfe_dmamap_ctx ctx;
607 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
610 m->m_len = m->m_pkthdr.len = MCLBYTES;
614 error = bus_dmamap_load_mbuf(sc->bfe_rxbuf_tag,
616 m, bfe_dmamap_buf_cb, &ctx,
618 if (error || ctx.nsegs == 0) {
620 bus_dmamap_unload(sc->bfe_rxbuf_tag,
623 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
628 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
632 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
633 r = &sc->bfe_rx_ring[c];
635 if (r->bfe_mbuf != NULL)
636 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
639 r->bfe_map = sc->bfe_rx_tmpmap;
640 sc->bfe_rx_tmpmap = map;
643 r->bfe_paddr = seg.ds_addr;
645 bfe_setup_rxdesc(sc, c);
650 bfe_setup_rxdesc(struct bfe_softc *sc, int c)
652 struct bfe_rxheader *rx_header;
658 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
659 r = &sc->bfe_rx_ring[c];
660 d = &sc->bfe_rx_list[c];
662 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
665 rx_header = mtod(m, struct bfe_rxheader *);
667 rx_header->flags = 0;
668 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
670 ctrl = ETHER_MAX_LEN + 32;
671 if (c == BFE_RX_LIST_CNT - 1)
672 ctrl |= BFE_DESC_EOT;
674 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
676 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREWRITE);
680 bfe_get_config(struct bfe_softc *sc)
684 bfe_read_eeprom(sc, eeprom);
686 sc->arpcom.ac_enaddr[0] = eeprom[79];
687 sc->arpcom.ac_enaddr[1] = eeprom[78];
688 sc->arpcom.ac_enaddr[2] = eeprom[81];
689 sc->arpcom.ac_enaddr[3] = eeprom[80];
690 sc->arpcom.ac_enaddr[4] = eeprom[83];
691 sc->arpcom.ac_enaddr[5] = eeprom[82];
693 sc->bfe_phyaddr = eeprom[90] & 0x1f;
694 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
696 sc->bfe_core_unit = 0;
697 sc->bfe_dma_offset = BFE_PCI_DMA;
701 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
703 uint32_t bar_orig, pci_rev, val;
705 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
706 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
707 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
709 val = CSR_READ_4(sc, BFE_SBINTVEC);
711 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
713 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
714 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
715 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
717 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
721 bfe_clear_stats(struct bfe_softc *sc)
725 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
726 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
728 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
733 bfe_resetphy(struct bfe_softc *sc)
737 bfe_writephy(sc, 0, BMCR_RESET);
739 bfe_readphy(sc, 0, &val);
740 if (val & BMCR_RESET) {
741 if_printf(&sc->arpcom.ac_if,
742 "PHY Reset would not complete.\n");
749 bfe_chip_halt(struct bfe_softc *sc)
751 /* disable interrupts - not that it actually does..*/
752 CSR_WRITE_4(sc, BFE_IMASK, 0);
753 CSR_READ_4(sc, BFE_IMASK);
755 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
756 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
758 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
759 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
764 bfe_chip_reset(struct bfe_softc *sc)
768 /* Set the interrupt vector for the enet core */
769 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
772 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
773 if (val == BFE_CLOCK) {
774 /* It is, so shut it down */
775 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
776 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
777 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
778 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
779 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
780 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
781 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
782 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
790 * We want the phy registers to be accessible even when
791 * the driver is "downed" so initialize MDC preamble, frequency,
792 * and whether internal or external phy here.
795 /* 4402 has 62.5Mhz SB clock and internal phy */
796 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
798 /* Internal or external PHY? */
799 val = CSR_READ_4(sc, BFE_DEVCTRL);
800 if (!(val & BFE_IPP))
801 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
802 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
803 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
807 /* Enable CRC32 generation and set proper LED modes */
808 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
810 /* Reset or clear powerdown control bit */
811 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
813 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
817 * We don't want lazy interrupts, so just send them at the end of a
820 BFE_OR(sc, BFE_RCV_LAZY, 0);
822 /* Set max lengths, accounting for VLAN tags */
823 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
824 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
826 /* Set watermark XXX - magic */
827 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
830 * Initialise DMA channels - not forgetting dma addresses need to be
831 * added to BFE_PCI_DMA
833 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
834 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
836 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
838 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
845 bfe_core_disable(struct bfe_softc *sc)
847 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
851 * Set reject, wait for it set, then wait for the core to stop being busy
852 * Then set reset and reject and enable the clocks
854 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
855 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
856 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
857 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
859 CSR_READ_4(sc, BFE_SBTMSLOW);
861 /* Leave reset and reject set */
862 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
867 bfe_core_reset(struct bfe_softc *sc)
871 /* Disable the core */
872 bfe_core_disable(sc);
874 /* and bring it back up */
875 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
876 CSR_READ_4(sc, BFE_SBTMSLOW);
879 /* Chip bug, clear SERR, IB and TO if they are set. */
880 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
881 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
882 val = CSR_READ_4(sc, BFE_SBIMSTATE);
883 if (val & (BFE_IBE | BFE_TO))
884 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
886 /* Clear reset and allow it to move through the core */
887 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
888 CSR_READ_4(sc, BFE_SBTMSLOW);
891 /* Leave the clock set */
892 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
893 CSR_READ_4(sc, BFE_SBTMSLOW);
898 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
902 val = ((uint32_t) data[2]) << 24;
903 val |= ((uint32_t) data[3]) << 16;
904 val |= ((uint32_t) data[4]) << 8;
905 val |= ((uint32_t) data[5]);
906 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
907 val = (BFE_CAM_HI_VALID |
908 (((uint32_t) data[0]) << 8) |
909 (((uint32_t) data[1])));
910 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
911 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
912 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
913 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
917 bfe_set_rx_mode(struct bfe_softc *sc)
919 struct ifnet *ifp = &sc->arpcom.ac_if;
920 struct ifmultiaddr *ifma;
924 val = CSR_READ_4(sc, BFE_RXCONF);
926 if (ifp->if_flags & IFF_PROMISC)
927 val |= BFE_RXCONF_PROMISC;
929 val &= ~BFE_RXCONF_PROMISC;
931 if (ifp->if_flags & IFF_BROADCAST)
932 val &= ~BFE_RXCONF_DBCAST;
934 val |= BFE_RXCONF_DBCAST;
937 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
938 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
940 if (ifp->if_flags & IFF_ALLMULTI) {
941 val |= BFE_RXCONF_ALLMULTI;
943 val &= ~BFE_RXCONF_ALLMULTI;
944 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
945 if (ifma->ifma_addr->sa_family != AF_LINK)
948 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
952 CSR_WRITE_4(sc, BFE_RXCONF, val);
953 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
957 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
962 *ptr = segs->ds_addr;
966 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
971 /* The chip needs all addresses to be added to BFE_PCI_DMA */
972 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
976 bfe_dma_free(struct bfe_softc *sc)
980 if (sc->bfe_tx_tag != NULL) {
981 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
982 if (sc->bfe_tx_list != NULL) {
983 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
985 sc->bfe_tx_list = NULL;
987 bus_dma_tag_destroy(sc->bfe_tx_tag);
988 sc->bfe_tx_tag = NULL;
991 if (sc->bfe_rx_tag != NULL) {
992 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
993 if (sc->bfe_rx_list != NULL) {
994 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
996 sc->bfe_rx_list = NULL;
998 bus_dma_tag_destroy(sc->bfe_rx_tag);
999 sc->bfe_rx_tag = NULL;
1002 if (sc->bfe_txbuf_tag != NULL) {
1003 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
1004 bus_dmamap_destroy(sc->bfe_txbuf_tag,
1005 sc->bfe_tx_ring[i].bfe_map);
1007 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
1008 sc->bfe_txbuf_tag = NULL;
1011 if (sc->bfe_rxbuf_tag != NULL) {
1012 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
1013 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
1014 sc->bfe_rx_ring[i].bfe_map);
1016 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
1017 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
1018 sc->bfe_rxbuf_tag = NULL;
1021 if (sc->bfe_parent_tag != NULL) {
1022 bus_dma_tag_destroy(sc->bfe_parent_tag);
1023 sc->bfe_parent_tag = NULL;
1028 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
1031 uint16_t *ptr = (uint16_t *)data;
1033 for (i = 0; i < 128; i += 2)
1034 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1038 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
1039 u_long timeout, const int clear)
1043 for (i = 0; i < timeout; i++) {
1044 uint32_t val = CSR_READ_4(sc, reg);
1046 if (clear && !(val & bit))
1048 if (!clear && (val & bit))
1053 if_printf(&sc->arpcom.ac_if,
1054 "BUG! Timeout waiting for bit %08x of register "
1055 "%x to %s.\n", bit, reg,
1056 (clear ? "clear" : "set"));
1063 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
1068 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1069 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1070 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1071 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1072 (reg << BFE_MDIO_RA_SHIFT) |
1073 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1074 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1075 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1080 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1084 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1085 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1086 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1087 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1088 (reg << BFE_MDIO_RA_SHIFT) |
1089 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1090 (val & BFE_MDIO_DATA_DATA)));
1091 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1097 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1101 bfe_setupphy(struct bfe_softc *sc)
1105 /* Enable activity LED */
1106 bfe_readphy(sc, 26, &val);
1107 bfe_writephy(sc, 26, val & 0x7fff);
1108 bfe_readphy(sc, 26, &val);
1110 /* Enable traffic meter LED mode */
1111 bfe_readphy(sc, 27, &val);
1112 bfe_writephy(sc, 27, val | (1 << 6));
1118 bfe_stats_update(struct bfe_softc *sc)
1123 val = &sc->bfe_hwstats.tx_good_octets;
1124 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1125 *val++ += CSR_READ_4(sc, reg);
1126 val = &sc->bfe_hwstats.rx_good_octets;
1127 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1128 *val++ += CSR_READ_4(sc, reg);
1132 bfe_txeof(struct bfe_softc *sc)
1134 struct ifnet *ifp = &sc->arpcom.ac_if;
1135 uint32_t i, chipidx;
1137 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1138 chipidx /= sizeof(struct bfe_desc);
1140 i = sc->bfe_tx_cons;
1141 /* Go through the mbufs and free those that have been transmitted */
1142 while (i != chipidx) {
1143 struct bfe_data *r = &sc->bfe_tx_ring[i];
1145 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1146 if (r->bfe_mbuf != NULL) {
1148 m_freem(r->bfe_mbuf);
1152 BFE_INC(i, BFE_TX_LIST_CNT);
1155 if (i != sc->bfe_tx_cons) {
1156 /* we freed up some mbufs */
1157 sc->bfe_tx_cons = i;
1158 ifp->if_flags &= ~IFF_OACTIVE;
1160 if (sc->bfe_tx_cnt == 0)
1166 /* Pass a received packet up the stack */
1168 bfe_rxeof(struct bfe_softc *sc)
1170 struct ifnet *ifp = &sc->arpcom.ac_if;
1172 struct bfe_rxheader *rxheader;
1174 uint32_t cons, status, current, len, flags;
1175 struct mbuf_chain chain[MAXCPU];
1177 cons = sc->bfe_rx_cons;
1178 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1179 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1181 ether_input_chain_init(chain);
1183 while (current != cons) {
1184 r = &sc->bfe_rx_ring[cons];
1185 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1186 BUS_DMASYNC_POSTREAD);
1188 KKASSERT(r->bfe_mbuf != NULL);
1190 rxheader = mtod(m, struct bfe_rxheader*);
1191 len = rxheader->len - ETHER_CRC_LEN;
1192 flags = rxheader->flags;
1194 /* flag an error and try again */
1195 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
1197 if (flags & BFE_RX_FLAG_SERR)
1198 ifp->if_collisions++;
1200 bfe_setup_rxdesc(sc, cons);
1201 BFE_INC(cons, BFE_RX_LIST_CNT);
1205 /* Go past the rx header */
1206 if (bfe_newbuf(sc, cons, 0) != 0) {
1207 bfe_setup_rxdesc(sc, cons);
1209 BFE_INC(cons, BFE_RX_LIST_CNT);
1213 m_adj(m, BFE_RX_OFFSET);
1214 m->m_len = m->m_pkthdr.len = len;
1217 m->m_pkthdr.rcvif = ifp;
1219 ether_input_chain(ifp, m, chain);
1220 BFE_INC(cons, BFE_RX_LIST_CNT);
1223 ether_input_dispatch(chain);
1225 sc->bfe_rx_cons = cons;
1231 struct bfe_softc *sc = xsc;
1232 struct ifnet *ifp = &sc->arpcom.ac_if;
1233 uint32_t istat, imask, flag;
1235 istat = CSR_READ_4(sc, BFE_ISTAT);
1236 imask = CSR_READ_4(sc, BFE_IMASK);
1239 * Defer unsolicited interrupts - This is necessary because setting the
1240 * chips interrupt mask register to 0 doesn't actually stop the
1244 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1245 CSR_READ_4(sc, BFE_ISTAT);
1247 /* not expecting this interrupt, disregard it */
1252 if (istat & BFE_ISTAT_ERRORS) {
1253 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1254 if (flag & BFE_STAT_EMASK)
1257 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1258 if (flag & BFE_RX_FLAG_ERRORS)
1261 ifp->if_flags &= ~IFF_RUNNING;
1265 /* A packet was received */
1266 if (istat & BFE_ISTAT_RX)
1269 /* A packet was sent */
1270 if (istat & BFE_ISTAT_TX)
1273 /* We have packets pending, fire them out */
1274 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1279 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1281 struct bfe_desc *d = NULL;
1282 struct bfe_data *r = NULL;
1284 uint32_t frag, cur, cnt = 0;
1285 int error, chainlen = 0;
1287 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt));
1290 * Count the number of frags in this chain to see if
1291 * we need to m_defrag. Since the descriptor list is shared
1292 * by all packets, we'll m_defrag long chains so that they
1293 * do not use up the entire list, even if they would fit.
1295 for (m = *m_head; m != NULL; m = m->m_next)
1298 if (chainlen > (BFE_TX_LIST_CNT / 4) ||
1299 BFE_TX_LIST_CNT < (2 + chainlen + sc->bfe_tx_cnt)) {
1300 m = m_defrag(*m_head, MB_DONTWAIT);
1309 * Start packing the mbufs in this chain into
1310 * the fragment pointers. Stop when we run out
1311 * of fragments or hit the end of the mbuf chain.
1313 cur = frag = *txidx;
1316 for (m = *m_head; m != NULL; m = m->m_next) {
1317 if (m->m_len != 0) {
1318 KKASSERT(BFE_TX_LIST_CNT >= (2 + sc->bfe_tx_cnt + cnt));
1320 d = &sc->bfe_tx_list[cur];
1321 r = &sc->bfe_tx_ring[cur];
1322 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1323 /* always intterupt on completion */
1324 d->bfe_ctrl |= BFE_DESC_IOC;
1326 /* Set start of frame */
1327 d->bfe_ctrl |= BFE_DESC_SOF;
1329 if (cur == BFE_TX_LIST_CNT - 1) {
1331 * Tell the chip to wrap to the start of the
1334 d->bfe_ctrl |= BFE_DESC_EOT;
1337 error = bus_dmamap_load(sc->bfe_txbuf_tag, r->bfe_map,
1338 mtod(m, void *), m->m_len,
1339 bfe_dma_map_desc, d,
1342 /* XXX This should be a fatal error. */
1343 if_printf(&sc->arpcom.ac_if,
1344 "%s bus_dmamap_load failed: %d",
1350 bus_dmamap_sync(sc->bfe_txbuf_tag, r->bfe_map,
1351 BUS_DMASYNC_PREWRITE);
1354 BFE_INC(cur, BFE_TX_LIST_CNT);
1359 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1360 sc->bfe_tx_ring[frag].bfe_mbuf = *m_head;
1361 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREWRITE);
1364 sc->bfe_tx_cnt += cnt;
1369 * Set up to transmit a packet
1372 bfe_start(struct ifnet *ifp)
1374 struct bfe_softc *sc = ifp->if_softc;
1375 struct mbuf *m_head = NULL;
1376 int idx, need_trans;
1378 ASSERT_SERIALIZED(ifp->if_serializer);
1381 * Not much point trying to send if the link is down
1382 * or we have nothing to send.
1384 if (!sc->bfe_link) {
1385 ifq_purge(&ifp->if_snd);
1389 if (ifp->if_flags & IFF_OACTIVE)
1392 idx = sc->bfe_tx_prod;
1395 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1396 if (BFE_TX_LIST_CNT < (2 + sc->bfe_tx_cnt)) {
1397 ifp->if_flags |= IFF_OACTIVE;
1401 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1406 * Pack the data into the tx ring. If we don't have
1407 * enough room, let the chip drain the ring.
1409 if (bfe_encap(sc, &m_head, &idx)) {
1410 ifp->if_flags |= IFF_OACTIVE;
1416 * If there's a BPF listener, bounce a copy of this frame
1419 BPF_MTAP(ifp, m_head);
1425 sc->bfe_tx_prod = idx;
1426 /* Transmit - twice due to apparent hardware bug */
1427 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1428 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1431 * Set a timeout in case the chip goes out to lunch.
1439 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1440 struct ifnet *ifp = &sc->arpcom.ac_if;
1442 ASSERT_SERIALIZED(ifp->if_serializer);
1444 if (ifp->if_flags & IFF_RUNNING)
1450 if (bfe_list_rx_init(sc) == ENOBUFS) {
1451 if_printf(ifp, "bfe_init failed. "
1452 " Not enough memory for list buffers\n");
1457 bfe_set_rx_mode(sc);
1459 /* Enable the chip and core */
1460 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1461 /* Enable interrupts */
1462 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1464 bfe_ifmedia_upd(ifp);
1465 ifp->if_flags |= IFF_RUNNING;
1466 ifp->if_flags &= ~IFF_OACTIVE;
1468 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1472 * Set media options.
1475 bfe_ifmedia_upd(struct ifnet *ifp)
1477 struct bfe_softc *sc = ifp->if_softc;
1478 struct mii_data *mii;
1480 ASSERT_SERIALIZED(ifp->if_serializer);
1482 mii = device_get_softc(sc->bfe_miibus);
1484 if (mii->mii_instance) {
1485 struct mii_softc *miisc;
1486 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1487 miisc = LIST_NEXT(miisc, mii_list))
1488 mii_phy_reset(miisc);
1498 * Report current media status.
1501 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1503 struct bfe_softc *sc = ifp->if_softc;
1504 struct mii_data *mii;
1506 ASSERT_SERIALIZED(ifp->if_serializer);
1508 mii = device_get_softc(sc->bfe_miibus);
1510 ifmr->ifm_active = mii->mii_media_active;
1511 ifmr->ifm_status = mii->mii_media_status;
1515 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1517 struct bfe_softc *sc = ifp->if_softc;
1518 struct ifreq *ifr = (struct ifreq *) data;
1519 struct mii_data *mii;
1522 ASSERT_SERIALIZED(ifp->if_serializer);
1526 if (ifp->if_flags & IFF_UP)
1527 if (ifp->if_flags & IFF_RUNNING)
1528 bfe_set_rx_mode(sc);
1531 else if (ifp->if_flags & IFF_RUNNING)
1536 if (ifp->if_flags & IFF_RUNNING)
1537 bfe_set_rx_mode(sc);
1541 mii = device_get_softc(sc->bfe_miibus);
1542 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1546 error = ether_ioctl(ifp, command, data);
1553 bfe_watchdog(struct ifnet *ifp)
1555 struct bfe_softc *sc = ifp->if_softc;
1557 ASSERT_SERIALIZED(ifp->if_serializer);
1559 if_printf(ifp, "watchdog timeout -- resetting\n");
1561 ifp->if_flags &= ~IFF_RUNNING;
1570 struct bfe_softc *sc = xsc;
1571 struct mii_data *mii;
1572 struct ifnet *ifp = &sc->arpcom.ac_if;
1574 mii = device_get_softc(sc->bfe_miibus);
1576 lwkt_serialize_enter(ifp->if_serializer);
1578 bfe_stats_update(sc);
1579 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1581 if (sc->bfe_link == 0) {
1583 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1584 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1590 lwkt_serialize_exit(ifp->if_serializer);
1594 * Stop the adapter and free any mbufs allocated to the
1598 bfe_stop(struct bfe_softc *sc)
1600 struct ifnet *ifp = &sc->arpcom.ac_if;
1602 ASSERT_SERIALIZED(ifp->if_serializer);
1604 callout_stop(&sc->bfe_stat_timer);
1607 bfe_tx_ring_free(sc);
1608 bfe_rx_ring_free(sc);
1610 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1614 bfe_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
1615 bus_size_t mapsz __unused, int error)
1617 struct bfe_dmamap_ctx *ctx = xctx;
1623 if (nsegs > ctx->nsegs) {
1629 for (i = 0; i < nsegs; ++i)
1630 ctx->segs[i] = segs[i];