2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c,v 1.4.4.4 2004/02/20 15:41:54 ru Exp $
32 * $DragonFly: src/sys/dev/netif/bfe/if_bfe.c,v 1.1 2004/02/27 11:56:12 joerg Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <net/if_arp.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/vlan/if_vlan_var.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in.h>
57 #include <netinet/ip.h>
59 #include <machine/bus_memio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/mii_layer/mii.h>
70 #include <dev/netif/mii_layer/miivar.h>
72 #include "if_bfereg.h"
74 MODULE_DEPEND(bfe, pci, 1, 1, 1);
75 MODULE_DEPEND(bfe, ether, 1, 1, 1);
76 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
78 /* "controller miibus0" required. See GENERIC if you get errors here. */
79 #include "miibus_if.h"
81 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
83 static struct bfe_type bfe_devs[] = {
84 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
85 "Broadcom BCM4401 Fast Ethernet" },
89 static int bfe_probe(device_t);
90 static int bfe_attach(device_t);
91 static int bfe_detach(device_t);
92 static void bfe_release_resources(struct bfe_softc *);
93 static void bfe_intr(void *);
94 static void bfe_start(struct ifnet *);
95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t);
96 static void bfe_init(void *);
97 static void bfe_stop(struct bfe_softc *);
98 static void bfe_watchdog(struct ifnet *);
99 static void bfe_shutdown(device_t);
100 static void bfe_tick(void *);
101 static void bfe_txeof(struct bfe_softc *);
102 static void bfe_rxeof(struct bfe_softc *);
103 static void bfe_set_rx_mode(struct bfe_softc *);
104 static int bfe_list_rx_init(struct bfe_softc *);
105 static int bfe_list_newbuf(struct bfe_softc *, int, struct mbuf*);
106 static void bfe_rx_ring_free(struct bfe_softc *);
108 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
109 static int bfe_ifmedia_upd(struct ifnet *);
110 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
111 static int bfe_miibus_readreg(device_t, int, int);
112 static int bfe_miibus_writereg(device_t, int, int, int);
113 static void bfe_miibus_statchg(device_t);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_map_desc(void *, bus_dma_segment_t *, int, int);
130 static void bfe_dma_map(void *, bus_dma_segment_t *, int, int);
131 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
133 static device_method_t bfe_methods[] = {
134 /* Device interface */
135 DEVMETHOD(device_probe, bfe_probe),
136 DEVMETHOD(device_attach, bfe_attach),
137 DEVMETHOD(device_detach, bfe_detach),
138 DEVMETHOD(device_shutdown, bfe_shutdown),
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
170 struct bfe_softc *sc;
174 sc = device_get_softc(dev);
175 bzero(sc, sizeof(struct bfe_softc));
176 sc->bfe_unit = device_get_unit(dev);
179 while (t->bfe_name != NULL) {
180 if ((pci_get_vendor(dev) == t->bfe_vid) &&
181 (pci_get_device(dev) == t->bfe_did)) {
182 device_set_desc_copy(dev, t->bfe_name);
192 bfe_dma_alloc(device_t dev)
194 struct bfe_softc *sc;
197 sc = device_get_softc(dev);
200 error = bus_dma_tag_create(NULL, /* parent */
201 PAGE_SIZE, 0, /* alignment, boundary */
202 BUS_SPACE_MAXADDR, /* lowaddr */
203 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
204 NULL, NULL, /* filter, filterarg */
205 MAXBSIZE, /* maxsize */
206 BUS_SPACE_UNRESTRICTED, /* num of segments */
207 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
208 BUS_DMA_ALLOCNOW, /* flags */
209 &sc->bfe_parent_tag);
212 device_printf(dev, "could not allocate dma tag\n");
217 /* tag for TX ring */
218 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_TX_LIST_SIZE,
219 BFE_TX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
220 NULL, NULL, BFE_TX_LIST_SIZE, 1,
221 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_tx_tag);
224 device_printf(dev, "could not allocate dma tag\n");
228 /* tag for RX ring */
229 error = bus_dma_tag_create(sc->bfe_parent_tag, BFE_RX_LIST_SIZE,
230 BFE_RX_LIST_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
231 NULL, NULL, BFE_RX_LIST_SIZE, 1,
232 BUS_SPACE_MAXSIZE_32BIT, 0, &sc->bfe_rx_tag);
235 device_printf(dev, "could not allocate dma tag\n");
240 error = bus_dma_tag_create(sc->bfe_parent_tag, ETHER_ALIGN, 0,
241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
242 1, BUS_SPACE_MAXSIZE_32BIT, 0,
246 device_printf(dev, "could not allocate dma tag\n");
250 /* pre allocate dmamaps for RX list */
251 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
252 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_rx_ring[i].bfe_map);
254 device_printf(dev, "cannot create DMA map for RX\n");
259 /* pre allocate dmamaps for TX list */
260 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
261 error = bus_dmamap_create(sc->bfe_tag, 0, &sc->bfe_tx_ring[i].bfe_map);
263 device_printf(dev, "cannot create DMA map for TX\n");
268 /* Alloc dma for rx ring */
269 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
270 BUS_DMA_WAITOK, &sc->bfe_rx_map);
275 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
276 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
277 sc->bfe_rx_list, sizeof(struct bfe_desc),
278 bfe_dma_map, &sc->bfe_rx_dma, 0);
283 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
285 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
286 BUS_DMA_WAITOK, &sc->bfe_tx_map);
290 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
291 sc->bfe_tx_list, sizeof(struct bfe_desc),
292 bfe_dma_map, &sc->bfe_tx_dma, 0);
296 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
297 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
303 bfe_attach(device_t dev)
306 struct bfe_softc *sc;
307 int unit, error = 0, rid;
309 sc = device_get_softc(dev);
311 unit = device_get_unit(dev);
316 * Handle power management nonsense.
318 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
319 uint32_t membase, irq;
321 /* Save important PCI config data. */
322 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
323 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
325 /* Reset the power state. */
326 printf("bfe%d: chip is is in D%d power mode -- setting to D0\n",
327 sc->bfe_unit, pci_get_powerstate(dev));
329 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
331 /* Restore PCI config data. */
332 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
333 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
337 * Map control/status registers.
339 pci_enable_busmaster(dev);
342 sc->bfe_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
344 if (sc->bfe_res == NULL) {
345 printf ("bfe%d: couldn't map memory\n", unit);
350 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
351 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
353 /* Allocate interrupt */
356 sc->bfe_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
357 RF_SHAREABLE | RF_ACTIVE);
358 if (sc->bfe_irq == NULL) {
359 printf("bfe%d: couldn't map interrupt\n", unit);
364 if (bfe_dma_alloc(dev)) {
365 printf("bfe%d: failed to allocate DMA resources\n", sc->bfe_unit);
366 bfe_release_resources(sc);
371 /* Set up ifnet structure */
372 ifp = &sc->arpcom.ac_if;
374 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
376 ifp->if_ioctl = bfe_ioctl;
377 ifp->if_output = ether_output;
378 ifp->if_start = bfe_start;
379 ifp->if_watchdog = bfe_watchdog;
380 ifp->if_init = bfe_init;
381 ifp->if_mtu = ETHERMTU;
382 ifp->if_baudrate = 10000000;
383 ifp->if_snd.ifq_maxlen = BFE_TX_QLEN;
387 printf("bfe%d: Ethernet address: %6D\n", unit, sc->arpcom.ac_enaddr, ":");
389 /* Reset the chip and turn on the PHY */
392 if (mii_phy_probe(dev, &sc->bfe_miibus,
393 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
394 printf("bfe%d: MII without any PHY!\n", sc->bfe_unit);
399 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
400 callout_handle_init(&sc->bfe_stat_ch);
403 * Hook interrupt last to avoid having to lock softc
405 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET,
406 bfe_intr, sc, &sc->bfe_intrhand);
409 bfe_release_resources(sc);
410 printf("bfe%d: couldn't set up irq\n", unit);
415 bfe_release_resources(sc);
420 bfe_detach(device_t dev)
422 struct bfe_softc *sc;
426 sc = device_get_softc(dev);
430 ifp = &sc->arpcom.ac_if;
432 if (device_is_attached(dev)) {
434 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
439 bus_generic_detach(dev);
440 if (sc->bfe_miibus != NULL)
441 device_delete_child(dev, sc->bfe_miibus);
443 bfe_release_resources(sc);
450 * Stop all chip I/O so that the kernel's probe routines don't
451 * get confused by errant DMAs when rebooting.
454 bfe_shutdown(device_t dev)
456 struct bfe_softc *sc;
459 sc = device_get_softc(dev);
469 bfe_miibus_readreg(device_t dev, int phy, int reg)
471 struct bfe_softc *sc;
474 sc = device_get_softc(dev);
475 if (phy != sc->bfe_phyaddr)
477 bfe_readphy(sc, reg, &ret);
483 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
485 struct bfe_softc *sc;
487 sc = device_get_softc(dev);
488 if (phy != sc->bfe_phyaddr)
490 bfe_writephy(sc, reg, val);
496 bfe_miibus_statchg(device_t dev)
502 bfe_tx_ring_free(struct bfe_softc *sc)
506 for (i = 0; i < BFE_TX_LIST_CNT; i++)
507 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
508 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
509 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
510 bus_dmamap_unload(sc->bfe_tag,
511 sc->bfe_tx_ring[i].bfe_map);
512 bus_dmamap_destroy(sc->bfe_tag,
513 sc->bfe_tx_ring[i].bfe_map);
515 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
516 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
520 bfe_rx_ring_free(struct bfe_softc *sc)
524 for (i = 0; i < BFE_RX_LIST_CNT; i++)
525 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
526 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
527 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
528 bus_dmamap_unload(sc->bfe_tag,
529 sc->bfe_rx_ring[i].bfe_map);
530 bus_dmamap_destroy(sc->bfe_tag,
531 sc->bfe_rx_ring[i].bfe_map);
533 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
534 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
539 bfe_list_rx_init(struct bfe_softc *sc)
543 for (i = 0; i < BFE_RX_LIST_CNT; i++)
544 if (bfe_list_newbuf(sc, i, NULL) == ENOBUFS)
547 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
548 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
556 bfe_list_newbuf(struct bfe_softc *sc, int c, struct mbuf *m)
558 struct bfe_rxheader *rx_header;
563 if ((c < 0) || (c >= BFE_RX_LIST_CNT))
567 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
570 m->m_len = m->m_pkthdr.len = MCLBYTES;
573 m->m_data = m->m_ext.ext_buf;
575 rx_header = mtod(m, struct bfe_rxheader *);
577 rx_header->flags = 0;
579 /* Map the mbuf into DMA */
581 d = &sc->bfe_rx_list[c];
582 r = &sc->bfe_rx_ring[c];
583 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void *),
584 MCLBYTES, bfe_dma_map_desc, d, 0);
585 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
587 ctrl = ETHER_MAX_LEN + 32;
589 if(c == BFE_RX_LIST_CNT - 1)
590 ctrl |= BFE_DESC_EOT;
594 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map, BUS_DMASYNC_PREREAD);
599 bfe_get_config(struct bfe_softc *sc)
603 bfe_read_eeprom(sc, eeprom);
605 sc->arpcom.ac_enaddr[0] = eeprom[79];
606 sc->arpcom.ac_enaddr[1] = eeprom[78];
607 sc->arpcom.ac_enaddr[2] = eeprom[81];
608 sc->arpcom.ac_enaddr[3] = eeprom[80];
609 sc->arpcom.ac_enaddr[4] = eeprom[83];
610 sc->arpcom.ac_enaddr[5] = eeprom[82];
612 sc->bfe_phyaddr = eeprom[90] & 0x1f;
613 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
615 sc->bfe_core_unit = 0;
616 sc->bfe_dma_offset = BFE_PCI_DMA;
620 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
622 uint32_t bar_orig, pci_rev, val;
624 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
625 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
626 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
628 val = CSR_READ_4(sc, BFE_SBINTVEC);
630 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
632 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
633 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
634 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
636 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
640 bfe_clear_stats(struct bfe_softc *sc)
647 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
648 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
650 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
657 bfe_resetphy(struct bfe_softc *sc)
663 bfe_writephy(sc, 0, BMCR_RESET);
665 bfe_readphy(sc, 0, &val);
666 if (val & BMCR_RESET) {
667 printf("bfe%d: PHY Reset would not complete.\n", sc->bfe_unit);
676 bfe_chip_halt(struct bfe_softc *sc)
681 /* disable interrupts - not that it actually does..*/
682 CSR_WRITE_4(sc, BFE_IMASK, 0);
683 CSR_READ_4(sc, BFE_IMASK);
685 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
686 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
688 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
689 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
696 bfe_chip_reset(struct bfe_softc *sc)
703 /* Set the interrupt vector for the enet core */
704 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
707 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
708 if (val == BFE_CLOCK) {
709 /* It is, so shut it down */
710 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
711 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
712 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
713 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
714 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
715 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
716 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
717 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
718 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
725 * We want the phy registers to be accessible even when
726 * the driver is "downed" so initialize MDC preamble, frequency,
727 * and whether internal or external phy here.
730 /* 4402 has 62.5Mhz SB clock and internal phy */
731 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
733 /* Internal or external PHY? */
734 val = CSR_READ_4(sc, BFE_DEVCTRL);
735 if (!(val & BFE_IPP))
736 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
737 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
738 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
742 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB);
743 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
747 * We don't want lazy interrupts, so just send them at the end of a
750 BFE_OR(sc, BFE_RCV_LAZY, 0);
752 /* Set max lengths, accounting for VLAN tags */
753 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
754 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
756 /* Set watermark XXX - magic */
757 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
760 * Initialise DMA channels - not forgetting dma addresses need to be
761 * added to BFE_PCI_DMA
763 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
764 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
766 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
768 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
777 bfe_core_disable(struct bfe_softc *sc)
779 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
783 * Set reject, wait for it set, then wait for the core to stop being busy
784 * Then set reset and reject and enable the clocks
786 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
787 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
788 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
789 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
791 CSR_READ_4(sc, BFE_SBTMSLOW);
793 /* Leave reset and reject set */
794 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
799 bfe_core_reset(struct bfe_softc *sc)
803 /* Disable the core */
804 bfe_core_disable(sc);
806 /* and bring it back up */
807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
808 CSR_READ_4(sc, BFE_SBTMSLOW);
811 /* Chip bug, clear SERR, IB and TO if they are set. */
812 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
813 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
814 val = CSR_READ_4(sc, BFE_SBIMSTATE);
815 if (val & (BFE_IBE | BFE_TO))
816 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
818 /* Clear reset and allow it to move through the core */
819 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
820 CSR_READ_4(sc, BFE_SBTMSLOW);
823 /* Leave the clock set */
824 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
825 CSR_READ_4(sc, BFE_SBTMSLOW);
830 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
834 val = ((uint32_t) data[2]) << 24;
835 val |= ((uint32_t) data[3]) << 16;
836 val |= ((uint32_t) data[4]) << 8;
837 val |= ((uint32_t) data[5]);
838 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
839 val = (BFE_CAM_HI_VALID |
840 (((uint32_t) data[0]) << 8) |
841 (((uint32_t) data[1])));
842 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
843 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
844 (index << BFE_CAM_INDEX_SHIFT)));
845 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
849 bfe_set_rx_mode(struct bfe_softc *sc)
851 struct ifnet *ifp = &sc->arpcom.ac_if;
855 val = CSR_READ_4(sc, BFE_RXCONF);
857 if (ifp->if_flags & IFF_PROMISC)
858 val |= BFE_RXCONF_PROMISC;
860 val &= ~BFE_RXCONF_PROMISC;
862 if (ifp->if_flags & IFF_BROADCAST)
863 val &= ~BFE_RXCONF_DBCAST;
865 val |= BFE_RXCONF_DBCAST;
868 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
869 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
871 CSR_WRITE_4(sc, BFE_RXCONF, val);
872 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
876 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
881 *ptr = segs->ds_addr;
885 bfe_dma_map_desc(void *arg, bus_dma_segment_t *segs, int nseg, int error)
890 /* The chip needs all addresses to be added to BFE_PCI_DMA */
891 d->bfe_addr = segs->ds_addr + BFE_PCI_DMA;
895 bfe_release_resources(struct bfe_softc *sc)
902 if (sc->bfe_intrhand != NULL)
903 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
905 if (sc->bfe_irq != NULL)
906 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
908 if (sc->bfe_res != NULL)
909 bus_release_resource(dev, SYS_RES_MEMORY, 0x10, sc->bfe_res);
911 if (sc->bfe_tx_tag != NULL) {
912 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
913 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list, sc->bfe_tx_map);
914 bus_dma_tag_destroy(sc->bfe_tx_tag);
915 sc->bfe_tx_tag = NULL;
918 if (sc->bfe_rx_tag != NULL) {
919 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
920 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list, sc->bfe_rx_map);
921 bus_dma_tag_destroy(sc->bfe_rx_tag);
922 sc->bfe_rx_tag = NULL;
925 if (sc->bfe_tag != NULL) {
926 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
927 bus_dmamap_destroy(sc->bfe_tag,
928 sc->bfe_tx_ring[i].bfe_map);
930 bus_dma_tag_destroy(sc->bfe_tag);
934 if (sc->bfe_parent_tag != NULL)
935 bus_dma_tag_destroy(sc->bfe_parent_tag);
939 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
942 uint16_t *ptr = (uint16_t *)data;
944 for (i = 0; i < 128; i += 2)
945 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
949 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
950 u_long timeout, const int clear)
954 for (i = 0; i < timeout; i++) {
955 uint32_t val = CSR_READ_4(sc, reg);
957 if (clear && !(val & bit))
959 if (!clear && (val & bit))
964 printf("bfe%d: BUG! Timeout waiting for bit %08x of register "
965 "%x to %s.\n", sc->bfe_unit, bit, reg,
966 (clear ? "clear" : "set"));
973 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
980 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
981 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
982 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
983 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
984 (reg << BFE_MDIO_RA_SHIFT) |
985 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
986 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
987 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
994 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1000 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1001 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1002 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1003 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1004 (reg << BFE_MDIO_RA_SHIFT) |
1005 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1006 (val & BFE_MDIO_DATA_DATA)));
1007 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1015 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1019 bfe_setupphy(struct bfe_softc *sc)
1026 /* Enable activity LED */
1027 bfe_readphy(sc, 26, &val);
1028 bfe_writephy(sc, 26, val & 0x7fff);
1029 bfe_readphy(sc, 26, &val);
1031 /* Enable traffic meter LED mode */
1032 bfe_readphy(sc, 27, &val);
1033 bfe_writephy(sc, 27, val | (1 << 6));
1040 bfe_stats_update(struct bfe_softc *sc)
1045 val = &sc->bfe_hwstats.tx_good_octets;
1046 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1047 *val++ += CSR_READ_4(sc, reg);
1048 val = &sc->bfe_hwstats.rx_good_octets;
1049 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1050 *val++ += CSR_READ_4(sc, reg);
1054 bfe_txeof(struct bfe_softc *sc)
1058 uint32_t i, chipidx;
1062 ifp = &sc->arpcom.ac_if;
1064 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1065 chipidx /= sizeof(struct bfe_desc);
1067 i = sc->bfe_tx_cons;
1068 /* Go through the mbufs and free those that have been transmitted */
1069 while (i != chipidx) {
1070 struct bfe_data *r = &sc->bfe_tx_ring[i];
1071 if (r->bfe_mbuf != NULL) {
1073 m_freem(r->bfe_mbuf);
1075 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1078 BFE_INC(i, BFE_TX_LIST_CNT);
1081 if (i != sc->bfe_tx_cons) {
1082 /* we freed up some mbufs */
1083 sc->bfe_tx_cons = i;
1084 ifp->if_flags &= ~IFF_OACTIVE;
1086 if (sc->bfe_tx_cnt == 0)
1094 /* Pass a received packet up the stack */
1096 bfe_rxeof(struct bfe_softc *sc)
1100 struct bfe_rxheader *rxheader;
1102 uint32_t cons, status, current, len, flags;
1106 cons = sc->bfe_rx_cons;
1107 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1108 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1110 ifp = &sc->arpcom.ac_if;
1112 while (current != cons) {
1113 r = &sc->bfe_rx_ring[cons];
1115 rxheader = mtod(m, struct bfe_rxheader*);
1116 bus_dmamap_sync(sc->bfe_tag, r->bfe_map, BUS_DMASYNC_POSTWRITE);
1117 len = rxheader->len;
1120 bus_dmamap_unload(sc->bfe_tag, r->bfe_map);
1121 flags = rxheader->flags;
1123 len -= ETHER_CRC_LEN;
1125 /* flag an error and try again */
1126 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1128 if (flags & BFE_RX_FLAG_SERR)
1129 ifp->if_collisions++;
1130 bfe_list_newbuf(sc, cons, m);
1134 /* Go past the rx header */
1135 if (bfe_list_newbuf(sc, cons, NULL) == 0) {
1136 m_adj(m, BFE_RX_OFFSET);
1137 m->m_len = m->m_pkthdr.len = len;
1139 bfe_list_newbuf(sc, cons, m);
1145 m->m_pkthdr.rcvif = ifp;
1147 ether_input(ifp, NULL, m);
1148 BFE_INC(cons, BFE_RX_LIST_CNT);
1150 sc->bfe_rx_cons = cons;
1157 struct bfe_softc *sc = xsc;
1159 uint32_t istat, imask, flag;
1162 ifp = &sc->arpcom.ac_if;
1166 istat = CSR_READ_4(sc, BFE_ISTAT);
1167 imask = CSR_READ_4(sc, BFE_IMASK);
1170 * Defer unsolicited interrupts - This is necessary because setting the
1171 * chips interrupt mask register to 0 doesn't actually stop the
1175 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1176 CSR_READ_4(sc, BFE_ISTAT);
1178 /* not expecting this interrupt, disregard it */
1184 if (istat & BFE_ISTAT_ERRORS) {
1185 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1186 if (flag & BFE_STAT_EMASK)
1189 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1190 if (flag & BFE_RX_FLAG_ERRORS)
1193 ifp->if_flags &= ~IFF_RUNNING;
1197 /* A packet was received */
1198 if (istat & BFE_ISTAT_RX)
1201 /* A packet was sent */
1202 if (istat & BFE_ISTAT_TX)
1205 /* We have packets pending, fire them out */
1206 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1213 bfe_encap(struct bfe_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1215 struct bfe_desc *d = NULL;
1216 struct bfe_data *r = NULL;
1218 uint32_t frag, cur, cnt = 0;
1220 if (BFE_TX_LIST_CNT - sc->bfe_tx_cnt < 2)
1224 * Start packing the mbufs in this chain into
1225 * the fragment pointers. Stop when we run out
1226 * of fragments or hit the end of the mbuf chain.
1229 cur = frag = *txidx;
1232 for (m = m_head; m != NULL; m = m->m_next) {
1233 if (m->m_len != 0) {
1234 if ((BFE_TX_LIST_CNT - (sc->bfe_tx_cnt + cnt)) < 2)
1237 d = &sc->bfe_tx_list[cur];
1238 r = &sc->bfe_tx_ring[cur];
1239 d->bfe_ctrl = BFE_DESC_LEN & m->m_len;
1240 /* always intterupt on completion */
1241 d->bfe_ctrl |= BFE_DESC_IOC;
1243 /* Set start of frame */
1244 d->bfe_ctrl |= BFE_DESC_SOF;
1245 if (cur == BFE_TX_LIST_CNT - 1)
1247 * Tell the chip to wrap to the start of the
1250 d->bfe_ctrl |= BFE_DESC_EOT;
1252 bus_dmamap_load(sc->bfe_tag, r->bfe_map, mtod(m, void*),
1253 m->m_len, bfe_dma_map_desc, d, 0);
1254 bus_dmamap_sync(sc->bfe_tag, r->bfe_map,
1255 BUS_DMASYNC_PREREAD);
1258 BFE_INC(cur, BFE_TX_LIST_CNT);
1266 sc->bfe_tx_list[frag].bfe_ctrl |= BFE_DESC_EOF;
1267 sc->bfe_tx_ring[frag].bfe_mbuf = m_head;
1268 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map, BUS_DMASYNC_PREREAD);
1271 sc->bfe_tx_cnt += cnt;
1276 * Set up to transmit a packet
1279 bfe_start(struct ifnet *ifp)
1281 struct bfe_softc *sc;
1282 struct mbuf *m_head = NULL;
1287 idx = sc->bfe_tx_prod;
1292 * not much point trying to send if the link is down or we have nothing to
1295 if (!sc->bfe_link && ifp->if_snd.ifq_len < 10) {
1300 if (ifp->if_flags & IFF_OACTIVE) {
1305 while (sc->bfe_tx_ring[idx].bfe_mbuf == NULL) {
1306 IF_DEQUEUE(&ifp->if_snd, m_head);
1311 * Pack the data into the tx ring. If we dont have enough room, let
1312 * the chip drain the ring
1314 if (bfe_encap(sc, m_head, &idx)) {
1315 IF_PREPEND(&ifp->if_snd, m_head);
1316 ifp->if_flags |= IFF_OACTIVE;
1321 * If there's a BPF listener, bounce a copy of this frame
1324 BPF_MTAP(ifp, m_head);
1327 sc->bfe_tx_prod = idx;
1328 /* Transmit - twice due to apparent hardware bug */
1329 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1330 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1333 * Set a timeout in case the chip goes out to lunch.
1342 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1343 struct ifnet *ifp = &sc->arpcom.ac_if;
1348 if (ifp->if_flags & IFF_RUNNING) {
1356 if (bfe_list_rx_init(sc) == ENOBUFS) {
1357 printf("bfe%d: bfe_init failed. Not enough memory for list buffers\n",
1363 bfe_set_rx_mode(sc);
1365 /* Enable the chip and core */
1366 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1367 /* Enable interrupts */
1368 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1370 bfe_ifmedia_upd(ifp);
1371 ifp->if_flags |= IFF_RUNNING;
1372 ifp->if_flags &= ~IFF_OACTIVE;
1374 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1379 * Set media options.
1382 bfe_ifmedia_upd(struct ifnet *ifp)
1384 struct bfe_softc *sc;
1385 struct mii_data *mii;
1392 mii = device_get_softc(sc->bfe_miibus);
1394 if (mii->mii_instance) {
1395 struct mii_softc *miisc;
1396 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1397 miisc = LIST_NEXT(miisc, mii_list))
1398 mii_phy_reset(miisc);
1407 * Report current media status.
1410 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1412 struct bfe_softc *sc = ifp->if_softc;
1413 struct mii_data *mii;
1418 mii = device_get_softc(sc->bfe_miibus);
1420 ifmr->ifm_active = mii->mii_media_active;
1421 ifmr->ifm_status = mii->mii_media_status;
1427 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1429 struct bfe_softc *sc = ifp->if_softc;
1430 struct ifreq *ifr = (struct ifreq *) data;
1431 struct mii_data *mii;
1439 if (ifp->if_flags & IFF_UP)
1440 if (ifp->if_flags & IFF_RUNNING)
1441 bfe_set_rx_mode(sc);
1444 else if (ifp->if_flags & IFF_RUNNING)
1449 if (ifp->if_flags & IFF_RUNNING)
1450 bfe_set_rx_mode(sc);
1454 mii = device_get_softc(sc->bfe_miibus);
1455 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1461 error = ether_ioctl(ifp, command, data);
1474 bfe_watchdog(struct ifnet *ifp)
1476 struct bfe_softc *sc;
1483 printf("bfe%d: watchdog timeout -- resetting\n", sc->bfe_unit);
1485 ifp->if_flags &= ~IFF_RUNNING;
1496 struct bfe_softc *sc = xsc;
1497 struct mii_data *mii;
1505 mii = device_get_softc(sc->bfe_miibus);
1507 bfe_stats_update(sc);
1508 sc->bfe_stat_ch = timeout(bfe_tick, sc, hz);
1516 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1517 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1527 * Stop the adapter and free any mbufs allocated to the
1531 bfe_stop(struct bfe_softc *sc)
1538 untimeout(bfe_tick, sc, sc->bfe_stat_ch);
1540 ifp = &sc->arpcom.ac_if;
1543 bfe_tx_ring_free(sc);
1544 bfe_rx_ring_free(sc);
1546 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);