2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.9 2004/01/23 15:35:13 asmodai Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/mpipe.h>
40 #include <sys/devicestat.h>
43 #include <bus/pci/pcivar.h>
44 #include <machine/bus.h>
49 static void cyrix_timing(struct ata_channel *, int, int);
50 static void promise_timing(struct ata_channel *, int, int);
51 static void hpt_timing(struct ata_channel *, int, int);
52 static int hpt_cable80(struct ata_channel *);
57 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
59 #define ATAPI_DEVICE(ch, device) \
60 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
61 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
64 ata_dmaalloc(struct ata_channel *ch, int device, int flags)
68 KKASSERT(ch->dma_mpipe.max_count != 0);
69 dmatab = mpipe_alloc(&ch->dma_mpipe, flags);
70 KKASSERT(((uintptr_t)dmatab & PAGE_MASK) == 0);
75 ata_dmafree(struct ata_channel *ch, void *dmatab)
78 mpipe_free(&ch->dma_mpipe, dmatab);
82 ata_dmainit(struct ata_channel *ch, int device,
83 int apiomode, int wdmamode, int udmamode)
85 struct ata_device *atadev = &ch->device[ATA_DEV(device)];
86 device_t parent = device_get_parent(ch->dev);
87 int devno = (ch->unit << 1) + ATA_DEV(device);
90 /* set our most pessimistic default mode */
91 atadev->mode = ATA_PIO;
96 /* if simplex controller, only allow DMA on primary channel */
98 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
99 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
100 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
101 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
102 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
107 /* DMA engine address alignment is usually 1 word (2 bytes) */
111 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
112 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
116 switch (ch->chiptype) {
118 case 0x24db8086: /* Intel ICH5 */
119 case 0x24ca8086: /* Intel ICH4 mobile */
120 case 0x24cb8086: /* Intel ICH4 */
121 case 0x248a8086: /* Intel ICH3 mobile */
122 case 0x248b8086: /* Intel ICH3 */
123 case 0x244a8086: /* Intel ICH2 mobile */
124 case 0x244b8086: /* Intel ICH2 */
126 int32_t mask48, new48;
129 word54 = pci_read_config(parent, 0x54, 2);
130 if (word54 & (0x10 << devno)) {
131 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
132 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
134 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
135 (error) ? "failed" : "success");
137 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
138 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
139 pci_write_config(parent, 0x48,
140 (pci_read_config(parent, 0x48, 4) &
141 ~mask48) | new48, 4);
142 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
143 atadev->mode = ATA_UDMA5;
148 /* make sure eventual ATA100 mode from the BIOS is disabled */
149 pci_write_config(parent, 0x54,
150 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
153 case 0x24118086: /* Intel ICH */
154 case 0x76018086: /* Intel ICH */
156 int32_t mask48, new48;
159 word54 = pci_read_config(parent, 0x54, 2);
160 if (word54 & (0x10 << devno)) {
161 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
162 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
164 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
165 (error) ? "failed" : "success");
167 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
168 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
169 pci_write_config(parent, 0x48,
170 (pci_read_config(parent, 0x48, 4) &
171 ~mask48) | new48, 4);
172 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
173 atadev->mode = ATA_UDMA4;
178 /* make sure eventual ATA66 mode from the BIOS is disabled */
179 pci_write_config(parent, 0x54,
180 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
183 case 0x71118086: /* Intel PIIX4 */
184 case 0x84CA8086: /* Intel PIIX4 */
185 case 0x71998086: /* Intel PIIX4e */
186 case 0x24218086: /* Intel ICH0 */
188 int32_t mask48, new48;
190 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
191 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
193 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
194 (error) ? "failed" : "success");
196 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
197 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
198 pci_write_config(parent, 0x48,
199 (pci_read_config(parent, 0x48, 4) &
200 ~mask48) | new48, 4);
201 atadev->mode = ATA_UDMA2;
205 /* make sure eventual ATA33 mode from the BIOS is disabled */
206 pci_write_config(parent, 0x48,
207 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
210 case 0x70108086: /* Intel PIIX3 */
211 if (wdmamode >= 2 && apiomode >= 4) {
212 int32_t mask40, new40, mask44, new44;
214 /* if SITRE not set doit for both channels */
215 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
216 new40 = pci_read_config(parent, 0x40, 4);
217 new44 = pci_read_config(parent, 0x44, 4);
218 if (!(new40 & 0x00004000)) {
219 new44 &= ~0x0000000f;
220 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
222 if (!(new40 & 0x40000000)) {
223 new44 &= ~0x000000f0;
224 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
227 pci_write_config(parent, 0x40, new40, 4);
228 pci_write_config(parent, 0x44, new44, 4);
230 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
231 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
233 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
234 (error) ? "failed" : "success");
236 if (device == ATA_MASTER) {
254 pci_write_config(parent, 0x40,
255 (pci_read_config(parent, 0x40, 4) & ~mask40)|
257 pci_write_config(parent, 0x44,
258 (pci_read_config(parent, 0x44, 4) & ~mask44)|
260 atadev->mode = ATA_WDMA2;
264 /* we could set PIO mode timings, but we assume the BIOS did that */
267 case 0x12308086: /* Intel PIIX */
268 if (wdmamode >= 2 && apiomode >= 4) {
271 word40 = pci_read_config(parent, 0x40, 4);
272 word40 >>= ch->unit * 16;
274 /* Check for timing config usable for DMA on controller */
275 if (!((word40 & 0x3300) == 0x2300 &&
276 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
279 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
280 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
282 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
283 (error) ? "failed" : "success");
285 atadev->mode = ATA_WDMA2;
291 case 0x522910b9: /* AcerLabs Aladdin IV/V */
292 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
293 if (pci_get_revid(parent) < 0xc2 &&
294 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
295 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
298 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
299 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
300 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
302 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
303 (error) ? "failed" : "success");
305 int32_t word54 = pci_read_config(parent, 0x54, 4);
307 pci_write_config(parent, 0x4b,
308 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
309 word54 &= ~(0x000f000f << (devno << 2));
310 word54 |= (0x000f0005 << (devno << 2));
311 pci_write_config(parent, 0x54, word54, 4);
312 pci_write_config(parent, 0x53,
313 pci_read_config(parent, 0x53, 1) | 0x03, 1);
314 atadev->mode = ATA_UDMA5;
318 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
319 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
320 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
322 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
323 (error) ? "failed" : "success");
325 int32_t word54 = pci_read_config(parent, 0x54, 4);
327 pci_write_config(parent, 0x4b,
328 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
329 word54 &= ~(0x000f000f << (devno << 2));
330 word54 |= (0x00080005 << (devno << 2));
331 pci_write_config(parent, 0x54, word54, 4);
332 pci_write_config(parent, 0x53,
333 pci_read_config(parent, 0x53, 1) | 0x03, 1);
334 atadev->mode = ATA_UDMA4;
338 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
339 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
340 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
342 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
343 (error) ? "failed" : "success");
345 int32_t word54 = pci_read_config(parent, 0x54, 4);
347 word54 &= ~(0x000f000f << (devno << 2));
348 word54 |= (0x000a0005 << (devno << 2));
349 pci_write_config(parent, 0x54, word54, 4);
350 pci_write_config(parent, 0x53,
351 pci_read_config(parent, 0x53, 1) | 0x03, 1);
352 ch->flags |= ATA_ATAPI_DMA_RO;
353 atadev->mode = ATA_UDMA2;
358 /* make sure eventual UDMA mode from the BIOS is disabled */
359 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
360 ~(0x0008 << (devno << 2)), 2);
362 if (wdmamode >= 2 && apiomode >= 4) {
363 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
364 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
366 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
367 (error) ? "failed" : "success");
369 pci_write_config(parent, 0x53,
370 pci_read_config(parent, 0x53, 1) | 0x03, 1);
371 ch->flags |= ATA_ATAPI_DMA_RO;
372 atadev->mode = ATA_WDMA2;
376 pci_write_config(parent, 0x53,
377 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
378 /* we could set PIO mode timings, but we assume the BIOS did that */
381 case 0x01bc10de: /* NVIDIA nForce */
382 case 0x006510de: /* NVIDIA nForce2 */
383 case 0x74411022: /* AMD 768 */
384 case 0x74111022: /* AMD 766 */
385 case 0x74091022: /* AMD 756 */
386 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
388 int via_modes[5][7] = {
389 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */
390 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */
391 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */
392 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
393 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
397 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
398 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */
399 udmamode = imin(udmamode, 6);
400 reg_val = via_modes[3];
402 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
403 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
404 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
405 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
406 udmamode = imin(udmamode, 5);
407 reg_val = via_modes[2];
409 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
410 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
411 udmamode = imin(udmamode, 4);
412 reg_val = via_modes[1];
414 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
415 udmamode = imin(udmamode, 2);
416 reg_val = via_modes[1];
418 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
419 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
420 udmamode = imin(udmamode, 2);
421 reg_val = via_modes[0];
423 else if (ch->chiptype == 0x74411022 || /* AMD 768 */
424 ch->chiptype == 0x74111022) { /* AMD 766 */
425 udmamode = imin(udmamode, 5);
426 reg_val = via_modes[4];
429 else if (ch->chiptype == 0x74091022) { /* AMD 756 */
430 udmamode = imin(udmamode, 4);
431 reg_val = via_modes[4];
434 else if (ch->chiptype == 0x01bc10de) { /* nForce */
435 udmamode = imin(udmamode, 5);
436 reg_val = via_modes[4];
439 else if (ch->chiptype == 0x006510de) { /* nForce2 */
440 udmamode = imin(udmamode, 6);
441 reg_val = via_modes[4];
448 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
449 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
451 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
452 (error) ? "failed" : "success", chip);
454 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
455 atadev->mode = ATA_UDMA6;
460 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
461 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
463 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
464 (error) ? "failed" : "success", chip);
466 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
467 atadev->mode = ATA_UDMA5;
472 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
473 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
475 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
476 (error) ? "failed" : "success", chip);
478 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
479 atadev->mode = ATA_UDMA4;
484 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
485 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
487 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
488 (error) ? "failed" : "success", chip);
490 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
491 atadev->mode = ATA_UDMA2;
495 if (wdmamode >= 2 && apiomode >= 4) {
496 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
497 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
499 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
500 (error) ? "failed" : "success", chip);
502 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
503 pci_write_config(parent, 0x4b - devno, 0x31, 1);
504 atadev->mode = ATA_WDMA2;
509 /* we could set PIO mode timings, but we assume the BIOS did that */
512 case 0x55131039: /* SiS 5591 */
513 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
514 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
515 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
516 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
517 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
518 ata_find_dev(parent, 0x06461039, 0) || /* SiS 645DX */
519 ata_find_dev(parent, 0x06481039, 0) || /* SiS 648 */
520 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
521 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
522 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
523 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
524 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
525 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
526 ata_find_dev(parent, 0x07461039, 0) || /* SiS 746 */
527 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
528 int8_t reg = 0x40 + (devno << 1);
529 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
532 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
533 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
535 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
536 (error) ? "failed" : "success");
538 pci_write_config(parent, reg, val | 0x8000, 2);
539 atadev->mode = ATA_UDMA5;
544 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
545 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
547 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
548 (error) ? "failed" : "success");
550 pci_write_config(parent, reg, val | 0x9000, 2);
551 atadev->mode = ATA_UDMA4;
556 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
557 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
559 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
560 (error) ? "failed" : "success");
562 pci_write_config(parent, reg, val | 0xb000, 2);
563 atadev->mode = ATA_UDMA2;
567 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
568 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
569 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
570 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
571 int8_t reg = 0x40 + (devno << 1);
572 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
575 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
576 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
578 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
579 (error) ? "failed" : "success");
581 pci_write_config(parent, reg, val | 0x9000, 2);
582 atadev->mode = ATA_UDMA4;
587 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
588 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
590 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
591 (error) ? "failed" : "success");
593 pci_write_config(parent, reg, val | 0xa000, 2);
594 atadev->mode = ATA_UDMA2;
598 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
599 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
600 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
602 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
603 (error) ? "failed" : "success");
605 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
606 atadev->mode = ATA_UDMA2;
610 if (wdmamode >=2 && apiomode >= 4) {
611 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
612 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
614 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
615 (error) ? "failed" : "success");
617 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
618 atadev->mode = ATA_WDMA2;
622 /* we could set PIO mode timings, but we assume the BIOS did that */
625 case 0x06801095: /* SiI 0680 ATA133 controller */
627 u_int8_t ureg = 0xac + (ATA_DEV(device) * 0x02) + (ch->unit * 0x10);
628 u_int8_t uval = pci_read_config(parent, ureg, 1);
629 u_int8_t mreg = ch->unit ? 0x84 : 0x80;
630 u_int8_t mask = ATA_DEV(device) ? 0x30 : 0x03;
631 u_int8_t mode = pci_read_config(parent, mreg, 1);
633 /* enable UDMA mode */
634 pci_write_config(parent, mreg,
635 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
637 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
638 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
640 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
641 (error) ? "failed" : "success");
643 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1);
644 atadev->mode = ATA_UDMA6;
649 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
650 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
652 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
653 (error) ? "failed" : "success");
655 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1);
656 atadev->mode = ATA_UDMA5;
661 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
662 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
664 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
665 (error) ? "failed" : "success");
667 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1);
668 atadev->mode = ATA_UDMA4;
673 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
674 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
676 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
677 (error) ? "failed" : "success");
679 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1);
680 atadev->mode = ATA_UDMA2;
685 /* disable UDMA mode and enable WDMA mode */
686 pci_write_config(parent, mreg,
687 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
688 if (wdmamode >= 2 && apiomode >= 4) {
689 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
690 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
692 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
693 (error) ? "failed" : "success");
695 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
696 atadev->mode = ATA_WDMA2;
701 /* restore PIO mode */
702 pci_write_config(parent, mreg, mode, 1);
704 /* we could set PIO mode timings, but we assume the BIOS did that */
708 case 0x06491095: /* CMD 649 ATA100 controller */
712 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
713 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
715 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
716 (error) ? "failed" : "success");
718 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
719 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
720 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
721 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
722 atadev->mode = ATA_UDMA5;
728 case 0x06481095: /* CMD 648 ATA66 controller */
732 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
733 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
735 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
736 (error) ? "failed" : "success");
738 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
739 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
740 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
741 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
742 atadev->mode = ATA_UDMA4;
749 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
750 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
752 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
753 (error) ? "failed" : "success");
755 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
756 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
757 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
758 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
759 atadev->mode = ATA_UDMA2;
763 /* make sure eventual UDMA mode from the BIOS is disabled */
764 pci_write_config(parent, ch->unit ? 0x7b : 0x73,
765 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
766 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
769 case 0x06461095: /* CMD 646 ATA controller */
770 if (wdmamode >= 2 && apiomode >= 4) {
771 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
772 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
774 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
775 error ? "failed" : "success");
777 int32_t offset = (devno < 3) ? (devno << 1) : 7;
779 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
780 atadev->mode = ATA_WDMA2;
784 /* we could set PIO mode timings, but we assume the BIOS did that */
787 case 0xc6931080: /* Cypress 82c693 ATA controller */
788 if (wdmamode >= 2 && apiomode >= 4) {
789 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
790 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
792 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
793 error ? "failed" : "success");
795 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
796 atadev->mode = ATA_WDMA2;
800 /* we could set PIO mode timings, but we assume the BIOS did that */
803 case 0x01021078: /* Cyrix 5530 ATA33 controller */
804 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */
806 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
807 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
809 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
810 (error) ? "failed" : "success");
812 cyrix_timing(ch, devno, ATA_UDMA2);
813 atadev->mode = ATA_UDMA2;
817 if (wdmamode >= 2 && apiomode >= 4) {
818 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
819 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
821 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
822 (error) ? "failed" : "success");
824 cyrix_timing(ch, devno, ATA_WDMA2);
825 atadev->mode = ATA_WDMA2;
829 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
830 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
833 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
834 (error) ? "failed" : "success",
835 ata_mode2str(ATA_PIO0 + apiomode));
836 cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
837 atadev->mode = ATA_PIO0 + apiomode;
840 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
841 if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) {
842 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
843 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
845 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
846 (error) ? "failed" : "success");
850 pci_write_config(parent, 0x54,
851 pci_read_config(parent, 0x54, 1) |
853 reg56 = pci_read_config(parent, 0x56, 2);
854 reg56 &= ~(0xf << (devno * 4));
855 reg56 |= (0x5 << (devno * 4));
856 pci_write_config(parent, 0x56, reg56, 2);
857 atadev->mode = ATA_UDMA5;
862 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
863 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
865 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
866 (error) ? "failed" : "success");
870 pci_write_config(parent, 0x54,
871 pci_read_config(parent, 0x54, 1) |
873 reg56 = pci_read_config(parent, 0x56, 2);
874 reg56 &= ~(0xf << (devno * 4));
875 reg56 |= (0x4 << (devno * 4));
876 pci_write_config(parent, 0x56, reg56, 2);
877 atadev->mode = ATA_UDMA4;
883 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
885 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
886 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
888 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
889 (error) ? "failed" : "success");
893 pci_write_config(parent, 0x54,
894 pci_read_config(parent, 0x54, 1) |
896 reg56 = pci_read_config(parent, 0x56, 2);
897 reg56 &= ~(0xf << (devno * 4));
898 reg56 |= (0x2 << (devno * 4));
899 pci_write_config(parent, 0x56, reg56, 2);
900 atadev->mode = ATA_UDMA2;
904 if (wdmamode >= 2 && apiomode >= 4) {
905 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
906 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
908 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
909 (error) ? "failed" : "success");
911 int offset = (ch->unit * 2) + (device == ATA_MASTER);
912 int word44 = pci_read_config(parent, 0x44, 4);
914 pci_write_config(parent, 0x54,
915 pci_read_config(parent, 0x54, 1) &
916 ~(0x01 << devno), 1);
917 word44 &= ~(0xff << (offset << 8));
918 word44 |= (0x20 << (offset << 8));
919 pci_write_config(parent, 0x44, 0x20, 4);
920 atadev->mode = ATA_WDMA2;
924 /* we could set PIO mode timings, but we assume the BIOS did that */
927 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
928 case 0x5275105a: /* Promise TX2 ATA133 controllers */
929 case 0x6269105a: /* Promise TX2 ATA133 controllers */
930 case 0x7275105a: /* Promise TX2 ATA133 controllers */
931 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
932 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
933 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
934 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
936 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
937 (error) ? "failed" : "success");
939 atadev->mode = ATA_UDMA6;
945 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
946 case 0x6268105a: /* Promise TX2 ATA100 controllers */
947 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
948 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
949 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
950 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
952 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
953 (error) ? "failed" : "success");
955 atadev->mode = ATA_UDMA5;
959 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
960 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
961 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
962 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
964 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
965 (error) ? "failed" : "success");
967 atadev->mode = ATA_UDMA4;
972 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
973 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
975 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
976 (error) ? "failed" : "success");
978 atadev->mode = ATA_UDMA2;
982 if (wdmamode >= 2 && apiomode >= 4) {
983 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
984 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
986 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
987 (error) ? "failed" : "success");
989 atadev->mode = ATA_WDMA2;
995 case 0x0d30105a: /* Promise OEM ATA100 controllers */
996 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
997 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
998 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
999 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1000 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1002 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
1003 (error) ? "failed" : "success");
1005 promise_timing(ch, devno, ATA_UDMA5);
1006 atadev->mode = ATA_UDMA5;
1012 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1013 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1014 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
1015 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
1016 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1017 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1019 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1020 (error) ? "failed" : "success");
1022 promise_timing(ch, devno, ATA_UDMA4);
1023 atadev->mode = ATA_UDMA4;
1029 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1030 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1031 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1032 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1034 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1035 (error) ? "failed" : "success");
1037 promise_timing(ch, devno, ATA_UDMA2);
1038 atadev->mode = ATA_UDMA2;
1042 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1043 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1044 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1046 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1047 (error) ? "failed" : "success");
1049 promise_timing(ch, devno, ATA_WDMA2);
1050 atadev->mode = ATA_WDMA2;
1054 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1055 ATA_PIO0 + apiomode,
1056 ATA_C_F_SETXFER, ATA_WAIT_READY);
1058 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1059 (error) ? "failed" : "success",
1060 (apiomode >= 0) ? apiomode : 0);
1061 promise_timing(ch, devno, ATA_PIO0 + apiomode);
1062 atadev->mode = ATA_PIO0 + apiomode;
1065 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1066 case 0x00051103: /* HighPoint HPT372 controllers */
1067 case 0x00081103: /* HighPoint HPT374 controllers */
1068 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) &&
1069 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1070 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1071 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1072 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1073 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1075 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1076 (error) ? "failed" : "success");
1078 hpt_timing(ch, devno, ATA_UDMA6);
1079 atadev->mode = ATA_UDMA6;
1083 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) &&
1084 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) ||
1085 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1086 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1087 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1088 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1090 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1091 (error) ? "failed" : "success");
1093 hpt_timing(ch, devno, ATA_UDMA5);
1094 atadev->mode = ATA_UDMA5;
1098 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) {
1099 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1100 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1102 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1103 (error) ? "failed" : "success");
1105 hpt_timing(ch, devno, ATA_UDMA4);
1106 atadev->mode = ATA_UDMA4;
1110 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1111 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1112 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1114 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1115 (error) ? "failed" : "success");
1117 hpt_timing(ch, devno, ATA_UDMA2);
1118 atadev->mode = ATA_UDMA2;
1122 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1123 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1124 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1126 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1127 (error) ? "failed" : "success");
1129 hpt_timing(ch, devno, ATA_WDMA2);
1130 atadev->mode = ATA_WDMA2;
1134 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1135 ATA_PIO0 + apiomode,
1136 ATA_C_F_SETXFER, ATA_WAIT_READY);
1138 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1139 (error) ? "failed" : "success",
1140 (apiomode >= 0) ? apiomode : 0);
1141 hpt_timing(ch, devno, ATA_PIO0 + apiomode);
1142 atadev->mode = ATA_PIO0 + apiomode;
1145 case 0x000116ca: /* Cenatek Rocket Drive controller */
1146 if (wdmamode >= 0 &&
1147 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1148 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE)))
1149 atadev->mode = ATA_DMA;
1151 atadev->mode = ATA_PIO;
1154 default: /* unknown controller chip */
1155 /* better not try generic DMA on ATAPI devices it almost never works */
1156 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
1157 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
1160 /* if controller says its setup for DMA take the easy way out */
1161 /* the downside is we dont know what DMA mode we are in */
1162 if ((udmamode >= 0 || wdmamode >= 2) &&
1163 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1164 ((device==ATA_MASTER) ?
1165 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1166 atadev->mode = ATA_DMA;
1170 /* well, we have no support for this, but try anyways */
1171 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
1172 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1173 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1175 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1176 (error) ? "failed" : "success");
1178 atadev->mode = ATA_WDMA2;
1183 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1184 ATA_C_F_SETXFER, ATA_WAIT_READY);
1186 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1187 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1189 atadev->mode = ATA_PIO0 + apiomode;
1192 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1193 atadev->mode = ATA_PIO;
1198 ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
1199 caddr_t data, int32_t count)
1201 u_int32_t dma_count, dma_base;
1204 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1205 ata_printf(ch, device, "non aligned DMA transfer attempted\n");
1210 ata_printf(ch, device, "zero length DMA transfer attempted\n");
1214 dma_base = vtophys(data);
1215 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1220 dmatab[i].base = dma_base;
1221 dmatab[i].count = (dma_count & 0xffff);
1223 if (i >= ATA_DMA_ENTRIES) {
1224 ata_printf(ch, device, "too many segments in DMA table\n");
1227 dma_base = vtophys(data);
1228 dma_count = imin(count, PAGE_SIZE);
1229 data += imin(count, PAGE_SIZE);
1230 count -= imin(count, PAGE_SIZE);
1232 dmatab[i].base = dma_base;
1233 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1238 ata_dmastart(struct ata_channel *ch, int device,
1239 struct ata_dmaentry *dmatab, int dir)
1241 ch->flags |= ATA_DMA_ACTIVE;
1242 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1243 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1244 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1245 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1246 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1247 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1248 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1252 ata_dmadone(struct ata_channel *ch)
1256 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1257 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1258 ch->flags &= ~ATA_DMA_ACTIVE;
1259 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1260 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1261 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1262 return error & ATA_BMSTAT_MASK;
1266 ata_dmastatus(struct ata_channel *ch)
1268 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1272 cyrix_timing(struct ata_channel *ch, int devno, int mode)
1274 u_int32_t reg20 = 0x0000e132;
1275 u_int32_t reg24 = 0x00017771;
1278 case ATA_PIO0: reg20 = 0x0000e132; break;
1279 case ATA_PIO1: reg20 = 0x00018121; break;
1280 case ATA_PIO2: reg20 = 0x00024020; break;
1281 case ATA_PIO3: reg20 = 0x00032010; break;
1282 case ATA_PIO4: reg20 = 0x00040010; break;
1283 case ATA_WDMA2: reg24 = 0x00002020; break;
1284 case ATA_UDMA2: reg24 = 0x00911030; break;
1286 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
1287 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
1291 promise_timing(struct ata_channel *ch, int devno, int mode)
1293 u_int32_t timing = 0;
1294 struct promise_timing {
1296 u_int8_t prefetch:1;
1307 u_int8_t reserved:8;
1308 } *t = (struct promise_timing*)&timing;
1310 t->iordy = 1; t->iordyp = 1;
1311 if (mode >= ATA_DMA) {
1312 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1315 switch (ch->chiptype) {
1316 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1319 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1320 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1321 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1322 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1323 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1324 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1325 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1329 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1330 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1331 case 0x0d30105a: /* Promise OEM ATA 100 */
1334 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1335 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1336 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1337 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1338 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1339 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1340 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1341 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1342 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1346 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
1350 hpt_timing(struct ata_channel *ch, int devno, int mode)
1352 device_t parent = device_get_parent(ch->dev);
1355 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) {
1356 switch (mode) { /* HPT374 */
1357 case ATA_PIO0: timing = 0x0ac1f48a; break;
1358 case ATA_PIO1: timing = 0x0ac1f465; break;
1359 case ATA_PIO2: timing = 0x0a81f454; break;
1360 case ATA_PIO3: timing = 0x0a81f443; break;
1361 case ATA_PIO4: timing = 0x0a81f442; break;
1362 case ATA_WDMA2: timing = 0x22808242; break;
1363 case ATA_UDMA2: timing = 0x120c8242; break;
1364 case ATA_UDMA4: timing = 0x12ac8242; break;
1365 case ATA_UDMA5: timing = 0x12848242; break;
1366 case ATA_UDMA6: timing = 0x12808242; break;
1367 default: timing = 0x0d029d5e;
1370 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1371 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) {
1372 switch (mode) { /* HPT372 */
1373 case ATA_PIO0: timing = 0x0d029d5e; break;
1374 case ATA_PIO1: timing = 0x0d029d26; break;
1375 case ATA_PIO2: timing = 0x0c829ca6; break;
1376 case ATA_PIO3: timing = 0x0c829c84; break;
1377 case ATA_PIO4: timing = 0x0c829c62; break;
1378 case ATA_WDMA2: timing = 0x2c829262; break;
1379 case ATA_UDMA2: timing = 0x1c91dc62; break;
1380 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1381 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1382 case ATA_UDMA6: timing = 0x1c81dc62; break;
1383 default: timing = 0x0d029d5e;
1386 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) {
1387 switch (mode) { /* HPT370 */
1388 case ATA_PIO0: timing = 0x06914e57; break;
1389 case ATA_PIO1: timing = 0x06914e43; break;
1390 case ATA_PIO2: timing = 0x06514e33; break;
1391 case ATA_PIO3: timing = 0x06514e22; break;
1392 case ATA_PIO4: timing = 0x06514e21; break;
1393 case ATA_WDMA2: timing = 0x26514e21; break;
1394 case ATA_UDMA2: timing = 0x16494e31; break;
1395 case ATA_UDMA4: timing = 0x16454e31; break;
1396 case ATA_UDMA5: timing = 0x16454e31; break;
1397 default: timing = 0x06514e57;
1399 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1401 else { /* HPT36[68] */
1402 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1403 case 0x85: /* 25Mhz */
1405 case ATA_PIO0: timing = 0x40d08585; break;
1406 case ATA_PIO1: timing = 0x40d08572; break;
1407 case ATA_PIO2: timing = 0x40ca8542; break;
1408 case ATA_PIO3: timing = 0x40ca8532; break;
1409 case ATA_PIO4: timing = 0x40ca8521; break;
1410 case ATA_WDMA2: timing = 0x20ca8521; break;
1411 case ATA_UDMA2: timing = 0x10cf8521; break;
1412 case ATA_UDMA4: timing = 0x10c98521; break;
1413 default: timing = 0x01208585;
1417 case 0xa7: /* 33MHz */
1419 case ATA_PIO0: timing = 0x40d0a7aa; break;
1420 case ATA_PIO1: timing = 0x40d0a7a3; break;
1421 case ATA_PIO2: timing = 0x40d0a753; break;
1422 case ATA_PIO3: timing = 0x40c8a742; break;
1423 case ATA_PIO4: timing = 0x40c8a731; break;
1424 case ATA_WDMA2: timing = 0x20c8a731; break;
1425 case ATA_UDMA2: timing = 0x10caa731; break;
1426 case ATA_UDMA4: timing = 0x10c9a731; break;
1427 default: timing = 0x0120a7a7;
1430 case 0xd9: /* 40Mhz */
1432 case ATA_PIO0: timing = 0x4018d9d9; break;
1433 case ATA_PIO1: timing = 0x4010d9c7; break;
1434 case ATA_PIO2: timing = 0x4010d997; break;
1435 case ATA_PIO3: timing = 0x4010d974; break;
1436 case ATA_PIO4: timing = 0x4008d963; break;
1437 case ATA_WDMA2: timing = 0x2008d943; break;
1438 case ATA_UDMA2: timing = 0x100bd943; break;
1439 case ATA_UDMA4: timing = 0x100fd943; break;
1440 default: timing = 0x0120d9d9;
1444 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1448 hpt_cable80(struct ata_channel *ch)
1450 device_t parent = device_get_parent(ch->dev);
1451 u_int8_t reg, val, res;
1453 if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1454 reg = ch->unit ? 0x57 : 0x53;
1455 val = pci_read_config(parent, reg, 1);
1456 pci_write_config(parent, reg, val | 0x80, 1);
1460 val = pci_read_config(parent, reg, 1);
1461 pci_write_config(parent, reg, val & 0xfe, 1);
1463 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02);
1464 pci_write_config(parent, reg, val, 1);