2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
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14 * similar Disclaimer requirement for further binary redistribution.
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19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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33 * Defintions for the Atheros Wireless LAN controller driver.
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
38 #include <machine/atomic.h>
40 #include <dev/ath/ath_hal/ah.h>
41 #include <dev/ath/ath_hal/ah_desc.h>
42 #include <net80211/ieee80211_radiotap.h>
43 #include <dev/ath/if_athioctl.h>
44 #include <dev/ath/if_athrate.h>
46 #include <dev/ath/if_ath_alq.h>
49 #define ATH_TIMEOUT 1000
52 * There is a separate TX ath_buf pool for management frames.
53 * This ensures that management frames such as probe responses
54 * and BAR frames can be transmitted during periods of high
57 #define ATH_MGMT_TXBUF 32
60 * 802.11n requires more TX and RX buffers to do AMPDU.
68 #define ATH_RXBUF 40 /* number of RX buffers */
71 #define ATH_TXBUF 200 /* number of TX buffers */
73 #define ATH_BCBUF 4 /* number of beacon buffers */
75 #define ATH_TXDESC 10 /* number of descriptors per buffer */
76 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
77 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
78 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
80 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */
81 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
82 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
85 * The following bits can be set during the PCI (and perhaps non-PCI
86 * later) device probe path.
88 * It controls some of the driver and HAL behaviour.
91 #define ATH_PCI_CUS198 0x0001
92 #define ATH_PCI_CUS230 0x0002
93 #define ATH_PCI_CUS217 0x0004
94 #define ATH_PCI_CUS252 0x0008
95 #define ATH_PCI_WOW 0x0010
96 #define ATH_PCI_BT_ANT_DIV 0x0020
97 #define ATH_PCI_D3_L1_WAR 0x0040
98 #define ATH_PCI_AR9565_1ANT 0x0080
99 #define ATH_PCI_AR9565_2ANT 0x0100
100 #define ATH_PCI_NO_PLL_PWRSAVE 0x0200
101 #define ATH_PCI_KILLER 0x0400
104 * The key cache is used for h/w cipher state and also for
105 * tracking station state such as the current tx antenna.
106 * We also setup a mapping table between key cache slot indices
107 * and station state to short-circuit node lookups on rx.
108 * Different parts have different size key caches. We handle
109 * up to ATH_KEYMAX entries (could dynamically allocate state).
111 #define ATH_KEYMAX 128 /* max key cache size we handle */
112 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
118 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX)
123 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
126 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */
127 struct ath_node *an; /* pointer to parent */
129 int ac; /* which AC gets this traffic */
130 int hwq_depth; /* how many buffers are on HW */
131 u_int axq_depth; /* SW queue depth */
134 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */
135 u_int axq_depth; /* SW queue depth */
139 * Entry on the ath_txq; when there's traffic
142 TAILQ_ENTRY(ath_tid) axq_qelem;
144 int paused; /* >0 if the TID has been paused */
147 * These are flags - perhaps later collapse
148 * down to a single uint32_t ?
150 int addba_tx_pending; /* TX ADDBA pending */
151 int bar_wait; /* waiting for BAR */
152 int bar_tx; /* BAR TXed */
153 int isfiltered; /* is this node currently filtered */
156 * Is the TID being cleaned up after a transition
157 * from aggregation to non-aggregation?
158 * When this is set to 1, this TID will be paused
159 * and no further traffic will be queued until all
160 * the hardware packets pending for this TID have been
161 * TXed/completed; at which point (non-aggregation)
162 * traffic will resume being TXed.
164 int cleanup_inprogress;
166 * How many hardware-queued packets are
167 * waiting to be cleaned up.
168 * This is only valid if cleanup_inprogress is 1.
173 * The following implements a ring representing
174 * the frames in the current BAW.
175 * To avoid copying the array content each time
176 * the BAW is moved, the baw_head/baw_tail point
177 * to the current BAW begin/end; when the BAW is
178 * shifted the head/tail of the array are also
179 * appropriately shifted.
181 /* active tx buffers, beginning at current BAW */
182 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
183 /* where the baw head is in the array */
185 /* where the BAW tail is in the array */
189 /* driver-specific node state */
191 struct ieee80211_node an_node; /* base class */
192 u_int8_t an_mgmtrix; /* min h/w rate index */
193 u_int8_t an_mcastrix; /* mcast h/w rate index */
194 uint32_t an_is_powersave; /* node is sleeping */
195 uint32_t an_stack_psq; /* net80211 psq isn't empty */
196 uint32_t an_tim_set; /* TIM has been set */
197 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */
198 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */
199 char an_name[32]; /* eg "wlan0_a1" */
200 struct mtx an_mtx; /* protecting the rate control state */
201 uint32_t an_swq_depth; /* how many SWQ packets for this
203 int clrdmask; /* has clrdmask been set */
204 uint32_t an_leak_count; /* How many frames to leak during pause */
205 /* variable-length rate control state follows */
207 #define ATH_NODE(ni) ((struct ath_node *)(ni))
208 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
210 #define ATH_RSSI_LPF_LEN 10
211 #define ATH_RSSI_DUMMY_MARKER 0x127
212 #define ATH_EP_MUL(x, mul) ((x) * (mul))
213 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
214 #define ATH_LPF_RSSI(x, y, len) \
215 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
216 #define ATH_RSSI_LPF(x, y) do { \
218 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
220 #define ATH_EP_RND(x,mul) \
221 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
222 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
225 ATH_BUFTYPE_NORMAL = 0,
226 ATH_BUFTYPE_MGMT = 1,
230 TAILQ_ENTRY(ath_buf) bf_list;
231 struct ath_buf * bf_next; /* next buffer in the aggregate */
233 HAL_STATUS bf_rxstatus;
234 uint16_t bf_flags; /* status flags (below) */
235 uint16_t bf_descid; /* 16 bit descriptor ID */
236 struct ath_desc *bf_desc; /* virtual addr of desc */
237 struct ath_desc_status bf_status; /* tx/rx status */
238 bus_addr_t bf_daddr; /* physical addr of desc */
239 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
240 struct mbuf *bf_m; /* mbuf for buf */
241 struct ieee80211_node *bf_node; /* pointer to the node */
242 struct ath_desc *bf_lastds; /* last descriptor for comp status */
243 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */
244 bus_size_t bf_mapsize;
245 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
246 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
247 uint32_t bf_nextfraglen; /* length of next fragment */
249 /* Completion function to call on TX complete (fail or not) */
251 * "fail" here is set to 1 if the queue entries were removed
252 * through a call to ath_tx_draintxq().
254 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail);
256 /* This state is kept to support software retries and aggregation */
258 uint16_t bfs_seqno; /* sequence number of this packet */
259 uint16_t bfs_ndelim; /* number of delims for padding */
261 uint8_t bfs_retries; /* retry count */
262 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */
263 uint8_t bfs_nframes; /* number of frames in aggregate */
264 uint8_t bfs_pri; /* packet AC priority */
265 uint8_t bfs_tx_queue; /* destination hardware TX queue */
267 u_int32_t bfs_aggr:1, /* part of aggregate? */
268 bfs_aggrburst:1, /* part of aggregate burst? */
269 bfs_isretried:1, /* retried frame? */
270 bfs_dobaw:1, /* actually check against BAW? */
271 bfs_addedbaw:1, /* has been added to the BAW */
272 bfs_shpream:1, /* use short preamble */
273 bfs_istxfrag:1, /* is fragmented */
274 bfs_ismrr:1, /* do multi-rate TX retry */
275 bfs_doprot:1, /* do RTS/CTS based protection */
276 bfs_doratelookup:1; /* do rate lookup before each TX */
279 * These fields are passed into the
280 * descriptor setup functions.
283 /* Make this an 8 bit value? */
284 HAL_PKT_TYPE bfs_atype; /* packet type */
286 uint32_t bfs_pktlen; /* length of this packet */
288 uint16_t bfs_hdrlen; /* length of this packet header */
289 uint16_t bfs_al; /* length of aggregate */
291 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */
292 uint8_t bfs_txrate0; /* first TX rate */
293 uint8_t bfs_try0; /* first try count */
295 uint16_t bfs_txpower; /* tx power */
296 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */
297 uint8_t bfs_ctsrate; /* CTS rate */
300 int32_t bfs_keyix; /* crypto key index */
301 int32_t bfs_txantenna; /* TX antenna config */
303 /* Make this an 8 bit value? */
304 enum ieee80211_protmode bfs_protmode;
307 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */
308 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */
311 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead;
313 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */
314 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */
315 #define ATH_BUF_FIFOEND 0x00000004
316 #define ATH_BUF_FIFOPTR 0x00000008
318 #define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT)
321 * DMA state for tx/rx descriptors.
325 struct ath_desc *dd_desc; /* descriptors */
326 int dd_descsize; /* size of single descriptor */
327 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
328 bus_size_t dd_desc_len; /* size of dd_desc */
329 bus_dma_segment_t dd_dseg;
330 bus_dma_tag_t dd_dmat; /* bus DMA tag */
331 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
332 struct ath_buf *dd_bufptr; /* associated buffers */
336 * Data transmit queue state. One of these exists for each
337 * hardware transmit queue. Packets sent to us from above
338 * are assigned to queues based on their priority. Not all
339 * devices support a complete set of hardware transmit queues.
340 * For those devices the array sc_ac2q will map multiple
341 * priorities to fewer hardware queues (typically all to one
345 struct ath_softc *axq_softc; /* Needed for scheduling */
346 u_int axq_qnum; /* hardware q number */
347 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */
348 u_int axq_ac; /* WME AC */
350 //#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */
351 #define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */
352 u_int axq_depth; /* queue depth (stat only) */
353 u_int axq_aggr_depth; /* how many aggregates are queued */
354 u_int axq_intrcnt; /* interrupt count */
355 u_int32_t *axq_link; /* link ptr in last TX desc */
356 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */
357 struct mtx axq_lock; /* lock on q and link */
360 * This is the FIFO staging buffer when doing EDMA.
362 * For legacy chips, we just push the head pointer to
363 * the hardware and we ignore this list.
365 * For EDMA, the staging buffer is treated as normal;
366 * when it's time to push a list of frames to the hardware
367 * we move that list here and we stamp buffers with
368 * flags to identify the beginning/end of that particular
372 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q;
375 u_int axq_fifo_depth; /* depth of FIFO frames */
378 * XXX the holdingbf field is protected by the TXBUF lock
379 * for now, NOT the TXQ lock.
381 * Architecturally, it would likely be better to move
382 * the holdingbf field to a separate array in ath_softc
383 * just to highlight that it's not protected by the normal
386 struct ath_buf *axq_holdingbf; /* holding TX buffer */
387 char axq_name[12]; /* e.g. "ath0_txq4" */
389 /* Per-TID traffic queue for software -> hardware TX */
391 * This is protected by the general TX path lock, not (for now)
394 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq;
397 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
398 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
399 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
400 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
402 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
403 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
404 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
405 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
406 #define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \
410 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx)
411 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx)
412 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED)
413 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \
417 * These are for the hardware queue.
419 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
420 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
421 (_tq)->axq_depth++; \
423 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
424 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
425 (_tq)->axq_depth++; \
427 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
428 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
429 (_tq)->axq_depth--; \
431 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q)
432 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field)
435 * These are for the TID software queue.
437 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \
438 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
439 (_tq)->axq_depth++; \
440 (_tq)->an->an_swq_depth++; \
442 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \
443 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
444 (_tq)->axq_depth++; \
445 (_tq)->an->an_swq_depth++; \
447 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \
448 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
449 (_tq)->axq_depth--; \
450 (_tq)->an->an_swq_depth--; \
452 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q)
453 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field)
456 * These are for the TID filtered frame queue
458 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \
459 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
460 (_tq)->axq_depth++; \
461 (_tq)->an->an_swq_depth++; \
463 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \
464 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
465 (_tq)->axq_depth++; \
466 (_tq)->an->an_swq_depth++; \
468 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \
469 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
470 (_tq)->axq_depth--; \
471 (_tq)->an->an_swq_depth--; \
473 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q)
474 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
477 struct ieee80211vap av_vap; /* base class */
478 int av_bslot; /* beacon slot index */
479 struct ath_buf *av_bcbuf; /* beacon buffer */
480 struct ath_txq av_mcastq; /* buffered mcast s/w queue */
482 void (*av_recv_mgmt)(struct ieee80211_node *,
484 const struct ieee80211_rx_stats *, int, int);
485 int (*av_newstate)(struct ieee80211vap *,
486 enum ieee80211_state, int);
487 void (*av_bmiss)(struct ieee80211vap *);
488 void (*av_node_ps)(struct ieee80211_node *, int);
489 int (*av_set_tim)(struct ieee80211_node *, int);
490 void (*av_recv_pspoll)(struct ieee80211_node *,
493 #define ATH_VAP(vap) ((struct ath_vap *)(vap))
499 * Whether to reset the TX/RX queue with or without
503 ATH_RESET_DEFAULT = 0,
504 ATH_RESET_NOLOSS = 1,
508 struct ath_rx_methods {
509 void (*recv_sched_queue)(struct ath_softc *sc,
510 HAL_RX_QUEUE q, int dosched);
511 void (*recv_sched)(struct ath_softc *sc, int dosched);
512 void (*recv_stop)(struct ath_softc *sc, int dodelay);
513 int (*recv_start)(struct ath_softc *sc);
514 void (*recv_flush)(struct ath_softc *sc);
515 void (*recv_tasklet)(void *arg, int npending);
516 int (*recv_rxbuf_init)(struct ath_softc *sc,
518 int (*recv_setup)(struct ath_softc *sc);
519 int (*recv_teardown)(struct ath_softc *sc);
523 * Represent the current state of the RX FIFO.
526 struct ath_buf **m_fifo;
531 struct mbuf *m_rxpending;
532 struct ath_buf *m_holdbf;
535 struct ath_tx_edma_fifo {
536 struct ath_buf **m_fifo;
543 struct ath_tx_methods {
544 int (*xmit_setup)(struct ath_softc *sc);
545 int (*xmit_teardown)(struct ath_softc *sc);
546 void (*xmit_attach_comp_func)(struct ath_softc *sc);
548 void (*xmit_dma_restart)(struct ath_softc *sc,
549 struct ath_txq *txq);
550 void (*xmit_handoff)(struct ath_softc *sc,
551 struct ath_txq *txq, struct ath_buf *bf);
552 void (*xmit_drain)(struct ath_softc *sc,
553 ATH_RESET_TYPE reset_type);
557 struct ieee80211com sc_ic;
558 struct ath_stats sc_stats; /* device statistics */
559 struct ath_tx_aggr_stats sc_aggr_stats;
560 struct ath_intr_stats sc_intr_stats;
562 uint64_t sc_ktrdebug;
563 int sc_nvaps; /* # vaps */
564 int sc_nstavaps; /* # station vaps */
565 int sc_nmeshvaps; /* # mbss vaps */
566 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
567 u_int8_t sc_nbssid0; /* # vap's using base mac */
568 uint32_t sc_bssidmask; /* bssid mask */
570 struct ath_rx_methods sc_rx;
571 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */
572 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */
573 struct ath_tx_methods sc_tx;
574 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES];
577 * This is (currently) protected by the TX queue lock;
578 * it should migrate to a separate lock later
579 * so as to minimise contention.
581 ath_bufhead sc_txbuf_list;
586 int sc_tx_nmaps; /* Number of TX maps */
588 int sc_rx_stopped; /* XXX only for EDMA */
589 int sc_rx_resetted; /* XXX only for EDMA */
591 void (*sc_node_cleanup)(struct ieee80211_node *);
592 void (*sc_node_free)(struct ieee80211_node *);
594 HAL_BUS_TAG sc_st; /* bus space tag */
595 HAL_BUS_HANDLE sc_sh; /* bus space handle */
596 bus_dma_tag_t sc_dmat; /* bus DMA tag */
597 struct mtx sc_mtx; /* master lock (recursive) */
598 struct mtx sc_pcu_mtx; /* PCU access mutex */
599 char sc_pcu_mtx_name[32];
600 struct mtx sc_rx_mtx; /* RX access mutex */
601 char sc_rx_mtx_name[32];
602 struct mtx sc_tx_mtx; /* TX handling/comp mutex */
603 char sc_tx_mtx_name[32];
604 struct mtx sc_tx_ic_mtx; /* TX queue mutex */
605 char sc_tx_ic_mtx_name[32];
606 struct taskqueue *sc_tq; /* private task queue */
607 struct ath_hal *sc_ah; /* Atheros HAL */
608 struct ath_ratectrl *sc_rc; /* tx rate control support */
609 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
610 void (*sc_setdefantenna)(struct ath_softc *, u_int);
613 * First set of flags.
615 uint32_t sc_invalid : 1,/* disable hardware accesses */
616 sc_mrretry : 1,/* multi-rate retry support */
617 sc_mrrprot : 1,/* MRR + protection support */
618 sc_softled : 1,/* enable LED gpio status */
619 sc_hardled : 1,/* enable MAC LED status */
620 sc_splitmic : 1,/* split TKIP MIC keys */
621 sc_needmib : 1,/* enable MIB stats intr */
622 sc_diversity: 1,/* enable rx diversity */
623 sc_hasveol : 1,/* tx VEOL support */
624 sc_ledstate : 1,/* LED on/off state */
625 sc_blinking : 1,/* LED blink operation active */
626 sc_mcastkey : 1,/* mcast key cache search */
627 sc_scanning : 1,/* scanning active */
628 sc_syncbeacon:1,/* sync/resync beacon timers */
629 sc_hasclrkey: 1,/* CLR key supported */
630 sc_xchanmode: 1,/* extended channel mode */
631 sc_outdoor : 1,/* outdoor operation */
632 sc_dturbo : 1,/* dynamic turbo in use */
633 sc_hasbmask : 1,/* bssid mask support */
634 sc_hasbmatch: 1,/* bssid match disable support*/
635 sc_hastsfadd: 1,/* tsf adjust support */
636 sc_beacons : 1,/* beacons running */
637 sc_swbmiss : 1,/* sta mode using sw bmiss */
638 sc_stagbeacons:1,/* use staggered beacons */
639 sc_wmetkipmic:1,/* can do WME+TKIP MIC */
640 sc_resume_up: 1,/* on resume, start all vaps */
641 sc_tdma : 1,/* TDMA in use */
642 sc_setcca : 1,/* set/clr CCA with TDMA */
643 sc_resetcal : 1,/* reset cal state next trip */
644 sc_rxslink : 1,/* do self-linked final descriptor */
645 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */
646 sc_isedma : 1,/* supports EDMA */
647 sc_do_mybeacon : 1; /* supports mybeacon */
650 * Second set of flags.
652 u_int32_t sc_running : 1, /* initialized */
657 sc_hasenforcetxop : 1, /* support enforce TxOP */
658 sc_hasdivcomb : 1, /* RX diversity combining */
659 sc_rx_lnamixer : 1; /* RX using LNA mixing */
661 int sc_cabq_enable; /* Enable cabq transmission */
664 * Enterprise mode configuration for AR9380 and later chipsets.
668 uint32_t sc_eerd; /* regdomain from EEPROM */
669 uint32_t sc_eecc; /* country code from EEPROM */
671 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
672 const HAL_RATE_TABLE *sc_currates; /* current rate table */
673 enum ieee80211_phymode sc_curmode; /* current phy mode */
674 HAL_OPMODE sc_opmode; /* current operating mode */
675 u_int16_t sc_curtxpow; /* current tx power limit */
676 u_int16_t sc_curaid; /* current association id */
677 struct ieee80211_channel *sc_curchan; /* current installed channel */
678 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
679 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
681 u_int8_t ieeerate; /* IEEE rate */
682 u_int8_t rxflags; /* radiotap rx flags */
683 u_int8_t txflags; /* radiotap tx flags */
684 u_int16_t ledon; /* softled on time */
685 u_int16_t ledoff; /* softled off time */
686 } sc_hwmap[32]; /* h/w rate ix mappings */
687 u_int8_t sc_protrix; /* protection rate index */
688 u_int8_t sc_lastdatarix; /* last data frame rate index */
689 u_int sc_mcastrate; /* ieee rate for mcastrateix */
690 u_int sc_fftxqmin; /* min frames before staging */
691 u_int sc_fftxqmax; /* max frames before drop */
692 u_int sc_txantenna; /* tx antenna (fixed or auto) */
694 HAL_INT sc_imask; /* interrupt mask copy */
697 * These are modified in the interrupt handler as well as
698 * the task queues and other contexts. Thus these must be
699 * protected by a mutex, or they could clash.
701 * For now, access to these is behind the ATH_LOCK,
704 uint32_t sc_txq_active; /* bitmap of active TXQs */
705 uint32_t sc_kickpcu; /* whether to kick the PCU */
706 uint32_t sc_rxproc_cnt; /* In RX processing */
707 uint32_t sc_txproc_cnt; /* In TX processing */
708 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */
709 uint32_t sc_inreset_cnt; /* In active reset/chanchange */
710 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */
711 uint32_t sc_intr_cnt; /* refcount on interrupt handling */
713 u_int sc_keymax; /* size of key cache */
714 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
717 * Software based LED blinking
719 u_int sc_ledpin; /* GPIO pin for driving LED */
720 u_int sc_ledon; /* pin setting for LED on */
721 u_int sc_ledidle; /* idle polling interval */
722 int sc_ledevent; /* time of last LED event */
723 u_int8_t sc_txrix; /* current tx rate for LED */
724 u_int16_t sc_ledoff; /* off time for current blink */
725 struct callout sc_ledtimer; /* led off timer */
728 * Hardware based LED blinking
730 int sc_led_pwr_pin; /* MAC power LED GPIO pin */
731 int sc_led_net_pin; /* MAC network LED GPIO pin */
733 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
734 u_int sc_rfsilentpol; /* pin setting for rfkill on */
736 struct ath_descdma sc_rxdma; /* RX descriptors */
737 ath_bufhead sc_rxbuf; /* receive buffer */
738 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
739 struct task sc_rxtask; /* rx int processing */
740 u_int8_t sc_defant; /* current default antenna */
741 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
742 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
743 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */
744 struct ath_rx_radiotap_header sc_rx_th;
746 u_int sc_monpass; /* frames to pass in mon.mode */
748 struct ath_descdma sc_txdma; /* TX descriptors */
749 uint16_t sc_txbuf_descid;
750 ath_bufhead sc_txbuf; /* transmit buffer */
751 int sc_txbuf_cnt; /* how many buffers avail */
752 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */
753 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */
754 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */
755 struct mtx sc_txbuflock; /* txbuf lock */
756 char sc_txname[12]; /* e.g. "ath0_buf" */
757 u_int sc_txqsetup; /* h/w queues setup */
758 u_int sc_txintrperiod;/* tx interrupt batching */
759 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
760 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
761 struct task sc_txtask; /* tx int processing */
762 struct task sc_txqtask; /* tx proc processing */
764 struct ath_descdma sc_txcompdma; /* TX EDMA completion */
765 struct mtx sc_txcomplock; /* TX EDMA completion lock */
766 char sc_txcompname[12]; /* eg ath0_txcomp */
768 int sc_wd_timer; /* count down for wd timer */
769 struct callout sc_wd_ch; /* tx watchdog timer */
770 struct ath_tx_radiotap_header sc_tx_th;
773 struct ath_descdma sc_bdma; /* beacon descriptors */
774 ath_bufhead sc_bbuf; /* beacon buffers */
775 u_int sc_bhalq; /* HAL q for outgoing beacons */
776 u_int sc_bmisscount; /* missed beacon transmits */
777 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
778 struct ath_txq *sc_cabq; /* tx q for cab frames */
779 struct task sc_bmisstask; /* bmiss int processing */
780 struct task sc_bstucktask; /* stuck beacon processing */
781 struct task sc_resettask; /* interface reset task */
782 struct task sc_fataltask; /* fatal task */
784 OK, /* no change needed */
785 UPDATE, /* update pending */
786 COMMIT /* beacon sent, commit change */
787 } sc_updateslot; /* slot time update fsm */
788 int sc_slotupdate; /* slot to advance fsm */
789 struct ieee80211vap *sc_bslot[ATH_BCBUF];
790 int sc_nbcnvaps; /* # vaps with beacons */
792 struct callout sc_cal_ch; /* callout handle for cals */
793 int sc_lastlongcal; /* last long cal completed */
794 int sc_lastcalreset;/* last cal reset done */
795 int sc_lastani; /* last ANI poll */
796 int sc_lastshortcal; /* last short calibration */
797 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */
798 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
799 u_int sc_tdmadbaprep; /* TDMA DBA prep time */
800 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */
801 u_int sc_tdmaswba; /* TDMA SWBA counter */
802 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */
803 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */
804 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */
805 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
806 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
807 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
808 uint32_t sc_txchainmask; /* hardware TX chainmask */
809 uint32_t sc_rxchainmask; /* hardware RX chainmask */
810 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */
811 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */
812 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */
813 int sc_aggr_limit; /* TX limit on all aggregates */
814 int sc_delim_min_pad; /* Minimum delimiter count */
819 * To avoid queue starvation in congested conditions,
820 * these parameters tune the maximum number of frames
821 * queued to the data/mcastq before they're dropped.
823 * This is to prevent:
824 * + a single destination overwhelming everything, including
825 * management/multicast frames;
826 * + multicast frames overwhelming everything (when the
827 * air is sufficiently busy that cabq can't drain.)
828 * + A node in powersave shouldn't be allowed to exhaust
829 * all available mbufs;
832 * + data_minfree is the maximum number of free buffers
833 * overall to successfully allow a data frame.
835 * + mcastq_maxdepth is the maximum depth allowed of the cabq.
837 int sc_txq_node_maxdepth;
838 int sc_txq_data_minfree;
839 int sc_txq_mcastq_maxdepth;
840 int sc_txq_node_psq_maxdepth;
843 * Software queue twiddles
846 * when to begin limiting non-aggregate frames to the
847 * hardware queue, regardless of the TID.
849 * when to begin limiting A-MPDU frames to the
850 * hardware queue, regardless of the TID.
851 * tid_hwq_lo: how low the per-TID hwq count has to be before the
852 * TID will be scheduled again
853 * tid_hwq_hi: how many frames to queue to the HWQ before the TID
854 * stops being scheduled.
856 int sc_hwq_limit_nonaggr;
857 int sc_hwq_limit_aggr;
861 /* DFS related state */
862 void *sc_dfs; /* Used by an optional DFS module */
863 int sc_dodfs; /* Whether to enable DFS rx filter bits */
864 struct task sc_dfstask; /* DFS processing task */
866 /* Spectral related state */
870 /* LNA diversity related state */
876 struct if_ath_alq sc_alq;
879 /* TX AMPDU handling */
880 int (*sc_addba_request)(struct ieee80211_node *,
881 struct ieee80211_tx_ampdu *, int, int, int);
882 int (*sc_addba_response)(struct ieee80211_node *,
883 struct ieee80211_tx_ampdu *, int, int, int);
884 void (*sc_addba_stop)(struct ieee80211_node *,
885 struct ieee80211_tx_ampdu *);
886 void (*sc_addba_response_timeout)
887 (struct ieee80211_node *,
888 struct ieee80211_tx_ampdu *);
889 void (*sc_bar_response)(struct ieee80211_node *ni,
890 struct ieee80211_tx_ampdu *tap,
894 * Powersave state tracking.
896 * target/cur powerstate is the chip power state.
897 * target selfgen state is the self-generated frames
898 * state. The chip can be awake but transmitted frames
899 * can have the PWRMGT bit set to 1 so the destination
900 * thinks the node is asleep.
902 HAL_POWER_MODE sc_target_powerstate;
903 HAL_POWER_MODE sc_target_selfgen_state;
905 HAL_POWER_MODE sc_cur_powerstate;
907 int sc_powersave_refcnt;
909 /* ATH_PCI_* flags */
910 uint32_t sc_pci_devinfo;
913 #define ATH_LOCK_INIT(_sc) \
914 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
915 NULL, MTX_DEF | MTX_RECURSE)
916 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
917 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
918 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
919 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
920 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
923 * The TX lock is non-reentrant and serialises the TX frame send
924 * and completion operations.
926 #define ATH_TX_LOCK_INIT(_sc) do {\
927 snprintf((_sc)->sc_tx_mtx_name, \
928 sizeof((_sc)->sc_tx_mtx_name), \
930 device_get_nameunit((_sc)->sc_dev)); \
931 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \
934 #define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx)
935 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx)
936 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx)
937 #define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
939 #define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
941 #define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \
942 mtx_trylock(&(_sc)->sc_tx_mtx))
945 * The PCU lock is non-recursive and should be treated as a spinlock.
946 * Although currently the interrupt code is run in netisr context and
947 * doesn't require this, this may change in the future.
948 * Please keep this in mind when protecting certain code paths
951 * The PCU lock is used to serialise access to the PCU so things such
952 * as TX, RX, state change (eg channel change), channel reset and updates
953 * from interrupt context (eg kickpcu, txqactive bits) do not clash.
955 * Although the current single-thread taskqueue mechanism protects the
956 * majority of these situations by simply serialising them, there are
957 * a few others which occur at the same time. These include the TX path
958 * (which only acquires ATH_LOCK when recycling buffers to the free list),
959 * ath_set_channel, the channel scanning API and perhaps quite a bit more.
961 #define ATH_PCU_LOCK_INIT(_sc) do {\
962 snprintf((_sc)->sc_pcu_mtx_name, \
963 sizeof((_sc)->sc_pcu_mtx_name), \
965 device_get_nameunit((_sc)->sc_dev)); \
966 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \
969 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx)
970 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx)
971 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx)
972 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
974 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
978 * The RX lock is primarily a(nother) workaround to ensure that the
979 * RX FIFO/list isn't modified by various execution paths.
980 * Even though RX occurs in a single context (the ath taskqueue), the
981 * RX path can be executed via various reset/channel change paths.
983 #define ATH_RX_LOCK_INIT(_sc) do {\
984 snprintf((_sc)->sc_rx_mtx_name, \
985 sizeof((_sc)->sc_rx_mtx_name), \
987 device_get_nameunit((_sc)->sc_dev)); \
988 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \
991 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx)
992 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx)
993 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx)
994 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
996 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
999 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
1001 #define ATH_TXBUF_LOCK_INIT(_sc) do { \
1002 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
1003 device_get_nameunit((_sc)->sc_dev)); \
1004 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
1006 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
1007 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
1008 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
1009 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
1010 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
1011 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) \
1012 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED)
1014 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \
1015 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \
1017 device_get_nameunit((_sc)->sc_dev)); \
1018 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \
1021 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock)
1022 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock)
1023 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock)
1024 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \
1025 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED)
1027 int ath_attach(u_int16_t, struct ath_softc *);
1028 int ath_detach(struct ath_softc *);
1029 void ath_resume(struct ath_softc *);
1030 void ath_suspend(struct ath_softc *);
1031 void ath_shutdown(struct ath_softc *);
1032 void ath_intr(void *);
1035 * HAL definitions to comply with local coding convention.
1037 #define ath_hal_detach(_ah) \
1038 ((*(_ah)->ah_detach)((_ah)))
1039 #define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \
1040 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \
1041 (_resettype), (_pstatus)))
1042 #define ath_hal_macversion(_ah) \
1043 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
1044 #define ath_hal_getratetable(_ah, _mode) \
1045 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
1046 #define ath_hal_getmac(_ah, _mac) \
1047 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
1048 #define ath_hal_setmac(_ah, _mac) \
1049 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
1050 #define ath_hal_getbssidmask(_ah, _mask) \
1051 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
1052 #define ath_hal_setbssidmask(_ah, _mask) \
1053 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
1054 #define ath_hal_intrset(_ah, _mask) \
1055 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
1056 #define ath_hal_intrget(_ah) \
1057 ((*(_ah)->ah_getInterrupts)((_ah)))
1058 #define ath_hal_intrpend(_ah) \
1059 ((*(_ah)->ah_isInterruptPending)((_ah)))
1060 #define ath_hal_getisr(_ah, _pmask) \
1061 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
1062 #define ath_hal_updatetxtriglevel(_ah, _inc) \
1063 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
1064 #define ath_hal_setpower(_ah, _mode) \
1065 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1066 #define ath_hal_setselfgenpower(_ah, _mode) \
1067 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE))
1068 #define ath_hal_keycachesize(_ah) \
1069 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
1070 #define ath_hal_keyreset(_ah, _ix) \
1071 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1072 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
1073 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1074 #define ath_hal_keyisvalid(_ah, _ix) \
1075 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1076 #define ath_hal_keysetmac(_ah, _ix, _mac) \
1077 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1078 #define ath_hal_getrxfilter(_ah) \
1079 ((*(_ah)->ah_getRxFilter)((_ah)))
1080 #define ath_hal_setrxfilter(_ah, _filter) \
1081 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1082 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
1083 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1084 #define ath_hal_waitforbeacon(_ah, _bf) \
1085 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
1086 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \
1087 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
1088 /* NB: common across all chips */
1089 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
1090 #define ath_hal_gettsf32(_ah) \
1091 OS_REG_READ(_ah, AR_TSF_L32)
1092 #define ath_hal_gettsf64(_ah) \
1093 ((*(_ah)->ah_getTsf64)((_ah)))
1094 #define ath_hal_settsf64(_ah, _val) \
1095 ((*(_ah)->ah_setTsf64)((_ah), (_val)))
1096 #define ath_hal_resettsf(_ah) \
1097 ((*(_ah)->ah_resetTsf)((_ah)))
1098 #define ath_hal_rxena(_ah) \
1099 ((*(_ah)->ah_enableReceive)((_ah)))
1100 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
1101 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1102 #define ath_hal_gettxbuf(_ah, _q) \
1103 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
1104 #define ath_hal_numtxpending(_ah, _q) \
1105 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
1106 #define ath_hal_getrxbuf(_ah, _rxq) \
1107 ((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
1108 #define ath_hal_txstart(_ah, _q) \
1109 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
1110 #define ath_hal_setchannel(_ah, _chan) \
1111 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
1112 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
1113 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
1114 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
1115 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1116 #define ath_hal_calreset(_ah, _chan) \
1117 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
1118 #define ath_hal_setledstate(_ah, _state) \
1119 ((*(_ah)->ah_setLedState)((_ah), (_state)))
1120 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
1121 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1122 #define ath_hal_beaconreset(_ah) \
1123 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
1124 #define ath_hal_beaconsettimers(_ah, _bt) \
1125 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
1126 #define ath_hal_beacontimers(_ah, _bs) \
1127 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
1128 #define ath_hal_getnexttbtt(_ah) \
1129 ((*(_ah)->ah_getNextTBTT)((_ah)))
1130 #define ath_hal_setassocid(_ah, _bss, _associd) \
1131 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1132 #define ath_hal_phydisable(_ah) \
1133 ((*(_ah)->ah_phyDisable)((_ah)))
1134 #define ath_hal_setopmode(_ah) \
1135 ((*(_ah)->ah_setPCUConfig)((_ah)))
1136 #define ath_hal_stoptxdma(_ah, _qnum) \
1137 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1138 #define ath_hal_stoppcurecv(_ah) \
1139 ((*(_ah)->ah_stopPcuReceive)((_ah)))
1140 #define ath_hal_startpcurecv(_ah) \
1141 ((*(_ah)->ah_startPcuReceive)((_ah)))
1142 #define ath_hal_stopdmarecv(_ah) \
1143 ((*(_ah)->ah_stopDmaReceive)((_ah)))
1144 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
1145 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
1146 (_indata), (_insize), (_outdata), (_outsize)))
1147 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
1148 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
1149 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
1150 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1151 #define ath_hal_resettxqueue(_ah, _q) \
1152 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1153 #define ath_hal_releasetxqueue(_ah, _q) \
1154 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1155 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
1156 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1157 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
1158 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
1159 /* NB: common across all chips */
1160 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
1161 #define ath_hal_txqenabled(_ah, _qnum) \
1162 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
1163 #define ath_hal_getrfgain(_ah) \
1164 ((*(_ah)->ah_getRfGain)((_ah)))
1165 #define ath_hal_getdefantenna(_ah) \
1166 ((*(_ah)->ah_getDefAntenna)((_ah)))
1167 #define ath_hal_setdefantenna(_ah, _ant) \
1168 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1169 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
1170 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
1171 #define ath_hal_ani_poll(_ah, _chan) \
1172 ((*(_ah)->ah_aniPoll)((_ah), (_chan)))
1173 #define ath_hal_mibevent(_ah, _stats) \
1174 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1175 #define ath_hal_setslottime(_ah, _us) \
1176 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1177 #define ath_hal_getslottime(_ah) \
1178 ((*(_ah)->ah_getSlotTime)((_ah)))
1179 #define ath_hal_setacktimeout(_ah, _us) \
1180 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1181 #define ath_hal_getacktimeout(_ah) \
1182 ((*(_ah)->ah_getAckTimeout)((_ah)))
1183 #define ath_hal_setctstimeout(_ah, _us) \
1184 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1185 #define ath_hal_getctstimeout(_ah) \
1186 ((*(_ah)->ah_getCTSTimeout)((_ah)))
1187 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
1188 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1189 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
1190 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1191 #define ath_hal_ciphersupported(_ah, _cipher) \
1192 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
1193 #define ath_hal_getregdomain(_ah, _prd) \
1194 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
1195 #define ath_hal_setregdomain(_ah, _rd) \
1196 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
1197 #define ath_hal_getcountrycode(_ah, _pcc) \
1198 (*(_pcc) = (_ah)->ah_countryCode)
1199 #define ath_hal_gettkipmic(_ah) \
1200 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
1201 #define ath_hal_settkipmic(_ah, _v) \
1202 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
1203 #define ath_hal_hastkipsplit(_ah) \
1204 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
1205 #define ath_hal_gettkipsplit(_ah) \
1206 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
1207 #define ath_hal_settkipsplit(_ah, _v) \
1208 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
1209 #define ath_hal_haswmetkipmic(_ah) \
1210 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
1211 #define ath_hal_hwphycounters(_ah) \
1212 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
1213 #define ath_hal_hasdiversity(_ah) \
1214 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
1215 #define ath_hal_getdiversity(_ah) \
1216 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
1217 #define ath_hal_setdiversity(_ah, _v) \
1218 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
1219 #define ath_hal_getantennaswitch(_ah) \
1220 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
1221 #define ath_hal_setantennaswitch(_ah, _v) \
1222 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
1223 #define ath_hal_getdiag(_ah, _pv) \
1224 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
1225 #define ath_hal_setdiag(_ah, _v) \
1226 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
1227 #define ath_hal_getnumtxqueues(_ah, _pv) \
1228 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
1229 #define ath_hal_hasveol(_ah) \
1230 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
1231 #define ath_hal_hastxpowlimit(_ah) \
1232 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
1233 #define ath_hal_settxpowlimit(_ah, _pow) \
1234 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1235 #define ath_hal_gettxpowlimit(_ah, _ppow) \
1236 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
1237 #define ath_hal_getmaxtxpow(_ah, _ppow) \
1238 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
1239 #define ath_hal_gettpscale(_ah, _scale) \
1240 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
1241 #define ath_hal_settpscale(_ah, _v) \
1242 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
1243 #define ath_hal_hastpc(_ah) \
1244 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
1245 #define ath_hal_gettpc(_ah) \
1246 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
1247 #define ath_hal_settpc(_ah, _v) \
1248 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
1249 #define ath_hal_hasbursting(_ah) \
1250 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
1251 #define ath_hal_setmcastkeysearch(_ah, _v) \
1252 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
1253 #define ath_hal_hasmcastkeysearch(_ah) \
1254 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
1255 #define ath_hal_getmcastkeysearch(_ah) \
1256 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
1257 #define ath_hal_hasfastframes(_ah) \
1258 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
1259 #define ath_hal_hasbssidmask(_ah) \
1260 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
1261 #define ath_hal_hasbssidmatch(_ah) \
1262 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
1263 #define ath_hal_hastsfadjust(_ah) \
1264 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
1265 #define ath_hal_gettsfadjust(_ah) \
1266 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
1267 #define ath_hal_settsfadjust(_ah, _onoff) \
1268 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
1269 #define ath_hal_hasrfsilent(_ah) \
1270 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
1271 #define ath_hal_getrfkill(_ah) \
1272 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
1273 #define ath_hal_setrfkill(_ah, _onoff) \
1274 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
1275 #define ath_hal_getrfsilent(_ah, _prfsilent) \
1276 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
1277 #define ath_hal_setrfsilent(_ah, _rfsilent) \
1278 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
1279 #define ath_hal_gettpack(_ah, _ptpack) \
1280 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
1281 #define ath_hal_settpack(_ah, _tpack) \
1282 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
1283 #define ath_hal_gettpcts(_ah, _ptpcts) \
1284 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
1285 #define ath_hal_settpcts(_ah, _tpcts) \
1286 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
1287 #define ath_hal_hasintmit(_ah) \
1288 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1289 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
1290 #define ath_hal_getintmit(_ah) \
1291 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1292 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
1293 #define ath_hal_setintmit(_ah, _v) \
1294 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
1295 HAL_CAP_INTMIT_ENABLE, _v, NULL)
1296 #define ath_hal_hasmybeacon(_ah) \
1297 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK)
1299 #define ath_hal_hasenforcetxop(_ah) \
1300 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK)
1301 #define ath_hal_getenforcetxop(_ah) \
1302 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK)
1303 #define ath_hal_setenforcetxop(_ah, _v) \
1304 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL)
1306 #define ath_hal_hasrxlnamixer(_ah) \
1307 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK)
1309 #define ath_hal_hasdivantcomb(_ah) \
1310 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK)
1311 #define ath_hal_hasldpc(_ah) \
1312 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK)
1313 #define ath_hal_hasldpcwar(_ah) \
1314 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK)
1316 /* EDMA definitions */
1317 #define ath_hal_hasedma(_ah) \
1318 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \
1320 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \
1321 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \
1323 #define ath_hal_getntxmaps(_ah, _req) \
1324 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \
1326 #define ath_hal_gettxdesclen(_ah, _req) \
1327 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \
1329 #define ath_hal_gettxstatuslen(_ah, _req) \
1330 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \
1332 #define ath_hal_getrxstatuslen(_ah, _req) \
1333 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \
1335 #define ath_hal_setrxbufsize(_ah, _req) \
1336 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \
1339 #define ath_hal_getchannoise(_ah, _c) \
1340 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
1342 /* 802.11n HAL methods */
1343 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \
1344 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
1345 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \
1346 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
1347 #define ath_hal_setrxchainmask(_ah, _rx) \
1348 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
1349 #define ath_hal_settxchainmask(_ah, _tx) \
1350 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
1351 #define ath_hal_split4ktrans(_ah) \
1352 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
1354 #define ath_hal_self_linked_final_rxdesc(_ah) \
1355 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
1357 #define ath_hal_gtxto_supported(_ah) \
1358 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
1359 #define ath_hal_has_long_rxdesc_tsf(_ah) \
1360 (ath_hal_getcapability(_ah, HAL_CAP_LONG_RXDESC_TSF, \
1362 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
1363 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
1364 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
1365 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
1366 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
1367 _txr0, _txtr0, _keyix, _ant, _flags, \
1368 _rtsrate, _rtsdura) \
1369 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1370 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
1371 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
1372 #define ath_hal_setupxtxdesc(_ah, _ds, \
1373 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
1374 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1375 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
1376 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \
1377 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1378 (_first), (_last), (_ds0)))
1379 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
1380 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
1381 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
1382 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
1383 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
1384 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1385 #define ath_hal_settxdesclink(_ah, _ds, _link) \
1386 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1387 #define ath_hal_gettxdesclink(_ah, _ds, _link) \
1388 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1389 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \
1390 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1391 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \
1392 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1394 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \
1395 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1397 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
1398 _txr0, _txtr0, _antm, _rcr, _rcd) \
1399 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1400 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
1401 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \
1402 _keyix, _cipher, _delims, _first, _last, _lastaggr) \
1403 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1404 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \
1405 (_first), (_last), (_lastaggr)))
1406 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
1407 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1409 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
1410 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1411 (_series), (_ns), (_flags)))
1413 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
1414 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1415 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \
1416 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1417 #define ath_hal_set11n_aggr_last(_ah, _ds) \
1418 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1420 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \
1421 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1422 #define ath_hal_clr11n_aggr(_ah, _ds) \
1423 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1424 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \
1425 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
1427 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
1428 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1429 #define ath_hal_gpioset(_ah, _gpio, _b) \
1430 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1431 #define ath_hal_gpioget(_ah, _gpio) \
1432 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1433 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
1434 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
1437 * PCIe suspend/resume/poweron/poweroff related macros
1439 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \
1440 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1441 #define ath_hal_disablepcie(_ah) \
1442 ((*(_ah)->ah_disablePCIE)((_ah)))
1445 * This is badly-named; you need to set the correct parameters
1446 * to begin to receive useful radar events; and even then
1447 * it doesn't "enable" DFS. See the ath_dfs/null/ module for
1450 #define ath_hal_enabledfs(_ah, _param) \
1451 ((*(_ah)->ah_enableDfs)((_ah), (_param)))
1452 #define ath_hal_getdfsthresh(_ah, _param) \
1453 ((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1454 #define ath_hal_getdfsdefaultthresh(_ah, _param) \
1455 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1456 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1457 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1459 #define ath_hal_is_fast_clock_enabled(_ah) \
1460 ((*(_ah)->ah_isFastClockEnabled)((_ah)))
1461 #define ath_hal_radar_wait(_ah, _chan) \
1462 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
1463 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \
1464 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1465 #define ath_hal_get_chan_ext_busy(_ah) \
1466 ((*(_ah)->ah_get11nExtBusy)((_ah)))
1467 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
1468 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1470 #define ath_hal_spectral_supported(_ah) \
1471 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)
1472 #define ath_hal_spectral_get_config(_ah, _p) \
1473 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1474 #define ath_hal_spectral_configure(_ah, _p) \
1475 ((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1476 #define ath_hal_spectral_start(_ah) \
1477 ((*(_ah)->ah_spectralStart)((_ah)))
1478 #define ath_hal_spectral_stop(_ah) \
1479 ((*(_ah)->ah_spectralStop)((_ah)))
1481 #define ath_hal_btcoex_supported(_ah) \
1482 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK)
1483 #define ath_hal_btcoex_set_info(_ah, _info) \
1484 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1485 #define ath_hal_btcoex_set_config(_ah, _cfg) \
1486 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1487 #define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \
1488 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1489 #define ath_hal_btcoex_set_weights(_ah, _weight) \
1490 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1491 #define ath_hal_btcoex_set_weights(_ah, _weight) \
1492 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1493 #define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \
1494 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1495 #define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \
1496 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1497 #define ath_hal_btcoex_enable(_ah) \
1498 ((*(_ah)->ah_btCoexEnable)((_ah)))
1499 #define ath_hal_btcoex_disable(_ah) \
1500 ((*(_ah)->ah_btCoexDisable)((_ah)))
1502 #define ath_hal_div_comb_conf_get(_ah, _conf) \
1503 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1504 #define ath_hal_div_comb_conf_set(_ah, _conf) \
1505 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))
1507 #endif /* _DEV_ATH_ATHVAR_H */