2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.c 254885 2013-08-25 19:37:15Z dumbbell $
32 #include <drm/drm_crtc_helper.h>
33 #include <uapi_drm/radeon_drm.h>
34 #include "radeon_reg.h"
36 #include "radeon_asic.h"
40 * Registers accessors functions.
43 * radeon_invalid_rreg - dummy reg read function
45 * @rdev: radeon device pointer
46 * @reg: offset of register
48 * Dummy register read function. Used for register blocks
49 * that certain asics don't have (all asics).
50 * Returns the value in the register.
52 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 panic("Invalid callback to read register 0x%04X\n", reg);
59 * radeon_invalid_wreg - dummy reg write function
61 * @rdev: radeon device pointer
62 * @reg: offset of register
63 * @v: value to write to the register
65 * Dummy register read function. Used for register blocks
66 * that certain asics don't have (all asics).
68 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
70 panic("Invalid callback to write register 0x%04X with 0x%08X\n",
75 * radeon_register_accessor_init - sets up the register accessor callbacks
77 * @rdev: radeon device pointer
79 * Sets up the register accessor callbacks for various register
80 * apertures. Not all asics have all apertures (all asics).
82 static void radeon_register_accessor_init(struct radeon_device *rdev)
84 rdev->mc_rreg = &radeon_invalid_rreg;
85 rdev->mc_wreg = &radeon_invalid_wreg;
86 rdev->pll_rreg = &radeon_invalid_rreg;
87 rdev->pll_wreg = &radeon_invalid_wreg;
88 rdev->pciep_rreg = &radeon_invalid_rreg;
89 rdev->pciep_wreg = &radeon_invalid_wreg;
91 /* Don't change order as we are overridding accessor. */
92 if (rdev->family < CHIP_RV515) {
93 rdev->pcie_reg_mask = 0xff;
95 rdev->pcie_reg_mask = 0x7ff;
97 /* FIXME: not sure here */
98 if (rdev->family <= CHIP_R580) {
99 rdev->pll_rreg = &r100_pll_rreg;
100 rdev->pll_wreg = &r100_pll_wreg;
102 if (rdev->family >= CHIP_R420) {
103 rdev->mc_rreg = &r420_mc_rreg;
104 rdev->mc_wreg = &r420_mc_wreg;
106 if (rdev->family >= CHIP_RV515) {
107 rdev->mc_rreg = &rv515_mc_rreg;
108 rdev->mc_wreg = &rv515_mc_wreg;
110 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
111 rdev->mc_rreg = &rs400_mc_rreg;
112 rdev->mc_wreg = &rs400_mc_wreg;
114 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
115 rdev->mc_rreg = &rs690_mc_rreg;
116 rdev->mc_wreg = &rs690_mc_wreg;
118 if (rdev->family == CHIP_RS600) {
119 rdev->mc_rreg = &rs600_mc_rreg;
120 rdev->mc_wreg = &rs600_mc_wreg;
122 if (rdev->family >= CHIP_R600) {
123 rdev->pciep_rreg = &r600_pciep_rreg;
124 rdev->pciep_wreg = &r600_pciep_wreg;
129 /* helper to disable agp */
131 * radeon_agp_disable - AGP disable helper function
133 * @rdev: radeon device pointer
135 * Removes AGP flags and changes the gart callbacks on AGP
136 * cards when using the internal gart rather than AGP (all asics).
138 void radeon_agp_disable(struct radeon_device *rdev)
140 rdev->flags &= ~RADEON_IS_AGP;
141 if (rdev->family >= CHIP_R600) {
142 DRM_INFO("Forcing AGP to PCIE mode\n");
143 rdev->flags |= RADEON_IS_PCIE;
144 } else if (rdev->family >= CHIP_RV515 ||
145 rdev->family == CHIP_RV380 ||
146 rdev->family == CHIP_RV410 ||
147 rdev->family == CHIP_R423) {
148 DRM_INFO("Forcing AGP to PCIE mode\n");
149 rdev->flags |= RADEON_IS_PCIE;
150 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
151 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
153 DRM_INFO("Forcing AGP to PCI mode\n");
154 rdev->flags |= RADEON_IS_PCI;
155 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
156 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
158 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
164 static struct radeon_asic r100_asic = {
167 .suspend = &r100_suspend,
168 .resume = &r100_resume,
169 .vga_set_state = &r100_vga_set_state,
170 .asic_reset = &r100_asic_reset,
171 .ioctl_wait_idle = NULL,
172 .gui_idle = &r100_gui_idle,
173 .mc_wait_for_idle = &r100_mc_wait_for_idle,
175 .tlb_flush = &r100_pci_gart_tlb_flush,
176 .set_page = &r100_pci_gart_set_page,
179 [RADEON_RING_TYPE_GFX_INDEX] = {
180 .ib_execute = &r100_ring_ib_execute,
181 .emit_fence = &r100_fence_ring_emit,
182 .emit_semaphore = &r100_semaphore_ring_emit,
183 .cs_parse = &r100_cs_parse,
184 .ring_start = &r100_ring_start,
185 .ring_test = &r100_ring_test,
186 .ib_test = &r100_ib_test,
187 .is_lockup = &r100_gpu_is_lockup,
191 .set = &r100_irq_set,
192 .process = &r100_irq_process,
195 .bandwidth_update = &r100_bandwidth_update,
196 .get_vblank_counter = &r100_get_vblank_counter,
197 .wait_for_vblank = &r100_wait_for_vblank,
198 .set_backlight_level = &radeon_legacy_set_backlight_level,
199 .get_backlight_level = &radeon_legacy_get_backlight_level,
202 .blit = &r100_copy_blit,
203 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
205 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
206 .copy = &r100_copy_blit,
207 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
210 .set_reg = r100_set_surface_reg,
211 .clear_reg = r100_clear_surface_reg,
214 .init = &r100_hpd_init,
215 .fini = &r100_hpd_fini,
216 .sense = &r100_hpd_sense,
217 .set_polarity = &r100_hpd_set_polarity,
220 .misc = &r100_pm_misc,
221 .prepare = &r100_pm_prepare,
222 .finish = &r100_pm_finish,
223 .init_profile = &r100_pm_init_profile,
224 .get_dynpm_state = &r100_pm_get_dynpm_state,
225 .get_engine_clock = &radeon_legacy_get_engine_clock,
226 .set_engine_clock = &radeon_legacy_set_engine_clock,
227 .get_memory_clock = &radeon_legacy_get_memory_clock,
228 .set_memory_clock = NULL,
229 .get_pcie_lanes = NULL,
230 .set_pcie_lanes = NULL,
231 .set_clock_gating = &radeon_legacy_set_clock_gating,
234 .pre_page_flip = &r100_pre_page_flip,
235 .page_flip = &r100_page_flip,
236 .post_page_flip = &r100_post_page_flip,
240 static struct radeon_asic r200_asic = {
243 .suspend = &r100_suspend,
244 .resume = &r100_resume,
245 .vga_set_state = &r100_vga_set_state,
246 .asic_reset = &r100_asic_reset,
247 .ioctl_wait_idle = NULL,
248 .gui_idle = &r100_gui_idle,
249 .mc_wait_for_idle = &r100_mc_wait_for_idle,
251 .tlb_flush = &r100_pci_gart_tlb_flush,
252 .set_page = &r100_pci_gart_set_page,
255 [RADEON_RING_TYPE_GFX_INDEX] = {
256 .ib_execute = &r100_ring_ib_execute,
257 .emit_fence = &r100_fence_ring_emit,
258 .emit_semaphore = &r100_semaphore_ring_emit,
259 .cs_parse = &r100_cs_parse,
260 .ring_start = &r100_ring_start,
261 .ring_test = &r100_ring_test,
262 .ib_test = &r100_ib_test,
263 .is_lockup = &r100_gpu_is_lockup,
267 .set = &r100_irq_set,
268 .process = &r100_irq_process,
271 .bandwidth_update = &r100_bandwidth_update,
272 .get_vblank_counter = &r100_get_vblank_counter,
273 .wait_for_vblank = &r100_wait_for_vblank,
274 .set_backlight_level = &radeon_legacy_set_backlight_level,
275 .get_backlight_level = &radeon_legacy_get_backlight_level,
278 .blit = &r100_copy_blit,
279 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
280 .dma = &r200_copy_dma,
281 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
282 .copy = &r100_copy_blit,
283 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
286 .set_reg = r100_set_surface_reg,
287 .clear_reg = r100_clear_surface_reg,
290 .init = &r100_hpd_init,
291 .fini = &r100_hpd_fini,
292 .sense = &r100_hpd_sense,
293 .set_polarity = &r100_hpd_set_polarity,
296 .misc = &r100_pm_misc,
297 .prepare = &r100_pm_prepare,
298 .finish = &r100_pm_finish,
299 .init_profile = &r100_pm_init_profile,
300 .get_dynpm_state = &r100_pm_get_dynpm_state,
301 .get_engine_clock = &radeon_legacy_get_engine_clock,
302 .set_engine_clock = &radeon_legacy_set_engine_clock,
303 .get_memory_clock = &radeon_legacy_get_memory_clock,
304 .set_memory_clock = NULL,
305 .get_pcie_lanes = NULL,
306 .set_pcie_lanes = NULL,
307 .set_clock_gating = &radeon_legacy_set_clock_gating,
310 .pre_page_flip = &r100_pre_page_flip,
311 .page_flip = &r100_page_flip,
312 .post_page_flip = &r100_post_page_flip,
316 static struct radeon_asic r300_asic = {
319 .suspend = &r300_suspend,
320 .resume = &r300_resume,
321 .vga_set_state = &r100_vga_set_state,
322 .asic_reset = &r300_asic_reset,
323 .ioctl_wait_idle = NULL,
324 .gui_idle = &r100_gui_idle,
325 .mc_wait_for_idle = &r300_mc_wait_for_idle,
327 .tlb_flush = &r100_pci_gart_tlb_flush,
328 .set_page = &r100_pci_gart_set_page,
331 [RADEON_RING_TYPE_GFX_INDEX] = {
332 .ib_execute = &r100_ring_ib_execute,
333 .emit_fence = &r300_fence_ring_emit,
334 .emit_semaphore = &r100_semaphore_ring_emit,
335 .cs_parse = &r300_cs_parse,
336 .ring_start = &r300_ring_start,
337 .ring_test = &r100_ring_test,
338 .ib_test = &r100_ib_test,
339 .is_lockup = &r100_gpu_is_lockup,
343 .set = &r100_irq_set,
344 .process = &r100_irq_process,
347 .bandwidth_update = &r100_bandwidth_update,
348 .get_vblank_counter = &r100_get_vblank_counter,
349 .wait_for_vblank = &r100_wait_for_vblank,
350 .set_backlight_level = &radeon_legacy_set_backlight_level,
351 .get_backlight_level = &radeon_legacy_get_backlight_level,
354 .blit = &r100_copy_blit,
355 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
356 .dma = &r200_copy_dma,
357 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
358 .copy = &r100_copy_blit,
359 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
362 .set_reg = r100_set_surface_reg,
363 .clear_reg = r100_clear_surface_reg,
366 .init = &r100_hpd_init,
367 .fini = &r100_hpd_fini,
368 .sense = &r100_hpd_sense,
369 .set_polarity = &r100_hpd_set_polarity,
372 .misc = &r100_pm_misc,
373 .prepare = &r100_pm_prepare,
374 .finish = &r100_pm_finish,
375 .init_profile = &r100_pm_init_profile,
376 .get_dynpm_state = &r100_pm_get_dynpm_state,
377 .get_engine_clock = &radeon_legacy_get_engine_clock,
378 .set_engine_clock = &radeon_legacy_set_engine_clock,
379 .get_memory_clock = &radeon_legacy_get_memory_clock,
380 .set_memory_clock = NULL,
381 .get_pcie_lanes = &rv370_get_pcie_lanes,
382 .set_pcie_lanes = &rv370_set_pcie_lanes,
383 .set_clock_gating = &radeon_legacy_set_clock_gating,
386 .pre_page_flip = &r100_pre_page_flip,
387 .page_flip = &r100_page_flip,
388 .post_page_flip = &r100_post_page_flip,
392 static struct radeon_asic r300_asic_pcie = {
395 .suspend = &r300_suspend,
396 .resume = &r300_resume,
397 .vga_set_state = &r100_vga_set_state,
398 .asic_reset = &r300_asic_reset,
399 .ioctl_wait_idle = NULL,
400 .gui_idle = &r100_gui_idle,
401 .mc_wait_for_idle = &r300_mc_wait_for_idle,
403 .tlb_flush = &rv370_pcie_gart_tlb_flush,
404 .set_page = &rv370_pcie_gart_set_page,
407 [RADEON_RING_TYPE_GFX_INDEX] = {
408 .ib_execute = &r100_ring_ib_execute,
409 .emit_fence = &r300_fence_ring_emit,
410 .emit_semaphore = &r100_semaphore_ring_emit,
411 .cs_parse = &r300_cs_parse,
412 .ring_start = &r300_ring_start,
413 .ring_test = &r100_ring_test,
414 .ib_test = &r100_ib_test,
415 .is_lockup = &r100_gpu_is_lockup,
419 .set = &r100_irq_set,
420 .process = &r100_irq_process,
423 .bandwidth_update = &r100_bandwidth_update,
424 .get_vblank_counter = &r100_get_vblank_counter,
425 .wait_for_vblank = &r100_wait_for_vblank,
426 .set_backlight_level = &radeon_legacy_set_backlight_level,
427 .get_backlight_level = &radeon_legacy_get_backlight_level,
430 .blit = &r100_copy_blit,
431 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
432 .dma = &r200_copy_dma,
433 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
434 .copy = &r100_copy_blit,
435 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
438 .set_reg = r100_set_surface_reg,
439 .clear_reg = r100_clear_surface_reg,
442 .init = &r100_hpd_init,
443 .fini = &r100_hpd_fini,
444 .sense = &r100_hpd_sense,
445 .set_polarity = &r100_hpd_set_polarity,
448 .misc = &r100_pm_misc,
449 .prepare = &r100_pm_prepare,
450 .finish = &r100_pm_finish,
451 .init_profile = &r100_pm_init_profile,
452 .get_dynpm_state = &r100_pm_get_dynpm_state,
453 .get_engine_clock = &radeon_legacy_get_engine_clock,
454 .set_engine_clock = &radeon_legacy_set_engine_clock,
455 .get_memory_clock = &radeon_legacy_get_memory_clock,
456 .set_memory_clock = NULL,
457 .get_pcie_lanes = &rv370_get_pcie_lanes,
458 .set_pcie_lanes = &rv370_set_pcie_lanes,
459 .set_clock_gating = &radeon_legacy_set_clock_gating,
462 .pre_page_flip = &r100_pre_page_flip,
463 .page_flip = &r100_page_flip,
464 .post_page_flip = &r100_post_page_flip,
468 static struct radeon_asic r420_asic = {
471 .suspend = &r420_suspend,
472 .resume = &r420_resume,
473 .vga_set_state = &r100_vga_set_state,
474 .asic_reset = &r300_asic_reset,
475 .ioctl_wait_idle = NULL,
476 .gui_idle = &r100_gui_idle,
477 .mc_wait_for_idle = &r300_mc_wait_for_idle,
479 .tlb_flush = &rv370_pcie_gart_tlb_flush,
480 .set_page = &rv370_pcie_gart_set_page,
483 [RADEON_RING_TYPE_GFX_INDEX] = {
484 .ib_execute = &r100_ring_ib_execute,
485 .emit_fence = &r300_fence_ring_emit,
486 .emit_semaphore = &r100_semaphore_ring_emit,
487 .cs_parse = &r300_cs_parse,
488 .ring_start = &r300_ring_start,
489 .ring_test = &r100_ring_test,
490 .ib_test = &r100_ib_test,
491 .is_lockup = &r100_gpu_is_lockup,
495 .set = &r100_irq_set,
496 .process = &r100_irq_process,
499 .bandwidth_update = &r100_bandwidth_update,
500 .get_vblank_counter = &r100_get_vblank_counter,
501 .wait_for_vblank = &r100_wait_for_vblank,
502 .set_backlight_level = &atombios_set_backlight_level,
503 .get_backlight_level = &atombios_get_backlight_level,
506 .blit = &r100_copy_blit,
507 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
508 .dma = &r200_copy_dma,
509 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
510 .copy = &r100_copy_blit,
511 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
514 .set_reg = r100_set_surface_reg,
515 .clear_reg = r100_clear_surface_reg,
518 .init = &r100_hpd_init,
519 .fini = &r100_hpd_fini,
520 .sense = &r100_hpd_sense,
521 .set_polarity = &r100_hpd_set_polarity,
524 .misc = &r100_pm_misc,
525 .prepare = &r100_pm_prepare,
526 .finish = &r100_pm_finish,
527 .init_profile = &r420_pm_init_profile,
528 .get_dynpm_state = &r100_pm_get_dynpm_state,
529 .get_engine_clock = &radeon_atom_get_engine_clock,
530 .set_engine_clock = &radeon_atom_set_engine_clock,
531 .get_memory_clock = &radeon_atom_get_memory_clock,
532 .set_memory_clock = &radeon_atom_set_memory_clock,
533 .get_pcie_lanes = &rv370_get_pcie_lanes,
534 .set_pcie_lanes = &rv370_set_pcie_lanes,
535 .set_clock_gating = &radeon_atom_set_clock_gating,
538 .pre_page_flip = &r100_pre_page_flip,
539 .page_flip = &r100_page_flip,
540 .post_page_flip = &r100_post_page_flip,
544 static struct radeon_asic rs400_asic = {
547 .suspend = &rs400_suspend,
548 .resume = &rs400_resume,
549 .vga_set_state = &r100_vga_set_state,
550 .asic_reset = &r300_asic_reset,
551 .ioctl_wait_idle = NULL,
552 .gui_idle = &r100_gui_idle,
553 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
555 .tlb_flush = &rs400_gart_tlb_flush,
556 .set_page = &rs400_gart_set_page,
559 [RADEON_RING_TYPE_GFX_INDEX] = {
560 .ib_execute = &r100_ring_ib_execute,
561 .emit_fence = &r300_fence_ring_emit,
562 .emit_semaphore = &r100_semaphore_ring_emit,
563 .cs_parse = &r300_cs_parse,
564 .ring_start = &r300_ring_start,
565 .ring_test = &r100_ring_test,
566 .ib_test = &r100_ib_test,
567 .is_lockup = &r100_gpu_is_lockup,
571 .set = &r100_irq_set,
572 .process = &r100_irq_process,
575 .bandwidth_update = &r100_bandwidth_update,
576 .get_vblank_counter = &r100_get_vblank_counter,
577 .wait_for_vblank = &r100_wait_for_vblank,
578 .set_backlight_level = &radeon_legacy_set_backlight_level,
579 .get_backlight_level = &radeon_legacy_get_backlight_level,
582 .blit = &r100_copy_blit,
583 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
584 .dma = &r200_copy_dma,
585 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
586 .copy = &r100_copy_blit,
587 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
590 .set_reg = r100_set_surface_reg,
591 .clear_reg = r100_clear_surface_reg,
594 .init = &r100_hpd_init,
595 .fini = &r100_hpd_fini,
596 .sense = &r100_hpd_sense,
597 .set_polarity = &r100_hpd_set_polarity,
600 .misc = &r100_pm_misc,
601 .prepare = &r100_pm_prepare,
602 .finish = &r100_pm_finish,
603 .init_profile = &r100_pm_init_profile,
604 .get_dynpm_state = &r100_pm_get_dynpm_state,
605 .get_engine_clock = &radeon_legacy_get_engine_clock,
606 .set_engine_clock = &radeon_legacy_set_engine_clock,
607 .get_memory_clock = &radeon_legacy_get_memory_clock,
608 .set_memory_clock = NULL,
609 .get_pcie_lanes = NULL,
610 .set_pcie_lanes = NULL,
611 .set_clock_gating = &radeon_legacy_set_clock_gating,
614 .pre_page_flip = &r100_pre_page_flip,
615 .page_flip = &r100_page_flip,
616 .post_page_flip = &r100_post_page_flip,
620 static struct radeon_asic rs600_asic = {
623 .suspend = &rs600_suspend,
624 .resume = &rs600_resume,
625 .vga_set_state = &r100_vga_set_state,
626 .asic_reset = &rs600_asic_reset,
627 .ioctl_wait_idle = NULL,
628 .gui_idle = &r100_gui_idle,
629 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
631 .tlb_flush = &rs600_gart_tlb_flush,
632 .set_page = &rs600_gart_set_page,
635 [RADEON_RING_TYPE_GFX_INDEX] = {
636 .ib_execute = &r100_ring_ib_execute,
637 .emit_fence = &r300_fence_ring_emit,
638 .emit_semaphore = &r100_semaphore_ring_emit,
639 .cs_parse = &r300_cs_parse,
640 .ring_start = &r300_ring_start,
641 .ring_test = &r100_ring_test,
642 .ib_test = &r100_ib_test,
643 .is_lockup = &r100_gpu_is_lockup,
647 .set = &rs600_irq_set,
648 .process = &rs600_irq_process,
651 .bandwidth_update = &rs600_bandwidth_update,
652 .get_vblank_counter = &rs600_get_vblank_counter,
653 .wait_for_vblank = &avivo_wait_for_vblank,
654 .set_backlight_level = &atombios_set_backlight_level,
655 .get_backlight_level = &atombios_get_backlight_level,
658 .blit = &r100_copy_blit,
659 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
660 .dma = &r200_copy_dma,
661 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
662 .copy = &r100_copy_blit,
663 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
666 .set_reg = r100_set_surface_reg,
667 .clear_reg = r100_clear_surface_reg,
670 .init = &rs600_hpd_init,
671 .fini = &rs600_hpd_fini,
672 .sense = &rs600_hpd_sense,
673 .set_polarity = &rs600_hpd_set_polarity,
676 .misc = &rs600_pm_misc,
677 .prepare = &rs600_pm_prepare,
678 .finish = &rs600_pm_finish,
679 .init_profile = &r420_pm_init_profile,
680 .get_dynpm_state = &r100_pm_get_dynpm_state,
681 .get_engine_clock = &radeon_atom_get_engine_clock,
682 .set_engine_clock = &radeon_atom_set_engine_clock,
683 .get_memory_clock = &radeon_atom_get_memory_clock,
684 .set_memory_clock = &radeon_atom_set_memory_clock,
685 .get_pcie_lanes = NULL,
686 .set_pcie_lanes = NULL,
687 .set_clock_gating = &radeon_atom_set_clock_gating,
690 .pre_page_flip = &rs600_pre_page_flip,
691 .page_flip = &rs600_page_flip,
692 .post_page_flip = &rs600_post_page_flip,
696 static struct radeon_asic rs690_asic = {
699 .suspend = &rs690_suspend,
700 .resume = &rs690_resume,
701 .vga_set_state = &r100_vga_set_state,
702 .asic_reset = &rs600_asic_reset,
703 .ioctl_wait_idle = NULL,
704 .gui_idle = &r100_gui_idle,
705 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
707 .tlb_flush = &rs400_gart_tlb_flush,
708 .set_page = &rs400_gart_set_page,
711 [RADEON_RING_TYPE_GFX_INDEX] = {
712 .ib_execute = &r100_ring_ib_execute,
713 .emit_fence = &r300_fence_ring_emit,
714 .emit_semaphore = &r100_semaphore_ring_emit,
715 .cs_parse = &r300_cs_parse,
716 .ring_start = &r300_ring_start,
717 .ring_test = &r100_ring_test,
718 .ib_test = &r100_ib_test,
719 .is_lockup = &r100_gpu_is_lockup,
723 .set = &rs600_irq_set,
724 .process = &rs600_irq_process,
727 .get_vblank_counter = &rs600_get_vblank_counter,
728 .bandwidth_update = &rs690_bandwidth_update,
729 .wait_for_vblank = &avivo_wait_for_vblank,
730 .set_backlight_level = &atombios_set_backlight_level,
731 .get_backlight_level = &atombios_get_backlight_level,
734 .blit = &r100_copy_blit,
735 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
736 .dma = &r200_copy_dma,
737 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
738 .copy = &r200_copy_dma,
739 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
742 .set_reg = r100_set_surface_reg,
743 .clear_reg = r100_clear_surface_reg,
746 .init = &rs600_hpd_init,
747 .fini = &rs600_hpd_fini,
748 .sense = &rs600_hpd_sense,
749 .set_polarity = &rs600_hpd_set_polarity,
752 .misc = &rs600_pm_misc,
753 .prepare = &rs600_pm_prepare,
754 .finish = &rs600_pm_finish,
755 .init_profile = &r420_pm_init_profile,
756 .get_dynpm_state = &r100_pm_get_dynpm_state,
757 .get_engine_clock = &radeon_atom_get_engine_clock,
758 .set_engine_clock = &radeon_atom_set_engine_clock,
759 .get_memory_clock = &radeon_atom_get_memory_clock,
760 .set_memory_clock = &radeon_atom_set_memory_clock,
761 .get_pcie_lanes = NULL,
762 .set_pcie_lanes = NULL,
763 .set_clock_gating = &radeon_atom_set_clock_gating,
766 .pre_page_flip = &rs600_pre_page_flip,
767 .page_flip = &rs600_page_flip,
768 .post_page_flip = &rs600_post_page_flip,
772 static struct radeon_asic rv515_asic = {
775 .suspend = &rv515_suspend,
776 .resume = &rv515_resume,
777 .vga_set_state = &r100_vga_set_state,
778 .asic_reset = &rs600_asic_reset,
779 .ioctl_wait_idle = NULL,
780 .gui_idle = &r100_gui_idle,
781 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
783 .tlb_flush = &rv370_pcie_gart_tlb_flush,
784 .set_page = &rv370_pcie_gart_set_page,
787 [RADEON_RING_TYPE_GFX_INDEX] = {
788 .ib_execute = &r100_ring_ib_execute,
789 .emit_fence = &r300_fence_ring_emit,
790 .emit_semaphore = &r100_semaphore_ring_emit,
791 .cs_parse = &r300_cs_parse,
792 .ring_start = &rv515_ring_start,
793 .ring_test = &r100_ring_test,
794 .ib_test = &r100_ib_test,
795 .is_lockup = &r100_gpu_is_lockup,
799 .set = &rs600_irq_set,
800 .process = &rs600_irq_process,
803 .get_vblank_counter = &rs600_get_vblank_counter,
804 .bandwidth_update = &rv515_bandwidth_update,
805 .wait_for_vblank = &avivo_wait_for_vblank,
806 .set_backlight_level = &atombios_set_backlight_level,
807 .get_backlight_level = &atombios_get_backlight_level,
810 .blit = &r100_copy_blit,
811 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
812 .dma = &r200_copy_dma,
813 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
814 .copy = &r100_copy_blit,
815 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
818 .set_reg = r100_set_surface_reg,
819 .clear_reg = r100_clear_surface_reg,
822 .init = &rs600_hpd_init,
823 .fini = &rs600_hpd_fini,
824 .sense = &rs600_hpd_sense,
825 .set_polarity = &rs600_hpd_set_polarity,
828 .misc = &rs600_pm_misc,
829 .prepare = &rs600_pm_prepare,
830 .finish = &rs600_pm_finish,
831 .init_profile = &r420_pm_init_profile,
832 .get_dynpm_state = &r100_pm_get_dynpm_state,
833 .get_engine_clock = &radeon_atom_get_engine_clock,
834 .set_engine_clock = &radeon_atom_set_engine_clock,
835 .get_memory_clock = &radeon_atom_get_memory_clock,
836 .set_memory_clock = &radeon_atom_set_memory_clock,
837 .get_pcie_lanes = &rv370_get_pcie_lanes,
838 .set_pcie_lanes = &rv370_set_pcie_lanes,
839 .set_clock_gating = &radeon_atom_set_clock_gating,
842 .pre_page_flip = &rs600_pre_page_flip,
843 .page_flip = &rs600_page_flip,
844 .post_page_flip = &rs600_post_page_flip,
848 static struct radeon_asic r520_asic = {
851 .suspend = &rv515_suspend,
852 .resume = &r520_resume,
853 .vga_set_state = &r100_vga_set_state,
854 .asic_reset = &rs600_asic_reset,
855 .ioctl_wait_idle = NULL,
856 .gui_idle = &r100_gui_idle,
857 .mc_wait_for_idle = &r520_mc_wait_for_idle,
859 .tlb_flush = &rv370_pcie_gart_tlb_flush,
860 .set_page = &rv370_pcie_gart_set_page,
863 [RADEON_RING_TYPE_GFX_INDEX] = {
864 .ib_execute = &r100_ring_ib_execute,
865 .emit_fence = &r300_fence_ring_emit,
866 .emit_semaphore = &r100_semaphore_ring_emit,
867 .cs_parse = &r300_cs_parse,
868 .ring_start = &rv515_ring_start,
869 .ring_test = &r100_ring_test,
870 .ib_test = &r100_ib_test,
871 .is_lockup = &r100_gpu_is_lockup,
875 .set = &rs600_irq_set,
876 .process = &rs600_irq_process,
879 .bandwidth_update = &rv515_bandwidth_update,
880 .get_vblank_counter = &rs600_get_vblank_counter,
881 .wait_for_vblank = &avivo_wait_for_vblank,
882 .set_backlight_level = &atombios_set_backlight_level,
883 .get_backlight_level = &atombios_get_backlight_level,
886 .blit = &r100_copy_blit,
887 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
888 .dma = &r200_copy_dma,
889 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
890 .copy = &r100_copy_blit,
891 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
894 .set_reg = r100_set_surface_reg,
895 .clear_reg = r100_clear_surface_reg,
898 .init = &rs600_hpd_init,
899 .fini = &rs600_hpd_fini,
900 .sense = &rs600_hpd_sense,
901 .set_polarity = &rs600_hpd_set_polarity,
904 .misc = &rs600_pm_misc,
905 .prepare = &rs600_pm_prepare,
906 .finish = &rs600_pm_finish,
907 .init_profile = &r420_pm_init_profile,
908 .get_dynpm_state = &r100_pm_get_dynpm_state,
909 .get_engine_clock = &radeon_atom_get_engine_clock,
910 .set_engine_clock = &radeon_atom_set_engine_clock,
911 .get_memory_clock = &radeon_atom_get_memory_clock,
912 .set_memory_clock = &radeon_atom_set_memory_clock,
913 .get_pcie_lanes = &rv370_get_pcie_lanes,
914 .set_pcie_lanes = &rv370_set_pcie_lanes,
915 .set_clock_gating = &radeon_atom_set_clock_gating,
918 .pre_page_flip = &rs600_pre_page_flip,
919 .page_flip = &rs600_page_flip,
920 .post_page_flip = &rs600_post_page_flip,
924 static struct radeon_asic r600_asic = {
927 .suspend = &r600_suspend,
928 .resume = &r600_resume,
929 .vga_set_state = &r600_vga_set_state,
930 .asic_reset = &r600_asic_reset,
931 .ioctl_wait_idle = r600_ioctl_wait_idle,
932 .gui_idle = &r600_gui_idle,
933 .mc_wait_for_idle = &r600_mc_wait_for_idle,
934 .get_xclk = &r600_get_xclk,
935 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
937 .tlb_flush = &r600_pcie_gart_tlb_flush,
938 .set_page = &rs600_gart_set_page,
941 [RADEON_RING_TYPE_GFX_INDEX] = {
942 .ib_execute = &r600_ring_ib_execute,
943 .emit_fence = &r600_fence_ring_emit,
944 .emit_semaphore = &r600_semaphore_ring_emit,
945 .cs_parse = &r600_cs_parse,
946 .ring_test = &r600_ring_test,
947 .ib_test = &r600_ib_test,
948 .is_lockup = &r600_gfx_is_lockup,
950 [R600_RING_TYPE_DMA_INDEX] = {
951 .ib_execute = &r600_dma_ring_ib_execute,
952 .emit_fence = &r600_dma_fence_ring_emit,
953 .emit_semaphore = &r600_dma_semaphore_ring_emit,
954 .cs_parse = &r600_dma_cs_parse,
955 .ring_test = &r600_dma_ring_test,
956 .ib_test = &r600_dma_ib_test,
957 .is_lockup = &r600_dma_is_lockup,
961 .set = &r600_irq_set,
962 .process = &r600_irq_process,
965 .bandwidth_update = &rv515_bandwidth_update,
966 .get_vblank_counter = &rs600_get_vblank_counter,
967 .wait_for_vblank = &avivo_wait_for_vblank,
968 .set_backlight_level = &atombios_set_backlight_level,
969 .get_backlight_level = &atombios_get_backlight_level,
972 .blit = &r600_copy_blit,
973 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
974 .dma = &r600_copy_dma,
975 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
976 .copy = &r600_copy_dma,
977 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
980 .set_reg = r600_set_surface_reg,
981 .clear_reg = r600_clear_surface_reg,
984 .init = &r600_hpd_init,
985 .fini = &r600_hpd_fini,
986 .sense = &r600_hpd_sense,
987 .set_polarity = &r600_hpd_set_polarity,
990 .misc = &r600_pm_misc,
991 .prepare = &rs600_pm_prepare,
992 .finish = &rs600_pm_finish,
993 .init_profile = &r600_pm_init_profile,
994 .get_dynpm_state = &r600_pm_get_dynpm_state,
995 .get_engine_clock = &radeon_atom_get_engine_clock,
996 .set_engine_clock = &radeon_atom_set_engine_clock,
997 .get_memory_clock = &radeon_atom_get_memory_clock,
998 .set_memory_clock = &radeon_atom_set_memory_clock,
999 .get_pcie_lanes = &r600_get_pcie_lanes,
1000 .set_pcie_lanes = &r600_set_pcie_lanes,
1001 .set_clock_gating = NULL,
1004 .pre_page_flip = &rs600_pre_page_flip,
1005 .page_flip = &rs600_page_flip,
1006 .post_page_flip = &rs600_post_page_flip,
1010 static struct radeon_asic rs780_asic = {
1013 .suspend = &r600_suspend,
1014 .resume = &r600_resume,
1015 .vga_set_state = &r600_vga_set_state,
1016 .asic_reset = &r600_asic_reset,
1017 .ioctl_wait_idle = r600_ioctl_wait_idle,
1018 .gui_idle = &r600_gui_idle,
1019 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1020 .get_xclk = &r600_get_xclk,
1021 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1023 .tlb_flush = &r600_pcie_gart_tlb_flush,
1024 .set_page = &rs600_gart_set_page,
1027 [RADEON_RING_TYPE_GFX_INDEX] = {
1028 .ib_execute = &r600_ring_ib_execute,
1029 .emit_fence = &r600_fence_ring_emit,
1030 .emit_semaphore = &r600_semaphore_ring_emit,
1031 .cs_parse = &r600_cs_parse,
1032 .ring_test = &r600_ring_test,
1033 .ib_test = &r600_ib_test,
1034 .is_lockup = &r600_gfx_is_lockup,
1036 [R600_RING_TYPE_DMA_INDEX] = {
1037 .ib_execute = &r600_dma_ring_ib_execute,
1038 .emit_fence = &r600_dma_fence_ring_emit,
1039 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1040 .cs_parse = &r600_dma_cs_parse,
1041 .ring_test = &r600_dma_ring_test,
1042 .ib_test = &r600_dma_ib_test,
1043 .is_lockup = &r600_dma_is_lockup,
1047 .set = &r600_irq_set,
1048 .process = &r600_irq_process,
1051 .bandwidth_update = &rs690_bandwidth_update,
1052 .get_vblank_counter = &rs600_get_vblank_counter,
1053 .wait_for_vblank = &avivo_wait_for_vblank,
1054 .set_backlight_level = &atombios_set_backlight_level,
1055 .get_backlight_level = &atombios_get_backlight_level,
1058 .blit = &r600_copy_blit,
1059 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1060 .dma = &r600_copy_dma,
1061 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1062 .copy = &r600_copy_dma,
1063 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1066 .set_reg = r600_set_surface_reg,
1067 .clear_reg = r600_clear_surface_reg,
1070 .init = &r600_hpd_init,
1071 .fini = &r600_hpd_fini,
1072 .sense = &r600_hpd_sense,
1073 .set_polarity = &r600_hpd_set_polarity,
1076 .misc = &r600_pm_misc,
1077 .prepare = &rs600_pm_prepare,
1078 .finish = &rs600_pm_finish,
1079 .init_profile = &rs780_pm_init_profile,
1080 .get_dynpm_state = &r600_pm_get_dynpm_state,
1081 .get_engine_clock = &radeon_atom_get_engine_clock,
1082 .set_engine_clock = &radeon_atom_set_engine_clock,
1083 .get_memory_clock = NULL,
1084 .set_memory_clock = NULL,
1085 .get_pcie_lanes = NULL,
1086 .set_pcie_lanes = NULL,
1087 .set_clock_gating = NULL,
1090 .pre_page_flip = &rs600_pre_page_flip,
1091 .page_flip = &rs600_page_flip,
1092 .post_page_flip = &rs600_post_page_flip,
1096 static struct radeon_asic rv770_asic = {
1097 .init = &rv770_init,
1098 .fini = &rv770_fini,
1099 .suspend = &rv770_suspend,
1100 .resume = &rv770_resume,
1101 .asic_reset = &r600_asic_reset,
1102 .vga_set_state = &r600_vga_set_state,
1103 .ioctl_wait_idle = r600_ioctl_wait_idle,
1104 .gui_idle = &r600_gui_idle,
1105 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1106 .get_xclk = &rv770_get_xclk,
1107 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1109 .tlb_flush = &r600_pcie_gart_tlb_flush,
1110 .set_page = &rs600_gart_set_page,
1113 [RADEON_RING_TYPE_GFX_INDEX] = {
1114 .ib_execute = &r600_ring_ib_execute,
1115 .emit_fence = &r600_fence_ring_emit,
1116 .emit_semaphore = &r600_semaphore_ring_emit,
1117 .cs_parse = &r600_cs_parse,
1118 .ring_test = &r600_ring_test,
1119 .ib_test = &r600_ib_test,
1120 .is_lockup = &r600_gfx_is_lockup,
1122 [R600_RING_TYPE_DMA_INDEX] = {
1123 .ib_execute = &r600_dma_ring_ib_execute,
1124 .emit_fence = &r600_dma_fence_ring_emit,
1125 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1126 .cs_parse = &r600_dma_cs_parse,
1127 .ring_test = &r600_dma_ring_test,
1128 .ib_test = &r600_dma_ib_test,
1129 .is_lockup = &r600_dma_is_lockup,
1133 .set = &r600_irq_set,
1134 .process = &r600_irq_process,
1137 .bandwidth_update = &rv515_bandwidth_update,
1138 .get_vblank_counter = &rs600_get_vblank_counter,
1139 .wait_for_vblank = &avivo_wait_for_vblank,
1140 .set_backlight_level = &atombios_set_backlight_level,
1141 .get_backlight_level = &atombios_get_backlight_level,
1144 .blit = &r600_copy_blit,
1145 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1146 .dma = &rv770_copy_dma,
1147 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1148 .copy = &rv770_copy_dma,
1149 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1152 .set_reg = r600_set_surface_reg,
1153 .clear_reg = r600_clear_surface_reg,
1156 .init = &r600_hpd_init,
1157 .fini = &r600_hpd_fini,
1158 .sense = &r600_hpd_sense,
1159 .set_polarity = &r600_hpd_set_polarity,
1162 .misc = &rv770_pm_misc,
1163 .prepare = &rs600_pm_prepare,
1164 .finish = &rs600_pm_finish,
1165 .init_profile = &r600_pm_init_profile,
1166 .get_dynpm_state = &r600_pm_get_dynpm_state,
1167 .get_engine_clock = &radeon_atom_get_engine_clock,
1168 .set_engine_clock = &radeon_atom_set_engine_clock,
1169 .get_memory_clock = &radeon_atom_get_memory_clock,
1170 .set_memory_clock = &radeon_atom_set_memory_clock,
1171 .get_pcie_lanes = &r600_get_pcie_lanes,
1172 .set_pcie_lanes = &r600_set_pcie_lanes,
1173 .set_clock_gating = &radeon_atom_set_clock_gating,
1176 .pre_page_flip = &rs600_pre_page_flip,
1177 .page_flip = &rv770_page_flip,
1178 .post_page_flip = &rs600_post_page_flip,
1182 static struct radeon_asic evergreen_asic = {
1183 .init = &evergreen_init,
1184 .fini = &evergreen_fini,
1185 .suspend = &evergreen_suspend,
1186 .resume = &evergreen_resume,
1187 .asic_reset = &evergreen_asic_reset,
1188 .vga_set_state = &r600_vga_set_state,
1189 .ioctl_wait_idle = r600_ioctl_wait_idle,
1190 .gui_idle = &r600_gui_idle,
1191 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1192 .get_xclk = &rv770_get_xclk,
1193 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1195 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1196 .set_page = &rs600_gart_set_page,
1199 [RADEON_RING_TYPE_GFX_INDEX] = {
1200 .ib_execute = &evergreen_ring_ib_execute,
1201 .emit_fence = &r600_fence_ring_emit,
1202 .emit_semaphore = &r600_semaphore_ring_emit,
1203 .cs_parse = &evergreen_cs_parse,
1204 .ring_test = &r600_ring_test,
1205 .ib_test = &r600_ib_test,
1206 .is_lockup = &evergreen_gfx_is_lockup,
1208 [R600_RING_TYPE_DMA_INDEX] = {
1209 .ib_execute = &evergreen_dma_ring_ib_execute,
1210 .emit_fence = &evergreen_dma_fence_ring_emit,
1211 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1212 .cs_parse = &evergreen_dma_cs_parse,
1213 .ring_test = &r600_dma_ring_test,
1214 .ib_test = &r600_dma_ib_test,
1215 .is_lockup = &evergreen_dma_is_lockup,
1219 .set = &evergreen_irq_set,
1220 .process = &evergreen_irq_process,
1223 .bandwidth_update = &evergreen_bandwidth_update,
1224 .get_vblank_counter = &evergreen_get_vblank_counter,
1225 .wait_for_vblank = &dce4_wait_for_vblank,
1226 .set_backlight_level = &atombios_set_backlight_level,
1227 .get_backlight_level = &atombios_get_backlight_level,
1230 .blit = &r600_copy_blit,
1231 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1232 .dma = &evergreen_copy_dma,
1233 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1234 .copy = &evergreen_copy_dma,
1235 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1238 .set_reg = r600_set_surface_reg,
1239 .clear_reg = r600_clear_surface_reg,
1242 .init = &evergreen_hpd_init,
1243 .fini = &evergreen_hpd_fini,
1244 .sense = &evergreen_hpd_sense,
1245 .set_polarity = &evergreen_hpd_set_polarity,
1248 .misc = &evergreen_pm_misc,
1249 .prepare = &evergreen_pm_prepare,
1250 .finish = &evergreen_pm_finish,
1251 .init_profile = &r600_pm_init_profile,
1252 .get_dynpm_state = &r600_pm_get_dynpm_state,
1253 .get_engine_clock = &radeon_atom_get_engine_clock,
1254 .set_engine_clock = &radeon_atom_set_engine_clock,
1255 .get_memory_clock = &radeon_atom_get_memory_clock,
1256 .set_memory_clock = &radeon_atom_set_memory_clock,
1257 .get_pcie_lanes = &r600_get_pcie_lanes,
1258 .set_pcie_lanes = &r600_set_pcie_lanes,
1259 .set_clock_gating = NULL,
1262 .pre_page_flip = &evergreen_pre_page_flip,
1263 .page_flip = &evergreen_page_flip,
1264 .post_page_flip = &evergreen_post_page_flip,
1268 static struct radeon_asic sumo_asic = {
1269 .init = &evergreen_init,
1270 .fini = &evergreen_fini,
1271 .suspend = &evergreen_suspend,
1272 .resume = &evergreen_resume,
1273 .asic_reset = &evergreen_asic_reset,
1274 .vga_set_state = &r600_vga_set_state,
1275 .ioctl_wait_idle = r600_ioctl_wait_idle,
1276 .gui_idle = &r600_gui_idle,
1277 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1278 .get_xclk = &r600_get_xclk,
1279 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1281 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1282 .set_page = &rs600_gart_set_page,
1285 [RADEON_RING_TYPE_GFX_INDEX] = {
1286 .ib_execute = &evergreen_ring_ib_execute,
1287 .emit_fence = &r600_fence_ring_emit,
1288 .emit_semaphore = &r600_semaphore_ring_emit,
1289 .cs_parse = &evergreen_cs_parse,
1290 .ring_test = &r600_ring_test,
1291 .ib_test = &r600_ib_test,
1292 .is_lockup = &evergreen_gfx_is_lockup,
1294 [R600_RING_TYPE_DMA_INDEX] = {
1295 .ib_execute = &evergreen_dma_ring_ib_execute,
1296 .emit_fence = &evergreen_dma_fence_ring_emit,
1297 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1298 .cs_parse = &evergreen_dma_cs_parse,
1299 .ring_test = &r600_dma_ring_test,
1300 .ib_test = &r600_dma_ib_test,
1301 .is_lockup = &evergreen_dma_is_lockup,
1305 .set = &evergreen_irq_set,
1306 .process = &evergreen_irq_process,
1309 .bandwidth_update = &evergreen_bandwidth_update,
1310 .get_vblank_counter = &evergreen_get_vblank_counter,
1311 .wait_for_vblank = &dce4_wait_for_vblank,
1312 .set_backlight_level = &atombios_set_backlight_level,
1313 .get_backlight_level = &atombios_get_backlight_level,
1316 .blit = &r600_copy_blit,
1317 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1318 .dma = &evergreen_copy_dma,
1319 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1320 .copy = &evergreen_copy_dma,
1321 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1324 .set_reg = r600_set_surface_reg,
1325 .clear_reg = r600_clear_surface_reg,
1328 .init = &evergreen_hpd_init,
1329 .fini = &evergreen_hpd_fini,
1330 .sense = &evergreen_hpd_sense,
1331 .set_polarity = &evergreen_hpd_set_polarity,
1334 .misc = &evergreen_pm_misc,
1335 .prepare = &evergreen_pm_prepare,
1336 .finish = &evergreen_pm_finish,
1337 .init_profile = &sumo_pm_init_profile,
1338 .get_dynpm_state = &r600_pm_get_dynpm_state,
1339 .get_engine_clock = &radeon_atom_get_engine_clock,
1340 .set_engine_clock = &radeon_atom_set_engine_clock,
1341 .get_memory_clock = NULL,
1342 .set_memory_clock = NULL,
1343 .get_pcie_lanes = NULL,
1344 .set_pcie_lanes = NULL,
1345 .set_clock_gating = NULL,
1348 .pre_page_flip = &evergreen_pre_page_flip,
1349 .page_flip = &evergreen_page_flip,
1350 .post_page_flip = &evergreen_post_page_flip,
1354 static struct radeon_asic btc_asic = {
1355 .init = &evergreen_init,
1356 .fini = &evergreen_fini,
1357 .suspend = &evergreen_suspend,
1358 .resume = &evergreen_resume,
1359 .asic_reset = &evergreen_asic_reset,
1360 .vga_set_state = &r600_vga_set_state,
1361 .ioctl_wait_idle = r600_ioctl_wait_idle,
1362 .gui_idle = &r600_gui_idle,
1363 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1364 .get_xclk = &rv770_get_xclk,
1365 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1367 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1368 .set_page = &rs600_gart_set_page,
1371 [RADEON_RING_TYPE_GFX_INDEX] = {
1372 .ib_execute = &evergreen_ring_ib_execute,
1373 .emit_fence = &r600_fence_ring_emit,
1374 .emit_semaphore = &r600_semaphore_ring_emit,
1375 .cs_parse = &evergreen_cs_parse,
1376 .ring_test = &r600_ring_test,
1377 .ib_test = &r600_ib_test,
1378 .is_lockup = &evergreen_gfx_is_lockup,
1380 [R600_RING_TYPE_DMA_INDEX] = {
1381 .ib_execute = &evergreen_dma_ring_ib_execute,
1382 .emit_fence = &evergreen_dma_fence_ring_emit,
1383 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1384 .cs_parse = &evergreen_dma_cs_parse,
1385 .ring_test = &r600_dma_ring_test,
1386 .ib_test = &r600_dma_ib_test,
1387 .is_lockup = &evergreen_dma_is_lockup,
1391 .set = &evergreen_irq_set,
1392 .process = &evergreen_irq_process,
1395 .bandwidth_update = &evergreen_bandwidth_update,
1396 .get_vblank_counter = &evergreen_get_vblank_counter,
1397 .wait_for_vblank = &dce4_wait_for_vblank,
1398 .set_backlight_level = &atombios_set_backlight_level,
1399 .get_backlight_level = &atombios_get_backlight_level,
1402 .blit = &r600_copy_blit,
1403 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1404 .dma = &evergreen_copy_dma,
1405 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1406 .copy = &evergreen_copy_dma,
1407 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1410 .set_reg = r600_set_surface_reg,
1411 .clear_reg = r600_clear_surface_reg,
1414 .init = &evergreen_hpd_init,
1415 .fini = &evergreen_hpd_fini,
1416 .sense = &evergreen_hpd_sense,
1417 .set_polarity = &evergreen_hpd_set_polarity,
1420 .misc = &evergreen_pm_misc,
1421 .prepare = &evergreen_pm_prepare,
1422 .finish = &evergreen_pm_finish,
1423 .init_profile = &btc_pm_init_profile,
1424 .get_dynpm_state = &r600_pm_get_dynpm_state,
1425 .get_engine_clock = &radeon_atom_get_engine_clock,
1426 .set_engine_clock = &radeon_atom_set_engine_clock,
1427 .get_memory_clock = &radeon_atom_get_memory_clock,
1428 .set_memory_clock = &radeon_atom_set_memory_clock,
1429 .get_pcie_lanes = NULL,
1430 .set_pcie_lanes = NULL,
1431 .set_clock_gating = NULL,
1434 .pre_page_flip = &evergreen_pre_page_flip,
1435 .page_flip = &evergreen_page_flip,
1436 .post_page_flip = &evergreen_post_page_flip,
1440 static struct radeon_asic cayman_asic = {
1441 .init = &cayman_init,
1442 .fini = &cayman_fini,
1443 .suspend = &cayman_suspend,
1444 .resume = &cayman_resume,
1445 .asic_reset = &cayman_asic_reset,
1446 .vga_set_state = &r600_vga_set_state,
1447 .ioctl_wait_idle = r600_ioctl_wait_idle,
1448 .gui_idle = &r600_gui_idle,
1449 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1450 .get_xclk = &rv770_get_xclk,
1451 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1453 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1454 .set_page = &rs600_gart_set_page,
1457 .init = &cayman_vm_init,
1458 .fini = &cayman_vm_fini,
1459 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1460 .set_page = &cayman_vm_set_page,
1463 [RADEON_RING_TYPE_GFX_INDEX] = {
1464 .ib_execute = &cayman_ring_ib_execute,
1465 .ib_parse = &evergreen_ib_parse,
1466 .emit_fence = &cayman_fence_ring_emit,
1467 .emit_semaphore = &r600_semaphore_ring_emit,
1468 .cs_parse = &evergreen_cs_parse,
1469 .ring_test = &r600_ring_test,
1470 .ib_test = &r600_ib_test,
1471 .is_lockup = &cayman_gfx_is_lockup,
1472 .vm_flush = &cayman_vm_flush,
1474 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1475 .ib_execute = &cayman_ring_ib_execute,
1476 .ib_parse = &evergreen_ib_parse,
1477 .emit_fence = &cayman_fence_ring_emit,
1478 .emit_semaphore = &r600_semaphore_ring_emit,
1479 .cs_parse = &evergreen_cs_parse,
1480 .ring_test = &r600_ring_test,
1481 .ib_test = &r600_ib_test,
1482 .is_lockup = &cayman_gfx_is_lockup,
1483 .vm_flush = &cayman_vm_flush,
1485 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1486 .ib_execute = &cayman_ring_ib_execute,
1487 .ib_parse = &evergreen_ib_parse,
1488 .emit_fence = &cayman_fence_ring_emit,
1489 .emit_semaphore = &r600_semaphore_ring_emit,
1490 .cs_parse = &evergreen_cs_parse,
1491 .ring_test = &r600_ring_test,
1492 .ib_test = &r600_ib_test,
1493 .is_lockup = &cayman_gfx_is_lockup,
1494 .vm_flush = &cayman_vm_flush,
1496 [R600_RING_TYPE_DMA_INDEX] = {
1497 .ib_execute = &cayman_dma_ring_ib_execute,
1498 .ib_parse = &evergreen_dma_ib_parse,
1499 .emit_fence = &evergreen_dma_fence_ring_emit,
1500 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1501 .cs_parse = &evergreen_dma_cs_parse,
1502 .ring_test = &r600_dma_ring_test,
1503 .ib_test = &r600_dma_ib_test,
1504 .is_lockup = &cayman_dma_is_lockup,
1505 .vm_flush = &cayman_dma_vm_flush,
1507 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1508 .ib_execute = &cayman_dma_ring_ib_execute,
1509 .ib_parse = &evergreen_dma_ib_parse,
1510 .emit_fence = &evergreen_dma_fence_ring_emit,
1511 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1512 .cs_parse = &evergreen_dma_cs_parse,
1513 .ring_test = &r600_dma_ring_test,
1514 .ib_test = &r600_dma_ib_test,
1515 .is_lockup = &cayman_dma_is_lockup,
1516 .vm_flush = &cayman_dma_vm_flush,
1520 .set = &evergreen_irq_set,
1521 .process = &evergreen_irq_process,
1524 .bandwidth_update = &evergreen_bandwidth_update,
1525 .get_vblank_counter = &evergreen_get_vblank_counter,
1526 .wait_for_vblank = &dce4_wait_for_vblank,
1527 .set_backlight_level = &atombios_set_backlight_level,
1528 .get_backlight_level = &atombios_get_backlight_level,
1531 .blit = &r600_copy_blit,
1532 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1533 .dma = &evergreen_copy_dma,
1534 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1535 .copy = &evergreen_copy_dma,
1536 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1539 .set_reg = r600_set_surface_reg,
1540 .clear_reg = r600_clear_surface_reg,
1543 .init = &evergreen_hpd_init,
1544 .fini = &evergreen_hpd_fini,
1545 .sense = &evergreen_hpd_sense,
1546 .set_polarity = &evergreen_hpd_set_polarity,
1549 .misc = &evergreen_pm_misc,
1550 .prepare = &evergreen_pm_prepare,
1551 .finish = &evergreen_pm_finish,
1552 .init_profile = &btc_pm_init_profile,
1553 .get_dynpm_state = &r600_pm_get_dynpm_state,
1554 .get_engine_clock = &radeon_atom_get_engine_clock,
1555 .set_engine_clock = &radeon_atom_set_engine_clock,
1556 .get_memory_clock = &radeon_atom_get_memory_clock,
1557 .set_memory_clock = &radeon_atom_set_memory_clock,
1558 .get_pcie_lanes = NULL,
1559 .set_pcie_lanes = NULL,
1560 .set_clock_gating = NULL,
1563 .pre_page_flip = &evergreen_pre_page_flip,
1564 .page_flip = &evergreen_page_flip,
1565 .post_page_flip = &evergreen_post_page_flip,
1569 static struct radeon_asic trinity_asic = {
1570 .init = &cayman_init,
1571 .fini = &cayman_fini,
1572 .suspend = &cayman_suspend,
1573 .resume = &cayman_resume,
1574 .asic_reset = &cayman_asic_reset,
1575 .vga_set_state = &r600_vga_set_state,
1576 .ioctl_wait_idle = r600_ioctl_wait_idle,
1577 .gui_idle = &r600_gui_idle,
1578 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1579 .get_xclk = &r600_get_xclk,
1580 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1582 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1583 .set_page = &rs600_gart_set_page,
1586 .init = &cayman_vm_init,
1587 .fini = &cayman_vm_fini,
1588 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1589 .set_page = &cayman_vm_set_page,
1592 [RADEON_RING_TYPE_GFX_INDEX] = {
1593 .ib_execute = &cayman_ring_ib_execute,
1594 .ib_parse = &evergreen_ib_parse,
1595 .emit_fence = &cayman_fence_ring_emit,
1596 .emit_semaphore = &r600_semaphore_ring_emit,
1597 .cs_parse = &evergreen_cs_parse,
1598 .ring_test = &r600_ring_test,
1599 .ib_test = &r600_ib_test,
1600 .is_lockup = &cayman_gfx_is_lockup,
1601 .vm_flush = &cayman_vm_flush,
1603 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1604 .ib_execute = &cayman_ring_ib_execute,
1605 .ib_parse = &evergreen_ib_parse,
1606 .emit_fence = &cayman_fence_ring_emit,
1607 .emit_semaphore = &r600_semaphore_ring_emit,
1608 .cs_parse = &evergreen_cs_parse,
1609 .ring_test = &r600_ring_test,
1610 .ib_test = &r600_ib_test,
1611 .is_lockup = &cayman_gfx_is_lockup,
1612 .vm_flush = &cayman_vm_flush,
1614 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1615 .ib_execute = &cayman_ring_ib_execute,
1616 .ib_parse = &evergreen_ib_parse,
1617 .emit_fence = &cayman_fence_ring_emit,
1618 .emit_semaphore = &r600_semaphore_ring_emit,
1619 .cs_parse = &evergreen_cs_parse,
1620 .ring_test = &r600_ring_test,
1621 .ib_test = &r600_ib_test,
1622 .is_lockup = &cayman_gfx_is_lockup,
1623 .vm_flush = &cayman_vm_flush,
1625 [R600_RING_TYPE_DMA_INDEX] = {
1626 .ib_execute = &cayman_dma_ring_ib_execute,
1627 .ib_parse = &evergreen_dma_ib_parse,
1628 .emit_fence = &evergreen_dma_fence_ring_emit,
1629 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1630 .cs_parse = &evergreen_dma_cs_parse,
1631 .ring_test = &r600_dma_ring_test,
1632 .ib_test = &r600_dma_ib_test,
1633 .is_lockup = &cayman_dma_is_lockup,
1634 .vm_flush = &cayman_dma_vm_flush,
1636 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1637 .ib_execute = &cayman_dma_ring_ib_execute,
1638 .ib_parse = &evergreen_dma_ib_parse,
1639 .emit_fence = &evergreen_dma_fence_ring_emit,
1640 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1641 .cs_parse = &evergreen_dma_cs_parse,
1642 .ring_test = &r600_dma_ring_test,
1643 .ib_test = &r600_dma_ib_test,
1644 .is_lockup = &cayman_dma_is_lockup,
1645 .vm_flush = &cayman_dma_vm_flush,
1649 .set = &evergreen_irq_set,
1650 .process = &evergreen_irq_process,
1653 .bandwidth_update = &dce6_bandwidth_update,
1654 .get_vblank_counter = &evergreen_get_vblank_counter,
1655 .wait_for_vblank = &dce4_wait_for_vblank,
1656 .set_backlight_level = &atombios_set_backlight_level,
1657 .get_backlight_level = &atombios_get_backlight_level,
1660 .blit = &r600_copy_blit,
1661 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1662 .dma = &evergreen_copy_dma,
1663 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1664 .copy = &evergreen_copy_dma,
1665 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1668 .set_reg = r600_set_surface_reg,
1669 .clear_reg = r600_clear_surface_reg,
1672 .init = &evergreen_hpd_init,
1673 .fini = &evergreen_hpd_fini,
1674 .sense = &evergreen_hpd_sense,
1675 .set_polarity = &evergreen_hpd_set_polarity,
1678 .misc = &evergreen_pm_misc,
1679 .prepare = &evergreen_pm_prepare,
1680 .finish = &evergreen_pm_finish,
1681 .init_profile = &sumo_pm_init_profile,
1682 .get_dynpm_state = &r600_pm_get_dynpm_state,
1683 .get_engine_clock = &radeon_atom_get_engine_clock,
1684 .set_engine_clock = &radeon_atom_set_engine_clock,
1685 .get_memory_clock = NULL,
1686 .set_memory_clock = NULL,
1687 .get_pcie_lanes = NULL,
1688 .set_pcie_lanes = NULL,
1689 .set_clock_gating = NULL,
1692 .pre_page_flip = &evergreen_pre_page_flip,
1693 .page_flip = &evergreen_page_flip,
1694 .post_page_flip = &evergreen_post_page_flip,
1698 static struct radeon_asic si_asic = {
1701 .suspend = &si_suspend,
1702 .resume = &si_resume,
1703 .asic_reset = &si_asic_reset,
1704 .vga_set_state = &r600_vga_set_state,
1705 .ioctl_wait_idle = r600_ioctl_wait_idle,
1706 .gui_idle = &r600_gui_idle,
1707 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1708 .get_xclk = &si_get_xclk,
1709 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1711 .tlb_flush = &si_pcie_gart_tlb_flush,
1712 .set_page = &rs600_gart_set_page,
1715 .init = &si_vm_init,
1716 .fini = &si_vm_fini,
1717 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1718 .set_page = &si_vm_set_page,
1721 [RADEON_RING_TYPE_GFX_INDEX] = {
1722 .ib_execute = &si_ring_ib_execute,
1723 .ib_parse = &si_ib_parse,
1724 .emit_fence = &si_fence_ring_emit,
1725 .emit_semaphore = &r600_semaphore_ring_emit,
1727 .ring_test = &r600_ring_test,
1728 .ib_test = &r600_ib_test,
1729 .is_lockup = &si_gfx_is_lockup,
1730 .vm_flush = &si_vm_flush,
1732 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1733 .ib_execute = &si_ring_ib_execute,
1734 .ib_parse = &si_ib_parse,
1735 .emit_fence = &si_fence_ring_emit,
1736 .emit_semaphore = &r600_semaphore_ring_emit,
1738 .ring_test = &r600_ring_test,
1739 .ib_test = &r600_ib_test,
1740 .is_lockup = &si_gfx_is_lockup,
1741 .vm_flush = &si_vm_flush,
1743 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1744 .ib_execute = &si_ring_ib_execute,
1745 .ib_parse = &si_ib_parse,
1746 .emit_fence = &si_fence_ring_emit,
1747 .emit_semaphore = &r600_semaphore_ring_emit,
1749 .ring_test = &r600_ring_test,
1750 .ib_test = &r600_ib_test,
1751 .is_lockup = &si_gfx_is_lockup,
1752 .vm_flush = &si_vm_flush,
1754 [R600_RING_TYPE_DMA_INDEX] = {
1755 .ib_execute = &cayman_dma_ring_ib_execute,
1756 .ib_parse = &evergreen_dma_ib_parse,
1757 .emit_fence = &evergreen_dma_fence_ring_emit,
1758 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1760 .ring_test = &r600_dma_ring_test,
1761 .ib_test = &r600_dma_ib_test,
1762 .is_lockup = &si_dma_is_lockup,
1763 .vm_flush = &si_dma_vm_flush,
1765 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1766 .ib_execute = &cayman_dma_ring_ib_execute,
1767 .ib_parse = &evergreen_dma_ib_parse,
1768 .emit_fence = &evergreen_dma_fence_ring_emit,
1769 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1771 .ring_test = &r600_dma_ring_test,
1772 .ib_test = &r600_dma_ib_test,
1773 .is_lockup = &si_dma_is_lockup,
1774 .vm_flush = &si_dma_vm_flush,
1779 .process = &si_irq_process,
1782 .bandwidth_update = &dce6_bandwidth_update,
1783 .get_vblank_counter = &evergreen_get_vblank_counter,
1784 .wait_for_vblank = &dce4_wait_for_vblank,
1785 .set_backlight_level = &atombios_set_backlight_level,
1786 .get_backlight_level = &atombios_get_backlight_level,
1790 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1791 .dma = &si_copy_dma,
1792 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1793 .copy = &si_copy_dma,
1794 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1797 .set_reg = r600_set_surface_reg,
1798 .clear_reg = r600_clear_surface_reg,
1801 .init = &evergreen_hpd_init,
1802 .fini = &evergreen_hpd_fini,
1803 .sense = &evergreen_hpd_sense,
1804 .set_polarity = &evergreen_hpd_set_polarity,
1807 .misc = &evergreen_pm_misc,
1808 .prepare = &evergreen_pm_prepare,
1809 .finish = &evergreen_pm_finish,
1810 .init_profile = &sumo_pm_init_profile,
1811 .get_dynpm_state = &r600_pm_get_dynpm_state,
1812 .get_engine_clock = &radeon_atom_get_engine_clock,
1813 .set_engine_clock = &radeon_atom_set_engine_clock,
1814 .get_memory_clock = &radeon_atom_get_memory_clock,
1815 .set_memory_clock = &radeon_atom_set_memory_clock,
1816 .get_pcie_lanes = NULL,
1817 .set_pcie_lanes = NULL,
1818 .set_clock_gating = NULL,
1821 .pre_page_flip = &evergreen_pre_page_flip,
1822 .page_flip = &evergreen_page_flip,
1823 .post_page_flip = &evergreen_post_page_flip,
1828 * radeon_asic_init - register asic specific callbacks
1830 * @rdev: radeon device pointer
1832 * Registers the appropriate asic specific callbacks for each
1833 * chip family. Also sets other asics specific info like the number
1834 * of crtcs and the register aperture accessors (all asics).
1835 * Returns 0 for success.
1837 int radeon_asic_init(struct radeon_device *rdev)
1839 radeon_register_accessor_init(rdev);
1841 /* set the number of crtcs */
1842 if (rdev->flags & RADEON_SINGLE_CRTC)
1847 switch (rdev->family) {
1853 rdev->asic = &r100_asic;
1859 rdev->asic = &r200_asic;
1865 if (rdev->flags & RADEON_IS_PCIE)
1866 rdev->asic = &r300_asic_pcie;
1868 rdev->asic = &r300_asic;
1873 rdev->asic = &r420_asic;
1875 if (rdev->bios == NULL) {
1876 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
1877 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
1878 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
1879 rdev->asic->pm.set_memory_clock = NULL;
1880 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
1885 rdev->asic = &rs400_asic;
1888 rdev->asic = &rs600_asic;
1892 rdev->asic = &rs690_asic;
1895 rdev->asic = &rv515_asic;
1902 rdev->asic = &r520_asic;
1910 rdev->asic = &r600_asic;
1914 rdev->asic = &rs780_asic;
1920 rdev->asic = &rv770_asic;
1928 if (rdev->family == CHIP_CEDAR)
1932 rdev->asic = &evergreen_asic;
1937 rdev->asic = &sumo_asic;
1943 if (rdev->family == CHIP_CAICOS)
1947 rdev->asic = &btc_asic;
1950 rdev->asic = &cayman_asic;
1955 rdev->asic = &trinity_asic;
1963 rdev->asic = &si_asic;
1965 if (rdev->family == CHIP_OLAND)
1971 /* FIXME: not supported yet */
1975 if (rdev->flags & RADEON_IS_IGP) {
1976 rdev->asic->pm.get_memory_clock = NULL;
1977 rdev->asic->pm.set_memory_clock = NULL;