90be9517c658db7512fc8e3ae261f6528dfe4aa9
[dragonfly.git] / sys / dev / netif / gx / if_gx.c
1 /*-
2  * Copyright (c) 1999,2000,2001 Jonathan Lemon
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the author nor the names of any co-contributors
14  *    may be used to endorse or promote products derived from this software
15  *    without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $FreeBSD: src/sys/dev/gx/if_gx.c,v 1.2.2.3 2001/12/14 19:51:39 jlemon Exp $
30  * $DragonFly: src/sys/dev/netif/gx/Attic/if_gx.c,v 1.28 2007/08/14 13:30:35 sephe Exp $
31  */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/serialize.h>
42 #include <sys/bus.h>
43 #include <sys/rman.h>
44 #include <sys/thread2.h>
45
46 #include <net/if.h>
47 #include <net/ifq_var.h>
48 #include <net/if_arp.h>
49 #include <net/ethernet.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52
53 #include <net/bpf.h>
54 #include <net/if_types.h>
55 #include <net/vlan/if_vlan_var.h>
56
57 #include <netinet/in_systm.h>
58 #include <netinet/in.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
61 #include <netinet/udp.h>
62
63 #include <vm/vm.h>              /* for vtophys */
64 #include <vm/pmap.h>            /* for vtophys */
65 #include <machine/clock.h>      /* for DELAY */
66
67 #include <bus/pci/pcidevs.h>
68 #include <bus/pci/pcireg.h>
69 #include <bus/pci/pcivar.h>
70
71 #include "../mii_layer/mii.h"
72 #include "../mii_layer/miivar.h"
73
74 #include "if_gxreg.h"
75 #include "if_gxvar.h"
76
77 #include "miibus_if.h"
78
79 #define TUNABLE_TX_INTR_DELAY   100
80 #define TUNABLE_RX_INTR_DELAY   100
81
82 #define GX_CSUM_FEATURES        (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
83
84 /*
85  * Various supported device vendors/types and their names.
86  */
87 struct gx_device {
88         u_int16_t       vendor;
89         u_int16_t       device;
90         int             version_flags;
91         u_int32_t       version_ipg;
92         char            *name;
93 };
94
95 static struct gx_device gx_devs[] = {
96         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542,
97             GXF_FORCE_TBI | GXF_OLD_REGS,
98             10 | 2 << 10 | 10 << 20,
99             "Intel Gigabit Ethernet (82542)" },
100         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER,
101             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
102             6 | 8 << 10 | 6 << 20,
103             "Intel Gigabit Ethernet (82543GC-F)" },
104         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER,
105             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
106             8 | 8 << 10 | 6 << 20,
107             "Intel Gigabit Ethernet (82543GC-T)" },
108 #if 0
109 /* notyet.. */
110         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER,
111             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
112             6 | 8 << 10 | 6 << 20,
113             "Intel Gigabit Ethernet (82544EI-F)" },
114         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER,
115             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
116             8 | 8 << 10 | 6 << 20,
117             "Intel Gigabit Ethernet (82544EI-T)" },
118         { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM,
119             GXF_DMA | GXF_ENABLE_MWI | GXF_CSUM,
120             8 | 8 << 10 | 6 << 20,
121             "Intel Gigabit Ethernet (82544GC-T)" },
122 #endif
123         { 0, 0, 0, NULL }
124 };
125
126 static struct gx_regs new_regs = {
127         GX_RX_RING_BASE, GX_RX_RING_LEN,
128         GX_RX_RING_HEAD, GX_RX_RING_TAIL,
129         GX_RX_INTR_DELAY, GX_RX_DMA_CTRL,
130
131         GX_TX_RING_BASE, GX_TX_RING_LEN,
132         GX_TX_RING_HEAD, GX_TX_RING_TAIL,
133         GX_TX_INTR_DELAY, GX_TX_DMA_CTRL,
134 };
135 static struct gx_regs old_regs = {
136         GX_RX_OLD_RING_BASE, GX_RX_OLD_RING_LEN,
137         GX_RX_OLD_RING_HEAD, GX_RX_OLD_RING_TAIL,
138         GX_RX_OLD_INTR_DELAY, GX_RX_OLD_DMA_CTRL,
139
140         GX_TX_OLD_RING_BASE, GX_TX_OLD_RING_LEN,
141         GX_TX_OLD_RING_HEAD, GX_TX_OLD_RING_TAIL,
142         GX_TX_OLD_INTR_DELAY, GX_TX_OLD_DMA_CTRL,
143 };
144
145 static int      gx_probe(device_t dev);
146 static int      gx_attach(device_t dev);
147 static int      gx_detach(device_t dev);
148 static void     gx_shutdown(device_t dev);
149
150 static void     gx_intr(void *xsc);
151 static void     gx_init(void *xsc);
152
153 static struct   gx_device *gx_match(device_t dev);
154 static void     gx_eeprom_getword(struct gx_softc *gx, int addr,
155                     u_int16_t *dest);
156 static int      gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off,
157                     int cnt);
158 static int      gx_ifmedia_upd(struct ifnet *ifp);
159 static void     gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
160 static int      gx_miibus_readreg(device_t dev, int phy, int reg);
161 static void     gx_miibus_writereg(device_t dev, int phy, int reg, int value);
162 static void     gx_miibus_statchg(device_t dev);
163 static int      gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
164                     struct ucred *);
165 static void     gx_setmulti(struct gx_softc *gx);
166 static void     gx_reset(struct gx_softc *gx);
167 static void     gx_phy_reset(struct gx_softc *gx);
168 static void     gx_stop(struct gx_softc *gx);
169 static void     gx_watchdog(struct ifnet *ifp);
170 static void     gx_start(struct ifnet *ifp);
171
172 static int      gx_init_rx_ring(struct gx_softc *gx);
173 static void     gx_free_rx_ring(struct gx_softc *gx);
174 static int      gx_init_tx_ring(struct gx_softc *gx);
175 static void     gx_free_tx_ring(struct gx_softc *gx);
176
177 static device_method_t gx_methods[] = {
178         /* Device interface */
179         DEVMETHOD(device_probe,         gx_probe),
180         DEVMETHOD(device_attach,        gx_attach),
181         DEVMETHOD(device_detach,        gx_detach),
182         DEVMETHOD(device_shutdown,      gx_shutdown),
183
184         /* MII interface */
185         DEVMETHOD(miibus_readreg,       gx_miibus_readreg),
186         DEVMETHOD(miibus_writereg,      gx_miibus_writereg),
187         DEVMETHOD(miibus_statchg,       gx_miibus_statchg),
188
189         { 0, 0 }
190 };
191
192 static driver_t gx_driver = {
193         "gx",
194         gx_methods,
195         sizeof(struct gx_softc)
196 };
197
198 static devclass_t gx_devclass;
199
200 DECLARE_DUMMY_MODULE(if_gx);
201 MODULE_DEPEND(if_gx, miibus, 1, 1, 1);
202 DRIVER_MODULE(if_gx, pci, gx_driver, gx_devclass, 0, 0);
203 DRIVER_MODULE(miibus, gx, miibus_driver, miibus_devclass, 0, 0);
204
205 static struct gx_device *
206 gx_match(device_t dev)
207 {
208         int i;
209
210         for (i = 0; gx_devs[i].name != NULL; i++) {
211                 if ((pci_get_vendor(dev) == gx_devs[i].vendor) &&
212                     (pci_get_device(dev) == gx_devs[i].device))
213                         return (&gx_devs[i]);
214         }
215         return (NULL);
216 }
217
218 static int
219 gx_probe(device_t dev)
220 {
221         struct gx_device *gx_dev;
222
223         gx_dev = gx_match(dev);
224         if (gx_dev == NULL)
225                 return (ENXIO);
226
227         device_set_desc(dev, gx_dev->name);
228         return (0);
229 }
230
231 static int
232 gx_attach(device_t dev)
233 {
234         struct gx_softc *gx;
235         struct gx_device *gx_dev;
236         struct ifnet *ifp;
237         u_int32_t command;
238         int rid;
239         int error = 0;
240
241         gx = device_get_softc(dev);
242         gx->gx_dev = dev;
243
244         gx_dev = gx_match(dev);
245         gx->gx_vflags = gx_dev->version_flags;
246         gx->gx_ipg = gx_dev->version_ipg;
247
248         /*
249          * Map control/status registers.
250          */
251         command = pci_read_config(dev, PCIR_COMMAND, 4);
252         command |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
253         if (gx->gx_vflags & GXF_ENABLE_MWI)
254                 command |= PCIM_CMD_MWIEN;
255         pci_write_config(dev, PCIR_COMMAND, command, 4);
256         command = pci_read_config(dev, PCIR_COMMAND, 4);
257
258 /* XXX check cache line size? */
259
260         if ((command & PCIM_CMD_MEMEN) == 0) {
261                 device_printf(dev, "failed to enable memory mapping!\n");
262                 error = ENXIO;
263                 goto fail;
264         }
265
266         rid = GX_PCI_LOMEM;
267         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
268             RF_ACTIVE);
269 #if 0
270 /* support PIO mode */
271         rid = PCI_LOIO;
272         gx->gx_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
273             RF_ACTIVE);
274 #endif
275
276         if (gx->gx_res == NULL) {
277                 device_printf(dev, "couldn't map memory\n");
278                 error = ENXIO;
279                 goto fail;
280         }
281
282         gx->gx_btag = rman_get_bustag(gx->gx_res);
283         gx->gx_bhandle = rman_get_bushandle(gx->gx_res);
284
285         /* Allocate interrupt */
286         rid = 0;
287         gx->gx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
288             RF_SHAREABLE | RF_ACTIVE);
289
290         if (gx->gx_irq == NULL) {
291                 device_printf(dev, "couldn't map interrupt\n");
292                 error = ENXIO;
293                 goto fail;
294         }
295
296         /* compensate for different register mappings */
297         if (gx->gx_vflags & GXF_OLD_REGS)
298                 gx->gx_reg = old_regs;
299         else
300                 gx->gx_reg = new_regs;
301
302         if (gx_read_eeprom(gx, (caddr_t)&gx->arpcom.ac_enaddr,
303             GX_EEMAP_MAC, 3)) {
304                 device_printf(dev, "failed to read station address\n");
305                 error = ENXIO;
306                 goto fail;
307         }
308
309         /* Allocate the ring buffers. */
310         gx->gx_rdata = contigmalloc(sizeof(struct gx_ring_data), M_DEVBUF,
311             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
312
313         if (gx->gx_rdata == NULL) {
314                 device_printf(dev, "no memory for list buffers!\n");
315                 error = ENXIO;
316                 goto fail;
317         }
318         bzero(gx->gx_rdata, sizeof(struct gx_ring_data));
319
320         /* Set default tuneable values. */
321         gx->gx_tx_intr_delay = TUNABLE_TX_INTR_DELAY;
322         gx->gx_rx_intr_delay = TUNABLE_RX_INTR_DELAY;
323
324         /* Set up ifnet structure */
325         ifp = &gx->arpcom.ac_if;
326         ifp->if_softc = gx;
327         if_initname(ifp, "gx", device_get_unit(dev));
328         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
329         ifp->if_ioctl = gx_ioctl;
330         ifp->if_start = gx_start;
331         ifp->if_watchdog = gx_watchdog;
332         ifp->if_init = gx_init;
333         ifp->if_mtu = ETHERMTU;
334         ifq_set_maxlen(&ifp->if_snd, GX_TX_RING_CNT - 1);
335         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING;
336         ifq_set_ready(&ifp->if_snd);
337
338         /* see if we can enable hardware checksumming */
339         if (gx->gx_vflags & GXF_CSUM) {
340                 ifp->if_capabilities |= IFCAP_HWCSUM;
341                 ifp->if_capenable = ifp->if_capabilities;
342         }
343
344         /* figure out transciever type */
345         if (gx->gx_vflags & GXF_FORCE_TBI ||
346             CSR_READ_4(gx, GX_STATUS) & GX_STAT_TBIMODE)
347                 gx->gx_tbimode = 1;
348
349         if (gx->gx_tbimode) {
350                 /* SERDES transceiver */
351                 ifmedia_init(&gx->gx_media, IFM_IMASK, gx_ifmedia_upd,
352                     gx_ifmedia_sts);
353                 ifmedia_add(&gx->gx_media,
354                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
355                 ifmedia_add(&gx->gx_media, IFM_ETHER|IFM_AUTO, 0, NULL);
356                 ifmedia_set(&gx->gx_media, IFM_ETHER|IFM_AUTO);
357         } else {
358                 /* GMII/MII transceiver */
359                 gx_phy_reset(gx);
360                 if (mii_phy_probe(dev, &gx->gx_miibus, gx_ifmedia_upd,
361                     gx_ifmedia_sts)) {
362                         device_printf(dev, "GMII/MII, PHY not detected\n");
363                         error = ENXIO;
364                         goto fail;
365                 }
366         }
367
368         /*
369          * Call MI attach routines.
370          */
371         ether_ifattach(ifp, gx->arpcom.ac_enaddr, NULL);
372
373         error = bus_setup_intr(dev, gx->gx_irq, INTR_NETSAFE,
374                                gx_intr, gx, &gx->gx_intrhand, 
375                                ifp->if_serializer);
376         if (error) {
377                 ether_ifdetach(ifp);
378                 device_printf(dev, "couldn't setup irq\n");
379                 goto fail;
380         }
381
382         return (0);
383
384 fail:
385         gx_detach(dev);
386         return (error);
387 }
388
389 static void
390 gx_init(void *xsc)
391 {
392         struct gx_softc *gx = (struct gx_softc *)xsc;
393         struct ifmedia *ifm;
394         struct ifnet *ifp = &gx->arpcom.ac_if;
395         u_int16_t *m;
396         u_int32_t ctrl;
397         int i, tmp;
398
399         /* Disable host interrupts, halt chip. */
400         gx_reset(gx);
401
402         /* disable I/O, flush RX/TX FIFOs, and free RX/TX buffers */
403         gx_stop(gx);
404
405         /* Load our MAC address, invalidate other 15 RX addresses. */
406         m = (u_int16_t *)&gx->arpcom.ac_enaddr[0];
407         CSR_WRITE_4(gx, GX_RX_ADDR_BASE, (m[1] << 16) | m[0]);
408         CSR_WRITE_4(gx, GX_RX_ADDR_BASE + 4, m[2] | GX_RA_VALID);
409         for (i = 1; i < 16; i++)
410                 CSR_WRITE_8(gx, GX_RX_ADDR_BASE + i * 8, (u_quad_t)0);
411
412         /* Program multicast filter. */
413         gx_setmulti(gx);
414
415         /* Init RX ring. */
416         gx_init_rx_ring(gx);
417
418         /* Init TX ring. */
419         gx_init_tx_ring(gx);
420
421         if (gx->gx_vflags & GXF_DMA) {
422                 /* set up DMA control */        
423                 CSR_WRITE_4(gx, gx->gx_reg.r_rx_dma_ctrl, 0x00010000);
424                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_dma_ctrl, 0x00000000);
425         }
426
427         /* enable receiver */
428         ctrl = GX_RXC_ENABLE | GX_RXC_RX_THOLD_EIGHTH | GX_RXC_RX_BSIZE_2K;
429         ctrl |= GX_RXC_BCAST_ACCEPT;
430
431         /* Enable or disable promiscuous mode as needed. */
432         if (ifp->if_flags & IFF_PROMISC)
433                 ctrl |= GX_RXC_UNI_PROMISC;
434
435         /* This is required if we want to accept jumbo frames */
436         if (ifp->if_mtu > ETHERMTU)
437                 ctrl |= GX_RXC_LONG_PKT_ENABLE;
438
439         /* setup receive checksum control */
440         if (ifp->if_capenable & IFCAP_RXCSUM)
441                 CSR_WRITE_4(gx, GX_RX_CSUM_CONTROL,
442                     GX_CSUM_TCP/* | GX_CSUM_IP*/);
443
444         /* setup transmit checksum control */
445         if (ifp->if_capenable & IFCAP_TXCSUM)
446                 ifp->if_hwassist = GX_CSUM_FEATURES;
447
448         ctrl |= GX_RXC_STRIP_ETHERCRC;          /* not on 82542? */
449         CSR_WRITE_4(gx, GX_RX_CONTROL, ctrl);
450
451         /* enable transmitter */
452         ctrl = GX_TXC_ENABLE | GX_TXC_PAD_SHORT_PKTS | GX_TXC_COLL_RETRY_16;
453
454         /* XXX we should support half-duplex here too... */
455         ctrl |= GX_TXC_COLL_TIME_FDX;
456
457         CSR_WRITE_4(gx, GX_TX_CONTROL, ctrl);
458
459         /*
460          * set up recommended IPG times, which vary depending on chip type:
461          *      IPG transmit time:  80ns
462          *      IPG receive time 1: 20ns
463          *      IPG receive time 2: 80ns
464          */
465         CSR_WRITE_4(gx, GX_TX_IPG, gx->gx_ipg);
466
467         /* set up 802.3x MAC flow control address -- 01:80:c2:00:00:01 */
468         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE, 0x00C28001);
469         CSR_WRITE_4(gx, GX_FLOW_CTRL_BASE+4, 0x00000100);
470
471         /* set up 802.3x MAC flow control type -- 88:08 */
472         CSR_WRITE_4(gx, GX_FLOW_CTRL_TYPE, 0x8808);
473
474         /* Set up tuneables */
475         CSR_WRITE_4(gx, gx->gx_reg.r_rx_delay, gx->gx_rx_intr_delay);
476         CSR_WRITE_4(gx, gx->gx_reg.r_tx_delay, gx->gx_tx_intr_delay);
477
478         /*
479          * Configure chip for correct operation.
480          */
481         ctrl = GX_CTRL_DUPLEX;
482 #if BYTE_ORDER == BIG_ENDIAN
483         ctrl |= GX_CTRL_BIGENDIAN;
484 #endif
485         ctrl |= GX_CTRL_VLAN_ENABLE;
486
487         if (gx->gx_tbimode) {
488                 /*
489                  * It seems that TXCW must be initialized from the EEPROM
490                  * manually.
491                  *
492                  * XXX
493                  * should probably read the eeprom and re-insert the
494                  * values here.
495                  */
496 #define TXCONFIG_WORD   0x000001A0
497                 CSR_WRITE_4(gx, GX_TX_CONFIG, TXCONFIG_WORD);
498
499                 /* turn on hardware autonegotiate */
500                 GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
501         } else {
502                 /*
503                  * Auto-detect speed from PHY, instead of using direct
504                  * indication.  The SLU bit doesn't force the link, but
505                  * must be present for ASDE to work.
506                  */
507                 gx_phy_reset(gx);
508                 ctrl |= GX_CTRL_SET_LINK_UP | GX_CTRL_AUTOSPEED;
509         }
510
511         /*
512          * Take chip out of reset and start it running.
513          */
514         CSR_WRITE_4(gx, GX_CTRL, ctrl);
515
516         /* Turn interrupts on. */
517         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
518
519         ifp->if_flags |= IFF_RUNNING;
520         ifp->if_flags &= ~IFF_OACTIVE;
521
522         /*
523          * Set the current media.
524          */
525         if (gx->gx_miibus != NULL) {
526                 mii_mediachg(device_get_softc(gx->gx_miibus));
527         } else {
528                 ifm = &gx->gx_media;
529                 tmp = ifm->ifm_media;
530                 ifm->ifm_media = ifm->ifm_cur->ifm_media;
531                 gx_ifmedia_upd(ifp);
532                 ifm->ifm_media = tmp;
533         }
534
535         /*
536          * XXX
537          * Have the LINK0 flag force the link in TBI mode.
538          */
539         if (gx->gx_tbimode && ifp->if_flags & IFF_LINK0) {
540                 GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
541                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
542         }
543
544 #if 0
545 kprintf("66mhz: %s  64bit: %s\n",
546         CSR_READ_4(gx, GX_STATUS) & GX_STAT_PCI66 ? "yes" : "no",
547         CSR_READ_4(gx, GX_STATUS) & GX_STAT_BUS64 ? "yes" : "no");
548 #endif
549 }
550
551 /*
552  * Stop all chip I/O so that the kernel's probe routines don't
553  * get confused by errant DMAs when rebooting.
554  */
555 static void
556 gx_shutdown(device_t dev)
557 {
558         struct gx_softc *gx;
559
560         gx = device_get_softc(dev);
561         gx_reset(gx);
562         gx_stop(gx);
563 }
564
565 static int
566 gx_detach(device_t dev)
567 {
568         struct gx_softc *gx = device_get_softc(dev);
569         struct ifnet *ifp = &gx->arpcom.ac_if;
570
571         if (device_is_attached(dev)) {
572                 lwkt_serialize_enter(ifp->if_serializer);
573                 gx_reset(gx);
574                 gx_stop(gx);
575                 bus_teardown_intr(gx->gx_dev, gx->gx_irq, gx->gx_intrhand);
576                 lwkt_serialize_exit(ifp->if_serializer);
577
578                 ether_ifdetach(ifp);
579         }
580         if (gx->gx_miibus)
581                 device_delete_child(gx->gx_dev, gx->gx_miibus);
582         bus_generic_detach(gx->gx_dev);
583
584         if (gx->gx_irq)
585                 bus_release_resource(gx->gx_dev, SYS_RES_IRQ, 0, gx->gx_irq);
586         if (gx->gx_res)
587                 bus_release_resource(gx->gx_dev, SYS_RES_MEMORY,
588                     GX_PCI_LOMEM, gx->gx_res);
589
590         if (gx->gx_rdata)
591                 contigfree(gx->gx_rdata, sizeof(struct gx_ring_data),
592                            M_DEVBUF);
593
594         if (gx->gx_tbimode)
595                 ifmedia_removeall(&gx->gx_media);
596
597         return (0);
598 }
599
600 static void
601 gx_eeprom_getword(struct gx_softc *gx, int addr, u_int16_t *dest)
602 {
603         u_int16_t word = 0;
604         u_int32_t base, reg;
605         int x;
606
607         addr = (GX_EE_OPC_READ << GX_EE_ADDR_SIZE) |
608             (addr & ((1 << GX_EE_ADDR_SIZE) - 1));
609
610         base = CSR_READ_4(gx, GX_EEPROM_CTRL);
611         base &= ~(GX_EE_DATA_OUT | GX_EE_DATA_IN | GX_EE_CLOCK);
612         base |= GX_EE_SELECT;
613
614         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
615
616         for (x = 1 << ((GX_EE_OPC_SIZE + GX_EE_ADDR_SIZE) - 1); x; x >>= 1) {
617                 reg = base | (addr & x ? GX_EE_DATA_IN : 0);
618                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
619                 DELAY(10);
620                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg | GX_EE_CLOCK);
621                 DELAY(10);
622                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, reg);
623                 DELAY(10);
624         }
625
626         for (x = 1 << 15; x; x >>= 1) {
627                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base | GX_EE_CLOCK);
628                 DELAY(10);
629                 reg = CSR_READ_4(gx, GX_EEPROM_CTRL);
630                 if (reg & GX_EE_DATA_OUT)
631                         word |= x;
632                 CSR_WRITE_4(gx, GX_EEPROM_CTRL, base);
633                 DELAY(10);
634         }
635
636         CSR_WRITE_4(gx, GX_EEPROM_CTRL, base & ~GX_EE_SELECT);
637         DELAY(10);
638
639         *dest = word;
640 }
641         
642 static int
643 gx_read_eeprom(struct gx_softc *gx, caddr_t dest, int off, int cnt)
644 {
645         u_int16_t *word;
646         int i;
647
648         word = (u_int16_t *)dest;
649         for (i = 0; i < cnt; i ++) {
650                 gx_eeprom_getword(gx, off + i, word);
651                 word++;
652         }
653         return (0);
654 }
655
656 /*
657  * Set media options.
658  */
659 static int
660 gx_ifmedia_upd(struct ifnet *ifp)
661 {
662         struct gx_softc *gx;
663         struct ifmedia *ifm;
664         struct mii_data *mii;
665
666         gx = ifp->if_softc;
667
668         if (gx->gx_tbimode) {
669                 ifm = &gx->gx_media;
670                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
671                         return (EINVAL);
672                 switch (IFM_SUBTYPE(ifm->ifm_media)) {
673                 case IFM_AUTO:
674                         GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
675                         GX_SETBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
676                         GX_CLRBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
677                         break;
678                 case IFM_1000_SX:
679                         device_printf(gx->gx_dev,
680                             "manual config not supported yet.\n");
681 #if 0
682                         GX_CLRBIT(gx, GX_TX_CONFIG, GX_TXCFG_AUTONEG);
683                         config = /* bit symbols for 802.3z */0;
684                         ctrl |= GX_CTRL_SET_LINK_UP;
685                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
686                                 ctrl |= GX_CTRL_DUPLEX;
687 #endif
688                         break;
689                 default:
690                         return (EINVAL);
691                 }
692         } else {
693                 ifm = &gx->gx_media;
694
695                 /*
696                  * 1000TX half duplex does not work.
697                  */
698                 if (IFM_TYPE(ifm->ifm_media) == IFM_ETHER &&
699                     IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T &&
700                     (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) == 0)
701                         return (EINVAL);
702                 mii = device_get_softc(gx->gx_miibus);
703                 mii_mediachg(mii);
704         }
705         return (0);
706 }
707
708 /*
709  * Report current media status.
710  */
711 static void
712 gx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
713 {
714         struct gx_softc *gx;
715         struct mii_data *mii;
716         u_int32_t status;
717
718         gx = ifp->if_softc;
719
720         if (gx->gx_tbimode) {
721                 ifmr->ifm_status = IFM_AVALID;
722                 ifmr->ifm_active = IFM_ETHER;
723
724                 status = CSR_READ_4(gx, GX_STATUS);
725                 if ((status & GX_STAT_LINKUP) == 0)
726                         return;
727
728                 ifmr->ifm_status |= IFM_ACTIVE;
729                 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
730         } else {
731                 mii = device_get_softc(gx->gx_miibus);
732                 mii_pollstat(mii);
733                 if ((mii->mii_media_active & (IFM_1000_T | IFM_HDX)) ==
734                     (IFM_1000_T | IFM_HDX))
735                         mii->mii_media_active = IFM_ETHER | IFM_NONE;
736                 ifmr->ifm_active = mii->mii_media_active;
737                 ifmr->ifm_status = mii->mii_media_status;
738         }
739 }
740
741 static void 
742 gx_mii_shiftin(struct gx_softc *gx, int data, int length)
743 {
744         u_int32_t reg, x;
745
746         /*
747          * Set up default GPIO direction + PHY data out.
748          */
749         reg = CSR_READ_4(gx, GX_CTRL);
750         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
751         reg |= GX_CTRL_GPIO_DIR | GX_CTRL_PHY_IO_DIR;
752
753         /*
754          * Shift in data to PHY.
755          */
756         for (x = 1 << (length - 1); x; x >>= 1) {
757                 if (data & x)
758                         reg |= GX_CTRL_PHY_IO;
759                 else
760                         reg &= ~GX_CTRL_PHY_IO;
761                 CSR_WRITE_4(gx, GX_CTRL, reg);
762                 DELAY(10);
763                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
764                 DELAY(10);
765                 CSR_WRITE_4(gx, GX_CTRL, reg);
766                 DELAY(10);
767         }
768 }
769
770 static u_int16_t 
771 gx_mii_shiftout(struct gx_softc *gx)
772 {
773         u_int32_t reg;
774         u_int16_t data;
775         int x;
776
777         /*
778          * Set up default GPIO direction + PHY data in.
779          */
780         reg = CSR_READ_4(gx, GX_CTRL);
781         reg &= ~(GX_CTRL_GPIO_DIR_MASK | GX_CTRL_PHY_IO | GX_CTRL_PHY_CLK);
782         reg |= GX_CTRL_GPIO_DIR;
783
784         CSR_WRITE_4(gx, GX_CTRL, reg);
785         DELAY(10);
786         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
787         DELAY(10);
788         CSR_WRITE_4(gx, GX_CTRL, reg);
789         DELAY(10);
790         /*
791          * Shift out data from PHY.
792          */
793         data = 0;
794         for (x = 1 << 15; x; x >>= 1) {
795                 CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
796                 DELAY(10);
797                 if (CSR_READ_4(gx, GX_CTRL) & GX_CTRL_PHY_IO)
798                         data |= x;
799                 CSR_WRITE_4(gx, GX_CTRL, reg);
800                 DELAY(10);
801         }
802         CSR_WRITE_4(gx, GX_CTRL, reg | GX_CTRL_PHY_CLK);
803         DELAY(10);
804         CSR_WRITE_4(gx, GX_CTRL, reg);
805         DELAY(10);
806
807         return (data);
808 }
809
810 static int
811 gx_miibus_readreg(device_t dev, int phy, int reg)
812 {
813         struct gx_softc *gx;
814
815         gx = device_get_softc(dev);
816         if (gx->gx_tbimode)
817                 return (0);
818
819         /*
820          * XXX
821          * Note: Cordova has a MDIC register. livingood and < have mii bits
822          */ 
823
824         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
825         gx_mii_shiftin(gx, (GX_PHY_SOF << 12) | (GX_PHY_OP_READ << 10) |
826             (phy << 5) | reg, GX_PHY_READ_LEN);
827         return (gx_mii_shiftout(gx));
828 }
829
830 static void
831 gx_miibus_writereg(device_t dev, int phy, int reg, int value)
832 {
833         struct gx_softc *gx;
834
835         gx = device_get_softc(dev);
836         if (gx->gx_tbimode)
837                 return;
838
839         gx_mii_shiftin(gx, GX_PHY_PREAMBLE, GX_PHY_PREAMBLE_LEN);
840         gx_mii_shiftin(gx, (GX_PHY_SOF << 30) | (GX_PHY_OP_WRITE << 28) |
841             (phy << 23) | (reg << 18) | (GX_PHY_TURNAROUND << 16) |
842             (value & 0xffff), GX_PHY_WRITE_LEN);
843 }
844
845 static void
846 gx_miibus_statchg(device_t dev)
847 {
848         struct gx_softc *gx = device_get_softc(dev);
849         struct mii_data *mii;
850         int reg;
851
852         if (gx->gx_tbimode)
853                 return;
854
855         /*
856          * Set flow control behavior to mirror what PHY negotiated.
857          */
858         mii = device_get_softc(gx->gx_miibus);
859
860         reg = CSR_READ_4(gx, GX_CTRL);
861         if (mii->mii_media_active & IFM_FLAG0)
862                 reg |= GX_CTRL_RX_FLOWCTRL;
863         else
864                 reg &= ~GX_CTRL_RX_FLOWCTRL;
865         if (mii->mii_media_active & IFM_FLAG1)
866                 reg |= GX_CTRL_TX_FLOWCTRL;
867         else
868                 reg &= ~GX_CTRL_TX_FLOWCTRL;
869         CSR_WRITE_4(gx, GX_CTRL, reg);
870 }
871
872 static int
873 gx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
874 {
875         struct gx_softc *gx = ifp->if_softc;
876         struct ifreq *ifr = (struct ifreq *)data;
877         struct mii_data *mii;
878         int mask, error = 0;
879
880         switch (command) {
881         case SIOCSIFMTU:
882                 if (ifr->ifr_mtu > GX_MAX_MTU) {
883                         error = EINVAL;
884                 } else {
885                         ifp->if_mtu = ifr->ifr_mtu;
886                         gx_init(gx);
887                 }
888                 break;
889         case SIOCSIFFLAGS:
890                 if ((ifp->if_flags & IFF_UP) == 0) {
891                         gx_stop(gx);
892                 } else if (ifp->if_flags & IFF_RUNNING &&
893                     ((ifp->if_flags & IFF_PROMISC) != 
894                     (gx->gx_if_flags & IFF_PROMISC))) {
895                         if (ifp->if_flags & IFF_PROMISC)
896                                 GX_SETBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
897                         else 
898                                 GX_CLRBIT(gx, GX_RX_CONTROL, GX_RXC_UNI_PROMISC);
899                 } else {
900                         gx_init(gx);
901                 }
902                 gx->gx_if_flags = ifp->if_flags;
903                 break;
904         case SIOCADDMULTI:
905         case SIOCDELMULTI:
906                 if (ifp->if_flags & IFF_RUNNING)
907                         gx_setmulti(gx);
908                 break;
909         case SIOCSIFMEDIA:
910         case SIOCGIFMEDIA:
911                 if (gx->gx_miibus != NULL) {
912                         mii = device_get_softc(gx->gx_miibus);
913                         error = ifmedia_ioctl(ifp, ifr,
914                             &mii->mii_media, command);
915                 } else {
916                         error = ifmedia_ioctl(ifp, ifr, &gx->gx_media, command);
917                 }
918                 break;
919         case SIOCSIFCAP:
920                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
921                 if (mask & IFCAP_HWCSUM) {
922                         if (IFCAP_HWCSUM & ifp->if_capenable)
923                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
924                         else
925                                 ifp->if_capenable |= IFCAP_HWCSUM;
926                         if (ifp->if_flags & IFF_RUNNING)
927                                 gx_init(gx);
928                 }
929                 break;
930         default:
931                 error = ether_ioctl(ifp, command, data);
932                 break;
933         }
934         return (error);
935 }
936
937 static void
938 gx_phy_reset(struct gx_softc *gx)
939 {
940         int reg;
941
942         GX_SETBIT(gx, GX_CTRL, GX_CTRL_SET_LINK_UP);
943
944         /*
945          * PHY reset is active low.
946          */
947         reg = CSR_READ_4(gx, GX_CTRL_EXT);
948         reg &= ~(GX_CTRLX_GPIO_DIR_MASK | GX_CTRLX_PHY_RESET);
949         reg |= GX_CTRLX_GPIO_DIR;
950
951         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
952         DELAY(10);
953         CSR_WRITE_4(gx, GX_CTRL_EXT, reg);
954         DELAY(10);
955         CSR_WRITE_4(gx, GX_CTRL_EXT, reg | GX_CTRLX_PHY_RESET);
956         DELAY(10);
957
958 #if 0
959         /* post-livingood (cordova) only */
960                 GX_SETBIT(gx, GX_CTRL, 0x80000000);
961                 DELAY(1000);
962                 GX_CLRBIT(gx, GX_CTRL, 0x80000000);
963 #endif
964 }
965
966 static void
967 gx_reset(struct gx_softc *gx)
968 {
969
970         /* Disable host interrupts. */
971         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
972
973         /* reset chip (THWAP!) */
974         GX_SETBIT(gx, GX_CTRL, GX_CTRL_DEVICE_RESET);
975         DELAY(10);
976 }
977
978 static void
979 gx_stop(struct gx_softc *gx)
980 {
981         struct ifnet *ifp;
982
983         ifp = &gx->arpcom.ac_if;
984
985         /* reset and flush transmitter */
986         CSR_WRITE_4(gx, GX_TX_CONTROL, GX_TXC_RESET);
987
988         /* reset and flush receiver */
989         CSR_WRITE_4(gx, GX_RX_CONTROL, GX_RXC_RESET);
990
991         /* reset link */
992         if (gx->gx_tbimode)
993                 GX_SETBIT(gx, GX_CTRL, GX_CTRL_LINK_RESET);
994
995         /* Free the RX lists. */
996         gx_free_rx_ring(gx);
997
998         /* Free TX buffers. */
999         gx_free_tx_ring(gx);
1000
1001         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1002 }
1003
1004 static void
1005 gx_watchdog(struct ifnet *ifp)
1006 {
1007         struct gx_softc *gx;
1008
1009         gx = ifp->if_softc;
1010
1011         device_printf(gx->gx_dev, "watchdog timeout -- resetting\n");
1012         gx_reset(gx);
1013         gx_init(gx);
1014
1015         ifp->if_oerrors++;
1016 }
1017
1018 /*
1019  * Intialize a receive ring descriptor.
1020  */
1021 static int
1022 gx_newbuf(struct gx_softc *gx, int idx, struct mbuf *m)
1023 {
1024         struct mbuf *m_new = NULL;
1025         struct gx_rx_desc *r;
1026
1027         if (m == NULL) {
1028                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1029                 if (m_new == NULL) {
1030                         device_printf(gx->gx_dev, 
1031                             "mbuf allocation failed -- packet dropped\n");
1032                         return (ENOBUFS);
1033                 }
1034                 MCLGET(m_new, MB_DONTWAIT);
1035                 if ((m_new->m_flags & M_EXT) == 0) {
1036                         device_printf(gx->gx_dev, 
1037                             "cluster allocation failed -- packet dropped\n");
1038                         m_freem(m_new);
1039                         return (ENOBUFS);
1040                 }
1041                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1042         } else {
1043                 m->m_len = m->m_pkthdr.len = MCLBYTES;
1044                 m->m_data = m->m_ext.ext_buf;
1045                 m->m_next = NULL;
1046                 m_new = m;
1047         }
1048
1049         /*
1050          * XXX
1051          * this will _NOT_ work for large MTU's; it will overwrite
1052          * the end of the buffer.  E.g.: take this out for jumbograms,
1053          * but then that breaks alignment.
1054          */
1055         if (gx->arpcom.ac_if.if_mtu <= ETHERMTU)
1056                 m_adj(m_new, ETHER_ALIGN);
1057
1058         gx->gx_cdata.gx_rx_chain[idx] = m_new;
1059         r = &gx->gx_rdata->gx_rx_ring[idx];
1060         r->rx_addr = vtophys(mtod(m_new, caddr_t));
1061         r->rx_staterr = 0;
1062
1063         return (0);
1064 }
1065
1066 /*
1067  * The receive ring can have up to 64K descriptors, which at 2K per mbuf
1068  * cluster, could add up to 128M of memory.  Due to alignment constraints,
1069  * the number of descriptors must be a multiple of 8.  For now, we
1070  * allocate 256 entries and hope that our CPU is fast enough to keep up
1071  * with the NIC.
1072  */
1073 static int
1074 gx_init_rx_ring(struct gx_softc *gx)
1075 {
1076         int i, error;
1077
1078         for (i = 0; i < GX_RX_RING_CNT; i++) {
1079                 error = gx_newbuf(gx, i, NULL);
1080                 if (error)
1081                         return (error);
1082         }
1083
1084         /* bring receiver out of reset state, leave disabled */
1085         CSR_WRITE_4(gx, GX_RX_CONTROL, 0);
1086
1087         /* set up ring registers */
1088         CSR_WRITE_8(gx, gx->gx_reg.r_rx_base,
1089             (u_quad_t)vtophys(gx->gx_rdata->gx_rx_ring));
1090
1091         CSR_WRITE_4(gx, gx->gx_reg.r_rx_length,
1092             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1093         CSR_WRITE_4(gx, gx->gx_reg.r_rx_head, 0);
1094         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, GX_RX_RING_CNT - 1);
1095         gx->gx_rx_tail_idx = 0;
1096
1097         return (0);
1098 }
1099
1100 static void
1101 gx_free_rx_ring(struct gx_softc *gx)
1102 {
1103         struct mbuf **mp;
1104         int i;
1105
1106         mp = gx->gx_cdata.gx_rx_chain;
1107         for (i = 0; i < GX_RX_RING_CNT; i++, mp++) {
1108                 if (*mp != NULL) {
1109                         m_freem(*mp);
1110                         *mp = NULL;
1111                 }
1112         }
1113         bzero((void *)gx->gx_rdata->gx_rx_ring,
1114             GX_RX_RING_CNT * sizeof(struct gx_rx_desc));
1115
1116         /* release any partially-received packet chain */
1117         if (gx->gx_pkthdr != NULL) {
1118                 m_freem(gx->gx_pkthdr);
1119                 gx->gx_pkthdr = NULL;
1120         }
1121 }
1122
1123 static int
1124 gx_init_tx_ring(struct gx_softc *gx)
1125 {
1126
1127         /* bring transmitter out of reset state, leave disabled */
1128         CSR_WRITE_4(gx, GX_TX_CONTROL, 0);
1129
1130         /* set up ring registers */
1131         CSR_WRITE_8(gx, gx->gx_reg.r_tx_base,
1132             (u_quad_t)vtophys(gx->gx_rdata->gx_tx_ring));
1133         CSR_WRITE_4(gx, gx->gx_reg.r_tx_length,
1134             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1135         CSR_WRITE_4(gx, gx->gx_reg.r_tx_head, 0);
1136         CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, 0);
1137         gx->gx_tx_head_idx = 0;
1138         gx->gx_tx_tail_idx = 0;
1139         gx->gx_txcnt = 0;
1140
1141         /* set up initial TX context */
1142         gx->gx_txcontext = GX_TXCONTEXT_NONE;
1143
1144         return (0);
1145 }
1146
1147 static void
1148 gx_free_tx_ring(struct gx_softc *gx)
1149 {
1150         struct mbuf **mp;
1151         int i;
1152
1153         mp = gx->gx_cdata.gx_tx_chain;
1154         for (i = 0; i < GX_TX_RING_CNT; i++, mp++) {
1155                 if (*mp != NULL) {
1156                         m_freem(*mp);
1157                         *mp = NULL;
1158                 }
1159         }
1160         bzero((void *)&gx->gx_rdata->gx_tx_ring,
1161             GX_TX_RING_CNT * sizeof(struct gx_tx_desc));
1162 }
1163
1164 static void
1165 gx_setmulti(struct gx_softc *gx)
1166 {
1167         int i;
1168
1169         /* wipe out the multicast table */
1170         for (i = 1; i < 128; i++)
1171                 CSR_WRITE_4(gx, GX_MULTICAST_BASE + i * 4, 0);
1172 }
1173
1174 static void
1175 gx_rxeof(struct gx_softc *gx)
1176 {
1177         struct gx_rx_desc *rx;
1178         struct ifnet *ifp;
1179         int idx, staterr, len;
1180         struct mbuf *m;
1181
1182         gx->gx_rx_interrupts++;
1183
1184         ifp = &gx->arpcom.ac_if;
1185         idx = gx->gx_rx_tail_idx;
1186
1187         while (gx->gx_rdata->gx_rx_ring[idx].rx_staterr & GX_RXSTAT_COMPLETED) {
1188
1189                 rx = &gx->gx_rdata->gx_rx_ring[idx];
1190                 m = gx->gx_cdata.gx_rx_chain[idx];
1191                 /*
1192                  * gx_newbuf overwrites status and length bits, so we 
1193                  * make a copy of them here.
1194                  */
1195                 len = rx->rx_len;
1196                 staterr = rx->rx_staterr;
1197
1198                 if (staterr & GX_INPUT_ERROR)
1199                         goto ierror;
1200
1201                 if (gx_newbuf(gx, idx, NULL) == ENOBUFS)
1202                         goto ierror;
1203
1204                 GX_INC(idx, GX_RX_RING_CNT);
1205
1206                 if (staterr & GX_RXSTAT_INEXACT_MATCH) {
1207                         /*
1208                          * multicast packet, must verify against
1209                          * multicast address.
1210                          */
1211                 }
1212
1213                 if ((staterr & GX_RXSTAT_END_OF_PACKET) == 0) {
1214                         if (gx->gx_pkthdr == NULL) {
1215                                 m->m_len = len;
1216                                 m->m_pkthdr.len = len;
1217                                 gx->gx_pkthdr = m;
1218                                 gx->gx_pktnextp = &m->m_next;
1219                         } else {
1220                                 m->m_len = len;
1221                                 gx->gx_pkthdr->m_pkthdr.len += len;
1222                                 *(gx->gx_pktnextp) = m;
1223                                 gx->gx_pktnextp = &m->m_next;
1224                         }
1225                         continue;
1226                 }
1227
1228                 if (gx->gx_pkthdr == NULL) {
1229                         m->m_len = len;
1230                         m->m_pkthdr.len = len;
1231                 } else {
1232                         m->m_len = len;
1233                         gx->gx_pkthdr->m_pkthdr.len += len;
1234                         *(gx->gx_pktnextp) = m;
1235                         m = gx->gx_pkthdr;
1236                         gx->gx_pkthdr = NULL;
1237                 }
1238
1239                 ifp->if_ipackets++;
1240                 m->m_pkthdr.rcvif = ifp;
1241
1242 #define IP_CSMASK       (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_IP_CSUM)
1243 #define TCP_CSMASK \
1244     (GX_RXSTAT_IGNORE_CSUM | GX_RXSTAT_HAS_TCP_CSUM | GX_RXERR_TCP_CSUM)
1245                 if (ifp->if_capenable & IFCAP_RXCSUM) {
1246 #if 0
1247                         /*
1248                          * Intel Erratum #23 indicates that the Receive IP
1249                          * Checksum offload feature has been completely
1250                          * disabled.
1251                          */
1252                         if ((staterr & IP_CSUM_MASK) == GX_RXSTAT_HAS_IP_CSUM) {
1253                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1254                                 if ((staterr & GX_RXERR_IP_CSUM) == 0)
1255                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1256                         }
1257 #endif
1258                         if ((staterr & TCP_CSMASK) == GX_RXSTAT_HAS_TCP_CSUM) {
1259                                 m->m_pkthdr.csum_flags |=
1260                                     CSUM_DATA_VALID | CSUM_PSEUDO_HDR |
1261                                     CSUM_FRAG_NOT_CHECKED;
1262                                 m->m_pkthdr.csum_data = 0xffff;
1263                         }
1264                 }
1265                 /*
1266                  * If we received a packet with a vlan tag, pass it
1267                  * to vlan_input() instead of ether_input().
1268                  */
1269                 if (staterr & GX_RXSTAT_VLAN_PKT)
1270                         VLAN_INPUT_TAG(m, rx->rx_special);
1271                 else
1272                         ifp->if_input(ifp, m);
1273                 continue;
1274
1275   ierror:
1276                 ifp->if_ierrors++;
1277                 gx_newbuf(gx, idx, m);
1278
1279                 /* 
1280                  * XXX
1281                  * this isn't quite right.  Suppose we have a packet that
1282                  * spans 5 descriptors (9K split into 2K buffers).  If
1283                  * the 3rd descriptor sets an error, we need to ignore
1284                  * the last two.  The way things stand now, the last two
1285                  * will be accepted as a single packet.
1286                  *
1287                  * we don't worry about this -- the chip may not set an
1288                  * error in this case, and the checksum of the upper layers
1289                  * will catch the error.
1290                  */
1291                 if (gx->gx_pkthdr != NULL) {
1292                         m_freem(gx->gx_pkthdr);
1293                         gx->gx_pkthdr = NULL;
1294                 }
1295                 GX_INC(idx, GX_RX_RING_CNT);
1296         }
1297
1298         gx->gx_rx_tail_idx = idx;
1299         if (--idx < 0)
1300                 idx = GX_RX_RING_CNT - 1;
1301         CSR_WRITE_4(gx, gx->gx_reg.r_rx_tail, idx);
1302 }
1303
1304 static void
1305 gx_txeof(struct gx_softc *gx)
1306 {
1307         struct ifnet *ifp;
1308         int idx, cnt;
1309
1310         gx->gx_tx_interrupts++;
1311
1312         ifp = &gx->arpcom.ac_if;
1313         idx = gx->gx_tx_head_idx;
1314         cnt = gx->gx_txcnt;
1315
1316         /*
1317          * If the system chipset performs I/O write buffering, it is 
1318          * possible for the PIO read of the head descriptor to bypass the
1319          * memory write of the descriptor, resulting in reading a descriptor
1320          * which has not been updated yet.
1321          */
1322         while (cnt) {
1323                 struct gx_tx_desc_old *tx;
1324
1325                 tx = (struct gx_tx_desc_old *)&gx->gx_rdata->gx_tx_ring[idx];
1326                 cnt--;
1327
1328                 if ((tx->tx_command & GX_TXOLD_END_OF_PKT) == 0) {
1329                         GX_INC(idx, GX_TX_RING_CNT);
1330                         continue;
1331                 }
1332
1333                 if ((tx->tx_status & GX_TXSTAT_DONE) == 0)
1334                         break;
1335
1336                 ifp->if_opackets++;
1337
1338                 m_freem(gx->gx_cdata.gx_tx_chain[idx]);
1339                 gx->gx_cdata.gx_tx_chain[idx] = NULL;
1340                 gx->gx_txcnt = cnt;
1341                 ifp->if_timer = 0;
1342
1343                 GX_INC(idx, GX_TX_RING_CNT);
1344                 gx->gx_tx_head_idx = idx;
1345         }
1346
1347         if (gx->gx_txcnt == 0)
1348                 ifp->if_flags &= ~IFF_OACTIVE;
1349 }
1350
1351 static void
1352 gx_intr(void *xsc)
1353 {
1354         struct gx_softc *gx = xsc;
1355         struct ifnet *ifp = &gx->arpcom.ac_if;
1356         u_int32_t intr;
1357
1358         gx->gx_interrupts++;
1359
1360         /* Disable host interrupts. */
1361         CSR_WRITE_4(gx, GX_INT_MASK_CLR, GX_INT_ALL);
1362
1363         /*
1364          * find out why we're being bothered.
1365          * reading this register automatically clears all bits.
1366          */
1367         intr = CSR_READ_4(gx, GX_INT_READ);
1368
1369         /* Check RX return ring producer/consumer */
1370         if (intr & (GX_INT_RCV_TIMER | GX_INT_RCV_THOLD | GX_INT_RCV_OVERRUN))
1371                 gx_rxeof(gx);
1372
1373         /* Check TX ring producer/consumer */
1374         if (intr & (GX_INT_XMIT_DONE | GX_INT_XMIT_EMPTY))
1375                 gx_txeof(gx);
1376
1377         /*
1378          * handle other interrupts here.
1379          */
1380
1381         /*
1382          * Link change interrupts are not reliable; the interrupt may
1383          * not be generated if the link is lost.  However, the register
1384          * read is reliable, so check that.  Use SEQ errors to possibly
1385          * indicate that the link has changed.
1386          */
1387         if (intr & GX_INT_LINK_CHANGE) {
1388                 if ((CSR_READ_4(gx, GX_STATUS) & GX_STAT_LINKUP) == 0) {
1389                         device_printf(gx->gx_dev, "link down\n");
1390                 } else {
1391                         device_printf(gx->gx_dev, "link up\n");
1392                 }
1393         }
1394
1395         /* Turn interrupts on. */
1396         CSR_WRITE_4(gx, GX_INT_MASK_SET, GX_INT_WANTED);
1397
1398         if (ifp->if_flags & IFF_RUNNING && !ifq_is_empty(&ifp->if_snd))
1399                 gx_start(ifp);
1400 }
1401
1402 /*
1403  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1404  * pointers to descriptors.
1405  */
1406 static int
1407 gx_encap(struct gx_softc *gx, struct mbuf *m_head)
1408 {
1409         struct gx_tx_desc_data *tx = NULL;
1410         struct gx_tx_desc_ctx *tctx;
1411         struct mbuf *m;
1412         int idx, cnt, csumopts, txcontext;
1413         struct ifvlan *ifv = NULL;
1414
1415         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1416             m_head->m_pkthdr.rcvif != NULL &&
1417             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1418                 ifv = m_head->m_pkthdr.rcvif->if_softc;
1419
1420         cnt = gx->gx_txcnt;
1421         idx = gx->gx_tx_tail_idx;
1422         txcontext = gx->gx_txcontext;
1423
1424         /*
1425          * Insure we have at least 4 descriptors pre-allocated.
1426          */
1427         if (cnt >= GX_TX_RING_CNT - 4)
1428                 return (ENOBUFS);
1429
1430         /*
1431          * Set up the appropriate offload context if necessary.
1432          */
1433         csumopts = 0;
1434         if (m_head->m_pkthdr.csum_flags) {
1435                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1436                         csumopts |= GX_TXTCP_OPT_IP_CSUM;
1437                 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) {
1438                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1439                         txcontext = GX_TXCONTEXT_TCPIP;
1440                 } else if (m_head->m_pkthdr.csum_flags & CSUM_UDP) {
1441                         csumopts |= GX_TXTCP_OPT_TCP_CSUM;
1442                         txcontext = GX_TXCONTEXT_UDPIP;
1443                 } else if (txcontext == GX_TXCONTEXT_NONE)
1444                         txcontext = GX_TXCONTEXT_TCPIP;
1445                 if (txcontext == gx->gx_txcontext)
1446                         goto context_done;
1447
1448                 tctx = (struct gx_tx_desc_ctx *)&gx->gx_rdata->gx_tx_ring[idx];
1449                 tctx->tx_ip_csum_start = ETHER_HDR_LEN;
1450                 tctx->tx_ip_csum_end = ETHER_HDR_LEN + sizeof(struct ip) - 1;
1451                 tctx->tx_ip_csum_offset = 
1452                     ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
1453                 tctx->tx_tcp_csum_start = ETHER_HDR_LEN + sizeof(struct ip);
1454                 tctx->tx_tcp_csum_end = 0;
1455                 if (txcontext == GX_TXCONTEXT_TCPIP)
1456                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1457                             sizeof(struct ip) + offsetof(struct tcphdr, th_sum);
1458                 else
1459                         tctx->tx_tcp_csum_offset = ETHER_HDR_LEN +
1460                             sizeof(struct ip) + offsetof(struct udphdr, uh_sum);
1461                 tctx->tx_command = GX_TXCTX_EXTENSION | GX_TXCTX_INT_DELAY;
1462                 tctx->tx_type = 0;
1463                 tctx->tx_status = 0;
1464                 GX_INC(idx, GX_TX_RING_CNT);
1465                 cnt++;
1466         }
1467 context_done:
1468
1469         /*
1470          * Start packing the mbufs in this chain into the transmit
1471          * descriptors.  Stop when we run out of descriptors or hit
1472          * the end of the mbuf chain.
1473          */
1474         for (m = m_head; m != NULL; m = m->m_next) {
1475                 if (m->m_len == 0)
1476                         continue;
1477
1478                 if (cnt == GX_TX_RING_CNT) {
1479 kprintf("overflow(2): %d, %d\n", cnt, GX_TX_RING_CNT);
1480                         return (ENOBUFS);
1481 }
1482
1483                 tx = (struct gx_tx_desc_data *)&gx->gx_rdata->gx_tx_ring[idx];
1484                 tx->tx_addr = vtophys(mtod(m, vm_offset_t));
1485                 tx->tx_status = 0;
1486                 tx->tx_len = m->m_len;
1487                 if (gx->arpcom.ac_if.if_hwassist) {
1488                         tx->tx_type = 1;
1489                         tx->tx_command = GX_TXTCP_EXTENSION;
1490                         tx->tx_options = csumopts;
1491                 } else {
1492                         /*
1493                          * This is really a struct gx_tx_desc_old.
1494                          */
1495                         tx->tx_command = 0;
1496                 }
1497                 GX_INC(idx, GX_TX_RING_CNT);
1498                 cnt++;
1499         }
1500
1501         if (tx != NULL) {
1502                 tx->tx_command |= GX_TXTCP_REPORT_STATUS | GX_TXTCP_INT_DELAY |
1503                     GX_TXTCP_ETHER_CRC | GX_TXTCP_END_OF_PKT;
1504                 if (ifv != NULL) {
1505                         tx->tx_command |= GX_TXTCP_VLAN_ENABLE;
1506                         tx->tx_vlan = ifv->ifv_tag;
1507                 }
1508                 gx->gx_txcnt = cnt;
1509                 gx->gx_tx_tail_idx = idx;
1510                 gx->gx_txcontext = txcontext;
1511                 idx = GX_PREV(idx, GX_TX_RING_CNT);
1512                 gx->gx_cdata.gx_tx_chain[idx] = m_head;
1513
1514                 CSR_WRITE_4(gx, gx->gx_reg.r_tx_tail, gx->gx_tx_tail_idx);
1515         }
1516         
1517         return (0);
1518 }
1519  
1520 /*
1521  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1522  * to the mbuf data regions directly in the transmit descriptors.
1523  */
1524 static void
1525 gx_start(struct ifnet *ifp)
1526 {
1527         struct gx_softc *gx = ifp->if_softc;
1528         struct mbuf *m_head;
1529
1530         for (;;) {
1531                 m_head = ifq_poll(&ifp->if_snd);
1532                 if (m_head == NULL)
1533                         break;
1534
1535                 /*
1536                  * Pack the data into the transmit ring. If we
1537                  * don't have room, set the OACTIVE flag and wait
1538                  * for the NIC to drain the ring.
1539                  */
1540                 if (gx_encap(gx, m_head) != 0) {
1541                         ifp->if_flags |= IFF_OACTIVE;
1542                         break;
1543                 }
1544                 ifq_dequeue(&ifp->if_snd, m_head);
1545
1546                 BPF_MTAP(ifp, m_head);
1547
1548                 /*
1549                  * Set a timeout in case the chip goes out to lunch.
1550                  */
1551                 ifp->if_timer = 5;
1552         }
1553 }