1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
30 #include <dev/drm/drmP.h>
31 #include <dev/drm/drm.h>
34 #include "intel_drv.h"
35 #include "intel_ringbuffer.h"
37 static struct drm_i915_private *i915_mch_dev;
39 * Lock protecting IPS related data structures
41 * - dev_priv->max_delay
42 * - dev_priv->min_delay
44 * - dev_priv->gpu_busy
46 static struct lock mchdev_lock;
47 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
49 static void i915_pineview_get_mem_freq(struct drm_device *dev);
50 static void i915_ironlake_get_mem_freq(struct drm_device *dev);
51 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
53 static void i915_write_hws_pga(struct drm_device *dev)
55 drm_i915_private_t *dev_priv = dev->dev_private;
58 addr = dev_priv->status_page_dmah->busaddr;
59 if (INTEL_INFO(dev)->gen >= 4)
60 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
61 I915_WRITE(HWS_PGA, addr);
65 * Sets up the hardware status page for devices that need a physical address
68 static int i915_init_phys_hws(struct drm_device *dev)
70 drm_i915_private_t *dev_priv = dev->dev_private;
71 struct intel_ring_buffer *ring = LP_RING(dev_priv);
74 * Program Hardware Status Page
75 * XXXKIB Keep 4GB limit for allocation for now. This method
76 * of allocation is used on <= 965 hardware, that has several
77 * erratas regarding the use of physical memory > 4 GB.
80 dev_priv->status_page_dmah =
81 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
83 if (!dev_priv->status_page_dmah) {
84 DRM_ERROR("Can not allocate hardware status page\n");
87 ring->status_page.page_addr = dev_priv->hw_status_page =
88 dev_priv->status_page_dmah->vaddr;
89 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
91 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
93 i915_write_hws_pga(dev);
94 DRM_DEBUG("Enabled hardware status page, phys %jx\n",
95 (uintmax_t)dev_priv->dma_status_page);
100 * Frees the hardware status page, whether it's a physical address or a virtual
101 * address set up by the X Server.
103 static void i915_free_hws(struct drm_device *dev)
105 drm_i915_private_t *dev_priv = dev->dev_private;
106 struct intel_ring_buffer *ring = LP_RING(dev_priv);
108 if (dev_priv->status_page_dmah) {
109 drm_pci_free(dev, dev_priv->status_page_dmah);
110 dev_priv->status_page_dmah = NULL;
113 if (dev_priv->status_gfx_addr) {
114 dev_priv->status_gfx_addr = 0;
115 ring->status_page.gfx_addr = 0;
116 drm_core_ioremapfree(&dev_priv->hws_map, dev);
119 /* Need to rewrite hardware status page */
120 I915_WRITE(HWS_PGA, 0x1ffff000);
123 void i915_kernel_lost_context(struct drm_device * dev)
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 struct intel_ring_buffer *ring = LP_RING(dev_priv);
129 * We should never lose context on the ring with modesetting
130 * as we don't expose it to userspace
132 if (drm_core_check_feature(dev, DRIVER_MODESET))
135 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
136 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
137 ring->space = ring->head - (ring->tail + 8);
139 ring->space += ring->size;
144 if (!dev->primary->master)
148 if (ring->head == ring->tail && dev_priv->sarea_priv)
149 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
152 static int i915_dma_cleanup(struct drm_device * dev)
154 drm_i915_private_t *dev_priv = dev->dev_private;
158 /* Make sure interrupts are disabled here because the uninstall ioctl
159 * may not have been called from userspace and after dev_private
160 * is freed, it's too late.
162 if (dev->irq_enabled)
163 drm_irq_uninstall(dev);
165 for (i = 0; i < I915_NUM_RINGS; i++)
166 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
168 /* Clear the HWS virtual address at teardown */
169 if (I915_NEED_GFX_HWS(dev))
175 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
177 drm_i915_private_t *dev_priv = dev->dev_private;
180 dev_priv->sarea = drm_getsarea(dev);
181 if (!dev_priv->sarea) {
182 DRM_ERROR("can not find sarea!\n");
183 i915_dma_cleanup(dev);
187 dev_priv->sarea_priv = (drm_i915_sarea_t *)
188 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
190 if (init->ring_size != 0) {
191 if (LP_RING(dev_priv)->obj != NULL) {
192 i915_dma_cleanup(dev);
193 DRM_ERROR("Client tried to initialize ringbuffer in "
198 ret = intel_render_ring_init_dri(dev,
202 i915_dma_cleanup(dev);
207 dev_priv->cpp = init->cpp;
208 dev_priv->back_offset = init->back_offset;
209 dev_priv->front_offset = init->front_offset;
210 dev_priv->current_page = 0;
211 dev_priv->sarea_priv->pf_current_page = 0;
213 /* Allow hardware batchbuffers unless told otherwise.
215 dev_priv->allow_batchbuffer = 1;
220 static int i915_dma_resume(struct drm_device * dev)
222 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
223 struct intel_ring_buffer *ring = LP_RING(dev_priv);
227 if (ring->map.handle == NULL) {
228 DRM_ERROR("can not ioremap virtual address for"
233 /* Program Hardware Status Page */
234 if (!ring->status_page.page_addr) {
235 DRM_ERROR("Can not find hardware status page\n");
238 DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
239 if (ring->status_page.gfx_addr != 0)
240 intel_ring_setup_status_page(ring);
242 i915_write_hws_pga(dev);
244 DRM_DEBUG("Enabled hardware status page\n");
249 static int i915_dma_init(struct drm_device *dev, void *data,
250 struct drm_file *file_priv)
252 drm_i915_init_t *init = data;
255 switch (init->func) {
257 retcode = i915_initialize(dev, init);
259 case I915_CLEANUP_DMA:
260 retcode = i915_dma_cleanup(dev);
262 case I915_RESUME_DMA:
263 retcode = i915_dma_resume(dev);
273 /* Implement basically the same security restrictions as hardware does
274 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
276 * Most of the calculations below involve calculating the size of a
277 * particular instruction. It's important to get the size right as
278 * that tells us where the next instruction to check is. Any illegal
279 * instruction detected will be given a size of zero, which is a
280 * signal to abort the rest of the buffer.
282 static int do_validate_cmd(int cmd)
284 switch (((cmd >> 29) & 0x7)) {
286 switch ((cmd >> 23) & 0x3f) {
288 return 1; /* MI_NOOP */
290 return 1; /* MI_FLUSH */
292 return 0; /* disallow everything else */
296 return 0; /* reserved */
298 return (cmd & 0xff) + 2; /* 2d commands */
300 if (((cmd >> 24) & 0x1f) <= 0x18)
303 switch ((cmd >> 24) & 0x1f) {
307 switch ((cmd >> 16) & 0xff) {
309 return (cmd & 0x1f) + 2;
311 return (cmd & 0xf) + 2;
313 return (cmd & 0xffff) + 2;
317 return (cmd & 0xffff) + 1;
321 if ((cmd & (1 << 23)) == 0) /* inline vertices */
322 return (cmd & 0x1ffff) + 2;
323 else if (cmd & (1 << 17)) /* indirect random */
324 if ((cmd & 0xffff) == 0)
325 return 0; /* unknown length, too hard */
327 return (((cmd & 0xffff) + 1) / 2) + 1;
329 return 2; /* indirect sequential */
340 static int validate_cmd(int cmd)
342 int ret = do_validate_cmd(cmd);
344 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
349 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
352 drm_i915_private_t *dev_priv = dev->dev_private;
355 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
358 BEGIN_LP_RING((dwords+1)&~1);
360 for (i = 0; i < dwords;) {
363 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
366 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
372 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
388 int i915_emit_box(struct drm_device * dev,
389 struct drm_clip_rect *boxes,
390 int i, int DR1, int DR4)
392 struct drm_clip_rect box;
394 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
398 return (i915_emit_box_p(dev, &box, DR1, DR4));
402 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
405 drm_i915_private_t *dev_priv = dev->dev_private;
408 if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
410 DRM_ERROR("Bad box %d,%d..%d,%d\n",
411 box->x1, box->y1, box->x2, box->y2);
415 if (INTEL_INFO(dev)->gen >= 4) {
416 ret = BEGIN_LP_RING(4);
420 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
421 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
422 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
425 ret = BEGIN_LP_RING(6);
429 OUT_RING(GFX_OP_DRAWRECT_INFO);
431 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
432 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
441 /* XXX: Emitting the counter should really be moved to part of the IRQ
442 * emit. For now, do it in both places:
445 static void i915_emit_breadcrumb(struct drm_device *dev)
447 drm_i915_private_t *dev_priv = dev->dev_private;
449 if (++dev_priv->counter > 0x7FFFFFFFUL)
450 dev_priv->counter = 0;
451 if (dev_priv->sarea_priv)
452 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
454 if (BEGIN_LP_RING(4) == 0) {
455 OUT_RING(MI_STORE_DWORD_INDEX);
456 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
457 OUT_RING(dev_priv->counter);
463 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
464 drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
466 int nbox = cmd->num_cliprects;
467 int i = 0, count, ret;
470 DRM_ERROR("alignment\n");
474 i915_kernel_lost_context(dev);
476 count = nbox ? nbox : 1;
478 for (i = 0; i < count; i++) {
480 ret = i915_emit_box_p(dev, &cmd->cliprects[i],
486 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
491 i915_emit_breadcrumb(dev);
496 i915_dispatch_batchbuffer(struct drm_device * dev,
497 drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
499 drm_i915_private_t *dev_priv = dev->dev_private;
500 int nbox = batch->num_cliprects;
503 if ((batch->start | batch->used) & 0x7) {
504 DRM_ERROR("alignment\n");
508 i915_kernel_lost_context(dev);
510 count = nbox ? nbox : 1;
512 for (i = 0; i < count; i++) {
514 int ret = i915_emit_box_p(dev, &cliprects[i],
515 batch->DR1, batch->DR4);
520 if (!IS_I830(dev) && !IS_845G(dev)) {
521 ret = BEGIN_LP_RING(2);
525 if (INTEL_INFO(dev)->gen >= 4) {
526 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
527 MI_BATCH_NON_SECURE_I965);
528 OUT_RING(batch->start);
530 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
531 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
534 ret = BEGIN_LP_RING(4);
538 OUT_RING(MI_BATCH_BUFFER);
539 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
540 OUT_RING(batch->start + batch->used - 4);
546 i915_emit_breadcrumb(dev);
551 static int i915_dispatch_flip(struct drm_device * dev)
553 drm_i915_private_t *dev_priv = dev->dev_private;
556 if (!dev_priv->sarea_priv)
559 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
561 dev_priv->current_page,
562 dev_priv->sarea_priv->pf_current_page);
564 i915_kernel_lost_context(dev);
566 ret = BEGIN_LP_RING(10);
569 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
572 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
574 if (dev_priv->current_page == 0) {
575 OUT_RING(dev_priv->back_offset);
576 dev_priv->current_page = 1;
578 OUT_RING(dev_priv->front_offset);
579 dev_priv->current_page = 0;
583 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
588 if (++dev_priv->counter > 0x7FFFFFFFUL)
589 dev_priv->counter = 0;
590 if (dev_priv->sarea_priv)
591 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
593 if (BEGIN_LP_RING(4) == 0) {
594 OUT_RING(MI_STORE_DWORD_INDEX);
595 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
596 OUT_RING(dev_priv->counter);
601 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
606 i915_quiescent(struct drm_device *dev)
608 struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
610 i915_kernel_lost_context(dev);
611 return (intel_wait_ring_idle(ring));
615 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
619 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
622 ret = i915_quiescent(dev);
628 static int i915_batchbuffer(struct drm_device *dev, void *data,
629 struct drm_file *file_priv)
631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
632 drm_i915_sarea_t *sarea_priv;
633 drm_i915_batchbuffer_t *batch = data;
634 struct drm_clip_rect *cliprects;
638 if (!dev_priv->allow_batchbuffer) {
639 DRM_ERROR("Batchbuffer ioctl disabled\n");
644 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
645 batch->start, batch->used, batch->num_cliprects);
647 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
648 if (batch->num_cliprects < 0)
650 if (batch->num_cliprects != 0) {
651 cliprects = kmalloc(batch->num_cliprects *
652 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
655 ret = -copyin(batch->cliprects, cliprects,
656 batch->num_cliprects * sizeof(struct drm_clip_rect));
665 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
666 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
668 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
670 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
673 drm_free(cliprects, DRM_MEM_DMA);
677 static int i915_cmdbuffer(struct drm_device *dev, void *data,
678 struct drm_file *file_priv)
680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
681 drm_i915_sarea_t *sarea_priv;
682 drm_i915_cmdbuffer_t *cmdbuf = data;
683 struct drm_clip_rect *cliprects = NULL;
687 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
688 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
690 if (cmdbuf->num_cliprects < 0)
695 batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
697 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
700 goto fail_batch_free;
703 if (cmdbuf->num_cliprects) {
704 cliprects = kmalloc(cmdbuf->num_cliprects *
705 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
707 ret = -copyin(cmdbuf->cliprects, cliprects,
708 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
716 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
717 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
719 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
723 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
725 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
728 drm_free(cliprects, DRM_MEM_DMA);
730 drm_free(batch_data, DRM_MEM_DMA);
734 static int i915_flip_bufs(struct drm_device *dev, void *data,
735 struct drm_file *file_priv)
739 DRM_DEBUG("%s\n", __func__);
741 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
743 ret = i915_dispatch_flip(dev);
748 static int i915_getparam(struct drm_device *dev, void *data,
749 struct drm_file *file_priv)
751 drm_i915_private_t *dev_priv = dev->dev_private;
752 drm_i915_getparam_t *param = data;
756 DRM_ERROR("called with no initialization\n");
760 switch (param->param) {
761 case I915_PARAM_IRQ_ACTIVE:
762 value = dev->irq_enabled ? 1 : 0;
764 case I915_PARAM_ALLOW_BATCHBUFFER:
765 value = dev_priv->allow_batchbuffer ? 1 : 0;
767 case I915_PARAM_LAST_DISPATCH:
768 value = READ_BREADCRUMB(dev_priv);
770 case I915_PARAM_CHIPSET_ID:
771 value = dev->pci_device;
773 case I915_PARAM_HAS_GEM:
776 case I915_PARAM_NUM_FENCES_AVAIL:
777 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
779 case I915_PARAM_HAS_OVERLAY:
780 value = dev_priv->overlay ? 1 : 0;
782 case I915_PARAM_HAS_PAGEFLIPPING:
785 case I915_PARAM_HAS_EXECBUF2:
788 case I915_PARAM_HAS_BSD:
789 value = HAS_BSD(dev);
791 case I915_PARAM_HAS_BLT:
792 value = HAS_BLT(dev);
794 case I915_PARAM_HAS_RELAXED_FENCING:
797 case I915_PARAM_HAS_COHERENT_RINGS:
800 case I915_PARAM_HAS_EXEC_CONSTANTS:
801 value = INTEL_INFO(dev)->gen >= 4;
803 case I915_PARAM_HAS_RELAXED_DELTA:
806 case I915_PARAM_HAS_GEN7_SOL_RESET:
809 case I915_PARAM_HAS_LLC:
810 value = HAS_LLC(dev);
813 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
818 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
819 DRM_ERROR("DRM_COPY_TO_USER failed\n");
826 static int i915_setparam(struct drm_device *dev, void *data,
827 struct drm_file *file_priv)
829 drm_i915_private_t *dev_priv = dev->dev_private;
830 drm_i915_setparam_t *param = data;
833 DRM_ERROR("called with no initialization\n");
837 switch (param->param) {
838 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
840 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
841 dev_priv->tex_lru_log_granularity = param->value;
843 case I915_SETPARAM_ALLOW_BATCHBUFFER:
844 dev_priv->allow_batchbuffer = param->value;
846 case I915_SETPARAM_NUM_USED_FENCES:
847 if (param->value > dev_priv->num_fence_regs ||
850 /* Userspace can use first N regs */
851 dev_priv->fence_reg_start = param->value;
854 DRM_DEBUG("unknown parameter %d\n", param->param);
861 static int i915_set_status_page(struct drm_device *dev, void *data,
862 struct drm_file *file_priv)
864 drm_i915_private_t *dev_priv = dev->dev_private;
865 drm_i915_hws_addr_t *hws = data;
866 struct intel_ring_buffer *ring = LP_RING(dev_priv);
868 if (!I915_NEED_GFX_HWS(dev))
872 DRM_ERROR("called with no initialization\n");
876 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
877 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
878 DRM_ERROR("tried to set status page when mode setting active\n");
882 ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
883 hws->addr & (0x1ffff<<12);
885 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
886 dev_priv->hws_map.size = 4*1024;
887 dev_priv->hws_map.type = 0;
888 dev_priv->hws_map.flags = 0;
889 dev_priv->hws_map.mtrr = 0;
891 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
892 if (dev_priv->hws_map.virtual == NULL) {
893 i915_dma_cleanup(dev);
894 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
895 DRM_ERROR("can not ioremap virtual address for"
896 " G33 hw status page\n");
899 ring->status_page.page_addr = dev_priv->hw_status_page =
900 dev_priv->hws_map.virtual;
902 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
903 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
904 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
905 dev_priv->status_gfx_addr);
906 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
911 intel_enable_ppgtt(struct drm_device *dev)
913 if (i915_enable_ppgtt >= 0)
914 return i915_enable_ppgtt;
916 /* Disable ppgtt on SNB if VT-d is on. */
917 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
924 i915_load_gem_init(struct drm_device *dev)
926 struct drm_i915_private *dev_priv = dev->dev_private;
927 unsigned long prealloc_size, gtt_size, mappable_size;
930 prealloc_size = dev_priv->mm.gtt.stolen_size;
931 gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT;
932 mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT;
934 /* Basic memrange allocator for stolen space */
935 drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
938 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
939 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
940 * aperture accordingly when using aliasing ppgtt. */
941 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
942 /* For paranoia keep the guard page in between. */
943 gtt_size -= PAGE_SIZE;
945 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
947 ret = i915_gem_init_aliasing_ppgtt(dev);
953 /* Let GEM Manage all of the aperture.
955 * However, leave one page at the end still bound to the scratch
956 * page. There are a number of places where the hardware
957 * apparently prefetches past the end of the object, and we've
958 * seen multiple hangs with the GPU head pointer stuck in a
959 * batchbuffer bound at the last page of the aperture. One page
960 * should be enough to keep any prefetching inside of the
963 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
966 ret = i915_gem_init_hw(dev);
969 i915_gem_cleanup_aliasing_ppgtt(dev);
974 /* Try to set up FBC with a reasonable compressed buffer size */
975 if (I915_HAS_FBC(dev) && i915_powersave) {
978 /* Leave 1M for line length buffer & misc. */
980 /* Try to get a 32M buffer... */
981 if (prealloc_size > (36*1024*1024))
982 cfb_size = 32*1024*1024;
983 else /* fall back to 7/8 of the stolen space */
984 cfb_size = prealloc_size * 7 / 8;
985 i915_setup_compression(dev, cfb_size);
989 /* Allow hardware batchbuffers unless told otherwise. */
990 dev_priv->allow_batchbuffer = 1;
995 i915_load_modeset_init(struct drm_device *dev)
997 struct drm_i915_private *dev_priv = dev->dev_private;
1000 ret = intel_parse_bios(dev);
1002 DRM_INFO("failed to find VBIOS tables\n");
1005 intel_register_dsm_handler();
1008 /* IIR "flip pending" bit means done if this bit is set */
1009 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1010 dev_priv->flip_pending_is_done = true;
1012 intel_modeset_init(dev);
1014 ret = i915_load_gem_init(dev);
1018 intel_modeset_gem_init(dev);
1020 ret = drm_irq_install(dev);
1024 dev->vblank_disable_allowed = 1;
1026 ret = intel_fbdev_init(dev);
1030 drm_kms_helper_poll_init(dev);
1032 /* We're off and running w/KMS */
1033 dev_priv->mm.suspended = 0;
1039 i915_gem_cleanup_ringbuffer(dev);
1041 i915_gem_cleanup_aliasing_ppgtt(dev);
1046 i915_get_bridge_dev(struct drm_device *dev)
1048 struct drm_i915_private *dev_priv;
1050 dev_priv = dev->dev_private;
1052 dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1053 if (dev_priv->bridge_dev == NULL) {
1054 DRM_ERROR("bridge device not found\n");
1060 #define MCHBAR_I915 0x44
1061 #define MCHBAR_I965 0x48
1062 #define MCHBAR_SIZE (4*4096)
1064 #define DEVEN_REG 0x54
1065 #define DEVEN_MCHBAR_EN (1 << 28)
1067 /* Allocate space for the MCH regs if needed, return nonzero on error */
1069 intel_alloc_mchbar_resource(struct drm_device *dev)
1071 drm_i915_private_t *dev_priv;
1074 u32 temp_lo, temp_hi;
1075 u64 mchbar_addr, temp;
1077 dev_priv = dev->dev_private;
1078 reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1080 if (INTEL_INFO(dev)->gen >= 4)
1081 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1084 temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1085 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1087 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1088 #ifdef XXX_CONFIG_PNP
1090 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1094 /* Get some space for it */
1095 vga = device_get_parent(dev->device);
1096 dev_priv->mch_res_rid = 0x100;
1097 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1098 dev->device, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1099 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1100 if (dev_priv->mch_res == NULL) {
1101 DRM_ERROR("failed mchbar resource alloc\n");
1105 if (INTEL_INFO(dev)->gen >= 4) {
1106 temp = rman_get_start(dev_priv->mch_res);
1108 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1110 pci_write_config(dev_priv->bridge_dev, reg,
1111 rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1116 intel_setup_mchbar(struct drm_device *dev)
1118 drm_i915_private_t *dev_priv;
1123 dev_priv = dev->dev_private;
1124 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1126 dev_priv->mchbar_need_disable = false;
1128 if (IS_I915G(dev) || IS_I915GM(dev)) {
1129 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1130 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1132 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1136 /* If it's already enabled, don't have to do anything */
1138 DRM_DEBUG("mchbar already enabled\n");
1142 if (intel_alloc_mchbar_resource(dev))
1145 dev_priv->mchbar_need_disable = true;
1147 /* Space is allocated or reserved, so enable it. */
1148 if (IS_I915G(dev) || IS_I915GM(dev)) {
1149 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1150 temp | DEVEN_MCHBAR_EN, 4);
1152 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1153 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1158 intel_teardown_mchbar(struct drm_device *dev)
1160 drm_i915_private_t *dev_priv;
1165 dev_priv = dev->dev_private;
1166 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1168 if (dev_priv->mchbar_need_disable) {
1169 if (IS_I915G(dev) || IS_I915GM(dev)) {
1170 temp = pci_read_config(dev_priv->bridge_dev,
1172 temp &= ~DEVEN_MCHBAR_EN;
1173 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1176 temp = pci_read_config(dev_priv->bridge_dev,
1179 pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1184 if (dev_priv->mch_res != NULL) {
1185 vga = device_get_parent(dev->device);
1186 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->device,
1187 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1188 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->device,
1189 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1190 dev_priv->mch_res = NULL;
1195 i915_driver_load(struct drm_device *dev, unsigned long flags)
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 unsigned long base, size;
1203 /* i915 has 4 more counters */
1205 dev->types[6] = _DRM_STAT_IRQ;
1206 dev->types[7] = _DRM_STAT_PRIMARY;
1207 dev->types[8] = _DRM_STAT_SECONDARY;
1208 dev->types[9] = _DRM_STAT_DMA;
1210 dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1212 if (dev_priv == NULL)
1215 dev->dev_private = (void *)dev_priv;
1216 dev_priv->dev = dev;
1217 dev_priv->info = i915_get_device_id(dev->pci_device);
1219 if (i915_get_bridge_dev(dev)) {
1220 drm_free(dev_priv, DRM_MEM_DRIVER);
1223 dev_priv->mm.gtt = intel_gtt_get();
1225 /* Add register map (needed for suspend/resume) */
1226 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1227 base = drm_get_resource_start(dev, mmio_bar);
1228 size = drm_get_resource_len(dev, mmio_bar);
1230 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1231 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1233 dev_priv->tq = taskqueue_create("915", M_WAITOK,
1234 taskqueue_thread_enqueue, &dev_priv->tq);
1235 taskqueue_start_threads(&dev_priv->tq, 1, 0, -1, "i915 taskq");
1236 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1237 lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1238 lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1239 lockinit(&dev_priv->rps_lock, "915rps", 0, LK_CANRECURSE);
1241 dev_priv->has_gem = 1;
1242 intel_irq_init(dev);
1244 intel_setup_mchbar(dev);
1245 intel_setup_gmbus(dev);
1246 intel_opregion_setup(dev);
1248 intel_setup_bios(dev);
1253 if (!I915_NEED_GFX_HWS(dev)) {
1254 ret = i915_init_phys_hws(dev);
1256 drm_rmmap(dev, dev_priv->mmio_map);
1257 drm_free(dev_priv, DRM_MEM_DRIVER);
1262 if (IS_PINEVIEW(dev))
1263 i915_pineview_get_mem_freq(dev);
1264 else if (IS_GEN5(dev))
1265 i915_ironlake_get_mem_freq(dev);
1267 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1269 if (IS_IVYBRIDGE(dev))
1270 dev_priv->num_pipe = 3;
1271 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1272 dev_priv->num_pipe = 2;
1274 dev_priv->num_pipe = 1;
1276 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1278 goto out_gem_unload;
1280 /* Start out suspended */
1281 dev_priv->mm.suspended = 1;
1283 intel_detect_pch(dev);
1285 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1287 ret = i915_load_modeset_init(dev);
1290 DRM_ERROR("failed to init modeset\n");
1291 goto out_gem_unload;
1295 intel_opregion_init(dev);
1297 callout_init_mp(&dev_priv->hangcheck_timer);
1298 callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1299 i915_hangcheck_elapsed, dev);
1302 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1303 i915_mch_dev = dev_priv;
1304 dev_priv->mchdev_lock = &mchdev_lock;
1305 lockmgr(&mchdev_lock, LK_RELEASE);
1312 (void) i915_driver_unload_int(dev, true);
1317 i915_driver_unload_int(struct drm_device *dev, bool locked)
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1324 ret = i915_gpu_idle(dev, true);
1326 DRM_ERROR("failed to idle hardware: %d\n", ret);
1332 intel_teardown_mchbar(dev);
1336 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1337 intel_fbdev_fini(dev);
1338 intel_modeset_cleanup(dev);
1341 /* Free error state after interrupts are fully disabled. */
1342 callout_stop(&dev_priv->hangcheck_timer);
1344 i915_destroy_error_state(dev);
1346 intel_opregion_fini(dev);
1351 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1354 i915_gem_free_all_phys_object(dev);
1355 i915_gem_cleanup_ringbuffer(dev);
1358 i915_gem_cleanup_aliasing_ppgtt(dev);
1362 if (I915_HAS_FBC(dev) && i915_powersave)
1363 i915_cleanup_compression(dev);
1365 drm_mm_takedown(&dev_priv->mm.stolen);
1367 intel_cleanup_overlay(dev);
1369 if (!I915_NEED_GFX_HWS(dev))
1373 i915_gem_unload(dev);
1375 lockuninit(&dev_priv->irq_lock);
1377 if (dev_priv->tq != NULL)
1378 taskqueue_free(dev_priv->tq);
1380 bus_generic_detach(dev->device);
1381 drm_rmmap(dev, dev_priv->mmio_map);
1382 intel_teardown_gmbus(dev);
1384 lockuninit(&dev_priv->error_lock);
1385 lockuninit(&dev_priv->error_completion_lock);
1386 lockuninit(&dev_priv->rps_lock);
1387 drm_free(dev->dev_private, DRM_MEM_DRIVER);
1393 i915_driver_unload(struct drm_device *dev)
1396 return (i915_driver_unload_int(dev, true));
1400 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1402 struct drm_i915_file_private *i915_file_priv;
1404 i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1407 spin_init(&i915_file_priv->mm.lock);
1408 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1409 file_priv->driver_priv = i915_file_priv;
1415 i915_driver_lastclose(struct drm_device * dev)
1417 drm_i915_private_t *dev_priv = dev->dev_private;
1419 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1423 drm_fb_helper_restore();
1424 vga_switcheroo_process_delayed_switch();
1428 i915_gem_lastclose(dev);
1429 i915_dma_cleanup(dev);
1432 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1435 i915_gem_release(dev, file_priv);
1438 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1440 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1442 spin_uninit(&i915_file_priv->mm.lock);
1443 drm_free(i915_file_priv, DRM_MEM_FILES);
1446 struct drm_ioctl_desc i915_ioctls[] = {
1447 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1448 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1449 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1450 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1451 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1452 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1453 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1454 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1455 DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1456 DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1457 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1458 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1459 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1460 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1461 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1462 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1463 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1464 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1465 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1466 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1467 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1468 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1469 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1470 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1471 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1472 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1473 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1474 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1475 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1476 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1477 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1478 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1479 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1480 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1481 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1482 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1483 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1484 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1485 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1486 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1487 DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1488 DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1491 struct drm_driver_info i915_driver_info = {
1492 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1493 DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1494 DRIVER_GEM /*| DRIVER_MODESET*/,
1496 .buf_priv_size = sizeof(drm_i915_private_t),
1497 .load = i915_driver_load,
1498 .open = i915_driver_open,
1499 .unload = i915_driver_unload,
1500 .preclose = i915_driver_preclose,
1501 .lastclose = i915_driver_lastclose,
1502 .postclose = i915_driver_postclose,
1503 .device_is_agp = i915_driver_device_is_agp,
1504 .gem_init_object = i915_gem_init_object,
1505 .gem_free_object = i915_gem_free_object,
1506 .gem_pager_ops = &i915_gem_pager_ops,
1507 .dumb_create = i915_gem_dumb_create,
1508 .dumb_map_offset = i915_gem_mmap_gtt,
1509 .dumb_destroy = i915_gem_dumb_destroy,
1510 .sysctl_init = i915_sysctl_init,
1511 .sysctl_cleanup = i915_sysctl_cleanup,
1513 .ioctls = i915_ioctls,
1514 .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls),
1516 .name = DRIVER_NAME,
1517 .desc = DRIVER_DESC,
1518 .date = DRIVER_DATE,
1519 .major = DRIVER_MAJOR,
1520 .minor = DRIVER_MINOR,
1521 .patchlevel = DRIVER_PATCHLEVEL,
1525 * Determine if the device really is AGP or not.
1527 * All Intel graphics chipsets are treated as AGP, even if they are really
1530 * \param dev The device to be tested.
1533 * A value of 1 is always retured to indictate every i9x5 is AGP.
1535 int i915_driver_device_is_agp(struct drm_device * dev)
1540 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1542 drm_i915_private_t *dev_priv = dev->dev_private;
1545 tmp = I915_READ(CLKCFG);
1547 switch (tmp & CLKCFG_FSB_MASK) {
1548 case CLKCFG_FSB_533:
1549 dev_priv->fsb_freq = 533; /* 133*4 */
1551 case CLKCFG_FSB_800:
1552 dev_priv->fsb_freq = 800; /* 200*4 */
1554 case CLKCFG_FSB_667:
1555 dev_priv->fsb_freq = 667; /* 167*4 */
1557 case CLKCFG_FSB_400:
1558 dev_priv->fsb_freq = 400; /* 100*4 */
1562 switch (tmp & CLKCFG_MEM_MASK) {
1563 case CLKCFG_MEM_533:
1564 dev_priv->mem_freq = 533;
1566 case CLKCFG_MEM_667:
1567 dev_priv->mem_freq = 667;
1569 case CLKCFG_MEM_800:
1570 dev_priv->mem_freq = 800;
1574 /* detect pineview DDR3 setting */
1575 tmp = I915_READ(CSHRDDR3CTL);
1576 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1579 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1581 drm_i915_private_t *dev_priv = dev->dev_private;
1584 ddrpll = I915_READ16(DDRMPLL1);
1585 csipll = I915_READ16(CSIPLL0);
1587 switch (ddrpll & 0xff) {
1589 dev_priv->mem_freq = 800;
1592 dev_priv->mem_freq = 1066;
1595 dev_priv->mem_freq = 1333;
1598 dev_priv->mem_freq = 1600;
1601 DRM_DEBUG("unknown memory frequency 0x%02x\n",
1603 dev_priv->mem_freq = 0;
1607 dev_priv->r_t = dev_priv->mem_freq;
1609 switch (csipll & 0x3ff) {
1611 dev_priv->fsb_freq = 3200;
1614 dev_priv->fsb_freq = 3733;
1617 dev_priv->fsb_freq = 4266;
1620 dev_priv->fsb_freq = 4800;
1623 dev_priv->fsb_freq = 5333;
1626 dev_priv->fsb_freq = 5866;
1629 dev_priv->fsb_freq = 6400;
1632 DRM_DEBUG("unknown fsb frequency 0x%04x\n",
1634 dev_priv->fsb_freq = 0;
1638 if (dev_priv->fsb_freq == 3200) {
1640 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1647 static const struct cparams {
1653 { 1, 1333, 301, 28664 },
1654 { 1, 1066, 294, 24460 },
1655 { 1, 800, 294, 25192 },
1656 { 0, 1333, 276, 27605 },
1657 { 0, 1066, 276, 27605 },
1658 { 0, 800, 231, 23784 },
1661 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1663 u64 total_count, diff, ret;
1664 u32 count1, count2, count3, m = 0, c = 0;
1665 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1668 diff1 = now - dev_priv->last_time1;
1670 * sysctl(8) reads the value of sysctl twice in rapid
1671 * succession. There is high chance that it happens in the
1672 * same timer tick. Use the cached value to not divide by
1673 * zero and give the hw a chance to gather more samples.
1676 return (dev_priv->chipset_power);
1678 count1 = I915_READ(DMIEC);
1679 count2 = I915_READ(DDREC);
1680 count3 = I915_READ(CSIEC);
1682 total_count = count1 + count2 + count3;
1684 /* FIXME: handle per-counter overflow */
1685 if (total_count < dev_priv->last_count1) {
1686 diff = ~0UL - dev_priv->last_count1;
1687 diff += total_count;
1689 diff = total_count - dev_priv->last_count1;
1692 for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) {
1693 if (cparams[i].i == dev_priv->c_m &&
1694 cparams[i].t == dev_priv->r_t) {
1701 diff = diff / diff1;
1702 ret = ((m * diff) + c);
1705 dev_priv->last_count1 = total_count;
1706 dev_priv->last_time1 = now;
1708 dev_priv->chipset_power = ret;
1712 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1714 unsigned long m, x, b;
1717 tsfs = I915_READ(TSFS);
1719 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1720 x = I915_READ8(I915_TR1);
1722 b = tsfs & TSFS_INTR_MASK;
1724 return ((m * x) / 127) - b;
1727 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1729 static const struct v_table {
1730 u16 vd; /* in .1 mil */
1731 u16 vm; /* in .1 mil */
1862 if (dev_priv->info->is_mobile)
1863 return v_table[pxvid].vm;
1865 return v_table[pxvid].vd;
1868 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1870 struct timespec now, diff1;
1872 unsigned long diffms;
1875 if (dev_priv->info->gen != 5)
1880 timespecsub(&diff1, &dev_priv->last_time2);
1882 /* Don't divide by 0 */
1883 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1887 count = I915_READ(GFXEC);
1889 if (count < dev_priv->last_count2) {
1890 diff = ~0UL - dev_priv->last_count2;
1893 diff = count - dev_priv->last_count2;
1896 dev_priv->last_count2 = count;
1897 dev_priv->last_time2 = now;
1899 /* More magic constants... */
1901 diff = diff / (diffms * 10);
1902 dev_priv->gfx_power = diff;
1905 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1907 unsigned long t, corr, state1, corr2, state2;
1910 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1911 pxvid = (pxvid >> 24) & 0x7f;
1912 ext_v = pvid_to_extvid(dev_priv, pxvid);
1916 t = i915_mch_val(dev_priv);
1918 /* Revel in the empirically derived constants */
1920 /* Correction factor in 1/100000 units */
1922 corr = ((t * 2349) + 135940);
1924 corr = ((t * 964) + 29317);
1926 corr = ((t * 301) + 1004);
1928 corr = corr * ((150142 * state1) / 10000 - 78642);
1930 corr2 = (corr * dev_priv->corr);
1932 state2 = (corr2 * state1) / 10000;
1933 state2 /= 100; /* convert to mW */
1935 i915_update_gfx_val(dev_priv);
1937 return dev_priv->gfx_power + state2;
1941 * i915_read_mch_val - return value for IPS use
1943 * Calculate and return a value for the IPS driver to use when deciding whether
1944 * we have thermal and power headroom to increase CPU or GPU power budget.
1946 unsigned long i915_read_mch_val(void)
1948 struct drm_i915_private *dev_priv;
1949 unsigned long chipset_val, graphics_val, ret = 0;
1951 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1954 dev_priv = i915_mch_dev;
1956 chipset_val = i915_chipset_val(dev_priv);
1957 graphics_val = i915_gfx_val(dev_priv);
1959 ret = chipset_val + graphics_val;
1962 lockmgr(&mchdev_lock, LK_RELEASE);
1968 * i915_gpu_raise - raise GPU frequency limit
1970 * Raise the limit; IPS indicates we have thermal headroom.
1972 bool i915_gpu_raise(void)
1974 struct drm_i915_private *dev_priv;
1977 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1978 if (!i915_mch_dev) {
1982 dev_priv = i915_mch_dev;
1984 if (dev_priv->max_delay > dev_priv->fmax)
1985 dev_priv->max_delay--;
1988 lockmgr(&mchdev_lock, LK_RELEASE);
1994 * i915_gpu_lower - lower GPU frequency limit
1996 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1997 * frequency maximum.
1999 bool i915_gpu_lower(void)
2001 struct drm_i915_private *dev_priv;
2004 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2005 if (!i915_mch_dev) {
2009 dev_priv = i915_mch_dev;
2011 if (dev_priv->max_delay < dev_priv->min_delay)
2012 dev_priv->max_delay++;
2015 lockmgr(&mchdev_lock, LK_RELEASE);
2021 * i915_gpu_busy - indicate GPU business to IPS
2023 * Tell the IPS driver whether or not the GPU is busy.
2025 bool i915_gpu_busy(void)
2027 struct drm_i915_private *dev_priv;
2030 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2033 dev_priv = i915_mch_dev;
2035 ret = dev_priv->busy;
2038 lockmgr(&mchdev_lock, LK_RELEASE);
2044 * i915_gpu_turbo_disable - disable graphics turbo
2046 * Disable graphics turbo by resetting the max frequency and setting the
2047 * current frequency to the default.
2049 bool i915_gpu_turbo_disable(void)
2051 struct drm_i915_private *dev_priv;
2054 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2055 if (!i915_mch_dev) {
2059 dev_priv = i915_mch_dev;
2061 dev_priv->max_delay = dev_priv->fstart;
2063 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2067 lockmgr(&mchdev_lock, LK_RELEASE);