2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eric Anholt <eric@anholt.net>
26 * $FreeBSD: src/sys/dev/drm2/i915/intel_bios.h,v 1.1 2012/05/22 11:07:44 kib Exp $
32 #include <dev/drm/drmP.h>
35 u8 signature[20]; /**< Always starts with 'VBT$' */
36 u16 version; /**< decimal */
37 u16 header_size; /**< in bytes */
38 u16 vbt_size; /**< in bytes */
41 u32 bdb_offset; /**< from beginning of VBT */
42 u32 aim_offset[4]; /**< from beginning of VBT */
43 } __attribute__((packed));
46 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
47 u16 version; /**< decimal */
48 u16 header_size; /**< in bytes */
49 u16 bdb_size; /**< in bytes */
52 /* strictly speaking, this is a "skip" block, but it has interesting info */
54 u8 type; /* 0 == desktop, 1 == mobile */
59 u8 rsvd2:6; /* finish byte */
66 u8 rsvd4; /* popup memory size */
68 u8 rsvd5; /* is crt already on ddc2 */
69 } __attribute__((packed));
72 * There are several types of BIOS data blocks (BDBs), each block has
73 * an ID and size in the first 3 bytes (ID in first, size in next 2).
74 * Known types are listed below.
76 #define BDB_GENERAL_FEATURES 1
77 #define BDB_GENERAL_DEFINITIONS 2
78 #define BDB_OLD_TOGGLE_LIST 3
79 #define BDB_MODE_SUPPORT_LIST 4
80 #define BDB_GENERIC_MODE_TABLE 5
81 #define BDB_EXT_MMIO_REGS 6
83 #define BDB_SWF_MMIO 8
84 #define BDB_DOT_CLOCK_TABLE 9
85 #define BDB_MODE_REMOVAL_TABLE 10
86 #define BDB_CHILD_DEVICE_TABLE 11
87 #define BDB_DRIVER_FEATURES 12
88 #define BDB_DRIVER_PERSISTENCE 13
89 #define BDB_EXT_TABLE_PTRS 14
90 #define BDB_DOT_CLOCK_OVERRIDE 15
91 #define BDB_DISPLAY_SELECT 16
93 #define BDB_DRIVER_ROTATION 18
94 #define BDB_DISPLAY_REMOVE 19
95 #define BDB_OEM_CUSTOM 20
96 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
97 #define BDB_SDVO_LVDS_OPTIONS 22
98 #define BDB_SDVO_PANEL_DTDS 23
99 #define BDB_SDVO_LVDS_PNP_IDS 24
100 #define BDB_SDVO_LVDS_POWER_SEQ 25
101 #define BDB_TV_OPTIONS 26
103 #define BDB_LVDS_OPTIONS 40
104 #define BDB_LVDS_LFP_DATA_PTRS 41
105 #define BDB_LVDS_LFP_DATA 42
106 #define BDB_LVDS_BACKLIGHT 43
107 #define BDB_LVDS_POWER 44
108 #define BDB_SKIP 254 /* VBIOS private block, ignore */
110 struct bdb_general_features {
119 u8 download_ext_vbt:1;
122 u8 enable_lfp_on_override:1;
123 u8 disable_ssc_ddt:1;
125 u8 display_clock_mode:1;
126 u8 rsvd8:1; /* finish byte */
129 u8 disable_smooth_vision:1;
131 u8 rsvd9:6; /* finish byte */
134 u8 legacy_monitor_detect;
137 u8 int_crt_support:1;
139 u8 int_efp_support:1;
140 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
141 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
142 u8 rsvd11:3; /* finish byte */
143 } __attribute__((packed));
146 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
147 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
148 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
149 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
152 #define DEVICE_TYPE_NONE 0x00
153 #define DEVICE_TYPE_CRT 0x01
154 #define DEVICE_TYPE_TV 0x09
155 #define DEVICE_TYPE_EFP 0x12
156 #define DEVICE_TYPE_LFP 0x22
158 #define DEVICE_TYPE_CRT_DPMS 0x6001
159 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
160 #define DEVICE_TYPE_TV_COMPOSITE 0x0209
161 #define DEVICE_TYPE_TV_MACROVISION 0x0289
162 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
163 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
164 #define DEVICE_TYPE_TV_SCART 0x0209
165 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
166 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
167 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
168 #define DEVICE_TYPE_EFP_DVI_I 0x6053
169 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
170 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
171 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
172 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
173 #define DEVICE_TYPE_LFP_PANELLINK 0x5012
174 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
175 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
176 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
177 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
179 #define DEVICE_CFG_NONE 0x00
180 #define DEVICE_CFG_12BIT_DVOB 0x01
181 #define DEVICE_CFG_12BIT_DVOC 0x02
182 #define DEVICE_CFG_24BIT_DVOBC 0x09
183 #define DEVICE_CFG_24BIT_DVOCB 0x0a
184 #define DEVICE_CFG_DUAL_DVOB 0x11
185 #define DEVICE_CFG_DUAL_DVOC 0x12
186 #define DEVICE_CFG_DUAL_DVOBC 0x13
187 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
188 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
190 #define DEVICE_WIRE_NONE 0x00
191 #define DEVICE_WIRE_DVOB 0x01
192 #define DEVICE_WIRE_DVOC 0x02
193 #define DEVICE_WIRE_DVOBC 0x03
194 #define DEVICE_WIRE_DVOBB 0x05
195 #define DEVICE_WIRE_DVOCC 0x06
196 #define DEVICE_WIRE_DVOB_MASTER 0x0d
197 #define DEVICE_WIRE_DVOC_MASTER 0x0e
199 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
200 #define DEVICE_PORT_DVOB 0x01
201 #define DEVICE_PORT_DVOC 0x02
203 struct child_device_config {
206 u8 device_id[10]; /* ascii string */
208 u8 dvo_port; /* See Device_PORT_* above */
213 u8 dvo_cfg; /* See DEVICE_CFG_* above */
219 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
223 } __attribute__((packed));
225 struct bdb_general_definitions {
227 u8 crt_ddc_gmbus_pin;
231 u8 skip_boot_crt_detect:1;
233 u8 rsvd1:5; /* finish byte */
235 /* boot device bits */
241 * If TV is present, it'll be at devices[0].
242 * LVDS will be next, either devices[0] or [1], if present.
243 * On some platforms the number of device is 6. But could be as few as
244 * 4 if both TV and LVDS are missing.
245 * And the device num is related with the size of general definition
246 * block. It is obtained by using the following formula:
247 * number = (block_size - sizeof(bdb_general_definitions))/
248 * sizeof(child_device_config);
250 struct child_device_config devices[0];
251 } __attribute__((packed));
253 struct bdb_lvds_options {
256 /* LVDS capabilities, stored in a dword */
258 u8 pfit_text_mode_enhanced:1;
259 u8 pfit_gfx_mode_enhanced:1;
260 u8 pfit_ratio_auto:1;
265 } __attribute__((packed));
267 /* LFP pointer table contains entries to the struct below */
268 struct bdb_lvds_lfp_data_ptr {
269 u16 fp_timing_offset; /* offsets are from start of bdb */
271 u16 dvo_timing_offset;
273 u16 panel_pnp_id_offset;
275 } __attribute__((packed));
277 struct bdb_lvds_lfp_data_ptrs {
278 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
279 struct bdb_lvds_lfp_data_ptr ptr[16];
280 } __attribute__((packed));
282 /* LFP data has 3 blocks per entry */
283 struct lvds_fp_timing {
293 u32 pp_cycle_reg_val;
297 } __attribute__((packed));
299 struct lvds_dvo_timing {
300 u16 clock; /**< In 10khz */
310 u8 hsync_pulse_width;
311 u8 vsync_pulse_width:4;
325 } __attribute__((packed));
333 } __attribute__((packed));
335 struct bdb_lvds_lfp_data_entry {
336 struct lvds_fp_timing fp_timing;
337 struct lvds_dvo_timing dvo_timing;
338 struct lvds_pnp_id pnp_id;
339 } __attribute__((packed));
341 struct bdb_lvds_lfp_data {
342 struct bdb_lvds_lfp_data_entry data[16];
343 } __attribute__((packed));
345 struct aimdb_header {
349 u16 aimdb_header_size;
351 } __attribute__((packed));
356 } __attribute__((packed));
358 struct vch_panel_data {
359 u16 fp_timing_offset;
361 u16 dvo_timing_offset;
363 u16 text_fitting_offset;
364 u8 text_fitting_size;
365 u16 graphics_fitting_offset;
366 u8 graphics_fitting_size;
367 } __attribute__((packed));
370 struct aimdb_block aimdb_block;
371 struct vch_panel_data panels[16];
372 } __attribute__((packed));
374 struct bdb_sdvo_lvds_options {
376 u8 h40_set_panel_type;
381 u8 sclalarcoeff_tab_row_num;
382 u8 sclalarcoeff_tab_row_size;
384 u8 panel_misc_bits_1;
385 u8 panel_misc_bits_2;
386 u8 panel_misc_bits_3;
387 u8 panel_misc_bits_4;
388 } __attribute__((packed));
391 #define BDB_DRIVER_FEATURE_NO_LVDS 0
392 #define BDB_DRIVER_FEATURE_INT_LVDS 1
393 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2
394 #define BDB_DRIVER_FEATURE_EDP 3
396 struct bdb_driver_features {
397 u8 boot_dev_algorithm:1;
398 u8 block_display_switch:1;
399 u8 allow_display_switch:1;
403 u8 sprite_in_clone:1;
409 u8 boot_mode_refresh;
411 u16 enable_lfp_primary:1;
412 u16 selective_mode_pruning:1;
413 u16 dual_frequency:1;
414 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
415 u16 nt_clone_support:1;
416 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
417 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
418 u16 cui_aspect_scaling:1;
419 u16 preserve_aspect_ratio:1;
420 u16 sdvo_device_power_down:1;
428 u16 legacy_crt_max_x;
429 u16 legacy_crt_max_y;
430 u8 legacy_crt_max_refresh;
433 u8 custom_vbt_version;
434 } __attribute__((packed));
439 #define EDP_RATE_1_62 0
440 #define EDP_RATE_2_7 1
444 #define EDP_PREEMPHASIS_NONE 0
445 #define EDP_PREEMPHASIS_3_5dB 1
446 #define EDP_PREEMPHASIS_6dB 2
447 #define EDP_PREEMPHASIS_9_5dB 3
448 #define EDP_VSWING_0_4V 0
449 #define EDP_VSWING_0_6V 1
450 #define EDP_VSWING_0_8V 2
451 #define EDP_VSWING_1_2V 3
453 struct edp_power_seq {
459 } __attribute__ ((packed));
461 struct edp_link_params {
466 } __attribute__ ((packed));
469 struct edp_power_seq power_seqs[16];
471 struct edp_link_params link_params[16];
472 u32 sdrrs_msa_timing_delay;
474 /* ith bit indicates enabled/disabled for (i+1)th panel */
476 u16 edp_t3_optimization;
477 } __attribute__ ((packed));
479 void intel_setup_bios(struct drm_device *dev);
480 bool intel_parse_bios(struct drm_device *dev);
483 * Driver<->VBIOS interaction occurs through scratch bits in
487 /* GR18 bits are set on display switch and hotkey events */
488 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
489 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
490 #define GR18_HK_NONE (0x0<<3)
491 #define GR18_HK_LFP_STRETCH (0x1<<3)
492 #define GR18_HK_TOGGLE_DISP (0x2<<3)
493 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
494 #define GR18_HK_POPUP_DISABLED (0x6<<3)
495 #define GR18_HK_POPUP_ENABLED (0x7<<3)
496 #define GR18_HK_PFIT (0x8<<3)
497 #define GR18_HK_APM_CHANGE (0xa<<3)
498 #define GR18_HK_MULTIPLE (0xc<<3)
499 #define GR18_USER_INT_EN (1<<2)
500 #define GR18_A0000_FLUSH_EN (1<<1)
501 #define GR18_SMM_EN (1<<0)
503 /* Set by driver, cleared by VBIOS */
504 #define SWF00_YRES_SHIFT 16
505 #define SWF00_XRES_SHIFT 0
506 #define SWF00_RES_MASK 0xffff
508 /* Set by VBIOS at boot time and driver at runtime */
509 #define SWF01_TV2_FORMAT_SHIFT 8
510 #define SWF01_TV1_FORMAT_SHIFT 0
511 #define SWF01_TV_FORMAT_MASK 0xffff
513 #define SWF10_VBIOS_BLC_I2C_EN (1<<29)
514 #define SWF10_GTT_OVERRIDE_EN (1<<28)
515 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
516 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
517 #define SWF10_OLD_TOGGLE 0x0
518 #define SWF10_TOGGLE_LIST_1 0x1
519 #define SWF10_TOGGLE_LIST_2 0x2
520 #define SWF10_TOGGLE_LIST_3 0x3
521 #define SWF10_TOGGLE_LIST_4 0x4
522 #define SWF10_PANNING_EN (1<<23)
523 #define SWF10_DRIVER_LOADED (1<<22)
524 #define SWF10_EXTENDED_DESKTOP (1<<21)
525 #define SWF10_EXCLUSIVE_MODE (1<<20)
526 #define SWF10_OVERLAY_EN (1<<19)
527 #define SWF10_PLANEB_HOLDOFF (1<<18)
528 #define SWF10_PLANEA_HOLDOFF (1<<17)
529 #define SWF10_VGA_HOLDOFF (1<<16)
530 #define SWF10_ACTIVE_DISP_MASK 0xffff
531 #define SWF10_PIPEB_LFP2 (1<<15)
532 #define SWF10_PIPEB_EFP2 (1<<14)
533 #define SWF10_PIPEB_TV2 (1<<13)
534 #define SWF10_PIPEB_CRT2 (1<<12)
535 #define SWF10_PIPEB_LFP (1<<11)
536 #define SWF10_PIPEB_EFP (1<<10)
537 #define SWF10_PIPEB_TV (1<<9)
538 #define SWF10_PIPEB_CRT (1<<8)
539 #define SWF10_PIPEA_LFP2 (1<<7)
540 #define SWF10_PIPEA_EFP2 (1<<6)
541 #define SWF10_PIPEA_TV2 (1<<5)
542 #define SWF10_PIPEA_CRT2 (1<<4)
543 #define SWF10_PIPEA_LFP (1<<3)
544 #define SWF10_PIPEA_EFP (1<<2)
545 #define SWF10_PIPEA_TV (1<<1)
546 #define SWF10_PIPEA_CRT (1<<0)
548 #define SWF11_MEMORY_SIZE_SHIFT 16
549 #define SWF11_SV_TEST_EN (1<<15)
550 #define SWF11_IS_AGP (1<<14)
551 #define SWF11_DISPLAY_HOLDOFF (1<<13)
552 #define SWF11_DPMS_REDUCED (1<<12)
553 #define SWF11_IS_VBE_MODE (1<<11)
554 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
555 #define SWF11_DPMS_MASK 0x07
556 #define SWF11_DPMS_OFF (1<<2)
557 #define SWF11_DPMS_SUSPEND (1<<1)
558 #define SWF11_DPMS_STANDBY (1<<0)
559 #define SWF11_DPMS_ON 0
561 #define SWF14_GFX_PFIT_EN (1<<31)
562 #define SWF14_TEXT_PFIT_EN (1<<30)
563 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
564 #define SWF14_POPUP_EN (1<<28)
565 #define SWF14_DISPLAY_HOLDOFF (1<<27)
566 #define SWF14_DISP_DETECT_EN (1<<26)
567 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
568 #define SWF14_DRIVER_STATUS (1<<24)
569 #define SWF14_OS_TYPE_WIN9X (1<<23)
570 #define SWF14_OS_TYPE_WINNT (1<<22)
572 #define SWF14_PM_TYPE_MASK 0x00070000
573 #define SWF14_PM_ACPI_VIDEO (0x4 << 16)
574 #define SWF14_PM_ACPI (0x3 << 16)
575 #define SWF14_PM_APM_12 (0x2 << 16)
576 #define SWF14_PM_APM_11 (0x1 << 16)
577 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
578 /* if GR18 indicates a display switch */
579 #define SWF14_DS_PIPEB_LFP2_EN (1<<15)
580 #define SWF14_DS_PIPEB_EFP2_EN (1<<14)
581 #define SWF14_DS_PIPEB_TV2_EN (1<<13)
582 #define SWF14_DS_PIPEB_CRT2_EN (1<<12)
583 #define SWF14_DS_PIPEB_LFP_EN (1<<11)
584 #define SWF14_DS_PIPEB_EFP_EN (1<<10)
585 #define SWF14_DS_PIPEB_TV_EN (1<<9)
586 #define SWF14_DS_PIPEB_CRT_EN (1<<8)
587 #define SWF14_DS_PIPEA_LFP2_EN (1<<7)
588 #define SWF14_DS_PIPEA_EFP2_EN (1<<6)
589 #define SWF14_DS_PIPEA_TV2_EN (1<<5)
590 #define SWF14_DS_PIPEA_CRT2_EN (1<<4)
591 #define SWF14_DS_PIPEA_LFP_EN (1<<3)
592 #define SWF14_DS_PIPEA_EFP_EN (1<<2)
593 #define SWF14_DS_PIPEA_TV_EN (1<<1)
594 #define SWF14_DS_PIPEA_CRT_EN (1<<0)
595 /* if GR18 indicates a panel fitting request */
596 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */
597 /* if GR18 indicates an APM change request */
598 #define SWF14_APM_HIBERNATE 0x4
599 #define SWF14_APM_SUSPEND 0x3
600 #define SWF14_APM_STANDBY 0x1
601 #define SWF14_APM_RESTORE 0x0
603 /* Add the device class for LFP, TV, HDMI */
604 #define DEVICE_TYPE_INT_LFP 0x1022
605 #define DEVICE_TYPE_INT_TV 0x1009
606 #define DEVICE_TYPE_HDMI 0x60D2
607 #define DEVICE_TYPE_DP 0x68C6
608 #define DEVICE_TYPE_eDP 0x78C6
610 /* define the DVO port for HDMI output type */
615 /* define the PORT for DP output type */
620 #endif /* _I830_BIOS_H_ */