2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine/cputypes.h>
57 #include <machine_base/apic/mpapic.h>
58 #include <machine/psl.h>
59 #include <machine/segments.h>
60 #include <machine/tss.h>
61 #include <machine/specialreg.h>
62 #include <machine/globaldata.h>
64 #include <machine/md_var.h> /* setidt() */
65 #include <machine_base/icu/icu.h> /* IPIs */
66 #include <machine_base/isa/intr_machdep.h> /* IPIs */
68 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
70 #define WARMBOOT_TARGET 0
71 #define WARMBOOT_OFF (KERNBASE + 0x0467)
72 #define WARMBOOT_SEG (KERNBASE + 0x0469)
74 #define BIOS_BASE (0xf0000)
75 #define BIOS_BASE2 (0xe0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 void *oem_table_pointer;
112 u_short oem_table_size;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_long cpu_signature;
127 u_long feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
169 typedef int (*mptable_iter_func)(void *, const void *, int);
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
189 #define CHECK_PRINT(S); \
190 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
199 #else /* CHECK_POINTS */
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
204 #endif /* CHECK_POINTS */
207 * Values to send to the POST hardware.
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
221 #define MP_ANNOUNCE_POST 0x19
223 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
224 int current_postcode;
226 /** XXX FIXME: what system files declare these??? */
227 extern struct region_descriptor r_gdt, r_idt;
229 int mp_naps; /* # of Applications processors */
231 static int mp_nbusses; /* # of busses */
232 int mp_napics; /* # of IO APICs */
235 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
236 u_int32_t *io_apic_versions;
240 u_int32_t cpu_apic_versions[MAXCPU];
242 extern int64_t tsc_offsets[];
244 extern u_long ebda_addr;
247 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
254 int cpu_num_to_apic_id[NAPICID];
256 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
264 /* Hotwire a 0->4MB V==P mapping */
265 extern pt_entry_t *KPTphys;
268 * SMP page table page. Setup by locore to point to a page table
269 * page from which we allocate per-cpu privatespace areas io_apics,
273 #define IO_MAPPING_START_INDEX \
274 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
276 extern pt_entry_t *SMPpt;
277 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
279 struct pcb stoppcbs[MAXCPU];
281 static basetable_entry basetable_entry_types[] =
283 {0, 20, "Processor"},
291 * Local data and functions.
294 static u_int boot_address;
295 static u_int base_memory;
296 static int mp_finish;
298 static void mp_enable(u_int boot_addr);
300 static int mptable_iterate_entries(const mpcth_t,
301 mptable_iter_func, void *);
302 static int mptable_probe(void);
303 static int mptable_search(void);
304 static int mptable_check(vm_paddr_t);
305 static int mptable_search_sig(u_int32_t target, int count);
306 static int mptable_hyperthread_fixup(u_int, int);
307 static void mptable_pass1(struct mptable_pos *);
308 static void mptable_pass2(struct mptable_pos *);
309 static void mptable_default(int type);
310 static void mptable_fix(void);
311 static int mptable_map(struct mptable_pos *, vm_paddr_t);
312 static void mptable_unmap(struct mptable_pos *);
313 static void mptable_imcr(struct mptable_pos *);
315 static int mptable_lapic_probe(struct lapic_enumerator *);
316 static void mptable_lapic_enumerate(struct lapic_enumerator *);
317 static void mptable_lapic_default(void);
320 static void setup_apic_irq_mapping(void);
321 static int apic_int_is_bus_type(int intr, int bus_type);
323 static int start_all_aps(u_int boot_addr);
324 static void install_ap_tramp(u_int boot_addr);
325 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
327 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
328 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
329 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
332 * Calculate usable address in base memory for AP trampoline code.
335 mp_bootaddress(u_int basemem)
337 POSTCODE(MP_BOOTADDRESS_POST);
339 base_memory = basemem;
341 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
342 if ((base_memory - boot_address) < bootMP_size)
343 boot_address -= 4096; /* not enough, lower by 4k */
354 mpfps_paddr = mptable_search();
355 if (mptable_check(mpfps_paddr))
362 * Look for an Intel MP spec table (ie, SMP capable hardware).
371 * Make sure our SMPpt[] page table is big enough to hold all the
374 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
376 POSTCODE(MP_PROBE_POST);
378 /* see if EBDA exists */
379 if (ebda_addr != 0) {
380 /* search first 1K of EBDA */
381 target = (u_int32_t)ebda_addr;
382 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
385 /* last 1K of base memory, effective 'top of base' passed in */
386 target = (u_int32_t)(base_memory - 0x400);
387 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
391 /* search the BIOS */
392 target = (u_int32_t)BIOS_BASE;
393 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
396 /* search the extended BIOS */
397 target = (u_int32_t)BIOS_BASE2;
398 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
405 struct mptable_check_cbarg {
411 mptable_check_callback(void *xarg, const void *pos, int type)
413 const struct PROCENTRY *ent;
414 struct mptable_check_cbarg *arg = xarg;
420 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
424 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
425 if (arg->found_bsp) {
426 kprintf("more than one BSP in base MP table\n");
435 mptable_check(vm_paddr_t mpfps_paddr)
437 struct mptable_pos mpt;
438 struct mptable_check_cbarg arg;
442 if (mpfps_paddr == 0)
445 error = mptable_map(&mpt, mpfps_paddr);
449 if (mpt.mp_fps->mpfb1 != 0)
457 if (cth->apic_address == 0)
460 bzero(&arg, sizeof(arg));
461 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
463 if (arg.cpu_count == 0) {
464 kprintf("MP table contains no processor entries\n");
466 } else if (!arg.found_bsp) {
467 kprintf("MP table does not contains BSP entry\n");
477 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
479 int count, total_size;
480 const void *position;
482 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
483 total_size = cth->base_table_length - sizeof(struct MPCTH);
484 position = (const uint8_t *)cth + sizeof(struct MPCTH);
485 count = cth->entry_count;
490 KKASSERT(total_size >= 0);
491 if (total_size == 0) {
492 kprintf("invalid base MP table, "
493 "entry count and length mismatch\n");
497 type = *(const uint8_t *)position;
499 case 0: /* processor_entry */
500 case 1: /* bus_entry */
501 case 2: /* io_apic_entry */
502 case 3: /* int_entry */
503 case 4: /* int_entry */
506 kprintf("unknown base MP table entry type %d\n", type);
510 if (total_size < basetable_entry_types[type].length) {
511 kprintf("invalid base MP table length, "
512 "does not contain all entries\n");
515 total_size -= basetable_entry_types[type].length;
517 error = func(arg, position, type);
521 position = (const uint8_t *)position +
522 basetable_entry_types[type].length;
529 * Startup the SMP processors.
534 POSTCODE(MP_START_POST);
535 mp_enable(boot_address);
540 * Print various information about the SMP system hardware and setup.
547 POSTCODE(MP_ANNOUNCE_POST);
549 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
550 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
551 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
552 for (x = 1; x <= mp_naps; ++x) {
553 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
554 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
558 for (x = 0; x < mp_napics; ++x) {
559 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
560 kprintf(", version: 0x%08x", io_apic_versions[x]);
561 kprintf(", at 0x%08lx\n", io_apic_address[x]);
564 kprintf(" Warning: APIC I/O disabled\n");
569 * AP cpu's call this to sync up protected mode.
571 * WARNING! We must ensure that the cpu is sufficiently initialized to
572 * be able to use to the FP for our optimized bzero/bcopy code before
573 * we enter more mainstream C code.
575 * WARNING! %fs is not set up on entry. This routine sets up %fs.
581 int x, myid = bootAP;
583 struct mdglobaldata *md;
584 struct privatespace *ps;
586 ps = &CPU_prvspace[myid];
588 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
589 gdt_segs[GPROC0_SEL].ssd_base =
590 (int) &ps->mdglobaldata.gd_common_tss;
591 ps->mdglobaldata.mi.gd_prvspace = ps;
593 for (x = 0; x < NGDT; x++) {
594 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
597 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
598 r_gdt.rd_base = (int) &gdt[myid * NGDT];
599 lgdt(&r_gdt); /* does magic intra-segment return */
604 mdcpu->gd_currentldt = _default_ldt;
606 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
607 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
609 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
611 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
612 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
613 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
614 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
615 md->gd_common_tssd = *md->gd_tss_gdt;
619 * Set to a known state:
620 * Set by mpboot.s: CR0_PG, CR0_PE
621 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
624 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
626 pmap_set_opt(); /* PSE/4MB pages, etc */
628 /* set up CPU registers and state */
631 /* set up FPU state on the AP */
632 npxinit(__INITIAL_NPXCW__);
634 /* set up SSE registers */
638 /*******************************************************************
639 * local functions and data
643 * start the SMP system
646 mp_enable(u_int boot_addr)
652 vm_paddr_t mpfps_paddr;
653 struct mptable_pos mpt;
655 POSTCODE(MP_ENABLE_POST);
659 mpfps_paddr = mptable_probe();
661 mptable_map(&mpt, mpfps_paddr);
668 panic("no MP table, disable APIC_IO!\n");
670 mptable_map(&mpt, mpfps_paddr);
673 * Examine the MP table for needed info
680 /* Post scan cleanup */
683 setup_apic_irq_mapping();
685 /* fill the LOGICAL io_apic_versions table */
686 for (apic = 0; apic < mp_napics; ++apic) {
687 ux = io_apic_read(apic, IOAPIC_VER);
688 io_apic_versions[apic] = ux;
689 io_apic_set_id(apic, IO_TO_ID(apic));
692 /* program each IO APIC in the system */
693 for (apic = 0; apic < mp_napics; ++apic)
694 if (io_apic_setup(apic) < 0)
695 panic("IO APIC setup failure");
700 * These are required for SMP operation
703 /* install a 'Spurious INTerrupt' vector */
704 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
705 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
707 /* install an inter-CPU IPI for TLB invalidation */
708 setidt(XINVLTLB_OFFSET, Xinvltlb,
709 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
711 /* install an inter-CPU IPI for IPIQ messaging */
712 setidt(XIPIQ_OFFSET, Xipiq,
713 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
715 /* install a timer vector */
716 setidt(XTIMER_OFFSET, Xtimer,
717 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
719 /* install an inter-CPU IPI for CPU stop/restart */
720 setidt(XCPUSTOP_OFFSET, Xcpustop,
721 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
723 /* start each Application Processor */
724 start_all_aps(boot_addr);
729 * look for the MP spec signature
732 /* string defined by the Intel MP Spec as identifying the MP table */
733 #define MP_SIG 0x5f504d5f /* _MP_ */
734 #define NEXT(X) ((X) += 4)
736 mptable_search_sig(u_int32_t target, int count)
742 KKASSERT(target != 0);
744 map_size = count * sizeof(u_int32_t);
745 addr = pmap_mapdev((vm_paddr_t)target, map_size);
748 for (x = 0; x < count; NEXT(x)) {
749 if (addr[x] == MP_SIG) {
750 /* make array index a byte index */
751 ret = target + (x * sizeof(u_int32_t));
756 pmap_unmapdev((vm_offset_t)addr, map_size);
761 typedef struct BUSDATA {
763 enum busTypes bus_type;
766 typedef struct INTDATA {
776 typedef struct BUSTYPENAME {
781 static bus_type_name bus_type_table[] =
787 {UNKNOWN_BUSTYPE, "---"},
790 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
796 {UNKNOWN_BUSTYPE, "---"},
797 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"}
803 /* from MP spec v1.4, table 5-1 */
804 static int default_data[7][5] =
806 /* nbus, id0, type0, id1, type1 */
807 {1, 0, ISA, 255, 255},
808 {1, 0, EISA, 255, 255},
809 {1, 0, EISA, 255, 255},
810 {1, 0, MCA, 255, 255},
812 {2, 0, EISA, 1, PCI},
820 static bus_datum *bus_data;
822 /* the IO INT data, one entry per possible APIC INTerrupt */
823 static io_int *io_apic_ints;
828 static int processor_entry (const struct PROCENTRY *entry, int cpu);
830 static int bus_entry (const struct BUSENTRY *entry, int bus);
831 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
832 static int int_entry (const struct INTENTRY *entry, int intr);
834 static int lookup_bus_type (char *name);
839 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
841 const struct IOAPICENTRY *ioapic_ent;
844 case 1: /* bus_entry */
848 case 2: /* io_apic_entry */
850 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
851 io_apic_address[mp_napics++] =
852 (vm_offset_t)ioapic_ent->apic_address;
856 case 3: /* int_entry */
866 * 1st pass on motherboard's Intel MP specification table.
875 mptable_pass1(struct mptable_pos *mpt)
881 POSTCODE(MPTABLE_PASS1_POST);
884 KKASSERT(fps != NULL);
886 /* clear various tables */
887 for (x = 0; x < NAPICID; ++x)
888 io_apic_address[x] = ~0; /* IO APIC address table */
894 /* check for use of 'default' configuration */
895 if (fps->mpfb1 != 0) {
896 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
897 mp_nbusses = default_data[fps->mpfb1 - 1][0];
903 error = mptable_iterate_entries(mpt->mp_cth,
904 mptable_ioapic_pass1_callback, NULL);
906 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
913 struct mptable_ioapic2_cbarg {
920 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
922 struct mptable_ioapic2_cbarg *arg = xarg;
926 if (bus_entry(pos, arg->bus))
931 if (io_apic_entry(pos, arg->apic))
936 if (int_entry(pos, arg->intr))
946 * 2nd pass on motherboard's Intel MP specification table.
949 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
950 * IO_TO_ID(N), logical IO to APIC ID table
955 mptable_pass2(struct mptable_pos *mpt)
958 struct mptable_ioapic2_cbarg arg;
962 POSTCODE(MPTABLE_PASS2_POST);
965 KKASSERT(fps != NULL);
967 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
969 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
970 M_DEVBUF, M_WAITOK | M_ZERO);
971 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
973 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
976 for (x = 0; x < mp_napics; x++)
977 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
979 /* clear various tables */
980 for (x = 0; x < NAPICID; ++x) {
981 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
982 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
985 /* clear bus data table */
986 for (x = 0; x < mp_nbusses; ++x)
987 bus_data[x].bus_id = 0xff;
989 /* clear IO APIC INT table */
990 for (x = 0; x < (nintrs + 1); ++x) {
991 io_apic_ints[x].int_type = 0xff;
992 io_apic_ints[x].int_vector = 0xff;
995 /* check for use of 'default' configuration */
996 if (fps->mpfb1 != 0) {
997 mptable_default(fps->mpfb1);
1001 bzero(&arg, sizeof(arg));
1002 error = mptable_iterate_entries(mpt->mp_cth,
1003 mptable_ioapic_pass2_callback, &arg);
1005 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1010 * Check if we should perform a hyperthreading "fix-up" to
1011 * enumerate any logical CPU's that aren't already listed
1014 * XXX: We assume that all of the physical CPUs in the
1015 * system have the same number of logical CPUs.
1017 * XXX: We assume that APIC ID's are allocated such that
1018 * the APIC ID's for a physical processor are aligned
1019 * with the number of logical CPU's in the processor.
1022 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1024 int i, id, lcpus_max, logical_cpus;
1026 if ((cpu_feature & CPUID_HTT) == 0)
1029 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1033 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1035 * INSTRUCTION SET REFERENCE, A-M (#253666)
1036 * Page 3-181, Table 3-20
1037 * "The nearest power-of-2 integer that is not smaller
1038 * than EBX[23:16] is the number of unique initial APIC
1039 * IDs reserved for addressing different logical
1040 * processors in a physical package."
1042 for (i = 0; ; ++i) {
1043 if ((1 << i) >= lcpus_max) {
1050 KKASSERT(cpu_count != 0);
1051 if (cpu_count == lcpus_max) {
1052 /* We have nothing to fix */
1054 } else if (cpu_count == 1) {
1055 /* XXX this may be incorrect */
1056 logical_cpus = lcpus_max;
1058 int cur, prev, dist;
1061 * Calculate the distances between two nearest
1062 * APIC IDs. If all such distances are same,
1063 * then it is the number of missing cpus that
1064 * we are going to fill later.
1066 dist = cur = prev = -1;
1067 for (id = 0; id < MAXCPU; ++id) {
1068 if ((id_mask & 1 << id) == 0)
1073 int new_dist = cur - prev;
1079 * Make sure that all distances
1080 * between two nearest APIC IDs
1083 if (dist != new_dist)
1091 /* Must be power of 2 */
1092 if (dist & (dist - 1))
1095 /* Can't exceed CPU package capacity */
1096 if (dist > lcpus_max)
1097 logical_cpus = lcpus_max;
1099 logical_cpus = dist;
1103 * For each APIC ID of a CPU that is set in the mask,
1104 * scan the other candidate APIC ID's for this
1105 * physical processor. If any of those ID's are
1106 * already in the table, then kill the fixup.
1108 for (id = 0; id < MAXCPU; id++) {
1109 if ((id_mask & 1 << id) == 0)
1111 /* First, make sure we are on a logical_cpus boundary. */
1112 if (id % logical_cpus != 0)
1114 for (i = id + 1; i < id + logical_cpus; i++)
1115 if ((id_mask & 1 << i) != 0)
1118 return logical_cpus;
1122 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1126 vm_size_t cth_mapsz = 0;
1128 bzero(mpt, sizeof(*mpt));
1130 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1131 if (fps->pap != 0) {
1133 * Map configuration table header to get
1134 * the base table size
1136 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1137 cth_mapsz = cth->base_table_length;
1138 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1140 if (cth_mapsz < sizeof(*cth)) {
1141 kprintf("invalid base MP table length %d\n",
1143 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1148 * Map the base table
1150 cth = pmap_mapdev(fps->pap, cth_mapsz);
1155 mpt->mp_cth_mapsz = cth_mapsz;
1161 mptable_unmap(struct mptable_pos *mpt)
1163 if (mpt->mp_cth != NULL) {
1164 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1166 mpt->mp_cth_mapsz = 0;
1168 if (mpt->mp_fps != NULL) {
1169 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1177 assign_apic_irq(int apic, int intpin, int irq)
1181 if (int_to_apicintpin[irq].ioapic != -1)
1182 panic("assign_apic_irq: inconsistent table");
1184 int_to_apicintpin[irq].ioapic = apic;
1185 int_to_apicintpin[irq].int_pin = intpin;
1186 int_to_apicintpin[irq].apic_address = ioapic[apic];
1187 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1189 for (x = 0; x < nintrs; x++) {
1190 if ((io_apic_ints[x].int_type == 0 ||
1191 io_apic_ints[x].int_type == 3) &&
1192 io_apic_ints[x].int_vector == 0xff &&
1193 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1194 io_apic_ints[x].dst_apic_int == intpin)
1195 io_apic_ints[x].int_vector = irq;
1200 revoke_apic_irq(int irq)
1206 if (int_to_apicintpin[irq].ioapic == -1)
1207 panic("revoke_apic_irq: inconsistent table");
1209 oldapic = int_to_apicintpin[irq].ioapic;
1210 oldintpin = int_to_apicintpin[irq].int_pin;
1212 int_to_apicintpin[irq].ioapic = -1;
1213 int_to_apicintpin[irq].int_pin = 0;
1214 int_to_apicintpin[irq].apic_address = NULL;
1215 int_to_apicintpin[irq].redirindex = 0;
1217 for (x = 0; x < nintrs; x++) {
1218 if ((io_apic_ints[x].int_type == 0 ||
1219 io_apic_ints[x].int_type == 3) &&
1220 io_apic_ints[x].int_vector != 0xff &&
1221 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1222 io_apic_ints[x].dst_apic_int == oldintpin)
1223 io_apic_ints[x].int_vector = 0xff;
1231 allocate_apic_irq(int intr)
1237 if (io_apic_ints[intr].int_vector != 0xff)
1238 return; /* Interrupt handler already assigned */
1240 if (io_apic_ints[intr].int_type != 0 &&
1241 (io_apic_ints[intr].int_type != 3 ||
1242 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1243 io_apic_ints[intr].dst_apic_int == 0)))
1244 return; /* Not INT or ExtInt on != (0, 0) */
1247 while (irq < APIC_INTMAPSIZE &&
1248 int_to_apicintpin[irq].ioapic != -1)
1251 if (irq >= APIC_INTMAPSIZE)
1252 return; /* No free interrupt handlers */
1254 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1255 intpin = io_apic_ints[intr].dst_apic_int;
1257 assign_apic_irq(apic, intpin, irq);
1258 io_apic_setup_intpin(apic, intpin);
1263 swap_apic_id(int apic, int oldid, int newid)
1270 return; /* Nothing to do */
1272 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1273 apic, oldid, newid);
1275 /* Swap physical APIC IDs in interrupt entries */
1276 for (x = 0; x < nintrs; x++) {
1277 if (io_apic_ints[x].dst_apic_id == oldid)
1278 io_apic_ints[x].dst_apic_id = newid;
1279 else if (io_apic_ints[x].dst_apic_id == newid)
1280 io_apic_ints[x].dst_apic_id = oldid;
1283 /* Swap physical APIC IDs in IO_TO_ID mappings */
1284 for (oapic = 0; oapic < mp_napics; oapic++)
1285 if (IO_TO_ID(oapic) == newid)
1288 if (oapic < mp_napics) {
1289 kprintf("Changing APIC ID for IO APIC #%d from "
1290 "%d to %d in MP table\n",
1291 oapic, newid, oldid);
1292 IO_TO_ID(oapic) = oldid;
1294 IO_TO_ID(apic) = newid;
1299 fix_id_to_io_mapping(void)
1303 for (x = 0; x < NAPICID; x++)
1306 for (x = 0; x <= mp_naps; x++)
1307 if (CPU_TO_ID(x) < NAPICID)
1308 ID_TO_IO(CPU_TO_ID(x)) = x;
1310 for (x = 0; x < mp_napics; x++)
1311 if (IO_TO_ID(x) < NAPICID)
1312 ID_TO_IO(IO_TO_ID(x)) = x;
1317 first_free_apic_id(void)
1321 for (freeid = 0; freeid < NAPICID; freeid++) {
1322 for (x = 0; x <= mp_naps; x++)
1323 if (CPU_TO_ID(x) == freeid)
1327 for (x = 0; x < mp_napics; x++)
1328 if (IO_TO_ID(x) == freeid)
1339 io_apic_id_acceptable(int apic, int id)
1341 int cpu; /* Logical CPU number */
1342 int oapic; /* Logical IO APIC number for other IO APIC */
1345 return 0; /* Out of range */
1347 for (cpu = 0; cpu <= mp_naps; cpu++)
1348 if (CPU_TO_ID(cpu) == id)
1349 return 0; /* Conflict with CPU */
1351 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1352 if (IO_TO_ID(oapic) == id)
1353 return 0; /* Conflict with other APIC */
1355 return 1; /* ID is acceptable for IO APIC */
1360 io_apic_find_int_entry(int apic, int pin)
1364 /* search each of the possible INTerrupt sources */
1365 for (x = 0; x < nintrs; ++x) {
1366 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1367 (pin == io_apic_ints[x].dst_apic_int))
1368 return (&io_apic_ints[x]);
1376 * parse an Intel MP specification table
1384 int apic; /* IO APIC unit number */
1385 int freeid; /* Free physical APIC ID */
1386 int physid; /* Current physical IO APIC ID */
1388 int bus_0 = 0; /* Stop GCC warning */
1389 int bus_pci = 0; /* Stop GCC warning */
1393 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1394 * did it wrong. The MP spec says that when more than 1 PCI bus
1395 * exists the BIOS must begin with bus entries for the PCI bus and use
1396 * actual PCI bus numbering. This implies that when only 1 PCI bus
1397 * exists the BIOS can choose to ignore this ordering, and indeed many
1398 * MP motherboards do ignore it. This causes a problem when the PCI
1399 * sub-system makes requests of the MP sub-system based on PCI bus
1400 * numbers. So here we look for the situation and renumber the
1401 * busses and associated INTs in an effort to "make it right".
1404 /* find bus 0, PCI bus, count the number of PCI busses */
1405 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1406 if (bus_data[x].bus_id == 0) {
1409 if (bus_data[x].bus_type == PCI) {
1415 * bus_0 == slot of bus with ID of 0
1416 * bus_pci == slot of last PCI bus encountered
1419 /* check the 1 PCI bus case for sanity */
1420 /* if it is number 0 all is well */
1421 if (num_pci_bus == 1 &&
1422 bus_data[bus_pci].bus_id != 0) {
1424 /* mis-numbered, swap with whichever bus uses slot 0 */
1426 /* swap the bus entry types */
1427 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1428 bus_data[bus_0].bus_type = PCI;
1430 /* swap each relavant INTerrupt entry */
1431 id = bus_data[bus_pci].bus_id;
1432 for (x = 0; x < nintrs; ++x) {
1433 if (io_apic_ints[x].src_bus_id == id) {
1434 io_apic_ints[x].src_bus_id = 0;
1436 else if (io_apic_ints[x].src_bus_id == 0) {
1437 io_apic_ints[x].src_bus_id = id;
1442 /* Assign IO APIC IDs.
1444 * First try the existing ID. If a conflict is detected, try
1445 * the ID in the MP table. If a conflict is still detected, find
1448 * We cannot use the ID_TO_IO table before all conflicts has been
1449 * resolved and the table has been corrected.
1451 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1453 /* First try to use the value set by the BIOS */
1454 physid = io_apic_get_id(apic);
1455 if (io_apic_id_acceptable(apic, physid)) {
1456 if (IO_TO_ID(apic) != physid)
1457 swap_apic_id(apic, IO_TO_ID(apic), physid);
1461 /* Then check if the value in the MP table is acceptable */
1462 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1465 /* Last resort, find a free APIC ID and use it */
1466 freeid = first_free_apic_id();
1467 if (freeid >= NAPICID)
1468 panic("No free physical APIC IDs found");
1470 if (io_apic_id_acceptable(apic, freeid)) {
1471 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1474 panic("Free physical APIC ID not usable");
1476 fix_id_to_io_mapping();
1478 /* detect and fix broken Compaq MP table */
1479 if (apic_int_type(0, 0) == -1) {
1480 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1481 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1482 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1483 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1484 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1485 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1487 } else if (apic_int_type(0, 0) == 0) {
1488 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1489 for (x = 0; x < nintrs; ++x)
1490 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1491 (0 == io_apic_ints[x].dst_apic_int)) {
1492 io_apic_ints[x].int_type = 3;
1493 io_apic_ints[x].int_vector = 0xff;
1499 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1500 * controllers universally come in pairs. If IRQ 14 is specified
1501 * as an ISA interrupt, then IRQ 15 had better be too.
1503 * [ Shuttle XPC / AMD Athlon X2 ]
1504 * The MPTable is missing an entry for IRQ 15. Note that the
1505 * ACPI table has an entry for both 14 and 15.
1507 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1508 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1509 io14 = io_apic_find_int_entry(0, 14);
1510 io_apic_ints[nintrs] = *io14;
1511 io_apic_ints[nintrs].src_bus_irq = 15;
1512 io_apic_ints[nintrs].dst_apic_int = 15;
1520 /* Assign low level interrupt handlers */
1522 setup_apic_irq_mapping(void)
1528 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1529 int_to_apicintpin[x].ioapic = -1;
1530 int_to_apicintpin[x].int_pin = 0;
1531 int_to_apicintpin[x].apic_address = NULL;
1532 int_to_apicintpin[x].redirindex = 0;
1534 /* Default to masked */
1535 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1538 /* First assign ISA/EISA interrupts */
1539 for (x = 0; x < nintrs; x++) {
1540 int_vector = io_apic_ints[x].src_bus_irq;
1541 if (int_vector < APIC_INTMAPSIZE &&
1542 io_apic_ints[x].int_vector == 0xff &&
1543 int_to_apicintpin[int_vector].ioapic == -1 &&
1544 (apic_int_is_bus_type(x, ISA) ||
1545 apic_int_is_bus_type(x, EISA)) &&
1546 io_apic_ints[x].int_type == 0) {
1547 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1548 io_apic_ints[x].dst_apic_int,
1553 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1554 for (x = 0; x < nintrs; x++) {
1555 if (io_apic_ints[x].dst_apic_int == 0 &&
1556 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1557 io_apic_ints[x].int_vector == 0xff &&
1558 int_to_apicintpin[0].ioapic == -1 &&
1559 io_apic_ints[x].int_type == 3) {
1560 assign_apic_irq(0, 0, 0);
1564 /* PCI interrupt assignment is deferred */
1570 mp_set_cpuids(int cpu_id, int apic_id)
1572 CPU_TO_ID(cpu_id) = apic_id;
1573 ID_TO_CPU(apic_id) = cpu_id;
1577 processor_entry(const struct PROCENTRY *entry, int cpu)
1581 /* check for usability */
1582 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1585 /* check for BSP flag */
1586 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1587 mp_set_cpuids(0, entry->apic_id);
1588 return 0; /* its already been counted */
1591 /* add another AP to list, if less than max number of CPUs */
1592 else if (cpu < MAXCPU) {
1593 mp_set_cpuids(cpu, entry->apic_id);
1603 bus_entry(const struct BUSENTRY *entry, int bus)
1608 /* encode the name into an index */
1609 for (x = 0; x < 6; ++x) {
1610 if ((c = entry->bus_type[x]) == ' ')
1616 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1617 panic("unknown bus type: '%s'", name);
1619 bus_data[bus].bus_id = entry->bus_id;
1620 bus_data[bus].bus_type = x;
1626 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1628 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1631 IO_TO_ID(apic) = entry->apic_id;
1632 ID_TO_IO(entry->apic_id) = apic;
1640 lookup_bus_type(char *name)
1644 for (x = 0; x < MAX_BUSTYPE; ++x)
1645 if (strcmp(bus_type_table[x].name, name) == 0)
1646 return bus_type_table[x].type;
1648 return UNKNOWN_BUSTYPE;
1654 int_entry(const struct INTENTRY *entry, int intr)
1658 io_apic_ints[intr].int_type = entry->int_type;
1659 io_apic_ints[intr].int_flags = entry->int_flags;
1660 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1661 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1662 if (entry->dst_apic_id == 255) {
1663 /* This signal goes to all IO APICS. Select an IO APIC
1664 with sufficient number of interrupt pins */
1665 for (apic = 0; apic < mp_napics; apic++)
1666 if (((io_apic_read(apic, IOAPIC_VER) &
1667 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1668 entry->dst_apic_int)
1670 if (apic < mp_napics)
1671 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1673 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1675 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1676 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1682 apic_int_is_bus_type(int intr, int bus_type)
1686 for (bus = 0; bus < mp_nbusses; ++bus)
1687 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1688 && ((int) bus_data[bus].bus_type == bus_type))
1695 * Given a traditional ISA INT mask, return an APIC mask.
1698 isa_apic_mask(u_int isa_mask)
1703 #if defined(SKIP_IRQ15_REDIRECT)
1704 if (isa_mask == (1 << 15)) {
1705 kprintf("skipping ISA IRQ15 redirect\n");
1708 #endif /* SKIP_IRQ15_REDIRECT */
1710 isa_irq = ffs(isa_mask); /* find its bit position */
1711 if (isa_irq == 0) /* doesn't exist */
1713 --isa_irq; /* make it zero based */
1715 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1719 return (1 << apic_pin); /* convert pin# to a mask */
1723 * Determine which APIC pin an ISA/EISA INT is attached to.
1725 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1726 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1727 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1728 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1730 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1732 isa_apic_irq(int isa_irq)
1736 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1737 if (INTTYPE(intr) == 0) { /* standard INT */
1738 if (SRCBUSIRQ(intr) == isa_irq) {
1739 if (apic_int_is_bus_type(intr, ISA) ||
1740 apic_int_is_bus_type(intr, EISA)) {
1741 if (INTIRQ(intr) == 0xff)
1742 return -1; /* unassigned */
1743 return INTIRQ(intr); /* found */
1748 return -1; /* NOT found */
1753 * Determine which APIC pin a PCI INT is attached to.
1755 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1756 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1757 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1759 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1763 --pciInt; /* zero based */
1765 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1766 if ((INTTYPE(intr) == 0) /* standard INT */
1767 && (SRCBUSID(intr) == pciBus)
1768 && (SRCBUSDEVICE(intr) == pciDevice)
1769 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1770 if (apic_int_is_bus_type(intr, PCI)) {
1771 if (INTIRQ(intr) == 0xff)
1772 allocate_apic_irq(intr);
1773 if (INTIRQ(intr) == 0xff)
1774 return -1; /* unassigned */
1775 return INTIRQ(intr); /* exact match */
1780 return -1; /* NOT found */
1784 next_apic_irq(int irq)
1791 for (intr = 0; intr < nintrs; intr++) {
1792 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1794 bus = SRCBUSID(intr);
1795 bustype = apic_bus_type(bus);
1796 if (bustype != ISA &&
1802 if (intr >= nintrs) {
1805 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1806 if (INTTYPE(ointr) != 0)
1808 if (bus != SRCBUSID(ointr))
1810 if (bustype == PCI) {
1811 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1813 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1816 if (bustype == ISA || bustype == EISA) {
1817 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1820 if (INTPIN(intr) == INTPIN(ointr))
1824 if (ointr >= nintrs) {
1827 return INTIRQ(ointr);
1842 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1845 * Exactly what this means is unclear at this point. It is a solution
1846 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1847 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1848 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1852 undirect_isa_irq(int rirq)
1856 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1857 /** FIXME: tickle the MB redirector chip */
1861 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1868 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1871 undirect_pci_irq(int rirq)
1875 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1877 /** FIXME: tickle the MB redirector chip */
1881 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1891 * given a bus ID, return:
1892 * the bus type if found
1896 apic_bus_type(int id)
1900 for (x = 0; x < mp_nbusses; ++x)
1901 if (bus_data[x].bus_id == id)
1902 return bus_data[x].bus_type;
1908 * given a LOGICAL APIC# and pin#, return:
1909 * the associated src bus ID if found
1913 apic_src_bus_id(int apic, int pin)
1917 /* search each of the possible INTerrupt sources */
1918 for (x = 0; x < nintrs; ++x)
1919 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1920 (pin == io_apic_ints[x].dst_apic_int))
1921 return (io_apic_ints[x].src_bus_id);
1923 return -1; /* NOT found */
1927 * given a LOGICAL APIC# and pin#, return:
1928 * the associated src bus IRQ if found
1932 apic_src_bus_irq(int apic, int pin)
1936 for (x = 0; x < nintrs; x++)
1937 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1938 (pin == io_apic_ints[x].dst_apic_int))
1939 return (io_apic_ints[x].src_bus_irq);
1941 return -1; /* NOT found */
1946 * given a LOGICAL APIC# and pin#, return:
1947 * the associated INTerrupt type if found
1951 apic_int_type(int apic, int pin)
1955 /* search each of the possible INTerrupt sources */
1956 for (x = 0; x < nintrs; ++x) {
1957 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1958 (pin == io_apic_ints[x].dst_apic_int))
1959 return (io_apic_ints[x].int_type);
1961 return -1; /* NOT found */
1965 * Return the IRQ associated with an APIC pin
1968 apic_irq(int apic, int pin)
1973 for (x = 0; x < nintrs; ++x) {
1974 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1975 (pin == io_apic_ints[x].dst_apic_int)) {
1976 res = io_apic_ints[x].int_vector;
1979 if (apic != int_to_apicintpin[res].ioapic)
1980 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1981 if (pin != int_to_apicintpin[res].int_pin)
1982 panic("apic_irq inconsistent table (2)");
1991 * given a LOGICAL APIC# and pin#, return:
1992 * the associated trigger mode if found
1996 apic_trigger(int apic, int pin)
2000 /* search each of the possible INTerrupt sources */
2001 for (x = 0; x < nintrs; ++x)
2002 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2003 (pin == io_apic_ints[x].dst_apic_int))
2004 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2006 return -1; /* NOT found */
2011 * given a LOGICAL APIC# and pin#, return:
2012 * the associated 'active' level if found
2016 apic_polarity(int apic, int pin)
2020 /* search each of the possible INTerrupt sources */
2021 for (x = 0; x < nintrs; ++x)
2022 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2023 (pin == io_apic_ints[x].dst_apic_int))
2024 return (io_apic_ints[x].int_flags & 0x03);
2026 return -1; /* NOT found */
2032 * set data according to MP defaults
2033 * FIXME: probably not complete yet...
2036 mptable_default(int type)
2038 #if defined(APIC_IO)
2043 kprintf(" MP default config type: %d\n", type);
2046 kprintf(" bus: ISA, APIC: 82489DX\n");
2049 kprintf(" bus: EISA, APIC: 82489DX\n");
2052 kprintf(" bus: EISA, APIC: 82489DX\n");
2055 kprintf(" bus: MCA, APIC: 82489DX\n");
2058 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2061 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2064 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2067 kprintf(" future type\n");
2073 /* one and only IO APIC */
2074 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2077 * sanity check, refer to MP spec section 3.6.6, last paragraph
2078 * necessary as some hardware isn't properly setting up the IO APIC
2080 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2081 if (io_apic_id != 2) {
2083 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2084 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2085 io_apic_set_id(0, 2);
2088 IO_TO_ID(0) = io_apic_id;
2089 ID_TO_IO(io_apic_id) = 0;
2091 /* fill out bus entries */
2100 bus_data[0].bus_id = default_data[type - 1][1];
2101 bus_data[0].bus_type = default_data[type - 1][2];
2102 bus_data[1].bus_id = default_data[type - 1][3];
2103 bus_data[1].bus_type = default_data[type - 1][4];
2106 /* case 4: case 7: MCA NOT supported */
2107 default: /* illegal/reserved */
2108 panic("BAD default MP config: %d", type);
2112 /* general cases from MP v1.4, table 5-2 */
2113 for (pin = 0; pin < 16; ++pin) {
2114 io_apic_ints[pin].int_type = 0;
2115 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2116 io_apic_ints[pin].src_bus_id = 0;
2117 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2118 io_apic_ints[pin].dst_apic_id = io_apic_id;
2119 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2122 /* special cases from MP v1.4, table 5-2 */
2124 io_apic_ints[2].int_type = 0xff; /* N/C */
2125 io_apic_ints[13].int_type = 0xff; /* N/C */
2126 #if !defined(APIC_MIXED_MODE)
2128 panic("sorry, can't support type 2 default yet");
2129 #endif /* APIC_MIXED_MODE */
2132 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2135 io_apic_ints[0].int_type = 0xff; /* N/C */
2137 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2138 #endif /* APIC_IO */
2142 * Map a physical memory address representing I/O into KVA. The I/O
2143 * block is assumed not to cross a page boundary.
2146 permanent_io_mapping(vm_paddr_t pa)
2152 KKASSERT(pa < 0x100000000LL);
2154 pgeflag = 0; /* not used for SMP yet */
2157 * If the requested physical address has already been incidently
2158 * mapped, just use the existing mapping. Otherwise create a new
2161 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2162 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2163 ((vm_offset_t)pa & PG_FRAME)) {
2167 if (i == SMPpt_alloc_index) {
2168 if (i == NPTEPG - 2) {
2169 panic("permanent_io_mapping: We ran out of space"
2172 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2173 ((vm_offset_t)pa & PG_FRAME));
2174 ++SMPpt_alloc_index;
2176 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2177 ((vm_offset_t)pa & PAGE_MASK);
2178 return ((void *)vaddr);
2182 * start each AP in our list
2185 start_all_aps(u_int boot_addr)
2189 u_char mpbiosreason;
2190 u_long mpbioswarmvec;
2191 struct mdglobaldata *gd;
2192 struct privatespace *ps;
2196 POSTCODE(START_ALL_APS_POST);
2198 /* Initialize BSP's local APIC */
2199 apic_initialize(TRUE);
2201 /* install the AP 1st level boot code */
2202 install_ap_tramp(boot_addr);
2205 /* save the current value of the warm-start vector */
2206 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2207 outb(CMOS_REG, BIOS_RESET);
2208 mpbiosreason = inb(CMOS_DATA);
2210 /* set up temporary P==V mapping for AP boot */
2211 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2212 kptbase = (uintptr_t)(void *)KPTphys;
2213 for (x = 0; x < NKPT; x++) {
2214 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2215 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2220 for (x = 1; x <= mp_naps; ++x) {
2222 /* This is a bit verbose, it will go away soon. */
2224 /* first page of AP's private space */
2225 pg = x * i386_btop(sizeof(struct privatespace));
2227 /* allocate new private data page(s) */
2228 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2229 MDGLOBALDATA_BASEALLOC_SIZE);
2230 /* wire it into the private page table page */
2231 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2232 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2233 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2235 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2237 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2238 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2239 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2240 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2242 /* allocate and set up an idle stack data page */
2243 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2244 for (i = 0; i < UPAGES; i++) {
2245 SMPpt[pg + 4 + i] = (pt_entry_t)
2246 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2249 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2250 bzero(gd, sizeof(*gd));
2251 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2253 /* prime data page for it to use */
2254 mi_gdinit(&gd->mi, x);
2256 gd->gd_CMAP1 = &SMPpt[pg + 0];
2257 gd->gd_CMAP2 = &SMPpt[pg + 1];
2258 gd->gd_CMAP3 = &SMPpt[pg + 2];
2259 gd->gd_PMAP1 = &SMPpt[pg + 3];
2260 gd->gd_CADDR1 = ps->CPAGE1;
2261 gd->gd_CADDR2 = ps->CPAGE2;
2262 gd->gd_CADDR3 = ps->CPAGE3;
2263 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2264 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2265 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2267 /* setup a vector to our boot code */
2268 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2269 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2270 outb(CMOS_REG, BIOS_RESET);
2271 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2274 * Setup the AP boot stack
2276 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2279 /* attempt to start the Application Processor */
2280 CHECK_INIT(99); /* setup checkpoints */
2281 if (!start_ap(gd, boot_addr)) {
2282 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2283 CHECK_PRINT("trace"); /* show checkpoints */
2284 /* better panic as the AP may be running loose */
2285 kprintf("panic y/n? [y] ");
2286 if (cngetc() != 'n')
2289 CHECK_PRINT("trace"); /* show checkpoints */
2291 /* record its version info */
2292 cpu_apic_versions[x] = cpu_apic_versions[0];
2295 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2298 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2299 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2302 ncpus2_shift = shift;
2303 ncpus2 = 1 << shift;
2304 ncpus2_mask = ncpus2 - 1;
2306 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2307 if ((1 << shift) < ncpus)
2309 ncpus_fit = 1 << shift;
2310 ncpus_fit_mask = ncpus_fit - 1;
2312 /* build our map of 'other' CPUs */
2313 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2314 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2315 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2317 /* fill in our (BSP) APIC version */
2318 cpu_apic_versions[0] = lapic.version;
2320 /* restore the warmstart vector */
2321 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2322 outb(CMOS_REG, BIOS_RESET);
2323 outb(CMOS_DATA, mpbiosreason);
2326 * NOTE! The idlestack for the BSP was setup by locore. Finish
2327 * up, clean out the P==V mapping we did earlier.
2329 for (x = 0; x < NKPT; x++)
2333 /* number of APs actually started */
2339 * load the 1st level AP boot code into base memory.
2342 /* targets for relocation */
2343 extern void bigJump(void);
2344 extern void bootCodeSeg(void);
2345 extern void bootDataSeg(void);
2346 extern void MPentry(void);
2347 extern u_int MP_GDT;
2348 extern u_int mp_gdtbase;
2351 install_ap_tramp(u_int boot_addr)
2354 int size = *(int *) ((u_long) & bootMP_size);
2355 u_char *src = (u_char *) ((u_long) bootMP);
2356 u_char *dst = (u_char *) boot_addr + KERNBASE;
2357 u_int boot_base = (u_int) bootMP;
2362 POSTCODE(INSTALL_AP_TRAMP_POST);
2364 for (x = 0; x < size; ++x)
2368 * modify addresses in code we just moved to basemem. unfortunately we
2369 * need fairly detailed info about mpboot.s for this to work. changes
2370 * to mpboot.s might require changes here.
2373 /* boot code is located in KERNEL space */
2374 dst = (u_char *) boot_addr + KERNBASE;
2376 /* modify the lgdt arg */
2377 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2378 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2380 /* modify the ljmp target for MPentry() */
2381 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2382 *dst32 = ((u_int) MPentry - KERNBASE);
2384 /* modify the target for boot code segment */
2385 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2386 dst8 = (u_int8_t *) (dst16 + 1);
2387 *dst16 = (u_int) boot_addr & 0xffff;
2388 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2390 /* modify the target for boot data segment */
2391 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2392 dst8 = (u_int8_t *) (dst16 + 1);
2393 *dst16 = (u_int) boot_addr & 0xffff;
2394 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2399 * this function starts the AP (application processor) identified
2400 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2401 * to accomplish this. This is necessary because of the nuances
2402 * of the different hardware we might encounter. It ain't pretty,
2403 * but it seems to work.
2405 * NOTE: eventually an AP gets to ap_init(), which is called just
2406 * before the AP goes into the LWKT scheduler's idle loop.
2409 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2413 u_long icr_lo, icr_hi;
2415 POSTCODE(START_AP_POST);
2417 /* get the PHYSICAL APIC ID# */
2418 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2420 /* calculate the vector */
2421 vector = (boot_addr >> 12) & 0xff;
2423 /* Make sure the target cpu sees everything */
2427 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2428 * and running the target CPU. OR this INIT IPI might be latched (P5
2429 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2433 /* setup the address for the target AP */
2434 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2435 icr_hi |= (physical_cpu << 24);
2436 lapic.icr_hi = icr_hi;
2438 /* do an INIT IPI: assert RESET */
2439 icr_lo = lapic.icr_lo & 0xfff00000;
2440 lapic.icr_lo = icr_lo | 0x0000c500;
2442 /* wait for pending status end */
2443 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2446 /* do an INIT IPI: deassert RESET */
2447 lapic.icr_lo = icr_lo | 0x00008500;
2449 /* wait for pending status end */
2450 u_sleep(10000); /* wait ~10mS */
2451 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2455 * next we do a STARTUP IPI: the previous INIT IPI might still be
2456 * latched, (P5 bug) this 1st STARTUP would then terminate
2457 * immediately, and the previously started INIT IPI would continue. OR
2458 * the previous INIT IPI has already run. and this STARTUP IPI will
2459 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2463 /* do a STARTUP IPI */
2464 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2465 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2467 u_sleep(200); /* wait ~200uS */
2470 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2471 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2472 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2473 * recognized after hardware RESET or INIT IPI.
2476 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2477 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2479 u_sleep(200); /* wait ~200uS */
2481 /* wait for it to start, see ap_init() */
2482 set_apic_timer(5000000);/* == 5 seconds */
2483 while (read_apic_timer()) {
2484 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2485 return 1; /* return SUCCESS */
2487 return 0; /* return FAILURE */
2492 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2494 * If for some reason we were unable to start all cpus we cannot safely
2495 * use broadcast IPIs.
2501 if (smp_startup_mask == smp_active_mask) {
2502 all_but_self_ipi(XINVLTLB_OFFSET);
2504 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2505 APIC_DELMODE_FIXED);
2511 * When called the executing CPU will send an IPI to all other CPUs
2512 * requesting that they halt execution.
2514 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2516 * - Signals all CPUs in map to stop.
2517 * - Waits for each to stop.
2524 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2525 * from executing at same time.
2528 stop_cpus(u_int map)
2530 map &= smp_active_mask;
2532 /* send the Xcpustop IPI to all CPUs in map */
2533 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2535 while ((stopped_cpus & map) != map)
2543 * Called by a CPU to restart stopped CPUs.
2545 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2547 * - Signals all CPUs in map to restart.
2548 * - Waits for each to restart.
2556 restart_cpus(u_int map)
2558 /* signal other cpus to restart */
2559 started_cpus = map & smp_active_mask;
2561 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2568 * This is called once the mpboot code has gotten us properly relocated
2569 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2570 * and when it returns the scheduler will call the real cpu_idle() main
2571 * loop for the idlethread. Interrupts are disabled on entry and should
2572 * remain disabled at return.
2580 * Adjust smp_startup_mask to signal the BSP that we have started
2581 * up successfully. Note that we do not yet hold the BGL. The BSP
2582 * is waiting for our signal.
2584 * We can't set our bit in smp_active_mask yet because we are holding
2585 * interrupts physically disabled and remote cpus could deadlock
2586 * trying to send us an IPI.
2588 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2592 * Interlock for finalization. Wait until mp_finish is non-zero,
2593 * then get the MP lock.
2595 * Note: We are in a critical section.
2597 * Note: We have to synchronize td_mpcount to our desired MP state
2598 * before calling cpu_try_mplock().
2600 * Note: we are the idle thread, we can only spin.
2602 * Note: The load fence is memory volatile and prevents the compiler
2603 * from improperly caching mp_finish, and the cpu from improperly
2606 while (mp_finish == 0)
2608 ++curthread->td_mpcount;
2609 while (cpu_try_mplock() == 0)
2612 if (cpu_feature & CPUID_TSC) {
2614 * The BSP is constantly updating tsc0_offset, figure out the
2615 * relative difference to synchronize ktrdump.
2617 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2620 /* BSP may have changed PTD while we're waiting for the lock */
2623 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2627 /* Build our map of 'other' CPUs. */
2628 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2630 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2632 /* A quick check from sanity claus */
2633 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2634 if (mycpu->gd_cpuid != apic_id) {
2635 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2636 kprintf("SMP: apic_id = %d\n", apic_id);
2637 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2638 panic("cpuid mismatch! boom!!");
2641 /* Initialize AP's local APIC for irq's */
2642 apic_initialize(FALSE);
2644 /* Set memory range attributes for this CPU to match the BSP */
2645 mem_range_AP_init();
2648 * Once we go active we must process any IPIQ messages that may
2649 * have been queued, because no actual IPI will occur until we
2650 * set our bit in the smp_active_mask. If we don't the IPI
2651 * message interlock could be left set which would also prevent
2654 * The idle loop doesn't expect the BGL to be held and while
2655 * lwkt_switch() normally cleans things up this is a special case
2656 * because we returning almost directly into the idle loop.
2658 * The idle thread is never placed on the runq, make sure
2659 * nothing we've done put it there.
2661 KKASSERT(curthread->td_mpcount == 1);
2662 smp_active_mask |= 1 << mycpu->gd_cpuid;
2665 * Enable interrupts here. idle_restore will also do it, but
2666 * doing it here lets us clean up any strays that got posted to
2667 * the CPU during the AP boot while we are still in a critical
2670 __asm __volatile("sti; pause; pause"::);
2671 mdcpu->gd_fpending = 0;
2673 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2674 lwkt_process_ipiq();
2677 * Releasing the mp lock lets the BSP finish up the SMP init
2680 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2684 * Get SMP fully working before we start initializing devices.
2692 kprintf("Finish MP startup\n");
2693 if (cpu_feature & CPUID_TSC)
2694 tsc0_offset = rdtsc();
2697 while (smp_active_mask != smp_startup_mask) {
2699 if (cpu_feature & CPUID_TSC)
2700 tsc0_offset = rdtsc();
2702 while (try_mplock() == 0)
2705 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2708 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2711 cpu_send_ipiq(int dcpu)
2713 if ((1 << dcpu) & smp_active_mask)
2714 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2717 #if 0 /* single_apic_ipi_passive() not working yet */
2719 * Returns 0 on failure, 1 on success
2722 cpu_send_ipiq_passive(int dcpu)
2725 if ((1 << dcpu) & smp_active_mask) {
2726 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2727 APIC_DELMODE_FIXED);
2733 struct mptable_lapic_cbarg1 {
2736 u_int ht_apicid_mask;
2740 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2742 const struct PROCENTRY *ent;
2743 struct mptable_lapic_cbarg1 *arg = xarg;
2749 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2753 if (ent->apic_id < 32) {
2754 arg->ht_apicid_mask |= 1 << ent->apic_id;
2755 } else if (arg->ht_fixup) {
2756 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2762 struct mptable_lapic_cbarg2 {
2769 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2771 const struct PROCENTRY *ent;
2772 struct mptable_lapic_cbarg2 *arg = xarg;
2778 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2779 KKASSERT(!arg->found_bsp);
2783 if (processor_entry(ent, arg->cpu))
2786 if (arg->logical_cpus) {
2787 struct PROCENTRY proc;
2791 * Create fake mptable processor entries
2792 * and feed them to processor_entry() to
2793 * enumerate the logical CPUs.
2795 bzero(&proc, sizeof(proc));
2797 proc.cpu_flags = PROCENTRY_FLAG_EN;
2798 proc.apic_id = ent->apic_id;
2800 for (i = 1; i < arg->logical_cpus; i++) {
2802 processor_entry(&proc, arg->cpu);
2810 mptable_imcr(struct mptable_pos *mpt)
2812 /* record whether PIC or virtual-wire mode */
2813 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2814 mpt->mp_fps->mpfb2 & 0x80);
2817 struct mptable_lapic_enumerator {
2818 struct lapic_enumerator enumerator;
2819 vm_paddr_t mpfps_paddr;
2823 mptable_lapic_default(void)
2825 int ap_apicid, bsp_apicid;
2827 mp_naps = 1; /* exclude BSP */
2829 /* Map local apic before the id field is accessed */
2830 lapic_map(DEFAULT_APIC_BASE);
2832 bsp_apicid = APIC_ID(lapic.id);
2833 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2836 mp_set_cpuids(0, bsp_apicid);
2837 /* one and only AP */
2838 mp_set_cpuids(1, ap_apicid);
2844 * ID_TO_CPU(N), APIC ID to logical CPU table
2845 * CPU_TO_ID(N), logical CPU to APIC ID table
2848 mptable_lapic_enumerate(struct lapic_enumerator *e)
2850 struct mptable_pos mpt;
2851 struct mptable_lapic_cbarg1 arg1;
2852 struct mptable_lapic_cbarg2 arg2;
2854 int error, logical_cpus = 0;
2855 vm_offset_t lapic_addr;
2856 vm_paddr_t mpfps_paddr;
2858 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2859 KKASSERT(mpfps_paddr != 0);
2861 error = mptable_map(&mpt, mpfps_paddr);
2863 panic("mptable_lapic_enumerate mptable_map failed\n");
2865 KKASSERT(mpt.mp_fps != NULL);
2868 * Check for use of 'default' configuration
2870 if (mpt.mp_fps->mpfb1 != 0) {
2871 mptable_lapic_default();
2872 mptable_unmap(&mpt);
2877 KKASSERT(cth != NULL);
2879 /* Save local apic address */
2880 lapic_addr = (vm_offset_t)cth->apic_address;
2881 KKASSERT(lapic_addr != 0);
2884 * Find out how many CPUs do we have
2886 bzero(&arg1, sizeof(arg1));
2887 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2889 error = mptable_iterate_entries(cth,
2890 mptable_lapic_pass1_callback, &arg1);
2892 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2893 KKASSERT(arg1.cpu_count != 0);
2895 /* See if we need to fixup HT logical CPUs. */
2896 if (arg1.ht_fixup) {
2897 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2899 if (logical_cpus != 0)
2900 arg1.cpu_count *= logical_cpus;
2902 mp_naps = arg1.cpu_count;
2904 /* Qualify the numbers again, after possible HT fixup */
2905 if (mp_naps > MAXCPU) {
2906 kprintf("Warning: only using %d of %d available CPUs!\n",
2911 --mp_naps; /* subtract the BSP */
2914 * Link logical CPU id to local apic id
2916 bzero(&arg2, sizeof(arg2));
2918 arg2.logical_cpus = logical_cpus;
2920 error = mptable_iterate_entries(cth,
2921 mptable_lapic_pass2_callback, &arg2);
2923 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2924 KKASSERT(arg2.found_bsp);
2926 /* Map local apic */
2927 lapic_map(lapic_addr);
2929 mptable_unmap(&mpt);
2933 mptable_lapic_probe(struct lapic_enumerator *e)
2935 vm_paddr_t mpfps_paddr;
2937 mpfps_paddr = mptable_probe();
2938 if (mpfps_paddr == 0)
2941 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
2945 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
2947 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2948 .lapic_probe = mptable_lapic_probe,
2949 .lapic_enumerate = mptable_lapic_enumerate
2954 mptable_apic_register(void)
2956 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
2958 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);