bge: BGE_PCI_MISC_CTL resides in PCI configuration space
[dragonfly.git] / sys / dev / netif / bge / if_bge.c
1 /*
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *      This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34  */
35
36 /*
37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
38  * 
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Engineer, Wind River Systems
41  */
42
43 /*
44  * The Broadcom BCM5700 is based on technology originally developed by
45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49  * frames, highly configurable RX filtering, and 16 RX and TX queues
50  * (which, along with RX filter rules, can be used for QOS applications).
51  * Other features, such as TCP segmentation, may be available as part
52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53  * firmware images can be stored in hardware and need not be compiled
54  * into the driver.
55  *
56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
58  * 
59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61  * does not support external SSRAM.
62  *
63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
64  * brand name, which is functionally similar but lacks PCI-X support.
65  *
66  * Without external SSRAM, you can only have at most 4 TX rings,
67  * and the use of the mini RX ring is disabled. This seems to imply
68  * that these features are simply not available on the BCM5701. As a
69  * result, this driver does not implement any support for the mini RX
70  * ring.
71  */
72
73 #include "opt_polling.h"
74
75 #include <sys/param.h>
76 #include <sys/bus.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
79 #include <sys/ktr.h>
80 #include <sys/interrupt.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99 #include <net/vlan/if_vlan_ether.h>
100
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
103 #include <dev/netif/mii_layer/brgphyreg.h>
104
105 #include <bus/pci/pcidevs.h>
106 #include <bus/pci/pcireg.h>
107 #include <bus/pci/pcivar.h>
108
109 #include <dev/netif/bge/if_bgereg.h>
110
111 /* "device miibus" required.  See GENERIC if you get errors here. */
112 #include "miibus_if.h"
113
114 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
115 #define BGE_MIN_FRAME           60
116
117 static const struct bge_type bge_devs[] = {
118         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
119                 "3COM 3C996 Gigabit Ethernet" },
120
121         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
122                 "Alteon BCM5700 Gigabit Ethernet" },
123         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
124                 "Alteon BCM5701 Gigabit Ethernet" },
125
126         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
127                 "Altima AC1000 Gigabit Ethernet" },
128         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
129                 "Altima AC1002 Gigabit Ethernet" },
130         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
131                 "Altima AC9100 Gigabit Ethernet" },
132
133         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
134                 "Apple BCM5701 Gigabit Ethernet" },
135
136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
137                 "Broadcom BCM5700 Gigabit Ethernet" },
138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
139                 "Broadcom BCM5701 Gigabit Ethernet" },
140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
141                 "Broadcom BCM5702 Gigabit Ethernet" },
142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
143                 "Broadcom BCM5702X Gigabit Ethernet" },
144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
145                 "Broadcom BCM5702 Gigabit Ethernet" },
146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
147                 "Broadcom BCM5703 Gigabit Ethernet" },
148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
149                 "Broadcom BCM5703X Gigabit Ethernet" },
150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
151                 "Broadcom BCM5703 Gigabit Ethernet" },
152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
153                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
155                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
157                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
159                 "Broadcom BCM5705 Gigabit Ethernet" },
160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
161                 "Broadcom BCM5705F Gigabit Ethernet" },
162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
163                 "Broadcom BCM5705K Gigabit Ethernet" },
164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
165                 "Broadcom BCM5705M Gigabit Ethernet" },
166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
167                 "Broadcom BCM5705M Gigabit Ethernet" },
168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
169                 "Broadcom BCM5714C Gigabit Ethernet" },
170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
171                 "Broadcom BCM5714S Gigabit Ethernet" },
172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
173                 "Broadcom BCM5715 Gigabit Ethernet" },
174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
175                 "Broadcom BCM5715S Gigabit Ethernet" },
176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
177                 "Broadcom BCM5720 Gigabit Ethernet" },
178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
179                 "Broadcom BCM5721 Gigabit Ethernet" },
180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
181                 "Broadcom BCM5722 Gigabit Ethernet" },
182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
183                 "Broadcom BCM5723 Gigabit Ethernet" },
184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
185                 "Broadcom BCM5750 Gigabit Ethernet" },
186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
187                 "Broadcom BCM5750M Gigabit Ethernet" },
188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
189                 "Broadcom BCM5751 Gigabit Ethernet" },
190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
191                 "Broadcom BCM5751F Gigabit Ethernet" },
192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
193                 "Broadcom BCM5751M Gigabit Ethernet" },
194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
195                 "Broadcom BCM5752 Gigabit Ethernet" },
196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
197                 "Broadcom BCM5752M Gigabit Ethernet" },
198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
199                 "Broadcom BCM5753 Gigabit Ethernet" },
200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
201                 "Broadcom BCM5753F Gigabit Ethernet" },
202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
203                 "Broadcom BCM5753M Gigabit Ethernet" },
204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
205                 "Broadcom BCM5754 Gigabit Ethernet" },
206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
207                 "Broadcom BCM5754M Gigabit Ethernet" },
208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
209                 "Broadcom BCM5755 Gigabit Ethernet" },
210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
211                 "Broadcom BCM5755M Gigabit Ethernet" },
212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
213                 "Broadcom BCM5756 Gigabit Ethernet" },
214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
215                 "Broadcom BCM5761 Gigabit Ethernet" },
216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
217                 "Broadcom BCM5761E Gigabit Ethernet" },
218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
219                 "Broadcom BCM5761S Gigabit Ethernet" },
220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
221                 "Broadcom BCM5761SE Gigabit Ethernet" },
222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
223                 "Broadcom BCM5764 Gigabit Ethernet" },
224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
225                 "Broadcom BCM5780 Gigabit Ethernet" },
226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
227                 "Broadcom BCM5780S Gigabit Ethernet" },
228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
229                 "Broadcom BCM5781 Gigabit Ethernet" },
230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
231                 "Broadcom BCM5782 Gigabit Ethernet" },
232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
233                 "Broadcom BCM5784 Gigabit Ethernet" },
234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
235                 "Broadcom BCM5785F Gigabit Ethernet" },
236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
237                 "Broadcom BCM5785G Gigabit Ethernet" },
238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
239                 "Broadcom BCM5786 Gigabit Ethernet" },
240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
241                 "Broadcom BCM5787 Gigabit Ethernet" },
242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
243                 "Broadcom BCM5787F Gigabit Ethernet" },
244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
245                 "Broadcom BCM5787M Gigabit Ethernet" },
246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
247                 "Broadcom BCM5788 Gigabit Ethernet" },
248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
249                 "Broadcom BCM5789 Gigabit Ethernet" },
250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
251                 "Broadcom BCM5901 Fast Ethernet" },
252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
253                 "Broadcom BCM5901A2 Fast Ethernet" },
254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
255                 "Broadcom BCM5903M Fast Ethernet" },
256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
257                 "Broadcom BCM5906 Fast Ethernet"},
258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
259                 "Broadcom BCM5906M Fast Ethernet"},
260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
261                 "Broadcom BCM57760 Gigabit Ethernet"},
262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
263                 "Broadcom BCM57780 Gigabit Ethernet"},
264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
265                 "Broadcom BCM57788 Gigabit Ethernet"},
266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
267                 "Broadcom BCM57790 Gigabit Ethernet"},
268         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
269                 "SysKonnect Gigabit Ethernet" },
270
271         { 0, 0, NULL }
272 };
273
274 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
275 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
276 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
277 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
278 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
279 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
280 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
281
282 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
283
284 static int      bge_probe(device_t);
285 static int      bge_attach(device_t);
286 static int      bge_detach(device_t);
287 static void     bge_txeof(struct bge_softc *);
288 static void     bge_rxeof(struct bge_softc *);
289
290 static void     bge_tick(void *);
291 static void     bge_stats_update(struct bge_softc *);
292 static void     bge_stats_update_regs(struct bge_softc *);
293 static struct mbuf *
294                 bge_defrag_shortdma(struct mbuf *);
295 static int      bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
296
297 #ifdef DEVICE_POLLING
298 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
299 #endif
300 static void     bge_intr(void *);
301 static void     bge_enable_intr(struct bge_softc *);
302 static void     bge_disable_intr(struct bge_softc *);
303 static void     bge_start(struct ifnet *);
304 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
305 static void     bge_init(void *);
306 static void     bge_stop(struct bge_softc *);
307 static void     bge_watchdog(struct ifnet *);
308 static void     bge_shutdown(device_t);
309 static int      bge_suspend(device_t);
310 static int      bge_resume(device_t);
311 static int      bge_ifmedia_upd(struct ifnet *);
312 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
313
314 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
315 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
316
317 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
318 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
319
320 static void     bge_setmulti(struct bge_softc *);
321 static void     bge_setpromisc(struct bge_softc *);
322
323 static int      bge_alloc_jumbo_mem(struct bge_softc *);
324 static void     bge_free_jumbo_mem(struct bge_softc *);
325 static struct bge_jslot
326                 *bge_jalloc(struct bge_softc *);
327 static void     bge_jfree(void *);
328 static void     bge_jref(void *);
329 static int      bge_newbuf_std(struct bge_softc *, int, int);
330 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
331 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
332 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
333 static int      bge_init_rx_ring_std(struct bge_softc *);
334 static void     bge_free_rx_ring_std(struct bge_softc *);
335 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
336 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
337 static void     bge_free_tx_ring(struct bge_softc *);
338 static int      bge_init_tx_ring(struct bge_softc *);
339
340 static int      bge_chipinit(struct bge_softc *);
341 static int      bge_blockinit(struct bge_softc *);
342 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
343
344 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
345 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
346 #ifdef notdef
347 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
348 #endif
349 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
350 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
351 static void     bge_writembx(struct bge_softc *, int, int);
352
353 static int      bge_miibus_readreg(device_t, int, int);
354 static int      bge_miibus_writereg(device_t, int, int, int);
355 static void     bge_miibus_statchg(device_t);
356 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
357 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
358 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
359 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
360
361 static void     bge_reset(struct bge_softc *);
362
363 static int      bge_dma_alloc(struct bge_softc *);
364 static void     bge_dma_free(struct bge_softc *);
365 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
366                                     bus_dma_tag_t *, bus_dmamap_t *,
367                                     void **, bus_addr_t *);
368 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
369
370 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
371 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
372 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
373 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
374
375 static void     bge_coal_change(struct bge_softc *);
376 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
377 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
378 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
379 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
380 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
381
382 /*
383  * Set following tunable to 1 for some IBM blade servers with the DNLK
384  * switch module. Auto negotiation is broken for those configurations.
385  */
386 static int      bge_fake_autoneg = 0;
387 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
388
389 /* Interrupt moderation control variables. */
390 static int      bge_rx_coal_ticks = 100;        /* usec */
391 static int      bge_tx_coal_ticks = 1023;       /* usec */
392 static int      bge_rx_max_coal_bds = 80;
393 static int      bge_tx_max_coal_bds = 128;
394
395 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
396 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
397 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
398 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
399
400 #if !defined(KTR_IF_BGE)
401 #define KTR_IF_BGE      KTR_ALL
402 #endif
403 KTR_INFO_MASTER(if_bge);
404 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
405 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
406 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
407 #define logif(name)     KTR_LOG(if_bge_ ## name)
408
409 static device_method_t bge_methods[] = {
410         /* Device interface */
411         DEVMETHOD(device_probe,         bge_probe),
412         DEVMETHOD(device_attach,        bge_attach),
413         DEVMETHOD(device_detach,        bge_detach),
414         DEVMETHOD(device_shutdown,      bge_shutdown),
415         DEVMETHOD(device_suspend,       bge_suspend),
416         DEVMETHOD(device_resume,        bge_resume),
417
418         /* bus interface */
419         DEVMETHOD(bus_print_child,      bus_generic_print_child),
420         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
421
422         /* MII interface */
423         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
424         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
425         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
426
427         { 0, 0 }
428 };
429
430 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
431 static devclass_t bge_devclass;
432
433 DECLARE_DUMMY_MODULE(if_bge);
434 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
435 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
436
437 static uint32_t
438 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
439 {
440         device_t dev = sc->bge_dev;
441         uint32_t val;
442
443         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
444             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
445                 return 0;
446
447         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
448         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
449         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
450         return (val);
451 }
452
453 static void
454 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
455 {
456         device_t dev = sc->bge_dev;
457
458         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
459             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
460                 return;
461
462         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
463         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
464         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
465 }
466
467 #ifdef notdef
468 static uint32_t
469 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
470 {
471         device_t dev = sc->bge_dev;
472
473         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
474         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
475 }
476 #endif
477
478 static void
479 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
480 {
481         device_t dev = sc->bge_dev;
482
483         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
484         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
485 }
486
487 static void
488 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
489 {
490         CSR_WRITE_4(sc, off, val);
491 }
492
493 static void
494 bge_writembx(struct bge_softc *sc, int off, int val)
495 {
496         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
497                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
498
499         CSR_WRITE_4(sc, off, val);
500         if (sc->bge_mbox_reorder)
501                 CSR_READ_4(sc, off);
502 }
503
504 static uint8_t
505 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
506 {
507         uint32_t access, byte = 0;
508         int i;
509
510         /* Lock. */
511         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
512         for (i = 0; i < 8000; i++) {
513                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
514                         break;
515                 DELAY(20);
516         }
517         if (i == 8000)
518                 return (1);
519
520         /* Enable access. */
521         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
522         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
523
524         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
525         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
526         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
527                 DELAY(10);
528                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
529                         DELAY(10);
530                         break;
531                 }
532         }
533
534         if (i == BGE_TIMEOUT * 10) {
535                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
536                 return (1);
537         }
538
539         /* Get result. */
540         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
541
542         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
543
544         /* Disable access. */
545         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
546
547         /* Unlock. */
548         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
549         CSR_READ_4(sc, BGE_NVRAM_SWARB);
550
551         return (0);
552 }
553
554 /*
555  * Read a sequence of bytes from NVRAM.
556  */
557 static int
558 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
559 {
560         int err = 0, i;
561         uint8_t byte = 0;
562
563         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
564                 return (1);
565
566         for (i = 0; i < cnt; i++) {
567                 err = bge_nvram_getbyte(sc, off + i, &byte);
568                 if (err)
569                         break;
570                 *(dest + i) = byte;
571         }
572
573         return (err ? 1 : 0);
574 }
575
576 /*
577  * Read a byte of data stored in the EEPROM at address 'addr.' The
578  * BCM570x supports both the traditional bitbang interface and an
579  * auto access interface for reading the EEPROM. We use the auto
580  * access method.
581  */
582 static uint8_t
583 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
584 {
585         int i;
586         uint32_t byte = 0;
587
588         /*
589          * Enable use of auto EEPROM access so we can avoid
590          * having to use the bitbang method.
591          */
592         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
593
594         /* Reset the EEPROM, load the clock period. */
595         CSR_WRITE_4(sc, BGE_EE_ADDR,
596             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
597         DELAY(20);
598
599         /* Issue the read EEPROM command. */
600         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
601
602         /* Wait for completion */
603         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
604                 DELAY(10);
605                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
606                         break;
607         }
608
609         if (i == BGE_TIMEOUT) {
610                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
611                 return(1);
612         }
613
614         /* Get result. */
615         byte = CSR_READ_4(sc, BGE_EE_DATA);
616
617         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
618
619         return(0);
620 }
621
622 /*
623  * Read a sequence of bytes from the EEPROM.
624  */
625 static int
626 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
627 {
628         size_t i;
629         int err;
630         uint8_t byte;
631
632         for (byte = 0, err = 0, i = 0; i < len; i++) {
633                 err = bge_eeprom_getbyte(sc, off + i, &byte);
634                 if (err)
635                         break;
636                 *(dest + i) = byte;
637         }
638
639         return(err ? 1 : 0);
640 }
641
642 static int
643 bge_miibus_readreg(device_t dev, int phy, int reg)
644 {
645         struct bge_softc *sc = device_get_softc(dev);
646         uint32_t val;
647         int i;
648
649         KASSERT(phy == sc->bge_phyno,
650             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
651
652         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
653         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
654                 CSR_WRITE_4(sc, BGE_MI_MODE,
655                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
656                 DELAY(80);
657         }
658
659         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
660             BGE_MIPHY(phy) | BGE_MIREG(reg));
661
662         /* Poll for the PHY register access to complete. */
663         for (i = 0; i < BGE_TIMEOUT; i++) {
664                 DELAY(10);
665                 val = CSR_READ_4(sc, BGE_MI_COMM);
666                 if ((val & BGE_MICOMM_BUSY) == 0) {
667                         DELAY(5);
668                         val = CSR_READ_4(sc, BGE_MI_COMM);
669                         break;
670                 }
671         }
672         if (i == BGE_TIMEOUT) {
673                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
674                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
675                 val = 0;
676         }
677
678         /* Restore the autopoll bit if necessary. */
679         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
680                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
681                 DELAY(80);
682         }
683
684         if (val & BGE_MICOMM_READFAIL)
685                 return 0;
686
687         return (val & 0xFFFF);
688 }
689
690 static int
691 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
692 {
693         struct bge_softc *sc = device_get_softc(dev);
694         int i;
695
696         KASSERT(phy == sc->bge_phyno,
697             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
698
699         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
700             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
701                return 0;
702
703         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
704         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
705                 CSR_WRITE_4(sc, BGE_MI_MODE,
706                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
707                 DELAY(80);
708         }
709
710         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
711             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
712
713         for (i = 0; i < BGE_TIMEOUT; i++) {
714                 DELAY(10);
715                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
716                         DELAY(5);
717                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
718                         break;
719                 }
720         }
721         if (i == BGE_TIMEOUT) {
722                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
723                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
724         }
725
726         /* Restore the autopoll bit if necessary. */
727         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
728                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
729                 DELAY(80);
730         }
731
732         return 0;
733 }
734
735 static void
736 bge_miibus_statchg(device_t dev)
737 {
738         struct bge_softc *sc;
739         struct mii_data *mii;
740
741         sc = device_get_softc(dev);
742         mii = device_get_softc(sc->bge_miibus);
743
744         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
745             (IFM_ACTIVE | IFM_AVALID)) {
746                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
747                 case IFM_10_T:
748                 case IFM_100_TX:
749                         sc->bge_link = 1;
750                         break;
751                 case IFM_1000_T:
752                 case IFM_1000_SX:
753                 case IFM_2500_SX:
754                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
755                                 sc->bge_link = 1;
756                         else
757                                 sc->bge_link = 0;
758                         break;
759                 default:
760                         sc->bge_link = 0;
761                         break;
762                 }
763         } else {
764                 sc->bge_link = 0;
765         }
766         if (sc->bge_link == 0)
767                 return;
768
769         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
770         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
771             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
772                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
773         } else {
774                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
775         }
776
777         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
778                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
779         } else {
780                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
781         }
782 }
783
784 /*
785  * Memory management for jumbo frames.
786  */
787 static int
788 bge_alloc_jumbo_mem(struct bge_softc *sc)
789 {
790         struct ifnet *ifp = &sc->arpcom.ac_if;
791         struct bge_jslot *entry;
792         uint8_t *ptr;
793         bus_addr_t paddr;
794         int i, error;
795
796         /*
797          * Create tag for jumbo mbufs.
798          * This is really a bit of a kludge. We allocate a special
799          * jumbo buffer pool which (thanks to the way our DMA
800          * memory allocation works) will consist of contiguous
801          * pages. This means that even though a jumbo buffer might
802          * be larger than a page size, we don't really need to
803          * map it into more than one DMA segment. However, the
804          * default mbuf tag will result in multi-segment mappings,
805          * so we have to create a special jumbo mbuf tag that
806          * lets us get away with mapping the jumbo buffers as
807          * a single segment. I think eventually the driver should
808          * be changed so that it uses ordinary mbufs and cluster
809          * buffers, i.e. jumbo frames can span multiple DMA
810          * descriptors. But that's a project for another day.
811          */
812
813         /*
814          * Create DMA stuffs for jumbo RX ring.
815          */
816         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
817                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
818                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
819                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
820                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
821         if (error) {
822                 if_printf(ifp, "could not create jumbo RX ring\n");
823                 return error;
824         }
825
826         /*
827          * Create DMA stuffs for jumbo buffer block.
828          */
829         error = bge_dma_block_alloc(sc, BGE_JMEM,
830                                     &sc->bge_cdata.bge_jumbo_tag,
831                                     &sc->bge_cdata.bge_jumbo_map,
832                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
833                                     &paddr);
834         if (error) {
835                 if_printf(ifp, "could not create jumbo buffer\n");
836                 return error;
837         }
838
839         SLIST_INIT(&sc->bge_jfree_listhead);
840
841         /*
842          * Now divide it up into 9K pieces and save the addresses
843          * in an array. Note that we play an evil trick here by using
844          * the first few bytes in the buffer to hold the the address
845          * of the softc structure for this interface. This is because
846          * bge_jfree() needs it, but it is called by the mbuf management
847          * code which will not pass it to us explicitly.
848          */
849         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
850                 entry = &sc->bge_cdata.bge_jslots[i];
851                 entry->bge_sc = sc;
852                 entry->bge_buf = ptr;
853                 entry->bge_paddr = paddr;
854                 entry->bge_inuse = 0;
855                 entry->bge_slot = i;
856                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
857
858                 ptr += BGE_JLEN;
859                 paddr += BGE_JLEN;
860         }
861         return 0;
862 }
863
864 static void
865 bge_free_jumbo_mem(struct bge_softc *sc)
866 {
867         /* Destroy jumbo RX ring. */
868         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
869                            sc->bge_cdata.bge_rx_jumbo_ring_map,
870                            sc->bge_ldata.bge_rx_jumbo_ring);
871
872         /* Destroy jumbo buffer block. */
873         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
874                            sc->bge_cdata.bge_jumbo_map,
875                            sc->bge_ldata.bge_jumbo_buf);
876 }
877
878 /*
879  * Allocate a jumbo buffer.
880  */
881 static struct bge_jslot *
882 bge_jalloc(struct bge_softc *sc)
883 {
884         struct bge_jslot *entry;
885
886         lwkt_serialize_enter(&sc->bge_jslot_serializer);
887         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
888         if (entry) {
889                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
890                 entry->bge_inuse = 1;
891         } else {
892                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
893         }
894         lwkt_serialize_exit(&sc->bge_jslot_serializer);
895         return(entry);
896 }
897
898 /*
899  * Adjust usage count on a jumbo buffer.
900  */
901 static void
902 bge_jref(void *arg)
903 {
904         struct bge_jslot *entry = (struct bge_jslot *)arg;
905         struct bge_softc *sc = entry->bge_sc;
906
907         if (sc == NULL)
908                 panic("bge_jref: can't find softc pointer!");
909
910         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
911                 panic("bge_jref: asked to reference buffer "
912                     "that we don't manage!");
913         } else if (entry->bge_inuse == 0) {
914                 panic("bge_jref: buffer already free!");
915         } else {
916                 atomic_add_int(&entry->bge_inuse, 1);
917         }
918 }
919
920 /*
921  * Release a jumbo buffer.
922  */
923 static void
924 bge_jfree(void *arg)
925 {
926         struct bge_jslot *entry = (struct bge_jslot *)arg;
927         struct bge_softc *sc = entry->bge_sc;
928
929         if (sc == NULL)
930                 panic("bge_jfree: can't find softc pointer!");
931
932         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
933                 panic("bge_jfree: asked to free buffer that we don't manage!");
934         } else if (entry->bge_inuse == 0) {
935                 panic("bge_jfree: buffer already free!");
936         } else {
937                 /*
938                  * Possible MP race to 0, use the serializer.  The atomic insn
939                  * is still needed for races against bge_jref().
940                  */
941                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
942                 atomic_subtract_int(&entry->bge_inuse, 1);
943                 if (entry->bge_inuse == 0) {
944                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
945                                           entry, jslot_link);
946                 }
947                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
948         }
949 }
950
951
952 /*
953  * Intialize a standard receive ring descriptor.
954  */
955 static int
956 bge_newbuf_std(struct bge_softc *sc, int i, int init)
957 {
958         struct mbuf *m_new = NULL;
959         bus_dma_segment_t seg;
960         bus_dmamap_t map;
961         int error, nsegs;
962
963         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
964         if (m_new == NULL)
965                 return ENOBUFS;
966         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
967
968         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
969                 m_adj(m_new, ETHER_ALIGN);
970
971         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
972                         sc->bge_cdata.bge_rx_tmpmap, m_new,
973                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
974         if (error) {
975                 m_freem(m_new);
976                 return error;
977         }
978
979         if (!init) {
980                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
981                                 sc->bge_cdata.bge_rx_std_dmamap[i],
982                                 BUS_DMASYNC_POSTREAD);
983                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
984                         sc->bge_cdata.bge_rx_std_dmamap[i]);
985         }
986
987         map = sc->bge_cdata.bge_rx_tmpmap;
988         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
989         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
990
991         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
992         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
993
994         bge_setup_rxdesc_std(sc, i);
995         return 0;
996 }
997
998 static void
999 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1000 {
1001         struct bge_rxchain *rc;
1002         struct bge_rx_bd *r;
1003
1004         rc = &sc->bge_cdata.bge_rx_std_chain[i];
1005         r = &sc->bge_ldata.bge_rx_std_ring[i];
1006
1007         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1008         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1009         r->bge_len = rc->bge_mbuf->m_len;
1010         r->bge_idx = i;
1011         r->bge_flags = BGE_RXBDFLAG_END;
1012 }
1013
1014 /*
1015  * Initialize a jumbo receive ring descriptor. This allocates
1016  * a jumbo buffer from the pool managed internally by the driver.
1017  */
1018 static int
1019 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1020 {
1021         struct mbuf *m_new = NULL;
1022         struct bge_jslot *buf;
1023         bus_addr_t paddr;
1024
1025         /* Allocate the mbuf. */
1026         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1027         if (m_new == NULL)
1028                 return ENOBUFS;
1029
1030         /* Allocate the jumbo buffer */
1031         buf = bge_jalloc(sc);
1032         if (buf == NULL) {
1033                 m_freem(m_new);
1034                 return ENOBUFS;
1035         }
1036
1037         /* Attach the buffer to the mbuf. */
1038         m_new->m_ext.ext_arg = buf;
1039         m_new->m_ext.ext_buf = buf->bge_buf;
1040         m_new->m_ext.ext_free = bge_jfree;
1041         m_new->m_ext.ext_ref = bge_jref;
1042         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1043
1044         m_new->m_flags |= M_EXT;
1045
1046         m_new->m_data = m_new->m_ext.ext_buf;
1047         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1048
1049         paddr = buf->bge_paddr;
1050         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1051                 m_adj(m_new, ETHER_ALIGN);
1052                 paddr += ETHER_ALIGN;
1053         }
1054
1055         /* Save necessary information */
1056         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1057         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1058
1059         /* Set up the descriptor. */
1060         bge_setup_rxdesc_jumbo(sc, i);
1061         return 0;
1062 }
1063
1064 static void
1065 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1066 {
1067         struct bge_rx_bd *r;
1068         struct bge_rxchain *rc;
1069
1070         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1071         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1072
1073         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1074         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1075         r->bge_len = rc->bge_mbuf->m_len;
1076         r->bge_idx = i;
1077         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1078 }
1079
1080 static int
1081 bge_init_rx_ring_std(struct bge_softc *sc)
1082 {
1083         int i, error;
1084
1085         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1086                 error = bge_newbuf_std(sc, i, 1);
1087                 if (error)
1088                         return error;
1089         };
1090
1091         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1092         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1093
1094         return(0);
1095 }
1096
1097 static void
1098 bge_free_rx_ring_std(struct bge_softc *sc)
1099 {
1100         int i;
1101
1102         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1103                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1104
1105                 if (rc->bge_mbuf != NULL) {
1106                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1107                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
1108                         m_freem(rc->bge_mbuf);
1109                         rc->bge_mbuf = NULL;
1110                 }
1111                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1112                     sizeof(struct bge_rx_bd));
1113         }
1114 }
1115
1116 static int
1117 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1118 {
1119         struct bge_rcb *rcb;
1120         int i, error;
1121
1122         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1123                 error = bge_newbuf_jumbo(sc, i, 1);
1124                 if (error)
1125                         return error;
1126         };
1127
1128         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1129
1130         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1131         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1132         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1133
1134         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1135
1136         return(0);
1137 }
1138
1139 static void
1140 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1141 {
1142         int i;
1143
1144         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1145                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1146
1147                 if (rc->bge_mbuf != NULL) {
1148                         m_freem(rc->bge_mbuf);
1149                         rc->bge_mbuf = NULL;
1150                 }
1151                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1152                     sizeof(struct bge_rx_bd));
1153         }
1154 }
1155
1156 static void
1157 bge_free_tx_ring(struct bge_softc *sc)
1158 {
1159         int i;
1160
1161         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1162                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1163                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1164                                           sc->bge_cdata.bge_tx_dmamap[i]);
1165                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1166                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1167                 }
1168                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1169                     sizeof(struct bge_tx_bd));
1170         }
1171 }
1172
1173 static int
1174 bge_init_tx_ring(struct bge_softc *sc)
1175 {
1176         sc->bge_txcnt = 0;
1177         sc->bge_tx_saved_considx = 0;
1178         sc->bge_tx_prodidx = 0;
1179
1180         /* Initialize transmit producer index for host-memory send ring. */
1181         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1182
1183         /* 5700 b2 errata */
1184         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1185                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1186
1187         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1188         /* 5700 b2 errata */
1189         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1190                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1191
1192         return(0);
1193 }
1194
1195 static void
1196 bge_setmulti(struct bge_softc *sc)
1197 {
1198         struct ifnet *ifp;
1199         struct ifmultiaddr *ifma;
1200         uint32_t hashes[4] = { 0, 0, 0, 0 };
1201         int h, i;
1202
1203         ifp = &sc->arpcom.ac_if;
1204
1205         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1206                 for (i = 0; i < 4; i++)
1207                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1208                 return;
1209         }
1210
1211         /* First, zot all the existing filters. */
1212         for (i = 0; i < 4; i++)
1213                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1214
1215         /* Now program new ones. */
1216         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1217                 if (ifma->ifma_addr->sa_family != AF_LINK)
1218                         continue;
1219                 h = ether_crc32_le(
1220                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1221                     ETHER_ADDR_LEN) & 0x7f;
1222                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1223         }
1224
1225         for (i = 0; i < 4; i++)
1226                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1227 }
1228
1229 /*
1230  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1231  * self-test results.
1232  */
1233 static int
1234 bge_chipinit(struct bge_softc *sc)
1235 {
1236         int i;
1237         uint32_t dma_rw_ctl;
1238         uint16_t val;
1239
1240         /* Set endian type before we access any non-PCI registers. */
1241         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1242
1243         /* Clear the MAC control register */
1244         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1245
1246         /*
1247          * Clear the MAC statistics block in the NIC's
1248          * internal memory.
1249          */
1250         for (i = BGE_STATS_BLOCK;
1251             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1252                 BGE_MEMWIN_WRITE(sc, i, 0);
1253
1254         for (i = BGE_STATUS_BLOCK;
1255             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1256                 BGE_MEMWIN_WRITE(sc, i, 0);
1257
1258         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1259                 /*
1260                  * Fix data corruption caused by non-qword write with WB.
1261                  * Fix master abort in PCI mode.
1262                  * Fix PCI latency timer.
1263                  */
1264                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1265                 val |= (1 << 10) | (1 << 12) | (1 << 13);
1266                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1267         }
1268
1269         /* Set up the PCI DMA control register. */
1270         if (sc->bge_flags & BGE_FLAG_PCIE) {
1271                 /* PCI Express */
1272                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1273                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1274                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1275         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1276                 /* PCI-X bus */
1277                 if (BGE_IS_5714_FAMILY(sc)) {
1278                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1279                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1280                         /* XXX magic values, Broadcom-supplied Linux driver */
1281                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1282                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | 
1283                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1284                         } else {
1285                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1286                         }
1287                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1288                         /*
1289                          * In the BCM5703, the DMA read watermark should
1290                          * be set to less than or equal to the maximum
1291                          * memory read byte count of the PCI-X command
1292                          * register.
1293                          */
1294                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1295                             (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1296                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1297                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1298                         /*
1299                          * The 5704 uses a different encoding of read/write
1300                          * watermarks.
1301                          */
1302                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1303                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1304                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1305                 } else {
1306                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1307                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1308                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1309                             (0x0F);
1310                 }
1311
1312                 /*
1313                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1314                  * for hardware bugs.
1315                  */
1316                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1317                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1318                         uint32_t tmp;
1319
1320                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1321                         if (tmp == 0x6 || tmp == 0x7)
1322                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1323                 }
1324         } else {
1325                 /* Conventional PCI bus */
1326                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1327                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1328                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1329                     (0x0F);
1330         }
1331
1332         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1333             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1334             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1335                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1336         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1337
1338         /*
1339          * Set up general mode register.
1340          */
1341         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1342             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1343             BGE_MODECTL_TX_NO_PHDR_CSUM);
1344
1345         /*
1346          * BCM5701 B5 have a bug causing data corruption when using
1347          * 64-bit DMA reads, which can be terminated early and then
1348          * completed later as 32-bit accesses, in combination with
1349          * certain bridges.
1350          */
1351         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1352             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1353                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32);
1354
1355         /*
1356          * Disable memory write invalidate.  Apparently it is not supported
1357          * properly by these devices.
1358          */
1359         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1360
1361         /* Set the timer prescaler (always 66Mhz) */
1362         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1363
1364         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1365                 DELAY(40);      /* XXX */
1366
1367                 /* Put PHY into ready state */
1368                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1369                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1370                 DELAY(40);
1371         }
1372
1373         return(0);
1374 }
1375
1376 static int
1377 bge_blockinit(struct bge_softc *sc)
1378 {
1379         struct bge_rcb *rcb;
1380         bus_size_t vrcb;
1381         bge_hostaddr taddr;
1382         uint32_t val;
1383         int i, limit;
1384
1385         /*
1386          * Initialize the memory window pointer register so that
1387          * we can access the first 32K of internal NIC RAM. This will
1388          * allow us to set up the TX send ring RCBs and the RX return
1389          * ring RCBs, plus other things which live in NIC memory.
1390          */
1391         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1392
1393         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1394
1395         if (!BGE_IS_5705_PLUS(sc)) {
1396                 /* Configure mbuf memory pool */
1397                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1398                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1399                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1400                 else
1401                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1402
1403                 /* Configure DMA resource pool */
1404                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1405                     BGE_DMA_DESCRIPTORS);
1406                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1407         }
1408
1409         /* Configure mbuf pool watermarks */
1410         if (!BGE_IS_5705_PLUS(sc)) {
1411                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1412                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1413                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1414         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1415                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1416                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1417                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1418         } else {
1419                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1420                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1421                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1422         }
1423
1424         /* Configure DMA resource watermarks */
1425         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1426         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1427
1428         /* Enable buffer manager */
1429         CSR_WRITE_4(sc, BGE_BMAN_MODE,
1430             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1431
1432         /* Poll for buffer manager start indication */
1433         for (i = 0; i < BGE_TIMEOUT; i++) {
1434                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1435                         break;
1436                 DELAY(10);
1437         }
1438
1439         if (i == BGE_TIMEOUT) {
1440                 if_printf(&sc->arpcom.ac_if,
1441                           "buffer manager failed to start\n");
1442                 return(ENXIO);
1443         }
1444
1445         /* Enable flow-through queues */
1446         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1447         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1448
1449         /* Wait until queue initialization is complete */
1450         for (i = 0; i < BGE_TIMEOUT; i++) {
1451                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1452                         break;
1453                 DELAY(10);
1454         }
1455
1456         if (i == BGE_TIMEOUT) {
1457                 if_printf(&sc->arpcom.ac_if,
1458                           "flow-through queue init failed\n");
1459                 return(ENXIO);
1460         }
1461
1462         /*
1463          * Summary of rings supported by the controller:
1464          *
1465          * Standard Receive Producer Ring
1466          * - This ring is used to feed receive buffers for "standard"
1467          *   sized frames (typically 1536 bytes) to the controller.
1468          *
1469          * Jumbo Receive Producer Ring
1470          * - This ring is used to feed receive buffers for jumbo sized
1471          *   frames (i.e. anything bigger than the "standard" frames)
1472          *   to the controller.
1473          *
1474          * Mini Receive Producer Ring
1475          * - This ring is used to feed receive buffers for "mini"
1476          *   sized frames to the controller.
1477          * - This feature required external memory for the controller
1478          *   but was never used in a production system.  Should always
1479          *   be disabled.
1480          *
1481          * Receive Return Ring
1482          * - After the controller has placed an incoming frame into a
1483          *   receive buffer that buffer is moved into a receive return
1484          *   ring.  The driver is then responsible to passing the
1485          *   buffer up to the stack.  Many versions of the controller
1486          *   support multiple RR rings.
1487          *
1488          * Send Ring
1489          * - This ring is used for outgoing frames.  Many versions of
1490          *   the controller support multiple send rings.
1491          */
1492
1493         /* Initialize the standard receive producer ring control block. */
1494         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1495         rcb->bge_hostaddr.bge_addr_lo =
1496             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1497         rcb->bge_hostaddr.bge_addr_hi =
1498             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1499         if (BGE_IS_5705_PLUS(sc)) {
1500                 /*
1501                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1502                  * Bits 15-2 : Reserved (should be 0)
1503                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1504                  * Bit 0     : Reserved
1505                  */
1506                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1507         } else {
1508                 /*
1509                  * Ring size is always XXX entries
1510                  * Bits 31-16: Maximum RX frame size
1511                  * Bits 15-2 : Reserved (should be 0)
1512                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1513                  * Bit 0     : Reserved
1514                  */
1515                 rcb->bge_maxlen_flags =
1516                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1517         }
1518         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1519         /* Write the standard receive producer ring control block. */
1520         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1521         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1522         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1523         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1524         /* Reset the standard receive producer ring producer index. */
1525         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1526
1527         /*
1528          * Initialize the jumbo RX producer ring control
1529          * block.  We set the 'ring disabled' bit in the
1530          * flags field until we're actually ready to start
1531          * using this ring (i.e. once we set the MTU
1532          * high enough to require it).
1533          */
1534         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1535                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1536                 /* Get the jumbo receive producer ring RCB parameters. */
1537                 rcb->bge_hostaddr.bge_addr_lo =
1538                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1539                 rcb->bge_hostaddr.bge_addr_hi =
1540                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1541                 rcb->bge_maxlen_flags =
1542                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1543                     BGE_RCB_FLAG_RING_DISABLED);
1544                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1545                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1546                     rcb->bge_hostaddr.bge_addr_hi);
1547                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1548                     rcb->bge_hostaddr.bge_addr_lo);
1549                 /* Program the jumbo receive producer ring RCB parameters. */
1550                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1551                     rcb->bge_maxlen_flags);
1552                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1553                 /* Reset the jumbo receive producer ring producer index. */
1554                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1555         }
1556
1557         /* Disable the mini receive producer ring RCB. */
1558         if (BGE_IS_5700_FAMILY(sc)) {
1559                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1560                 rcb->bge_maxlen_flags =
1561                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1562                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1563                     rcb->bge_maxlen_flags);
1564                 /* Reset the mini receive producer ring producer index. */
1565                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1566         }
1567
1568         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1569         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1570             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1571              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1572              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1573                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1574                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1575         }
1576
1577         /*
1578          * The BD ring replenish thresholds control how often the
1579          * hardware fetches new BD's from the producer rings in host
1580          * memory.  Setting the value too low on a busy system can
1581          * starve the hardware and recue the throughpout.
1582          *
1583          * Set the BD ring replentish thresholds. The recommended
1584          * values are 1/8th the number of descriptors allocated to
1585          * each ring.
1586          */
1587         if (BGE_IS_5705_PLUS(sc))
1588                 val = 8;
1589         else
1590                 val = BGE_STD_RX_RING_CNT / 8;
1591         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1592         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1593                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1594                     BGE_JUMBO_RX_RING_CNT/8);
1595         }
1596
1597         /*
1598          * Disable all send rings by setting the 'ring disabled' bit
1599          * in the flags field of all the TX send ring control blocks,
1600          * located in NIC memory.
1601          */
1602         if (!BGE_IS_5705_PLUS(sc)) {
1603                 /* 5700 to 5704 had 16 send rings. */
1604                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1605         } else {
1606                 limit = 1;
1607         }
1608         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1609         for (i = 0; i < limit; i++) {
1610                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1611                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1612                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1613                 vrcb += sizeof(struct bge_rcb);
1614         }
1615
1616         /* Configure send ring RCB 0 (we use only the first ring) */
1617         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1618         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1619         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1620         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1621         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1622             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1623         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1624             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1625
1626         /*
1627          * Disable all receive return rings by setting the
1628          * 'ring diabled' bit in the flags field of all the receive
1629          * return ring control blocks, located in NIC memory.
1630          */
1631         if (!BGE_IS_5705_PLUS(sc))
1632                 limit = BGE_RX_RINGS_MAX;
1633         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1634                 limit = 4;
1635         else
1636                 limit = 1;
1637         /* Disable all receive return rings. */
1638         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1639         for (i = 0; i < limit; i++) {
1640                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1641                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1642                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1643                     BGE_RCB_FLAG_RING_DISABLED);
1644                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1645                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1646                     (i * (sizeof(uint64_t))), 0);
1647                 vrcb += sizeof(struct bge_rcb);
1648         }
1649
1650         /*
1651          * Set up receive return ring 0.  Note that the NIC address
1652          * for RX return rings is 0x0.  The return rings live entirely
1653          * within the host, so the nicaddr field in the RCB isn't used.
1654          */
1655         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1656         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1657         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1658         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1659         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1660         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1661             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1662
1663         /* Set random backoff seed for TX */
1664         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1665             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1666             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1667             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1668             BGE_TX_BACKOFF_SEED_MASK);
1669
1670         /* Set inter-packet gap */
1671         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1672
1673         /*
1674          * Specify which ring to use for packets that don't match
1675          * any RX rules.
1676          */
1677         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1678
1679         /*
1680          * Configure number of RX lists. One interrupt distribution
1681          * list, sixteen active lists, one bad frames class.
1682          */
1683         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1684
1685         /* Inialize RX list placement stats mask. */
1686         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1687         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1688
1689         /* Disable host coalescing until we get it set up */
1690         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1691
1692         /* Poll to make sure it's shut down. */
1693         for (i = 0; i < BGE_TIMEOUT; i++) {
1694                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1695                         break;
1696                 DELAY(10);
1697         }
1698
1699         if (i == BGE_TIMEOUT) {
1700                 if_printf(&sc->arpcom.ac_if,
1701                           "host coalescing engine failed to idle\n");
1702                 return(ENXIO);
1703         }
1704
1705         /* Set up host coalescing defaults */
1706         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1707         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1708         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1709         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1710         if (!BGE_IS_5705_PLUS(sc)) {
1711                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1712                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1713         }
1714         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1715         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1716
1717         /* Set up address of statistics block */
1718         if (!BGE_IS_5705_PLUS(sc)) {
1719                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1720                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1721                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1722                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1723
1724                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1725                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1726                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1727         }
1728
1729         /* Set up address of status block */
1730         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1731         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1732             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1733         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1734             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1735
1736         /*
1737          * Set up status block partail update size.
1738          *
1739          * Because only single TX ring, RX produce ring and Rx return ring
1740          * are used, ask device to update only minimum part of status block
1741          * except for BCM5700 AX/BX, whose status block partial update size
1742          * can't be configured.
1743          */
1744         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1745             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1746                 /* XXX Actually reserved on BCM5700 AX/BX */
1747                 val = BGE_STATBLKSZ_FULL;
1748         } else {
1749                 val = BGE_STATBLKSZ_32BYTE;
1750         }
1751
1752         /* Turn on host coalescing state machine */
1753         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1754
1755         /* Turn on RX BD completion state machine and enable attentions */
1756         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1757             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1758
1759         /* Turn on RX list placement state machine */
1760         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1761
1762         /* Turn on RX list selector state machine. */
1763         if (!BGE_IS_5705_PLUS(sc))
1764                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1765
1766         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1767             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1768             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1769             BGE_MACMODE_FRMHDR_DMA_ENB;
1770
1771         if (sc->bge_flags & BGE_FLAG_TBI)
1772                 val |= BGE_PORTMODE_TBI;
1773         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1774                 val |= BGE_PORTMODE_GMII;
1775         else
1776                 val |= BGE_PORTMODE_MII;
1777
1778         /* Turn on DMA, clear stats */
1779         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1780
1781         /* Set misc. local control, enable interrupts on attentions */
1782         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1783
1784 #ifdef notdef
1785         /* Assert GPIO pins for PHY reset */
1786         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1787             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1788         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1789             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1790 #endif
1791
1792         /* Turn on DMA completion state machine */
1793         if (!BGE_IS_5705_PLUS(sc))
1794                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1795
1796         /* Turn on write DMA state machine */
1797         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1798         if (BGE_IS_5755_PLUS(sc)) {
1799                 /* Enable host coalescing bug fix. */
1800                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1801         }
1802         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1803                 /* Request larger DMA burst size to get better performance. */
1804                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1805         }
1806         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1807         DELAY(40);
1808
1809         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1810             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1811             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1812             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1813                 /*
1814                  * Enable fix for read DMA FIFO overruns.
1815                  * The fix is to limit the number of RX BDs
1816                  * the hardware would fetch at a fime.
1817                  */
1818                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1819                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1820                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1821         }
1822
1823         /* Turn on read DMA state machine */
1824         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1825         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1826             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1827             sc->bge_asicrev == BGE_ASICREV_BCM57780)
1828                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1829                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1830                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1831         if (sc->bge_flags & BGE_FLAG_PCIE)
1832                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1833         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1834         DELAY(40);
1835
1836         /* Turn on RX data completion state machine */
1837         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1838
1839         /* Turn on RX BD initiator state machine */
1840         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1841
1842         /* Turn on RX data and RX BD initiator state machine */
1843         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1844
1845         /* Turn on Mbuf cluster free state machine */
1846         if (!BGE_IS_5705_PLUS(sc))
1847                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1848
1849         /* Turn on send BD completion state machine */
1850         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1851
1852         /* Turn on send data completion state machine */
1853         val = BGE_SDCMODE_ENABLE;
1854         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1855                 val |= BGE_SDCMODE_CDELAY; 
1856         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1857
1858         /* Turn on send data initiator state machine */
1859         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1860
1861         /* Turn on send BD initiator state machine */
1862         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1863
1864         /* Turn on send BD selector state machine */
1865         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1866
1867         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1868         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1869             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1870
1871         /* ack/clear link change events */
1872         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1873             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1874             BGE_MACSTAT_LINK_CHANGED);
1875         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1876
1877         /*
1878          * Enable attention when the link has changed state for
1879          * devices that use auto polling.
1880          */
1881         if (sc->bge_flags & BGE_FLAG_TBI) {
1882                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1883         } else {
1884                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1885                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1886                         DELAY(80);
1887                 }
1888                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1889                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1890                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1891                             BGE_EVTENB_MI_INTERRUPT);
1892                 }
1893         }
1894
1895         /*
1896          * Clear any pending link state attention.
1897          * Otherwise some link state change events may be lost until attention
1898          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1899          * It's not necessary on newer BCM chips - perhaps enabling link
1900          * state change attentions implies clearing pending attention.
1901          */
1902         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1903             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1904             BGE_MACSTAT_LINK_CHANGED);
1905
1906         /* Enable link state change attentions. */
1907         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1908
1909         return(0);
1910 }
1911
1912 /*
1913  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1914  * against our list and return its name if we find a match. Note
1915  * that since the Broadcom controller contains VPD support, we
1916  * can get the device name string from the controller itself instead
1917  * of the compiled-in string. This is a little slow, but it guarantees
1918  * we'll always announce the right product name.
1919  */
1920 static int
1921 bge_probe(device_t dev)
1922 {
1923         const struct bge_type *t;
1924         uint16_t product, vendor;
1925
1926         product = pci_get_device(dev);
1927         vendor = pci_get_vendor(dev);
1928
1929         for (t = bge_devs; t->bge_name != NULL; t++) {
1930                 if (vendor == t->bge_vid && product == t->bge_did)
1931                         break;
1932         }
1933         if (t->bge_name == NULL)
1934                 return(ENXIO);
1935
1936         device_set_desc(dev, t->bge_name);
1937         return(0);
1938 }
1939
1940 static int
1941 bge_attach(device_t dev)
1942 {
1943         struct ifnet *ifp;
1944         struct bge_softc *sc;
1945         uint32_t hwcfg = 0, misccfg;
1946         int error = 0, rid, capmask;
1947         uint8_t ether_addr[ETHER_ADDR_LEN];
1948         uint16_t product, vendor;
1949
1950         sc = device_get_softc(dev);
1951         sc->bge_dev = dev;
1952         callout_init(&sc->bge_stat_timer);
1953         lwkt_serialize_init(&sc->bge_jslot_serializer);
1954
1955 #ifndef BURN_BRIDGES
1956         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1957                 uint32_t irq, mem;
1958
1959                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1960                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1961
1962                 device_printf(dev, "chip is in D%d power mode "
1963                     "-- setting to D0\n", pci_get_powerstate(dev));
1964
1965                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1966
1967                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1968                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1969         }
1970 #endif  /* !BURN_BRIDGE */
1971
1972         /*
1973          * Map control/status registers.
1974          */
1975         pci_enable_busmaster(dev);
1976
1977         rid = BGE_PCI_BAR0;
1978         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1979             RF_ACTIVE);
1980
1981         if (sc->bge_res == NULL) {
1982                 device_printf(dev, "couldn't map memory\n");
1983                 return ENXIO;
1984         }
1985
1986         sc->bge_btag = rman_get_bustag(sc->bge_res);
1987         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1988
1989         /* Save various chip information */
1990         sc->bge_chipid =
1991             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1992             BGE_PCIMISCCTL_ASICREV_SHIFT;
1993         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG)
1994                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
1995         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1996         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1997
1998         /* Save chipset family. */
1999         switch (sc->bge_asicrev) {
2000         case BGE_ASICREV_BCM5755:
2001         case BGE_ASICREV_BCM5761:
2002         case BGE_ASICREV_BCM5784:
2003         case BGE_ASICREV_BCM5785:
2004         case BGE_ASICREV_BCM5787:
2005         case BGE_ASICREV_BCM57780:
2006             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2007                 BGE_FLAG_5705_PLUS;
2008             break;
2009
2010         case BGE_ASICREV_BCM5700:
2011         case BGE_ASICREV_BCM5701:
2012         case BGE_ASICREV_BCM5703:
2013         case BGE_ASICREV_BCM5704:
2014                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2015                 break;
2016
2017         case BGE_ASICREV_BCM5714_A0:
2018         case BGE_ASICREV_BCM5780:
2019         case BGE_ASICREV_BCM5714:
2020                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2021                 /* Fall through */
2022
2023         case BGE_ASICREV_BCM5750:
2024         case BGE_ASICREV_BCM5752:
2025         case BGE_ASICREV_BCM5906:
2026                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2027                 /* Fall through */
2028
2029         case BGE_ASICREV_BCM5705:
2030                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2031                 break;
2032         }
2033
2034         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2035                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2036
2037         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2038         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2039             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2040              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2041                 sc->bge_flags |= BGE_FLAG_5788;
2042
2043         /* BCM5755 or higher and BCM5906 have short DMA bug. */
2044         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2045                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2046
2047         /*
2048          * Check if this is a PCI-X or PCI Express device.
2049          */
2050         if (BGE_IS_5705_PLUS(sc)) {
2051                 if (pci_is_pcie(dev)) {
2052                         sc->bge_flags |= BGE_FLAG_PCIE;
2053                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2054                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2055                 }
2056         } else {
2057                 /*
2058                  * Check if the device is in PCI-X Mode.
2059                  * (This bit is not valid on PCI Express controllers.)
2060                  */
2061                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2062                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
2063                         sc->bge_flags |= BGE_FLAG_PCIX;
2064                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2065                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2066                             "mbox_reorder", 0);
2067                 }
2068         }
2069         device_printf(dev, "CHIP ID 0x%08x; "
2070                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2071                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2072                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2073                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2074                         "PCI-E" : "PCI"));
2075
2076         /*
2077          * The 40bit DMA bug applies to the 5714/5715 controllers and is
2078          * not actually a MAC controller bug but an issue with the embedded
2079          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2080          */
2081         if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
2082                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2083
2084         /* Identify the chips that use an CPMU. */
2085         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2086             sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2087             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2088             sc->bge_asicrev == BGE_ASICREV_BCM57780)
2089                 sc->bge_flags |= BGE_FLAG_CPMU;
2090
2091         /*
2092          * When using the BCM5701 in PCI-X mode, data corruption has
2093          * been observed in the first few bytes of some received packets.
2094          * Aligning the packet buffer in memory eliminates the corruption.
2095          * Unfortunately, this misaligns the packet payloads.  On platforms
2096          * which do not support unaligned accesses, we will realign the
2097          * payloads by copying the received packets.
2098          */
2099         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2100             (sc->bge_flags & BGE_FLAG_PCIX))
2101                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2102
2103         /*
2104          * Set various PHY quirk flags.
2105          */
2106         product = pci_get_device(dev);
2107         vendor = pci_get_vendor(dev);
2108
2109         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2110              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2111             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2112                 sc->bge_phy_flags |= BGE_PHY_NO_3LED;
2113
2114         capmask = MII_CAPMASK_DEFAULT;
2115         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2116              (misccfg == 0x4000 || misccfg == 0x8000)) ||
2117             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2118              vendor == PCI_VENDOR_BROADCOM &&
2119              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2120               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2121               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2122             (vendor == PCI_VENDOR_BROADCOM &&
2123              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2124               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2125               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2126             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2127             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2128                 /* 10/100 only */
2129                 capmask &= ~BMSR_EXTSTAT;
2130         }
2131
2132         sc->bge_phy_flags |= BGE_PHY_WIRESPEED;
2133         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2134             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2135              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2136               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2137             sc->bge_asicrev == BGE_ASICREV_BCM5906)
2138                 sc->bge_phy_flags &= ~BGE_PHY_WIRESPEED;
2139
2140         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2141             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2142                 sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
2143
2144         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2145             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2146                 sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
2147
2148         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2149                 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
2150
2151         if (BGE_IS_5705_PLUS(sc) &&
2152             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2153             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2154             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2155             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2156             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2157                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2158                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2159                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2160                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2161                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2162                             product != PCI_PRODUCT_BROADCOM_BCM5756)
2163                                 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
2164                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2165                                 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
2166                 } else {
2167                         sc->bge_phy_flags |= BGE_PHY_BER_BUG;
2168                 }
2169         }
2170
2171         /* Allocate interrupt */
2172         rid = 0;
2173         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2174             RF_SHAREABLE | RF_ACTIVE);
2175         if (sc->bge_irq == NULL) {
2176                 device_printf(dev, "couldn't map interrupt\n");
2177                 error = ENXIO;
2178                 goto fail;
2179         }
2180
2181         /* Initialize if_name earlier, so if_printf could be used */
2182         ifp = &sc->arpcom.ac_if;
2183         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2184
2185         /* Try to reset the chip. */
2186         bge_reset(sc);
2187
2188         if (bge_chipinit(sc)) {
2189                 device_printf(dev, "chip initialization failed\n");
2190                 error = ENXIO;
2191                 goto fail;
2192         }
2193
2194         /*
2195          * Get station address
2196          */
2197         error = bge_get_eaddr(sc, ether_addr);
2198         if (error) {
2199                 device_printf(dev, "failed to read station address\n");
2200                 goto fail;
2201         }
2202
2203         /* 5705/5750 limits RX return ring to 512 entries. */
2204         if (BGE_IS_5705_PLUS(sc))
2205                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2206         else
2207                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2208
2209         error = bge_dma_alloc(sc);
2210         if (error)
2211                 goto fail;
2212
2213         /* Set default tuneable values. */
2214         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2215         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
2216         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
2217         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
2218         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
2219
2220         /* Set up ifnet structure */
2221         ifp->if_softc = sc;
2222         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2223         ifp->if_ioctl = bge_ioctl;
2224         ifp->if_start = bge_start;
2225 #ifdef DEVICE_POLLING
2226         ifp->if_poll = bge_poll;
2227 #endif
2228         ifp->if_watchdog = bge_watchdog;
2229         ifp->if_init = bge_init;
2230         ifp->if_mtu = ETHERMTU;
2231         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2232         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2233         ifq_set_ready(&ifp->if_snd);
2234
2235         /*
2236          * 5700 B0 chips do not support checksumming correctly due
2237          * to hardware bugs.
2238          */
2239         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2240                 ifp->if_capabilities |= IFCAP_HWCSUM;
2241                 ifp->if_hwassist = BGE_CSUM_FEATURES;
2242         }
2243         ifp->if_capenable = ifp->if_capabilities;
2244
2245         /*
2246          * Figure out what sort of media we have by checking the
2247          * hardware config word in the first 32k of NIC internal memory,
2248          * or fall back to examining the EEPROM if necessary.
2249          * Note: on some BCM5700 cards, this value appears to be unset.
2250          * If that's the case, we have to rely on identifying the NIC
2251          * by its PCI subsystem ID, as we do below for the SysKonnect
2252          * SK-9D41.
2253          */
2254         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2255                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2256         } else {
2257                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2258                                     sizeof(hwcfg))) {
2259                         device_printf(dev, "failed to read EEPROM\n");
2260                         error = ENXIO;
2261                         goto fail;
2262                 }
2263                 hwcfg = ntohl(hwcfg);
2264         }
2265
2266         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2267         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2268             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2269                 if (BGE_IS_5714_FAMILY(sc))
2270                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
2271                 else
2272                         sc->bge_flags |= BGE_FLAG_TBI;
2273         }
2274
2275         /* Setup MI MODE */
2276         if (sc->bge_flags & BGE_FLAG_CPMU)
2277                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2278         else
2279                 sc->bge_mi_mode = BGE_MIMODE_BASE;
2280         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2281                 /* Enable auto polling for BCM570[0-5]. */
2282                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2283         }
2284
2285         /* Setup link status update stuffs */
2286         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2287             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2288                 sc->bge_link_upd = bge_bcm5700_link_upd;
2289                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2290         } else if (sc->bge_flags & BGE_FLAG_TBI) {
2291                 sc->bge_link_upd = bge_tbi_link_upd;
2292                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2293         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2294                 sc->bge_link_upd = bge_autopoll_link_upd;
2295                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2296         } else {
2297                 sc->bge_link_upd = bge_copper_link_upd;
2298                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2299         }
2300
2301         /*
2302          * Broadcom's own driver always assumes the internal
2303          * PHY is at GMII address 1.  On some chips, the PHY responds
2304          * to accesses at all addresses, which could cause us to
2305          * bogusly attach the PHY 32 times at probe type.  Always
2306          * restricting the lookup to address 1 is simpler than
2307          * trying to figure out which chips revisions should be
2308          * special-cased.
2309          */
2310         sc->bge_phyno = 1;
2311
2312         if (sc->bge_flags & BGE_FLAG_TBI) {
2313                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2314                     bge_ifmedia_upd, bge_ifmedia_sts);
2315                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2316                 ifmedia_add(&sc->bge_ifmedia,
2317                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2318                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2319                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2320                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2321         } else {
2322                 struct mii_probe_args mii_args;
2323
2324                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2325                 mii_args.mii_probemask = 1 << sc->bge_phyno;
2326                 mii_args.mii_capmask = capmask;
2327
2328                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2329                 if (error) {
2330                         device_printf(dev, "MII without any PHY!\n");
2331                         goto fail;
2332                 }
2333         }
2334
2335         /*
2336          * Create sysctl nodes.
2337          */
2338         sysctl_ctx_init(&sc->bge_sysctl_ctx);
2339         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2340                                               SYSCTL_STATIC_CHILDREN(_hw),
2341                                               OID_AUTO,
2342                                               device_get_nameunit(dev),
2343                                               CTLFLAG_RD, 0, "");
2344         if (sc->bge_sysctl_tree == NULL) {
2345                 device_printf(dev, "can't add sysctl node\n");
2346                 error = ENXIO;
2347                 goto fail;
2348         }
2349
2350         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2351                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2352                         OID_AUTO, "rx_coal_ticks",
2353                         CTLTYPE_INT | CTLFLAG_RW,
2354                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
2355                         "Receive coalescing ticks (usec).");
2356         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2357                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2358                         OID_AUTO, "tx_coal_ticks",
2359                         CTLTYPE_INT | CTLFLAG_RW,
2360                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
2361                         "Transmit coalescing ticks (usec).");
2362         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2363                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2364                         OID_AUTO, "rx_max_coal_bds",
2365                         CTLTYPE_INT | CTLFLAG_RW,
2366                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
2367                         "Receive max coalesced BD count.");
2368         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2369                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2370                         OID_AUTO, "tx_max_coal_bds",
2371                         CTLTYPE_INT | CTLFLAG_RW,
2372                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
2373                         "Transmit max coalesced BD count.");
2374         if (sc->bge_flags & BGE_FLAG_PCIE) {
2375                 /*
2376                  * A common design characteristic for many Broadcom
2377                  * client controllers is that they only support a
2378                  * single outstanding DMA read operation on the PCIe
2379                  * bus. This means that it will take twice as long to
2380                  * fetch a TX frame that is split into header and
2381                  * payload buffers as it does to fetch a single,
2382                  * contiguous TX frame (2 reads vs. 1 read). For these
2383                  * controllers, coalescing buffers to reduce the number
2384                  * of memory reads is effective way to get maximum
2385                  * performance(about 940Mbps).  Without collapsing TX
2386                  * buffers the maximum TCP bulk transfer performance
2387                  * is about 850Mbps. However forcing coalescing mbufs
2388                  * consumes a lot of CPU cycles, so leave it off by
2389                  * default.
2390                  */
2391                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2392                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2393                                OID_AUTO, "force_defrag", CTLFLAG_RW,
2394                                &sc->bge_force_defrag, 0,
2395                                "Force defragment on TX path");
2396         }
2397
2398         /*
2399          * Call MI attach routine.
2400          */
2401         ether_ifattach(ifp, ether_addr, NULL);
2402
2403         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE,
2404                                bge_intr, sc, &sc->bge_intrhand, 
2405                                ifp->if_serializer);
2406         if (error) {
2407                 ether_ifdetach(ifp);
2408                 device_printf(dev, "couldn't set up irq\n");
2409                 goto fail;
2410         }
2411
2412         ifp->if_cpuid = rman_get_cpuid(sc->bge_irq);
2413         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
2414
2415         return(0);
2416 fail:
2417         bge_detach(dev);
2418         return(error);
2419 }
2420
2421 static int
2422 bge_detach(device_t dev)
2423 {
2424         struct bge_softc *sc = device_get_softc(dev);
2425
2426         if (device_is_attached(dev)) {
2427                 struct ifnet *ifp = &sc->arpcom.ac_if;
2428
2429                 lwkt_serialize_enter(ifp->if_serializer);
2430                 bge_stop(sc);
2431                 bge_reset(sc);
2432                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2433                 lwkt_serialize_exit(ifp->if_serializer);
2434
2435                 ether_ifdetach(ifp);
2436         }
2437
2438         if (sc->bge_flags & BGE_FLAG_TBI)
2439                 ifmedia_removeall(&sc->bge_ifmedia);
2440         if (sc->bge_miibus)
2441                 device_delete_child(dev, sc->bge_miibus);
2442         bus_generic_detach(dev);
2443
2444         if (sc->bge_irq != NULL)
2445                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
2446
2447         if (sc->bge_res != NULL)
2448                 bus_release_resource(dev, SYS_RES_MEMORY,
2449                     BGE_PCI_BAR0, sc->bge_res);
2450
2451         if (sc->bge_sysctl_tree != NULL)
2452                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2453
2454         bge_dma_free(sc);
2455
2456         return 0;
2457 }
2458
2459 static void
2460 bge_reset(struct bge_softc *sc)
2461 {
2462         device_t dev;
2463         uint32_t cachesize, command, pcistate, reset;
2464         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2465         int i, val = 0;
2466
2467         dev = sc->bge_dev;
2468
2469         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2470             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2471                 if (sc->bge_flags & BGE_FLAG_PCIE)
2472                         write_op = bge_writemem_direct;
2473                 else
2474                         write_op = bge_writemem_ind;
2475         } else {
2476                 write_op = bge_writereg_ind;
2477         }
2478
2479         /* Save some important PCI state. */
2480         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2481         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2482         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2483
2484         pci_write_config(dev, BGE_PCI_MISC_CTL,
2485             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2486             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2487
2488         /* Disable fastboot on controllers that support it. */
2489         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2490             BGE_IS_5755_PLUS(sc)) {
2491                 if (bootverbose)
2492                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2493                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2494         }
2495
2496         /*
2497          * Write the magic number to SRAM at offset 0xB50.
2498          * When firmware finishes its initialization it will
2499          * write ~BGE_MAGIC_NUMBER to the same location.
2500          */
2501         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2502
2503         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2504
2505         /* XXX: Broadcom Linux driver. */
2506         if (sc->bge_flags & BGE_FLAG_PCIE) {
2507                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2508                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2509                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2510                         /* Prevent PCIE link training during global reset */
2511                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2512                         reset |= (1<<29);
2513                 }
2514         }
2515
2516         /* 
2517          * Set GPHY Power Down Override to leave GPHY
2518          * powered up in D0 uninitialized.
2519          */
2520         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2521                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2522
2523         /* Issue global reset */
2524         write_op(sc, BGE_MISC_CFG, reset);
2525
2526         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2527                 uint32_t status, ctrl;
2528
2529                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2530                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2531                     status | BGE_VCPU_STATUS_DRV_RESET);
2532                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2533                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2534                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2535         }
2536
2537         DELAY(1000);
2538
2539         /* XXX: Broadcom Linux driver. */
2540         if (sc->bge_flags & BGE_FLAG_PCIE) {
2541                 uint16_t devctl;
2542
2543                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2544                         uint32_t v;
2545
2546                         DELAY(500000); /* wait for link training to complete */
2547                         v = pci_read_config(dev, 0xc4, 4);
2548                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2549                 }
2550
2551                 /* Clear enable no snoop and disable relaxed ordering. */
2552                 devctl = pci_read_config(dev,
2553                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
2554                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2555                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2556                     devctl, 2);
2557
2558                 /* Clear error status. */
2559                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2560                     PCIEM_DEVSTS_CORR_ERR |
2561                     PCIEM_DEVSTS_NFATAL_ERR |
2562                     PCIEM_DEVSTS_FATAL_ERR |
2563                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
2564         }
2565
2566         /* Reset some of the PCI state that got zapped by reset */
2567         pci_write_config(dev, BGE_PCI_MISC_CTL,
2568             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2569             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2570         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2571         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2572         write_op(sc, BGE_MISC_CFG, (65 << 1));
2573
2574         /*
2575          * Disable PCI-X relaxed ordering to ensure status block update
2576          * comes first then packet buffer DMA. Otherwise driver may
2577          * read stale status block.
2578          */
2579         if (sc->bge_flags & BGE_FLAG_PCIX) {
2580                 uint16_t devctl;
2581
2582                 devctl = pci_read_config(dev,
2583                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
2584                 devctl &= ~PCIXM_COMMAND_ERO;
2585                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2586                         devctl &= ~PCIXM_COMMAND_MAX_READ;
2587                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2588                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2589                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2590                             PCIXM_COMMAND_MAX_READ);
2591                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
2592                 }
2593                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2594                     devctl, 2);
2595         }
2596
2597         /* Enable memory arbiter. */
2598         if (BGE_IS_5714_FAMILY(sc)) {
2599                 uint32_t val;
2600
2601                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2602                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2603         } else {
2604                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2605         }
2606
2607         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2608                 for (i = 0; i < BGE_TIMEOUT; i++) {
2609                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2610                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2611                                 break;
2612                         DELAY(100);
2613                 }
2614                 if (i == BGE_TIMEOUT) {
2615                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2616                         return;
2617                 }
2618         } else {
2619                 /*
2620                  * Poll until we see the 1's complement of the magic number.
2621                  * This indicates that the firmware initialization
2622                  * is complete.
2623                  */
2624                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2625                         val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2626                         if (val == ~BGE_MAGIC_NUMBER)
2627                                 break;
2628                         DELAY(10);
2629                 }
2630                 if (i == BGE_FIRMWARE_TIMEOUT) {
2631                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2632                                   "timed out, found 0x%08x\n", val);
2633                         return;
2634                 }
2635         }
2636
2637         /*
2638          * XXX Wait for the value of the PCISTATE register to
2639          * return to its original pre-reset state. This is a
2640          * fairly good indicator of reset completion. If we don't
2641          * wait for the reset to fully complete, trying to read
2642          * from the device's non-PCI registers may yield garbage
2643          * results.
2644          */
2645         for (i = 0; i < BGE_TIMEOUT; i++) {
2646                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2647                         break;
2648                 DELAY(10);
2649         }
2650
2651         /* Fix up byte swapping */
2652         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2653             BGE_MODECTL_BYTESWAP_DATA);
2654
2655         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2656
2657         /*
2658          * The 5704 in TBI mode apparently needs some special
2659          * adjustment to insure the SERDES drive level is set
2660          * to 1.2V.
2661          */
2662         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2663             (sc->bge_flags & BGE_FLAG_TBI)) {
2664                 uint32_t serdescfg;
2665
2666                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2667                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2668                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2669         }
2670
2671         /* XXX: Broadcom Linux driver. */
2672         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2673             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2674             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2675                 uint32_t v;
2676
2677                 /* Enable Data FIFO protection. */
2678                 v = CSR_READ_4(sc, 0x7c00);
2679                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2680         }
2681
2682         DELAY(10000);
2683 }
2684
2685 /*
2686  * Frame reception handling. This is called if there's a frame
2687  * on the receive return list.
2688  *
2689  * Note: we have to be able to handle two possibilities here:
2690  * 1) the frame is from the jumbo recieve ring
2691  * 2) the frame is from the standard receive ring
2692  */
2693
2694 static void
2695 bge_rxeof(struct bge_softc *sc)
2696 {
2697         struct ifnet *ifp;
2698         int stdcnt = 0, jumbocnt = 0;
2699
2700         if (sc->bge_rx_saved_considx ==
2701             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2702                 return;
2703
2704         ifp = &sc->arpcom.ac_if;
2705
2706         while (sc->bge_rx_saved_considx !=
2707                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2708                 struct bge_rx_bd        *cur_rx;
2709                 uint32_t                rxidx;
2710                 struct mbuf             *m = NULL;
2711                 uint16_t                vlan_tag = 0;
2712                 int                     have_tag = 0;
2713
2714                 cur_rx =
2715             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2716
2717                 rxidx = cur_rx->bge_idx;
2718                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2719                 logif(rx_pkt);
2720
2721                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2722                         have_tag = 1;
2723                         vlan_tag = cur_rx->bge_vlan_tag;
2724                 }
2725
2726                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2727                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2728                         jumbocnt++;
2729
2730                         if (rxidx != sc->bge_jumbo) {
2731                                 ifp->if_ierrors++;
2732                                 if_printf(ifp, "sw jumbo index(%d) "
2733                                     "and hw jumbo index(%d) mismatch, drop!\n",
2734                                     sc->bge_jumbo, rxidx);
2735                                 bge_setup_rxdesc_jumbo(sc, rxidx);
2736                                 continue;
2737                         }
2738
2739                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
2740                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2741                                 ifp->if_ierrors++;
2742                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2743                                 continue;
2744                         }
2745                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
2746                                 ifp->if_ierrors++;
2747                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
2748                                 continue;
2749                         }
2750                 } else {
2751                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2752                         stdcnt++;
2753
2754                         if (rxidx != sc->bge_std) {
2755                                 ifp->if_ierrors++;
2756                                 if_printf(ifp, "sw std index(%d) "
2757                                     "and hw std index(%d) mismatch, drop!\n",
2758                                     sc->bge_std, rxidx);
2759                                 bge_setup_rxdesc_std(sc, rxidx);
2760                                 continue;
2761                         }
2762
2763                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
2764                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2765                                 ifp->if_ierrors++;
2766                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2767                                 continue;
2768                         }
2769                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
2770                                 ifp->if_ierrors++;
2771                                 bge_setup_rxdesc_std(sc, sc->bge_std);
2772                                 continue;
2773                         }
2774                 }
2775
2776                 ifp->if_ipackets++;
2777 #if !defined(__i386__) && !defined(__x86_64__)
2778                 /*
2779                  * The x86 allows unaligned accesses, but for other
2780                  * platforms we must make sure the payload is aligned.
2781                  */
2782                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2783                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2784                             cur_rx->bge_len);
2785                         m->m_data += ETHER_ALIGN;
2786                 }
2787 #endif
2788                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2789                 m->m_pkthdr.rcvif = ifp;
2790
2791                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2792                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2793                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2794                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2795                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2796                         }
2797                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
2798                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2799                                 m->m_pkthdr.csum_data =
2800                                         cur_rx->bge_tcp_udp_csum;
2801                                 m->m_pkthdr.csum_flags |=
2802                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2803                         }
2804                 }
2805
2806                 /*
2807                  * If we received a packet with a vlan tag, pass it
2808                  * to vlan_input() instead of ether_input().
2809                  */
2810                 if (have_tag) {
2811                         m->m_flags |= M_VLANTAG;
2812                         m->m_pkthdr.ether_vlantag = vlan_tag;
2813                         have_tag = vlan_tag = 0;
2814                 }
2815                 ifp->if_input(ifp, m);
2816         }
2817
2818         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2819         if (stdcnt)
2820                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2821         if (jumbocnt)
2822                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2823 }
2824
2825 static void
2826 bge_txeof(struct bge_softc *sc)
2827 {
2828         struct bge_tx_bd *cur_tx = NULL;
2829         struct ifnet *ifp;
2830
2831         if (sc->bge_tx_saved_considx ==
2832             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2833                 return;
2834
2835         ifp = &sc->arpcom.ac_if;
2836
2837         /*
2838          * Go through our tx ring and free mbufs for those
2839          * frames that have been sent.
2840          */
2841         while (sc->bge_tx_saved_considx !=
2842                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2843                 uint32_t idx = 0;
2844
2845                 idx = sc->bge_tx_saved_considx;
2846                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2847                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2848                         ifp->if_opackets++;
2849                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2850                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
2851                             sc->bge_cdata.bge_tx_dmamap[idx]);
2852                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2853                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2854                 }
2855                 sc->bge_txcnt--;
2856                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2857                 logif(tx_pkt);
2858         }
2859
2860         if (cur_tx != NULL &&
2861             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2862             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2863                 ifp->if_flags &= ~IFF_OACTIVE;
2864
2865         if (sc->bge_txcnt == 0)
2866                 ifp->if_timer = 0;
2867
2868         if (!ifq_is_empty(&ifp->if_snd))
2869                 if_devstart(ifp);
2870 }
2871
2872 #ifdef DEVICE_POLLING
2873
2874 static void
2875 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2876 {
2877         struct bge_softc *sc = ifp->if_softc;
2878         uint32_t status;
2879
2880         switch(cmd) {
2881         case POLL_REGISTER:
2882                 bge_disable_intr(sc);
2883                 break;
2884         case POLL_DEREGISTER:
2885                 bge_enable_intr(sc);
2886                 break;
2887         case POLL_AND_CHECK_STATUS:
2888                 /*
2889                  * Process link state changes.
2890                  */
2891                 status = CSR_READ_4(sc, BGE_MAC_STS);
2892                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2893                         sc->bge_link_evt = 0;
2894                         sc->bge_link_upd(sc, status);
2895                 }
2896                 /* fall through */
2897         case POLL_ONLY:
2898                 if (ifp->if_flags & IFF_RUNNING) {
2899                         bge_rxeof(sc);
2900                         bge_txeof(sc);
2901                 }
2902                 break;
2903         }
2904 }
2905
2906 #endif
2907
2908 static void
2909 bge_intr(void *xsc)
2910 {
2911         struct bge_softc *sc = xsc;
2912         struct ifnet *ifp = &sc->arpcom.ac_if;
2913         uint32_t status;
2914
2915         logif(intr);
2916
2917         /*
2918          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2919          * disable interrupts by writing nonzero like we used to, since with
2920          * our current organization this just gives complications and
2921          * pessimizations for re-enabling interrupts.  We used to have races
2922          * instead of the necessary complications.  Disabling interrupts
2923          * would just reduce the chance of a status update while we are
2924          * running (by switching to the interrupt-mode coalescence
2925          * parameters), but this chance is already very low so it is more
2926          * efficient to get another interrupt than prevent it.
2927          *
2928          * We do the ack first to ensure another interrupt if there is a
2929          * status update after the ack.  We don't check for the status
2930          * changing later because it is more efficient to get another
2931          * interrupt than prevent it, not quite as above (not checking is
2932          * a smaller optimization than not toggling the interrupt enable,
2933          * since checking doesn't involve PCI accesses and toggling require
2934          * the status check).  So toggling would probably be a pessimization
2935          * even with MSI.  It would only be needed for using a task queue.
2936          */
2937         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
2938
2939         /*
2940          * Process link state changes.
2941          */
2942         status = CSR_READ_4(sc, BGE_MAC_STS);
2943         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2944                 sc->bge_link_evt = 0;
2945                 sc->bge_link_upd(sc, status);
2946         }
2947
2948         if (ifp->if_flags & IFF_RUNNING) {
2949                 /* Check RX return ring producer/consumer */
2950                 bge_rxeof(sc);
2951
2952                 /* Check TX ring producer/consumer */
2953                 bge_txeof(sc);
2954         }
2955
2956         if (sc->bge_coal_chg)
2957                 bge_coal_change(sc);
2958 }
2959
2960 static void
2961 bge_tick(void *xsc)
2962 {
2963         struct bge_softc *sc = xsc;
2964         struct ifnet *ifp = &sc->arpcom.ac_if;
2965
2966         lwkt_serialize_enter(ifp->if_serializer);
2967
2968         if (BGE_IS_5705_PLUS(sc))
2969                 bge_stats_update_regs(sc);
2970         else
2971                 bge_stats_update(sc);
2972
2973         if (sc->bge_flags & BGE_FLAG_TBI) {
2974                 /*
2975                  * Since in TBI mode auto-polling can't be used we should poll
2976                  * link status manually. Here we register pending link event
2977                  * and trigger interrupt.
2978                  */
2979                 sc->bge_link_evt++;
2980                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2981                     BGE_IS_5788(sc))
2982                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2983                 else
2984                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2985         } else if (!sc->bge_link) {
2986                 mii_tick(device_get_softc(sc->bge_miibus));
2987         }
2988
2989         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2990
2991         lwkt_serialize_exit(ifp->if_serializer);
2992 }
2993
2994 static void
2995 bge_stats_update_regs(struct bge_softc *sc)
2996 {
2997         struct ifnet *ifp = &sc->arpcom.ac_if;
2998         struct bge_mac_stats_regs stats;
2999         uint32_t *s;
3000         int i;
3001
3002         s = (uint32_t *)&stats;
3003         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3004                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3005                 s++;
3006         }
3007
3008         ifp->if_collisions +=
3009            (stats.dot3StatsSingleCollisionFrames +
3010            stats.dot3StatsMultipleCollisionFrames +
3011            stats.dot3StatsExcessiveCollisions +
3012            stats.dot3StatsLateCollisions) -
3013            ifp->if_collisions;
3014 }
3015
3016 static void
3017 bge_stats_update(struct bge_softc *sc)
3018 {
3019         struct ifnet *ifp = &sc->arpcom.ac_if;
3020         bus_size_t stats;
3021
3022         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3023
3024 #define READ_STAT(sc, stats, stat)      \
3025         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3026
3027         ifp->if_collisions +=
3028            (READ_STAT(sc, stats,
3029                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3030             READ_STAT(sc, stats,
3031                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3032             READ_STAT(sc, stats,
3033                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3034             READ_STAT(sc, stats,
3035                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
3036            ifp->if_collisions;
3037
3038 #undef READ_STAT
3039
3040 #ifdef notdef
3041         ifp->if_collisions +=
3042            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3043            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3044            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3045            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
3046            ifp->if_collisions;
3047 #endif
3048 }
3049
3050 /*
3051  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
3052  * pointers to descriptors.
3053  */
3054 static int
3055 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx)
3056 {
3057         struct bge_tx_bd *d = NULL;
3058         uint16_t csum_flags = 0;
3059         bus_dma_segment_t segs[BGE_NSEG_NEW];
3060         bus_dmamap_t map;
3061         int error, maxsegs, nsegs, idx, i;
3062         struct mbuf *m_head = *m_head0, *m_new;
3063
3064         if (m_head->m_pkthdr.csum_flags) {
3065                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3066                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3067                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3068                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3069                 if (m_head->m_flags & M_LASTFRAG)
3070                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3071                 else if (m_head->m_flags & M_FRAG)
3072                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3073         }
3074
3075         idx = *txidx;
3076         map = sc->bge_cdata.bge_tx_dmamap[idx];
3077
3078         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
3079         KASSERT(maxsegs >= BGE_NSEG_SPARE,
3080                 ("not enough segments %d", maxsegs));
3081
3082         if (maxsegs > BGE_NSEG_NEW)
3083                 maxsegs = BGE_NSEG_NEW;
3084
3085         /*
3086          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
3087          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
3088          * but when such padded frames employ the bge IP/TCP checksum
3089          * offload, the hardware checksum assist gives incorrect results
3090          * (possibly from incorporating its own padding into the UDP/TCP
3091          * checksum; who knows).  If we pad such runts with zeros, the
3092          * onboard checksum comes out correct.
3093          */
3094         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3095             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
3096                 error = m_devpad(m_head, BGE_MIN_FRAME);
3097                 if (error)
3098                         goto back;
3099         }
3100
3101         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3102                 m_new = bge_defrag_shortdma(m_head);
3103                 if (m_new == NULL) {
3104                         error = ENOBUFS;
3105                         goto back;
3106                 }
3107                 *m_head0 = m_head = m_new;
3108         }
3109         if (sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3110             m_head->m_next != NULL) {
3111                 /*
3112                  * Forcefully defragment mbuf chain to overcome hardware
3113                  * limitation which only support a single outstanding
3114                  * DMA read operation.  If it fails, keep moving on using
3115                  * the original mbuf chain.
3116                  */
3117                 m_new = m_defrag(m_head, MB_DONTWAIT);
3118                 if (m_new != NULL)
3119                         *m_head0 = m_head = m_new;
3120         }
3121
3122         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3123                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3124         if (error)
3125                 goto back;
3126
3127         m_head = *m_head0;
3128         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3129
3130         for (i = 0; ; i++) {
3131                 d = &sc->bge_ldata.bge_tx_ring[idx];
3132
3133                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3134                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3135                 d->bge_len = segs[i].ds_len;
3136                 d->bge_flags = csum_flags;
3137
3138                 if (i == nsegs - 1)
3139                         break;
3140                 BGE_INC(idx, BGE_TX_RING_CNT);
3141         }
3142         /* Mark the last segment as end of packet... */
3143         d->bge_flags |= BGE_TXBDFLAG_END;
3144
3145         /* Set vlan tag to the first segment of the packet. */
3146         d = &sc->bge_ldata.bge_tx_ring[*txidx];
3147         if (m_head->m_flags & M_VLANTAG) {
3148                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3149                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3150         } else {
3151                 d->bge_vlan_tag = 0;
3152         }
3153
3154         /*
3155          * Insure that the map for this transmission is placed at
3156          * the array index of the last descriptor in this chain.
3157          */
3158         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3159         sc->bge_cdata.bge_tx_dmamap[idx] = map;
3160         sc->bge_cdata.bge_tx_chain[idx] = m_head;
3161         sc->bge_txcnt += nsegs;
3162
3163         BGE_INC(idx, BGE_TX_RING_CNT);
3164         *txidx = idx;
3165 back:
3166         if (error) {
3167                 m_freem(*m_head0);
3168                 *m_head0 = NULL;
3169         }
3170         return error;
3171 }
3172
3173 /*
3174  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3175  * to the mbuf data regions directly in the transmit descriptors.
3176  */
3177 static void
3178 bge_start(struct ifnet *ifp)
3179 {
3180         struct bge_softc *sc = ifp->if_softc;
3181         struct mbuf *m_head = NULL;
3182         uint32_t prodidx;
3183         int need_trans;
3184
3185         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3186                 return;
3187
3188         prodidx = sc->bge_tx_prodidx;
3189
3190         need_trans = 0;
3191         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3192                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3193                 if (m_head == NULL)
3194                         break;
3195
3196                 /*
3197                  * XXX
3198                  * The code inside the if() block is never reached since we
3199                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3200                  * requests to checksum TCP/UDP in a fragmented packet.
3201                  * 
3202                  * XXX
3203                  * safety overkill.  If this is a fragmented packet chain
3204                  * with delayed TCP/UDP checksums, then only encapsulate
3205                  * it if we have enough descriptors to handle the entire
3206                  * chain at once.
3207                  * (paranoia -- may not actually be needed)
3208                  */
3209                 if ((m_head->m_flags & M_FIRSTFRAG) &&
3210                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3211                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3212                             m_head->m_pkthdr.csum_data + BGE_NSEG_RSVD) {
3213                                 ifp->if_flags |= IFF_OACTIVE;
3214                                 ifq_prepend(&ifp->if_snd, m_head);
3215                                 break;
3216                         }
3217                 }
3218
3219                 /*
3220                  * Sanity check: avoid coming within BGE_NSEG_RSVD
3221                  * descriptors of the end of the ring.  Also make
3222                  * sure there are BGE_NSEG_SPARE descriptors for
3223                  * jumbo buffers' defragmentation.
3224                  */
3225                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3226                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
3227                         ifp->if_flags |= IFF_OACTIVE;
3228                         ifq_prepend(&ifp->if_snd, m_head);
3229                         break;
3230                 }
3231
3232                 /*
3233                  * Pack the data into the transmit ring. If we
3234                  * don't have room, set the OACTIVE flag and wait
3235                  * for the NIC to drain the ring.
3236                  */
3237                 if (bge_encap(sc, &m_head, &prodidx)) {
3238                         ifp->if_flags |= IFF_OACTIVE;
3239                         ifp->if_oerrors++;
3240                         break;
3241                 }
3242                 need_trans = 1;
3243
3244                 ETHER_BPF_MTAP(ifp, m_head);
3245         }
3246
3247         if (!need_trans)
3248                 return;
3249
3250         /* Transmit */
3251         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3252         /* 5700 b2 errata */
3253         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3254                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3255
3256         sc->bge_tx_prodidx = prodidx;
3257
3258         /*
3259          * Set a timeout in case the chip goes out to lunch.
3260          */
3261         ifp->if_timer = 5;
3262 }
3263
3264 static void
3265 bge_init(void *xsc)
3266 {
3267         struct bge_softc *sc = xsc;
3268         struct ifnet *ifp = &sc->arpcom.ac_if;
3269         uint16_t *m;
3270         uint32_t mode;
3271
3272         ASSERT_SERIALIZED(ifp->if_serializer);
3273
3274         /* Cancel pending I/O and flush buffers. */
3275         bge_stop(sc);
3276         bge_reset(sc);
3277         bge_chipinit(sc);
3278
3279         /*
3280          * Init the various state machines, ring
3281          * control blocks and firmware.
3282          */
3283         if (bge_blockinit(sc)) {
3284                 if_printf(ifp, "initialization failure\n");
3285                 bge_stop(sc);
3286                 return;
3287         }
3288
3289         /* Specify MTU. */
3290         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3291             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3292
3293         /* Load our MAC address. */
3294         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3295         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3296         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3297
3298         /* Enable or disable promiscuous mode as needed. */
3299         bge_setpromisc(sc);
3300
3301         /* Program multicast filter. */
3302         bge_setmulti(sc);
3303
3304         /* Init RX ring. */
3305         if (bge_init_rx_ring_std(sc)) {
3306                 if_printf(ifp, "RX ring initialization failed\n");
3307                 bge_stop(sc);
3308                 return;
3309         }
3310
3311         /*
3312          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3313          * memory to insure that the chip has in fact read the first
3314          * entry of the ring.
3315          */
3316         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3317                 uint32_t                v, i;
3318                 for (i = 0; i < 10; i++) {
3319                         DELAY(20);
3320                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3321                         if (v == (MCLBYTES - ETHER_ALIGN))
3322                                 break;
3323                 }
3324                 if (i == 10)
3325                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3326         }
3327
3328         /* Init jumbo RX ring. */
3329         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3330                 if (bge_init_rx_ring_jumbo(sc)) {
3331                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3332                         bge_stop(sc);
3333                         return;
3334                 }
3335         }
3336
3337         /* Init our RX return ring index */
3338         sc->bge_rx_saved_considx = 0;
3339
3340         /* Init TX ring. */
3341         bge_init_tx_ring(sc);
3342
3343         /* Enable TX MAC state machine lockup fix. */
3344         mode = CSR_READ_4(sc, BGE_TX_MODE);
3345         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3346                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3347         /* Turn on transmitter */
3348         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3349
3350         /* Turn on receiver */
3351         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3352
3353         /*
3354          * Set the number of good frames to receive after RX MBUF
3355          * Low Watermark has been reached.  After the RX MAC receives
3356          * this number of frames, it will drop subsequent incoming
3357          * frames until the MBUF High Watermark is reached.
3358          */
3359         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3360
3361         /* Tell firmware we're alive. */
3362         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3363
3364         /* Enable host interrupts if polling(4) is not enabled. */
3365         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3366 #ifdef DEVICE_POLLING
3367         if (ifp->if_flags & IFF_POLLING)
3368                 bge_disable_intr(sc);
3369         else
3370 #endif
3371         bge_enable_intr(sc);
3372
3373         bge_ifmedia_upd(ifp);
3374
3375         ifp->if_flags |= IFF_RUNNING;
3376         ifp->if_flags &= ~IFF_OACTIVE;
3377
3378         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3379 }
3380
3381 /*
3382  * Set media options.
3383  */
3384 static int
3385 bge_ifmedia_upd(struct ifnet *ifp)
3386 {
3387         struct bge_softc *sc = ifp->if_softc;
3388
3389         /* If this is a 1000baseX NIC, enable the TBI port. */
3390         if (sc->bge_flags & BGE_FLAG_TBI) {
3391                 struct ifmedia *ifm = &sc->bge_ifmedia;
3392
3393                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3394                         return(EINVAL);
3395
3396                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3397                 case IFM_AUTO:
3398                         /*
3399                          * The BCM5704 ASIC appears to have a special
3400                          * mechanism for programming the autoneg
3401                          * advertisement registers in TBI mode.
3402                          */
3403                         if (!bge_fake_autoneg &&
3404                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3405                                 uint32_t sgdig;
3406
3407                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3408                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3409                                 sgdig |= BGE_SGDIGCFG_AUTO |
3410                                          BGE_SGDIGCFG_PAUSE_CAP |
3411                                          BGE_SGDIGCFG_ASYM_PAUSE;
3412                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3413                                             sgdig | BGE_SGDIGCFG_SEND);
3414                                 DELAY(5);
3415                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3416                         }
3417                         break;
3418                 case IFM_1000_SX:
3419                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3420                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3421                                     BGE_MACMODE_HALF_DUPLEX);
3422                         } else {
3423                                 BGE_SETBIT(sc, BGE_MAC_MODE,
3424                                     BGE_MACMODE_HALF_DUPLEX);
3425                         }
3426                         break;
3427                 default:
3428                         return(EINVAL);
3429                 }
3430         } else {
3431                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3432
3433                 sc->bge_link_evt++;
3434                 sc->bge_link = 0;
3435                 if (mii->mii_instance) {
3436                         struct mii_softc *miisc;
3437
3438                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3439                                 mii_phy_reset(miisc);
3440                 }
3441                 mii_mediachg(mii);
3442
3443                 /*
3444                  * Force an interrupt so that we will call bge_link_upd
3445                  * if needed and clear any pending link state attention.
3446                  * Without this we are not getting any further interrupts
3447                  * for link state changes and thus will not UP the link and
3448                  * not be able to send in bge_start.  The only way to get
3449                  * things working was to receive a packet and get an RX
3450                  * intr.
3451                  *
3452                  * bge_tick should help for fiber cards and we might not
3453                  * need to do this here if BGE_FLAG_TBI is set but as
3454                  * we poll for fiber anyway it should not harm.
3455                  */
3456                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3457                     BGE_IS_5788(sc))
3458                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3459                 else
3460                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3461         }
3462         return(0);
3463 }
3464
3465 /*
3466  * Report current media status.
3467  */
3468 static void
3469 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3470 {
3471         struct bge_softc *sc = ifp->if_softc;
3472
3473         if (sc->bge_flags & BGE_FLAG_TBI) {
3474                 ifmr->ifm_status = IFM_AVALID;
3475                 ifmr->ifm_active = IFM_ETHER;
3476                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3477                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3478                         ifmr->ifm_status |= IFM_ACTIVE;
3479                 } else {
3480                         ifmr->ifm_active |= IFM_NONE;
3481                         return;
3482                 }
3483
3484                 ifmr->ifm_active |= IFM_1000_SX;
3485                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3486                         ifmr->ifm_active |= IFM_HDX;    
3487                 else
3488                         ifmr->ifm_active |= IFM_FDX;
3489         } else {
3490                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3491
3492                 mii_pollstat(mii);
3493                 ifmr->ifm_active = mii->mii_media_active;
3494                 ifmr->ifm_status = mii->mii_media_status;
3495         }
3496 }
3497
3498 static int
3499 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3500 {
3501         struct bge_softc *sc = ifp->if_softc;
3502         struct ifreq *ifr = (struct ifreq *)data;
3503         int mask, error = 0;
3504
3505         ASSERT_SERIALIZED(ifp->if_serializer);
3506
3507         switch (command) {
3508         case SIOCSIFMTU:
3509                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3510                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3511                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3512                         error = EINVAL;
3513                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3514                         ifp->if_mtu = ifr->ifr_mtu;
3515                         if (ifp->if_flags & IFF_RUNNING)
3516                                 bge_init(sc);
3517                 }
3518                 break;
3519         case SIOCSIFFLAGS:
3520                 if (ifp->if_flags & IFF_UP) {
3521                         if (ifp->if_flags & IFF_RUNNING) {
3522                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3523
3524                                 /*
3525                                  * If only the state of the PROMISC flag
3526                                  * changed, then just use the 'set promisc
3527                                  * mode' command instead of reinitializing
3528                                  * the entire NIC. Doing a full re-init
3529                                  * means reloading the firmware and waiting
3530                                  * for it to start up, which may take a
3531                                  * second or two.  Similarly for ALLMULTI.
3532                                  */
3533                                 if (mask & IFF_PROMISC)
3534                                         bge_setpromisc(sc);
3535                                 if (mask & IFF_ALLMULTI)
3536                                         bge_setmulti(sc);
3537                         } else {
3538                                 bge_init(sc);
3539                         }
3540                 } else if (ifp->if_flags & IFF_RUNNING) {
3541                         bge_stop(sc);
3542                 }
3543                 sc->bge_if_flags = ifp->if_flags;
3544                 break;
3545         case SIOCADDMULTI:
3546         case SIOCDELMULTI:
3547                 if (ifp->if_flags & IFF_RUNNING)
3548                         bge_setmulti(sc);
3549                 break;
3550         case SIOCSIFMEDIA:
3551         case SIOCGIFMEDIA:
3552                 if (sc->bge_flags & BGE_FLAG_TBI) {
3553                         error = ifmedia_ioctl(ifp, ifr,
3554                             &sc->bge_ifmedia, command);
3555                 } else {
3556                         struct mii_data *mii;
3557
3558                         mii = device_get_softc(sc->bge_miibus);
3559                         error = ifmedia_ioctl(ifp, ifr,
3560                                               &mii->mii_media, command);
3561                 }
3562                 break;
3563         case SIOCSIFCAP:
3564                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3565                 if (mask & IFCAP_HWCSUM) {
3566                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3567                         if (IFCAP_HWCSUM & ifp->if_capenable)
3568                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3569                         else
3570                                 ifp->if_hwassist = 0;
3571                 }
3572                 break;
3573         default:
3574                 error = ether_ioctl(ifp, command, data);
3575                 break;
3576         }
3577         return error;
3578 }
3579
3580 static void
3581 bge_watchdog(struct ifnet *ifp)
3582 {
3583         struct bge_softc *sc = ifp->if_softc;
3584
3585         if_printf(ifp, "watchdog timeout -- resetting\n");
3586
3587         bge_init(sc);
3588
3589         ifp->if_oerrors++;
3590
3591         if (!ifq_is_empty(&ifp->if_snd))
3592                 if_devstart(ifp);
3593 }
3594
3595 /*
3596  * Stop the adapter and free any mbufs allocated to the
3597  * RX and TX lists.
3598  */
3599 static void
3600 bge_stop(struct bge_softc *sc)
3601 {
3602         struct ifnet *ifp = &sc->arpcom.ac_if;
3603
3604         ASSERT_SERIALIZED(ifp->if_serializer);
3605
3606         callout_stop(&sc->bge_stat_timer);
3607
3608         /*
3609          * Disable all of the receiver blocks
3610          */
3611         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3612         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3613         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3614         if (BGE_IS_5700_FAMILY(sc))
3615                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3616         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3617         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3618         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3619
3620         /*
3621          * Disable all of the transmit blocks
3622          */
3623         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3624         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3625         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3626         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3627         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3628         if (BGE_IS_5700_FAMILY(sc))
3629                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3630         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3631
3632         /*
3633          * Shut down all of the memory managers and related
3634          * state machines.
3635          */
3636         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3637         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3638         if (BGE_IS_5700_FAMILY(sc))
3639                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3640         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3641         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3642         if (!BGE_IS_5705_PLUS(sc)) {
3643                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3644                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3645         }
3646
3647         /* Disable host interrupts. */
3648         bge_disable_intr(sc);
3649
3650         /*
3651          * Tell firmware we're shutting down.
3652          */
3653         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3654
3655         /* Free the RX lists. */
3656         bge_free_rx_ring_std(sc);
3657
3658         /* Free jumbo RX list. */
3659         if (BGE_IS_JUMBO_CAPABLE(sc))
3660                 bge_free_rx_ring_jumbo(sc);
3661
3662         /* Free TX buffers. */
3663         bge_free_tx_ring(sc);
3664
3665         sc->bge_link = 0;
3666         sc->bge_coal_chg = 0;
3667
3668         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3669
3670         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3671         ifp->if_timer = 0;
3672 }
3673
3674 /*
3675  * Stop all chip I/O so that the kernel's probe routines don't
3676  * get confused by errant DMAs when rebooting.
3677  */
3678 static void
3679 bge_shutdown(device_t dev)
3680 {
3681         struct bge_softc *sc = device_get_softc(dev);
3682         struct ifnet *ifp = &sc->arpcom.ac_if;
3683
3684         lwkt_serialize_enter(ifp->if_serializer);
3685         bge_stop(sc);
3686         bge_reset(sc);
3687         lwkt_serialize_exit(ifp->if_serializer);
3688 }
3689
3690 static int
3691 bge_suspend(device_t dev)
3692 {
3693         struct bge_softc *sc = device_get_softc(dev);
3694         struct ifnet *ifp = &sc->arpcom.ac_if;
3695
3696         lwkt_serialize_enter(ifp->if_serializer);
3697         bge_stop(sc);
3698         lwkt_serialize_exit(ifp->if_serializer);
3699
3700         return 0;
3701 }
3702
3703 static int
3704 bge_resume(device_t dev)
3705 {
3706         struct bge_softc *sc = device_get_softc(dev);
3707         struct ifnet *ifp = &sc->arpcom.ac_if;
3708
3709         lwkt_serialize_enter(ifp->if_serializer);
3710
3711         if (ifp->if_flags & IFF_UP) {
3712                 bge_init(sc);
3713
3714                 if (!ifq_is_empty(&ifp->if_snd))
3715                         if_devstart(ifp);
3716         }
3717
3718         lwkt_serialize_exit(ifp->if_serializer);
3719
3720         return 0;
3721 }
3722
3723 static void
3724 bge_setpromisc(struct bge_softc *sc)
3725 {
3726         struct ifnet *ifp = &sc->arpcom.ac_if;
3727
3728         if (ifp->if_flags & IFF_PROMISC)
3729                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3730         else
3731                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3732 }
3733
3734 static void
3735 bge_dma_free(struct bge_softc *sc)
3736 {
3737         int i;
3738
3739         /* Destroy RX mbuf DMA stuffs. */
3740         if (sc->bge_cdata.bge_rx_mtag != NULL) {
3741                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3742                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3743                             sc->bge_cdata.bge_rx_std_dmamap[i]);
3744                 }
3745                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3746                                    sc->bge_cdata.bge_rx_tmpmap);
3747                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3748         }
3749
3750         /* Destroy TX mbuf DMA stuffs. */
3751         if (sc->bge_cdata.bge_tx_mtag != NULL) {
3752                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3753                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3754                             sc->bge_cdata.bge_tx_dmamap[i]);
3755                 }
3756                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3757         }
3758
3759         /* Destroy standard RX ring */
3760         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3761                            sc->bge_cdata.bge_rx_std_ring_map,
3762                            sc->bge_ldata.bge_rx_std_ring);
3763
3764         if (BGE_IS_JUMBO_CAPABLE(sc))
3765                 bge_free_jumbo_mem(sc);
3766
3767         /* Destroy RX return ring */
3768         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3769                            sc->bge_cdata.bge_rx_return_ring_map,
3770                            sc->bge_ldata.bge_rx_return_ring);
3771
3772         /* Destroy TX ring */
3773         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3774                            sc->bge_cdata.bge_tx_ring_map,
3775                            sc->bge_ldata.bge_tx_ring);
3776
3777         /* Destroy status block */
3778         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3779                            sc->bge_cdata.bge_status_map,
3780                            sc->bge_ldata.bge_status_block);
3781
3782         /* Destroy statistics block */
3783         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3784                            sc->bge_cdata.bge_stats_map,
3785                            sc->bge_ldata.bge_stats);
3786
3787         /* Destroy the parent tag */
3788         if (sc->bge_cdata.bge_parent_tag != NULL)
3789                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3790 }
3791
3792 static int
3793 bge_dma_alloc(struct bge_softc *sc)
3794 {
3795         struct ifnet *ifp = &sc->arpcom.ac_if;
3796         int i, error;
3797         bus_addr_t lowaddr;
3798
3799         lowaddr = BUS_SPACE_MAXADDR;
3800         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
3801                 lowaddr = BGE_DMA_MAXADDR_40BIT;
3802
3803         /*
3804          * Allocate the parent bus DMA tag appropriate for PCI.
3805          *
3806          * All of the NetExtreme/NetLink controllers have 4GB boundary
3807          * DMA bug.
3808          * Whenever an address crosses a multiple of the 4GB boundary
3809          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3810          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3811          * state machine will lockup and cause the device to hang.
3812          */
3813         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3814                                    lowaddr, BUS_SPACE_MAXADDR,
3815                                    NULL, NULL,
3816                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3817                                    BUS_SPACE_MAXSIZE_32BIT,
3818                                    0, &sc->bge_cdata.bge_parent_tag);
3819         if (error) {
3820                 if_printf(ifp, "could not allocate parent dma tag\n");
3821                 return error;
3822         }
3823
3824         /*
3825          * Create DMA tag and maps for RX mbufs.
3826          */
3827         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3828                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3829                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3830                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3831                                    &sc->bge_cdata.bge_rx_mtag);
3832         if (error) {
3833                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3834                 return error;
3835         }
3836
3837         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3838                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
3839         if (error) {
3840                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3841                 sc->bge_cdata.bge_rx_mtag = NULL;
3842                 return error;
3843         }
3844
3845         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3846                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
3847                                           BUS_DMA_WAITOK,
3848                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3849                 if (error) {
3850                         int j;
3851
3852                         for (j = 0; j < i; ++j) {
3853                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
3854                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3855                         }
3856                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
3857                         sc->bge_cdata.bge_rx_mtag = NULL;
3858
3859                         if_printf(ifp, "could not create DMA map for RX\n");
3860                         return error;
3861                 }
3862         }
3863
3864         /*
3865          * Create DMA tag and maps for TX mbufs.
3866          */
3867         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3868                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3869                                    NULL, NULL,
3870                                    BGE_JUMBO_FRAMELEN, BGE_NSEG_NEW, MCLBYTES,
3871                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3872                                    BUS_DMA_ONEBPAGE,
3873                                    &sc->bge_cdata.bge_tx_mtag);
3874         if (error) {
3875                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3876                 return error;
3877         }
3878
3879         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3880                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
3881                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3882                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3883                 if (error) {
3884                         int j;
3885
3886                         for (j = 0; j < i; ++j) {
3887                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
3888                                         sc->bge_cdata.bge_tx_dmamap[j]);
3889                         }
3890                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
3891                         sc->bge_cdata.bge_tx_mtag = NULL;
3892
3893                         if_printf(ifp, "could not create DMA map for TX\n");
3894                         return error;
3895                 }
3896         }
3897
3898         /*
3899          * Create DMA stuffs for standard RX ring.
3900          */
3901         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3902                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3903                                     &sc->bge_cdata.bge_rx_std_ring_map,
3904                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
3905                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3906         if (error) {
3907                 if_printf(ifp, "could not create std RX ring\n");
3908                 return error;
3909         }
3910
3911         /*
3912          * Create jumbo buffer pool.
3913          */
3914         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3915                 error = bge_alloc_jumbo_mem(sc);
3916                 if (error) {
3917                         if_printf(ifp, "could not create jumbo buffer pool\n");
3918                         return error;
3919                 }
3920         }
3921
3922         /*
3923          * Create DMA stuffs for RX return ring.
3924          */
3925         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3926                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3927                                     &sc->bge_cdata.bge_rx_return_ring_map,
3928                                     (void *)&sc->bge_ldata.bge_rx_return_ring,
3929                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3930         if (error) {
3931                 if_printf(ifp, "could not create RX ret ring\n");
3932                 return error;