2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
88 #include "miibus_if.h"
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
93 /****************************************************************************/
94 /* BCE Debug Options */
95 /****************************************************************************/
98 static uint32_t bce_debug = BCE_WARN;
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
109 * 1073741824 = 1 in 2
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
126 static int bce_debug_l2fhdr_status_check = 0;
127 static int bce_debug_unexpected_attention = 0;
128 static int bce_debug_mbuf_allocation_failure = 0;
129 static int bce_debug_dma_map_addr_failure = 0;
130 static int bce_debug_bootcode_running_failure = 0;
132 #endif /* BCE_DEBUG */
135 /****************************************************************************/
136 /* PCI Device ID Table */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
142 static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
149 "Broadcom NetXtreme II BCM5706 1000Base-T" },
151 /* BCM5706S controllers and OEM boards. */
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
153 "HP NC370F Multifunction Gigabit Server Adapter" },
154 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
155 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
157 /* BCM5708C controllers and OEM boards. */
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5708 1000Base-T" },
161 /* BCM5708S controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
163 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
165 /* BCM5709C controllers and OEM boards. */
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
167 "Broadcom NetXtreme II BCM5709 1000Base-T" },
169 /* BCM5709S controllers and OEM boards. */
170 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
171 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
173 /* BCM5716 controllers and OEM boards. */
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
175 "Broadcom NetXtreme II BCM5716 1000Base-T" },
181 /****************************************************************************/
182 /* Supported Flash NVRAM device data. */
183 /****************************************************************************/
184 static const struct flash_spec flash_table[] =
186 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
187 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
190 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
191 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
192 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
194 /* Expansion entry 0001 */
195 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
196 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
197 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
199 /* Saifun SA25F010 (non-buffered flash) */
200 /* strap, cfg1, & write1 need updates */
201 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
202 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
203 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
204 "Non-buffered flash (128kB)"},
205 /* Saifun SA25F020 (non-buffered flash) */
206 /* strap, cfg1, & write1 need updates */
207 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
210 "Non-buffered flash (256kB)"},
211 /* Expansion entry 0100 */
212 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
213 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
214 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
216 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
217 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
219 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
220 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
221 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
222 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
224 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
225 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
226 /* Saifun SA25F005 (non-buffered flash) */
227 /* strap, cfg1, & write1 need updates */
228 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
229 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
230 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
231 "Non-buffered flash (64kB)"},
233 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
234 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
235 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
237 /* Expansion entry 1001 */
238 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
239 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
240 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
242 /* Expansion entry 1010 */
243 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
244 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
245 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
247 /* ATMEL AT45DB011B (buffered flash) */
248 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
249 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
250 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
251 "Buffered flash (128kB)"},
252 /* Expansion entry 1100 */
253 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
254 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
255 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
257 /* Expansion entry 1101 */
258 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
259 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
260 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
262 /* Ateml Expansion entry 1110 */
263 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
264 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
265 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
266 "Entry 1110 (Atmel)"},
267 /* ATMEL AT45DB021B (buffered flash) */
268 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
269 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
270 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
271 "Buffered flash (256kB)"},
275 * The BCM5709 controllers transparently handle the
276 * differences between Atmel 264 byte pages and all
277 * flash devices which use 256 byte pages, so no
278 * logical-to-physical mapping is required in the
281 static struct flash_spec flash_5709 = {
282 .flags = BCE_NV_BUFFERED,
283 .page_bits = BCM5709_FLASH_PAGE_BITS,
284 .page_size = BCM5709_FLASH_PAGE_SIZE,
285 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
286 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
287 .name = "5709/5716 buffered flash (256kB)",
291 /****************************************************************************/
292 /* DragonFly device entry points. */
293 /****************************************************************************/
294 static int bce_probe(device_t);
295 static int bce_attach(device_t);
296 static int bce_detach(device_t);
297 static void bce_shutdown(device_t);
299 /****************************************************************************/
300 /* BCE Debug Data Structure Dump Routines */
301 /****************************************************************************/
303 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
304 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
305 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
306 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
307 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
308 static void bce_dump_l2fhdr(struct bce_softc *, int,
309 struct l2_fhdr *) __unused;
310 static void bce_dump_tx_chain(struct bce_softc *, int, int);
311 static void bce_dump_rx_chain(struct bce_softc *, int, int);
312 static void bce_dump_status_block(struct bce_softc *);
313 static void bce_dump_driver_state(struct bce_softc *);
314 static void bce_dump_stats_block(struct bce_softc *) __unused;
315 static void bce_dump_hw_state(struct bce_softc *);
316 static void bce_dump_txp_state(struct bce_softc *);
317 static void bce_dump_rxp_state(struct bce_softc *) __unused;
318 static void bce_dump_tpat_state(struct bce_softc *) __unused;
319 static void bce_freeze_controller(struct bce_softc *) __unused;
320 static void bce_unfreeze_controller(struct bce_softc *) __unused;
321 static void bce_breakpoint(struct bce_softc *);
322 #endif /* BCE_DEBUG */
325 /****************************************************************************/
326 /* BCE Register/Memory Access Routines */
327 /****************************************************************************/
328 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
329 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
330 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
331 static int bce_miibus_read_reg(device_t, int, int);
332 static int bce_miibus_write_reg(device_t, int, int, int);
333 static void bce_miibus_statchg(device_t);
336 /****************************************************************************/
337 /* BCE NVRAM Access Routines */
338 /****************************************************************************/
339 static int bce_acquire_nvram_lock(struct bce_softc *);
340 static int bce_release_nvram_lock(struct bce_softc *);
341 static void bce_enable_nvram_access(struct bce_softc *);
342 static void bce_disable_nvram_access(struct bce_softc *);
343 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
345 static int bce_init_nvram(struct bce_softc *);
346 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
347 static int bce_nvram_test(struct bce_softc *);
349 /****************************************************************************/
350 /* BCE DMA Allocate/Free Routines */
351 /****************************************************************************/
352 static int bce_dma_alloc(struct bce_softc *);
353 static void bce_dma_free(struct bce_softc *);
354 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
356 /****************************************************************************/
357 /* BCE Firmware Synchronization and Load */
358 /****************************************************************************/
359 static int bce_fw_sync(struct bce_softc *, uint32_t);
360 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
362 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
364 static void bce_init_rxp_cpu(struct bce_softc *);
365 static void bce_init_txp_cpu(struct bce_softc *);
366 static void bce_init_tpat_cpu(struct bce_softc *);
367 static void bce_init_cp_cpu(struct bce_softc *);
368 static void bce_init_com_cpu(struct bce_softc *);
369 static void bce_init_cpus(struct bce_softc *);
371 static void bce_stop(struct bce_softc *);
372 static int bce_reset(struct bce_softc *, uint32_t);
373 static int bce_chipinit(struct bce_softc *);
374 static int bce_blockinit(struct bce_softc *);
375 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
377 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
378 static void bce_probe_pci_caps(struct bce_softc *);
379 static void bce_print_adapter_info(struct bce_softc *);
380 static void bce_get_media(struct bce_softc *);
382 static void bce_init_tx_context(struct bce_softc *);
383 static int bce_init_tx_chain(struct bce_softc *);
384 static void bce_init_rx_context(struct bce_softc *);
385 static int bce_init_rx_chain(struct bce_softc *);
386 static void bce_free_rx_chain(struct bce_softc *);
387 static void bce_free_tx_chain(struct bce_softc *);
389 static int bce_encap(struct bce_softc *, struct mbuf **);
390 static void bce_start(struct ifnet *);
391 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
392 static void bce_watchdog(struct ifnet *);
393 static int bce_ifmedia_upd(struct ifnet *);
394 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
395 static void bce_init(void *);
396 static void bce_mgmt_init(struct bce_softc *);
398 static void bce_init_ctx(struct bce_softc *);
399 static void bce_get_mac_addr(struct bce_softc *);
400 static void bce_set_mac_addr(struct bce_softc *);
401 static void bce_phy_intr(struct bce_softc *);
402 static void bce_rx_intr(struct bce_softc *, int);
403 static void bce_tx_intr(struct bce_softc *);
404 static void bce_disable_intr(struct bce_softc *);
405 static void bce_enable_intr(struct bce_softc *, int);
407 #ifdef DEVICE_POLLING
408 static void bce_poll(struct ifnet *, enum poll_cmd, int);
410 static void bce_intr(void *);
411 static void bce_set_rx_mode(struct bce_softc *);
412 static void bce_stats_update(struct bce_softc *);
413 static void bce_tick(void *);
414 static void bce_tick_serialized(struct bce_softc *);
415 static void bce_pulse(void *);
416 static void bce_add_sysctls(struct bce_softc *);
418 static void bce_coal_change(struct bce_softc *);
419 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
420 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
421 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
422 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
423 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
424 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
425 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
426 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
427 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
428 uint32_t *, uint32_t);
432 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
433 * takes 1023 as the TX ticks limit. However, using 1023 will
434 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
435 * there is _no_ network activity on the NIC.
437 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
438 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
439 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
440 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
441 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
442 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
443 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
444 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
446 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
447 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
448 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
449 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
450 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
451 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
452 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
453 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
455 /****************************************************************************/
456 /* DragonFly device dispatch table. */
457 /****************************************************************************/
458 static device_method_t bce_methods[] = {
459 /* Device interface */
460 DEVMETHOD(device_probe, bce_probe),
461 DEVMETHOD(device_attach, bce_attach),
462 DEVMETHOD(device_detach, bce_detach),
463 DEVMETHOD(device_shutdown, bce_shutdown),
466 DEVMETHOD(bus_print_child, bus_generic_print_child),
467 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
470 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
471 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
472 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
477 static driver_t bce_driver = {
480 sizeof(struct bce_softc)
483 static devclass_t bce_devclass;
486 DECLARE_DUMMY_MODULE(if_bce);
487 MODULE_DEPEND(bce, miibus, 1, 1, 1);
488 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
489 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
492 /****************************************************************************/
493 /* Device probe function. */
495 /* Compares the device to the driver's list of supported devices and */
496 /* reports back to the OS whether this is the right driver for the device. */
499 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
500 /****************************************************************************/
502 bce_probe(device_t dev)
505 uint16_t vid, did, svid, sdid;
507 /* Get the data for the device to be probed. */
508 vid = pci_get_vendor(dev);
509 did = pci_get_device(dev);
510 svid = pci_get_subvendor(dev);
511 sdid = pci_get_subdevice(dev);
513 /* Look through the list of known devices for a match. */
514 for (t = bce_devs; t->bce_name != NULL; ++t) {
515 if (vid == t->bce_vid && did == t->bce_did &&
516 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
517 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
518 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
521 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
523 /* Print out the device identity. */
524 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
526 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
528 device_set_desc_copy(dev, descbuf);
529 kfree(descbuf, M_TEMP);
537 /****************************************************************************/
538 /* PCI Capabilities Probe Function. */
540 /* Walks the PCI capabiites list for the device to find what features are */
545 /****************************************************************************/
547 bce_print_adapter_info(struct bce_softc *sc)
549 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
551 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
552 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
555 if (sc->bce_flags & BCE_PCIE_FLAG) {
556 kprintf("Bus (PCIe x%d, ", sc->link_width);
557 switch (sc->link_speed) {
559 kprintf("2.5Gbps); ");
565 kprintf("Unknown link speed); ");
569 kprintf("Bus (PCI%s, %s, %dMHz); ",
570 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
571 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
575 /* Firmware version and device features. */
576 kprintf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
578 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
580 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
586 /****************************************************************************/
587 /* PCI Capabilities Probe Function. */
589 /* Walks the PCI capabiites list for the device to find what features are */
594 /****************************************************************************/
596 bce_probe_pci_caps(struct bce_softc *sc)
598 device_t dev = sc->bce_dev;
601 if (pci_is_pcix(dev))
602 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
604 ptr = pci_get_pciecap_ptr(dev);
606 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
608 sc->link_speed = link_status & 0xf;
609 sc->link_width = (link_status >> 4) & 0x3f;
610 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
611 sc->bce_flags |= BCE_PCIE_FLAG;
616 /****************************************************************************/
617 /* Device attach function. */
619 /* Allocates device resources, performs secondary chip identification, */
620 /* resets and initializes the hardware, and initializes driver instance */
624 /* 0 on success, positive value on failure. */
625 /****************************************************************************/
627 bce_attach(device_t dev)
629 struct bce_softc *sc = device_get_softc(dev);
630 struct ifnet *ifp = &sc->arpcom.ac_if;
638 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
640 pci_enable_busmaster(dev);
642 bce_probe_pci_caps(sc);
644 /* Allocate PCI memory resources. */
646 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
647 RF_ACTIVE | PCI_RF_DENSE);
648 if (sc->bce_res_mem == NULL) {
649 device_printf(dev, "PCI memory allocation failed\n");
652 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
653 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
655 /* Allocate PCI IRQ resources. */
657 count = pci_msi_count(dev);
658 if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
660 sc->bce_flags |= BCE_USING_MSI_FLAG;
664 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
665 RF_SHAREABLE | RF_ACTIVE);
666 if (sc->bce_res_irq == NULL) {
667 device_printf(dev, "PCI map interrupt failed\n");
673 * Configure byte swap and enable indirect register access.
674 * Rely on CPU to do target byte swapping on big endian systems.
675 * Access to registers outside of PCI configurtion space are not
676 * valid until this is done.
678 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
679 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
680 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
682 /* Save ASIC revsion info. */
683 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
685 /* Weed out any non-production controller revisions. */
686 switch(BCE_CHIP_ID(sc)) {
687 case BCE_CHIP_ID_5706_A0:
688 case BCE_CHIP_ID_5706_A1:
689 case BCE_CHIP_ID_5708_A0:
690 case BCE_CHIP_ID_5708_B0:
691 case BCE_CHIP_ID_5709_A0:
692 case BCE_CHIP_ID_5709_B0:
693 case BCE_CHIP_ID_5709_B1:
695 /* 5709C B2 seems to work fine */
696 case BCE_CHIP_ID_5709_B2:
698 device_printf(dev, "Unsupported chip id 0x%08x!\n",
705 * Find the base address for shared memory access.
706 * Newer versions of bootcode use a signature and offset
707 * while older versions use a fixed address.
709 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
710 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
711 BCE_SHM_HDR_SIGNATURE_SIG) {
712 /* Multi-port devices use different offsets in shared memory. */
713 sc->bce_shmem_base = REG_RD_IND(sc,
714 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
716 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
718 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
720 /* Fetch the bootcode revision. */
721 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
722 BCE_DEV_INFO_BC_REV);
724 /* Check if any management firmware is running. */
725 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
726 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
727 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
729 /* Get PCI bus information (speed and type). */
730 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
731 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
734 sc->bce_flags |= BCE_PCIX_FLAG;
736 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
737 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
739 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
740 sc->bus_speed_mhz = 133;
743 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
744 sc->bus_speed_mhz = 100;
747 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
748 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
749 sc->bus_speed_mhz = 66;
752 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
753 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
754 sc->bus_speed_mhz = 50;
757 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
758 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
759 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
760 sc->bus_speed_mhz = 33;
764 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
765 sc->bus_speed_mhz = 66;
767 sc->bus_speed_mhz = 33;
770 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
771 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
773 /* Reset the controller. */
774 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
778 /* Initialize the controller. */
779 rc = bce_chipinit(sc);
781 device_printf(dev, "Controller initialization failed!\n");
785 /* Perform NVRAM test. */
786 rc = bce_nvram_test(sc);
788 device_printf(dev, "NVRAM test failed!\n");
792 /* Fetch the permanent Ethernet MAC address. */
793 bce_get_mac_addr(sc);
796 * Trip points control how many BDs
797 * should be ready before generating an
798 * interrupt while ticks control how long
799 * a BD can sit in the chain before
800 * generating an interrupt. Set the default
801 * values for the RX and TX rings.
805 /* Force more frequent interrupts. */
806 sc->bce_tx_quick_cons_trip_int = 1;
807 sc->bce_tx_quick_cons_trip = 1;
808 sc->bce_tx_ticks_int = 0;
809 sc->bce_tx_ticks = 0;
811 sc->bce_rx_quick_cons_trip_int = 1;
812 sc->bce_rx_quick_cons_trip = 1;
813 sc->bce_rx_ticks_int = 0;
814 sc->bce_rx_ticks = 0;
816 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
817 sc->bce_tx_quick_cons_trip = bce_tx_bds;
818 sc->bce_tx_ticks_int = bce_tx_ticks_int;
819 sc->bce_tx_ticks = bce_tx_ticks;
821 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
822 sc->bce_rx_quick_cons_trip = bce_rx_bds;
823 sc->bce_rx_ticks_int = bce_rx_ticks_int;
824 sc->bce_rx_ticks = bce_rx_ticks;
827 /* Update statistics once every second. */
828 sc->bce_stats_ticks = 1000000 & 0xffff00;
830 /* Find the media type for the adapter. */
833 /* Allocate DMA memory resources. */
834 rc = bce_dma_alloc(sc);
836 device_printf(dev, "DMA resource allocation failed!\n");
840 /* Initialize the ifnet interface. */
842 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
843 ifp->if_ioctl = bce_ioctl;
844 ifp->if_start = bce_start;
845 ifp->if_init = bce_init;
846 ifp->if_watchdog = bce_watchdog;
847 #ifdef DEVICE_POLLING
848 ifp->if_poll = bce_poll;
850 ifp->if_mtu = ETHERMTU;
851 ifp->if_hwassist = BCE_IF_HWASSIST;
852 ifp->if_capabilities = BCE_IF_CAPABILITIES;
853 ifp->if_capenable = ifp->if_capabilities;
854 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
855 ifq_set_ready(&ifp->if_snd);
857 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
858 ifp->if_baudrate = IF_Gbps(2.5);
860 ifp->if_baudrate = IF_Gbps(1);
862 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
863 sc->mbuf_alloc_size = MCLBYTES;
865 /* Look for our PHY. */
866 rc = mii_phy_probe(dev, &sc->bce_miibus,
867 bce_ifmedia_upd, bce_ifmedia_sts);
869 device_printf(dev, "PHY probe failed!\n");
873 /* Attach to the Ethernet interface list. */
874 ether_ifattach(ifp, sc->eaddr, NULL);
876 callout_init(&sc->bce_tick_callout);
877 callout_init(&sc->bce_pulse_callout);
879 /* Hookup IRQ last. */
880 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
881 &sc->bce_intrhand, ifp->if_serializer);
883 device_printf(dev, "Failed to setup IRQ!\n");
888 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
889 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
891 /* Print some important debugging info. */
892 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
894 /* Add the supported sysctls to the kernel. */
898 * The chip reset earlier notified the bootcode that
899 * a driver is present. We now need to start our pulse
900 * routine so that the bootcode is reminded that we're
905 /* Get the firmware running so IPMI still works */
908 bce_print_adapter_info(sc);
917 /****************************************************************************/
918 /* Device detach function. */
920 /* Stops the controller, resets the controller, and releases resources. */
923 /* 0 on success, positive value on failure. */
924 /****************************************************************************/
926 bce_detach(device_t dev)
928 struct bce_softc *sc = device_get_softc(dev);
930 if (device_is_attached(dev)) {
931 struct ifnet *ifp = &sc->arpcom.ac_if;
934 /* Stop and reset the controller. */
935 lwkt_serialize_enter(ifp->if_serializer);
936 callout_stop(&sc->bce_pulse_callout);
938 if (sc->bce_flags & BCE_NO_WOL_FLAG)
939 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
941 msg = BCE_DRV_MSG_CODE_UNLOAD;
943 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
944 lwkt_serialize_exit(ifp->if_serializer);
949 /* If we have a child device on the MII bus remove it too. */
951 device_delete_child(dev, sc->bce_miibus);
952 bus_generic_detach(dev);
954 if (sc->bce_res_irq != NULL) {
955 bus_release_resource(dev, SYS_RES_IRQ,
956 sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
961 if (sc->bce_flags & BCE_USING_MSI_FLAG)
962 pci_release_msi(dev);
965 if (sc->bce_res_mem != NULL) {
966 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
972 if (sc->bce_sysctl_tree != NULL)
973 sysctl_ctx_free(&sc->bce_sysctl_ctx);
979 /****************************************************************************/
980 /* Device shutdown function. */
982 /* Stops and resets the controller. */
986 /****************************************************************************/
988 bce_shutdown(device_t dev)
990 struct bce_softc *sc = device_get_softc(dev);
991 struct ifnet *ifp = &sc->arpcom.ac_if;
994 lwkt_serialize_enter(ifp->if_serializer);
996 if (sc->bce_flags & BCE_NO_WOL_FLAG)
997 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
999 msg = BCE_DRV_MSG_CODE_UNLOAD;
1001 lwkt_serialize_exit(ifp->if_serializer);
1005 /****************************************************************************/
1006 /* Indirect register read. */
1008 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1009 /* configuration space. Using this mechanism avoids issues with posted */
1010 /* reads but is much slower than memory-mapped I/O. */
1013 /* The value of the register. */
1014 /****************************************************************************/
1016 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1018 device_t dev = sc->bce_dev;
1020 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1024 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1025 DBPRINT(sc, BCE_EXCESSIVE,
1026 "%s(); offset = 0x%08X, val = 0x%08X\n",
1027 __func__, offset, val);
1031 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1036 /****************************************************************************/
1037 /* Indirect register write. */
1039 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1040 /* configuration space. Using this mechanism avoids issues with posted */
1041 /* writes but is muchh slower than memory-mapped I/O. */
1045 /****************************************************************************/
1047 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1049 device_t dev = sc->bce_dev;
1051 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1052 __func__, offset, val);
1054 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1055 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1059 /****************************************************************************/
1060 /* Context memory write. */
1062 /* The NetXtreme II controller uses context memory to track connection */
1063 /* information for L2 and higher network protocols. */
1067 /****************************************************************************/
1069 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1072 uint32_t idx, offset = ctx_offset + cid_addr;
1073 uint32_t val, retry_cnt = 5;
1075 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1076 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1077 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1078 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1080 for (idx = 0; idx < retry_cnt; idx++) {
1081 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1082 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1087 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1088 device_printf(sc->bce_dev,
1089 "Unable to write CTX memory: "
1090 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1091 cid_addr, ctx_offset);
1094 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1095 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1100 /****************************************************************************/
1101 /* PHY register read. */
1103 /* Implements register reads on the MII bus. */
1106 /* The value of the register. */
1107 /****************************************************************************/
1109 bce_miibus_read_reg(device_t dev, int phy, int reg)
1111 struct bce_softc *sc = device_get_softc(dev);
1115 /* Make sure we are accessing the correct PHY address. */
1116 if (phy != sc->bce_phy_addr) {
1117 DBPRINT(sc, BCE_VERBOSE,
1118 "Invalid PHY address %d for PHY read!\n", phy);
1122 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1123 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1124 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1126 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1127 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1132 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1133 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1134 BCE_EMAC_MDIO_COMM_START_BUSY;
1135 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1137 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1140 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1141 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1144 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1145 val &= BCE_EMAC_MDIO_COMM_DATA;
1150 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1151 if_printf(&sc->arpcom.ac_if,
1152 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1156 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1159 DBPRINT(sc, BCE_EXCESSIVE,
1160 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1161 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1163 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1164 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1165 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1167 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1168 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1172 return (val & 0xffff);
1176 /****************************************************************************/
1177 /* PHY register write. */
1179 /* Implements register writes on the MII bus. */
1182 /* The value of the register. */
1183 /****************************************************************************/
1185 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1187 struct bce_softc *sc = device_get_softc(dev);
1191 /* Make sure we are accessing the correct PHY address. */
1192 if (phy != sc->bce_phy_addr) {
1193 DBPRINT(sc, BCE_WARN,
1194 "Invalid PHY address %d for PHY write!\n", phy);
1198 DBPRINT(sc, BCE_EXCESSIVE,
1199 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1200 __func__, phy, (uint16_t)(reg & 0xffff),
1201 (uint16_t)(val & 0xffff));
1203 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1204 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1205 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1207 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1208 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1213 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1214 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1215 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1216 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1218 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1221 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1222 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1228 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1229 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1231 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1232 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1233 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1235 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1236 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1244 /****************************************************************************/
1245 /* MII bus status change. */
1247 /* Called by the MII bus driver when the PHY establishes link to set the */
1248 /* MAC interface registers. */
1252 /****************************************************************************/
1254 bce_miibus_statchg(device_t dev)
1256 struct bce_softc *sc = device_get_softc(dev);
1257 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1259 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1260 mii->mii_media_active);
1263 /* Decode the interface media flags. */
1264 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1265 switch(IFM_TYPE(mii->mii_media_active)) {
1267 kprintf("Ethernet )");
1270 kprintf("Unknown )");
1274 kprintf(" Media Options: ( ");
1275 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1277 kprintf("Autoselect )");
1280 kprintf("Manual )");
1286 kprintf("10Base-T )");
1289 kprintf("100Base-TX )");
1292 kprintf("1000Base-SX )");
1295 kprintf("1000Base-T )");
1302 kprintf(" Global Options: (");
1303 if (mii->mii_media_active & IFM_FDX)
1304 kprintf(" FullDuplex");
1305 if (mii->mii_media_active & IFM_HDX)
1306 kprintf(" HalfDuplex");
1307 if (mii->mii_media_active & IFM_LOOP)
1308 kprintf(" Loopback");
1309 if (mii->mii_media_active & IFM_FLAG0)
1311 if (mii->mii_media_active & IFM_FLAG1)
1313 if (mii->mii_media_active & IFM_FLAG2)
1318 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1321 * Set MII or GMII interface based on the speed negotiated
1324 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1325 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1326 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1327 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1329 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1330 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1334 * Set half or full duplex based on the duplicity negotiated
1337 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1338 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1339 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1341 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1342 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1347 /****************************************************************************/
1348 /* Acquire NVRAM lock. */
1350 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1351 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1352 /* for use by the driver. */
1355 /* 0 on success, positive value on failure. */
1356 /****************************************************************************/
1358 bce_acquire_nvram_lock(struct bce_softc *sc)
1363 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1365 /* Request access to the flash interface. */
1366 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1367 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1368 val = REG_RD(sc, BCE_NVM_SW_ARB);
1369 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1375 if (j >= NVRAM_TIMEOUT_COUNT) {
1376 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1383 /****************************************************************************/
1384 /* Release NVRAM lock. */
1386 /* When the caller is finished accessing NVRAM the lock must be released. */
1387 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1388 /* for use by the driver. */
1391 /* 0 on success, positive value on failure. */
1392 /****************************************************************************/
1394 bce_release_nvram_lock(struct bce_softc *sc)
1399 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1402 * Relinquish nvram interface.
1404 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1406 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1407 val = REG_RD(sc, BCE_NVM_SW_ARB);
1408 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1414 if (j >= NVRAM_TIMEOUT_COUNT) {
1415 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1422 /****************************************************************************/
1423 /* Enable NVRAM access. */
1425 /* Before accessing NVRAM for read or write operations the caller must */
1426 /* enabled NVRAM access. */
1430 /****************************************************************************/
1432 bce_enable_nvram_access(struct bce_softc *sc)
1436 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1438 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1439 /* Enable both bits, even on read. */
1440 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1441 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1445 /****************************************************************************/
1446 /* Disable NVRAM access. */
1448 /* When the caller is finished accessing NVRAM access must be disabled. */
1452 /****************************************************************************/
1454 bce_disable_nvram_access(struct bce_softc *sc)
1458 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1460 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1462 /* Disable both bits, even after read. */
1463 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1464 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1468 /****************************************************************************/
1469 /* Read a dword (32 bits) from NVRAM. */
1471 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1472 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1475 /* 0 on success and the 32 bit value read, positive value on failure. */
1476 /****************************************************************************/
1478 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1484 /* Build the command word. */
1485 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1487 /* Calculate the offset for buffered flash. */
1488 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1489 offset = ((offset / sc->bce_flash_info->page_size) <<
1490 sc->bce_flash_info->page_bits) +
1491 (offset % sc->bce_flash_info->page_size);
1495 * Clear the DONE bit separately, set the address to read,
1496 * and issue the read.
1498 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1499 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1500 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1502 /* Wait for completion. */
1503 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1508 val = REG_RD(sc, BCE_NVM_COMMAND);
1509 if (val & BCE_NVM_COMMAND_DONE) {
1510 val = REG_RD(sc, BCE_NVM_READ);
1513 memcpy(ret_val, &val, 4);
1518 /* Check for errors. */
1519 if (i >= NVRAM_TIMEOUT_COUNT) {
1520 if_printf(&sc->arpcom.ac_if,
1521 "Timeout error reading NVRAM at offset 0x%08X!\n",
1529 /****************************************************************************/
1530 /* Initialize NVRAM access. */
1532 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1533 /* access that device. */
1536 /* 0 on success, positive value on failure. */
1537 /****************************************************************************/
1539 bce_init_nvram(struct bce_softc *sc)
1542 int j, entry_count, rc = 0;
1543 const struct flash_spec *flash;
1545 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1547 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1548 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1549 sc->bce_flash_info = &flash_5709;
1550 goto bce_init_nvram_get_flash_size;
1553 /* Determine the selected interface. */
1554 val = REG_RD(sc, BCE_NVM_CFG1);
1556 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1559 * Flash reconfiguration is required to support additional
1560 * NVRAM devices not directly supported in hardware.
1561 * Check if the flash interface was reconfigured
1565 if (val & 0x40000000) {
1566 /* Flash interface reconfigured by bootcode. */
1568 DBPRINT(sc, BCE_INFO_LOAD,
1569 "%s(): Flash WAS reconfigured.\n", __func__);
1571 for (j = 0, flash = flash_table; j < entry_count;
1573 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1574 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1575 sc->bce_flash_info = flash;
1580 /* Flash interface not yet reconfigured. */
1583 DBPRINT(sc, BCE_INFO_LOAD,
1584 "%s(): Flash was NOT reconfigured.\n", __func__);
1586 if (val & (1 << 23))
1587 mask = FLASH_BACKUP_STRAP_MASK;
1589 mask = FLASH_STRAP_MASK;
1591 /* Look for the matching NVRAM device configuration data. */
1592 for (j = 0, flash = flash_table; j < entry_count;
1594 /* Check if the device matches any of the known devices. */
1595 if ((val & mask) == (flash->strapping & mask)) {
1596 /* Found a device match. */
1597 sc->bce_flash_info = flash;
1599 /* Request access to the flash interface. */
1600 rc = bce_acquire_nvram_lock(sc);
1604 /* Reconfigure the flash interface. */
1605 bce_enable_nvram_access(sc);
1606 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1607 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1608 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1609 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1610 bce_disable_nvram_access(sc);
1611 bce_release_nvram_lock(sc);
1617 /* Check if a matching device was found. */
1618 if (j == entry_count) {
1619 sc->bce_flash_info = NULL;
1620 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1624 bce_init_nvram_get_flash_size:
1625 /* Write the flash config data to the shared memory interface. */
1626 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1627 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1629 sc->bce_flash_size = val;
1631 sc->bce_flash_size = sc->bce_flash_info->total_size;
1633 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1634 __func__, sc->bce_flash_info->total_size);
1636 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1642 /****************************************************************************/
1643 /* Read an arbitrary range of data from NVRAM. */
1645 /* Prepares the NVRAM interface for access and reads the requested data */
1646 /* into the supplied buffer. */
1649 /* 0 on success and the data read, positive value on failure. */
1650 /****************************************************************************/
1652 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1655 uint32_t cmd_flags, offset32, len32, extra;
1661 /* Request access to the flash interface. */
1662 rc = bce_acquire_nvram_lock(sc);
1666 /* Enable access to flash interface */
1667 bce_enable_nvram_access(sc);
1675 /* XXX should we release nvram lock if read_dword() fails? */
1681 pre_len = 4 - (offset & 3);
1683 if (pre_len >= len32) {
1685 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1687 cmd_flags = BCE_NVM_COMMAND_FIRST;
1690 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1694 memcpy(ret_buf, buf + (offset & 3), pre_len);
1702 extra = 4 - (len32 & 3);
1703 len32 = (len32 + 4) & ~3;
1710 cmd_flags = BCE_NVM_COMMAND_LAST;
1712 cmd_flags = BCE_NVM_COMMAND_FIRST |
1713 BCE_NVM_COMMAND_LAST;
1715 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1717 memcpy(ret_buf, buf, 4 - extra);
1718 } else if (len32 > 0) {
1721 /* Read the first word. */
1725 cmd_flags = BCE_NVM_COMMAND_FIRST;
1727 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1729 /* Advance to the next dword. */
1734 while (len32 > 4 && rc == 0) {
1735 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1737 /* Advance to the next dword. */
1744 goto bce_nvram_read_locked_exit;
1746 cmd_flags = BCE_NVM_COMMAND_LAST;
1747 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1749 memcpy(ret_buf, buf, 4 - extra);
1752 bce_nvram_read_locked_exit:
1753 /* Disable access to flash interface and release the lock. */
1754 bce_disable_nvram_access(sc);
1755 bce_release_nvram_lock(sc);
1761 /****************************************************************************/
1762 /* Verifies that NVRAM is accessible and contains valid data. */
1764 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1768 /* 0 on success, positive value on failure. */
1769 /****************************************************************************/
1771 bce_nvram_test(struct bce_softc *sc)
1773 uint32_t buf[BCE_NVRAM_SIZE / 4];
1774 uint32_t magic, csum;
1775 uint8_t *data = (uint8_t *)buf;
1779 * Check that the device NVRAM is valid by reading
1780 * the magic value at offset 0.
1782 rc = bce_nvram_read(sc, 0, data, 4);
1786 magic = be32toh(buf[0]);
1787 if (magic != BCE_NVRAM_MAGIC) {
1788 if_printf(&sc->arpcom.ac_if,
1789 "Invalid NVRAM magic value! Expected: 0x%08X, "
1790 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1795 * Verify that the device NVRAM includes valid
1796 * configuration data.
1798 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1802 csum = ether_crc32_le(data, 0x100);
1803 if (csum != BCE_CRC32_RESIDUAL) {
1804 if_printf(&sc->arpcom.ac_if,
1805 "Invalid Manufacturing Information NVRAM CRC! "
1806 "Expected: 0x%08X, Found: 0x%08X\n",
1807 BCE_CRC32_RESIDUAL, csum);
1811 csum = ether_crc32_le(data + 0x100, 0x100);
1812 if (csum != BCE_CRC32_RESIDUAL) {
1813 if_printf(&sc->arpcom.ac_if,
1814 "Invalid Feature Configuration Information "
1815 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1816 BCE_CRC32_RESIDUAL, csum);
1823 /****************************************************************************/
1824 /* Identifies the current media type of the controller and sets the PHY */
1829 /****************************************************************************/
1831 bce_get_media(struct bce_softc *sc)
1835 sc->bce_phy_addr = 1;
1837 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1838 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1839 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1840 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1844 * The BCM5709S is software configurable
1845 * for Copper or SerDes operation.
1847 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1849 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1850 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1854 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1855 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1858 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1861 if (pci_get_function(sc->bce_dev) == 0) {
1866 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1874 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1878 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1879 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1882 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1883 sc->bce_flags |= BCE_NO_WOL_FLAG;
1884 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1885 sc->bce_phy_addr = 2;
1886 val = REG_RD_IND(sc, sc->bce_shmem_base +
1887 BCE_SHARED_HW_CFG_CONFIG);
1888 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1889 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1891 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1892 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1893 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1898 /****************************************************************************/
1899 /* Free any DMA memory owned by the driver. */
1901 /* Scans through each data structre that requires DMA memory and frees */
1902 /* the memory if allocated. */
1906 /****************************************************************************/
1908 bce_dma_free(struct bce_softc *sc)
1912 /* Destroy the status block. */
1913 if (sc->status_tag != NULL) {
1914 if (sc->status_block != NULL) {
1915 bus_dmamap_unload(sc->status_tag, sc->status_map);
1916 bus_dmamem_free(sc->status_tag, sc->status_block,
1919 bus_dma_tag_destroy(sc->status_tag);
1923 /* Destroy the statistics block. */
1924 if (sc->stats_tag != NULL) {
1925 if (sc->stats_block != NULL) {
1926 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
1927 bus_dmamem_free(sc->stats_tag, sc->stats_block,
1930 bus_dma_tag_destroy(sc->stats_tag);
1933 /* Destroy the CTX DMA stuffs. */
1934 if (sc->ctx_tag != NULL) {
1935 for (i = 0; i < sc->ctx_pages; i++) {
1936 if (sc->ctx_block[i] != NULL) {
1937 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
1938 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
1942 bus_dma_tag_destroy(sc->ctx_tag);
1945 /* Destroy the TX buffer descriptor DMA stuffs. */
1946 if (sc->tx_bd_chain_tag != NULL) {
1947 for (i = 0; i < TX_PAGES; i++) {
1948 if (sc->tx_bd_chain[i] != NULL) {
1949 bus_dmamap_unload(sc->tx_bd_chain_tag,
1950 sc->tx_bd_chain_map[i]);
1951 bus_dmamem_free(sc->tx_bd_chain_tag,
1953 sc->tx_bd_chain_map[i]);
1956 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
1959 /* Destroy the RX buffer descriptor DMA stuffs. */
1960 if (sc->rx_bd_chain_tag != NULL) {
1961 for (i = 0; i < RX_PAGES; i++) {
1962 if (sc->rx_bd_chain[i] != NULL) {
1963 bus_dmamap_unload(sc->rx_bd_chain_tag,
1964 sc->rx_bd_chain_map[i]);
1965 bus_dmamem_free(sc->rx_bd_chain_tag,
1967 sc->rx_bd_chain_map[i]);
1970 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
1973 /* Destroy the TX mbuf DMA stuffs. */
1974 if (sc->tx_mbuf_tag != NULL) {
1975 for (i = 0; i < TOTAL_TX_BD; i++) {
1976 /* Must have been unloaded in bce_stop() */
1977 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
1978 bus_dmamap_destroy(sc->tx_mbuf_tag,
1979 sc->tx_mbuf_map[i]);
1981 bus_dma_tag_destroy(sc->tx_mbuf_tag);
1984 /* Destroy the RX mbuf DMA stuffs. */
1985 if (sc->rx_mbuf_tag != NULL) {
1986 for (i = 0; i < TOTAL_RX_BD; i++) {
1987 /* Must have been unloaded in bce_stop() */
1988 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
1989 bus_dmamap_destroy(sc->rx_mbuf_tag,
1990 sc->rx_mbuf_map[i]);
1992 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
1993 bus_dma_tag_destroy(sc->rx_mbuf_tag);
1996 /* Destroy the parent tag */
1997 if (sc->parent_tag != NULL)
1998 bus_dma_tag_destroy(sc->parent_tag);
2002 /****************************************************************************/
2003 /* Get DMA memory from the OS. */
2005 /* Validates that the OS has provided DMA buffers in response to a */
2006 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2007 /* When the callback is used the OS will return 0 for the mapping function */
2008 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2009 /* failures back to the caller. */
2013 /****************************************************************************/
2015 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2017 bus_addr_t *busaddr = arg;
2020 * Simulate a mapping failure.
2023 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2024 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2025 __FILE__, __LINE__);
2028 /* Check for an error and signal the caller that an error occurred. */
2032 KASSERT(nseg == 1, ("only one segment is allowed\n"));
2033 *busaddr = segs->ds_addr;
2037 /****************************************************************************/
2038 /* Allocate any DMA memory needed by the driver. */
2040 /* Allocates DMA memory needed for the various global structures needed by */
2043 /* Memory alignment requirements: */
2044 /* -----------------+----------+----------+----------+----------+ */
2045 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2046 /* -----------------+----------+----------+----------+----------+ */
2047 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2048 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2049 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2050 /* PG Buffers | none | none | none | none | */
2051 /* TX Buffers | none | none | none | none | */
2052 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2053 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2054 /* -----------------+----------+----------+----------+----------+ */
2056 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2059 /* 0 for success, positive value for failure. */
2060 /****************************************************************************/
2062 bce_dma_alloc(struct bce_softc *sc)
2064 struct ifnet *ifp = &sc->arpcom.ac_if;
2066 bus_addr_t busaddr, max_busaddr;
2067 bus_size_t status_align, stats_align;
2070 * The embedded PCIe to PCI-X bridge (EPB)
2071 * in the 5708 cannot address memory above
2072 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2074 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2075 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2077 max_busaddr = BUS_SPACE_MAXADDR;
2080 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2082 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2083 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2084 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2085 if (sc->ctx_pages == 0)
2087 if (sc->ctx_pages > BCE_CTX_PAGES) {
2088 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2100 * Allocate the parent bus DMA tag appropriate for PCI.
2102 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2103 max_busaddr, BUS_SPACE_MAXADDR,
2105 BUS_SPACE_MAXSIZE_32BIT, 0,
2106 BUS_SPACE_MAXSIZE_32BIT,
2107 0, &sc->parent_tag);
2109 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2114 * Allocate status block.
2116 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2117 status_align, BCE_STATUS_BLK_SZ,
2118 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2119 &sc->status_tag, &sc->status_map,
2120 &sc->status_block_paddr);
2121 if (sc->status_block == NULL) {
2122 if_printf(ifp, "Could not allocate status block!\n");
2127 * Allocate statistics block.
2129 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2130 stats_align, BCE_STATS_BLK_SZ,
2131 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2132 &sc->stats_tag, &sc->stats_map,
2133 &sc->stats_block_paddr);
2134 if (sc->stats_block == NULL) {
2135 if_printf(ifp, "Could not allocate statistics block!\n");
2140 * Allocate context block, if needed
2142 if (sc->ctx_pages != 0) {
2143 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2144 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2146 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2149 if_printf(ifp, "Could not allocate "
2150 "context block DMA tag!\n");
2154 for (i = 0; i < sc->ctx_pages; i++) {
2155 rc = bus_dmamem_alloc(sc->ctx_tag,
2156 (void **)&sc->ctx_block[i],
2157 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2161 if_printf(ifp, "Could not allocate %dth context "
2162 "DMA memory!\n", i);
2166 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2167 sc->ctx_block[i], BCM_PAGE_SIZE,
2168 bce_dma_map_addr, &busaddr,
2171 if (rc == EINPROGRESS) {
2172 panic("%s coherent memory loading "
2173 "is still in progress!", ifp->if_xname);
2175 if_printf(ifp, "Could not map %dth context "
2176 "DMA memory!\n", i);
2177 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2179 sc->ctx_block[i] = NULL;
2182 sc->ctx_paddr[i] = busaddr;
2187 * Create a DMA tag for the TX buffer descriptor chain,
2188 * allocate and clear the memory, and fetch the
2189 * physical address of the block.
2191 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2192 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2194 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2195 0, &sc->tx_bd_chain_tag);
2197 if_printf(ifp, "Could not allocate "
2198 "TX descriptor chain DMA tag!\n");
2202 for (i = 0; i < TX_PAGES; i++) {
2203 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2204 (void **)&sc->tx_bd_chain[i],
2205 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2207 &sc->tx_bd_chain_map[i]);
2209 if_printf(ifp, "Could not allocate %dth TX descriptor "
2210 "chain DMA memory!\n", i);
2214 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2215 sc->tx_bd_chain_map[i],
2216 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2217 bce_dma_map_addr, &busaddr,
2220 if (rc == EINPROGRESS) {
2221 panic("%s coherent memory loading "
2222 "is still in progress!", ifp->if_xname);
2224 if_printf(ifp, "Could not map %dth TX descriptor "
2225 "chain DMA memory!\n", i);
2226 bus_dmamem_free(sc->tx_bd_chain_tag,
2228 sc->tx_bd_chain_map[i]);
2229 sc->tx_bd_chain[i] = NULL;
2233 sc->tx_bd_chain_paddr[i] = busaddr;
2234 /* DRC - Fix for 64 bit systems. */
2235 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2236 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2239 /* Create a DMA tag for TX mbufs. */
2240 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2243 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2244 BCE_MAX_SEGMENTS, MCLBYTES,
2245 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2249 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2253 /* Create DMA maps for the TX mbufs clusters. */
2254 for (i = 0; i < TOTAL_TX_BD; i++) {
2255 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2256 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2257 &sc->tx_mbuf_map[i]);
2259 for (j = 0; j < i; ++j) {
2260 bus_dmamap_destroy(sc->tx_mbuf_tag,
2261 sc->tx_mbuf_map[i]);
2263 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2264 sc->tx_mbuf_tag = NULL;
2266 if_printf(ifp, "Unable to create "
2267 "%dth TX mbuf DMA map!\n", i);
2273 * Create a DMA tag for the RX buffer descriptor chain,
2274 * allocate and clear the memory, and fetch the physical
2275 * address of the blocks.
2277 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2278 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2280 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2281 0, &sc->rx_bd_chain_tag);
2283 if_printf(ifp, "Could not allocate "
2284 "RX descriptor chain DMA tag!\n");
2288 for (i = 0; i < RX_PAGES; i++) {
2289 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2290 (void **)&sc->rx_bd_chain[i],
2291 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2293 &sc->rx_bd_chain_map[i]);
2295 if_printf(ifp, "Could not allocate %dth RX descriptor "
2296 "chain DMA memory!\n", i);
2300 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2301 sc->rx_bd_chain_map[i],
2302 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2303 bce_dma_map_addr, &busaddr,
2306 if (rc == EINPROGRESS) {
2307 panic("%s coherent memory loading "
2308 "is still in progress!", ifp->if_xname);
2310 if_printf(ifp, "Could not map %dth RX descriptor "
2311 "chain DMA memory!\n", i);
2312 bus_dmamem_free(sc->rx_bd_chain_tag,
2314 sc->rx_bd_chain_map[i]);
2315 sc->rx_bd_chain[i] = NULL;
2319 sc->rx_bd_chain_paddr[i] = busaddr;
2320 /* DRC - Fix for 64 bit systems. */
2321 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2322 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2325 /* Create a DMA tag for RX mbufs. */
2326 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2327 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2329 MCLBYTES, 1, MCLBYTES,
2330 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2334 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2338 /* Create tmp DMA map for RX mbuf clusters. */
2339 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2340 &sc->rx_mbuf_tmpmap);
2342 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2343 sc->rx_mbuf_tag = NULL;
2345 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2349 /* Create DMA maps for the RX mbuf clusters. */
2350 for (i = 0; i < TOTAL_RX_BD; i++) {
2351 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2352 &sc->rx_mbuf_map[i]);
2354 for (j = 0; j < i; ++j) {
2355 bus_dmamap_destroy(sc->rx_mbuf_tag,
2356 sc->rx_mbuf_map[j]);
2358 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2359 sc->rx_mbuf_tag = NULL;
2361 if_printf(ifp, "Unable to create "
2362 "%dth RX mbuf DMA map!\n", i);
2370 /****************************************************************************/
2371 /* Firmware synchronization. */
2373 /* Before performing certain events such as a chip reset, synchronize with */
2374 /* the firmware first. */
2377 /* 0 for success, positive value for failure. */
2378 /****************************************************************************/
2380 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2385 /* Don't waste any time if we've timed out before. */
2386 if (sc->bce_fw_timed_out)
2389 /* Increment the message sequence number. */
2390 sc->bce_fw_wr_seq++;
2391 msg_data |= sc->bce_fw_wr_seq;
2393 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2395 /* Send the message to the bootcode driver mailbox. */
2396 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2398 /* Wait for the bootcode to acknowledge the message. */
2399 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2400 /* Check for a response in the bootcode firmware mailbox. */
2401 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2402 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2407 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2408 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2409 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2410 if_printf(&sc->arpcom.ac_if,
2411 "Firmware synchronization timeout! "
2412 "msg_data = 0x%08X\n", msg_data);
2414 msg_data &= ~BCE_DRV_MSG_CODE;
2415 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2417 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2419 sc->bce_fw_timed_out = 1;
2426 /****************************************************************************/
2427 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2431 /****************************************************************************/
2433 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2434 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2439 for (i = 0; i < rv2p_code_len; i += 8) {
2440 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2442 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2445 if (rv2p_proc == RV2P_PROC1) {
2446 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2447 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2449 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2450 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2454 /* Reset the processor, un-stall is done later. */
2455 if (rv2p_proc == RV2P_PROC1)
2456 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2458 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2462 /****************************************************************************/
2463 /* Load RISC processor firmware. */
2465 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2466 /* associated with a particular processor. */
2470 /****************************************************************************/
2472 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2475 uint32_t offset, val;
2479 val = REG_RD_IND(sc, cpu_reg->mode);
2480 val |= cpu_reg->mode_value_halt;
2481 REG_WR_IND(sc, cpu_reg->mode, val);
2482 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2484 /* Load the Text area. */
2485 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2487 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2488 REG_WR_IND(sc, offset, fw->text[j]);
2491 /* Load the Data area. */
2492 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2494 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2495 REG_WR_IND(sc, offset, fw->data[j]);
2498 /* Load the SBSS area. */
2499 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2501 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2502 REG_WR_IND(sc, offset, fw->sbss[j]);
2505 /* Load the BSS area. */
2506 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2508 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2509 REG_WR_IND(sc, offset, fw->bss[j]);
2512 /* Load the Read-Only area. */
2513 offset = cpu_reg->spad_base +
2514 (fw->rodata_addr - cpu_reg->mips_view_base);
2516 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2517 REG_WR_IND(sc, offset, fw->rodata[j]);
2520 /* Clear the pre-fetch instruction. */
2521 REG_WR_IND(sc, cpu_reg->inst, 0);
2522 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2524 /* Start the CPU. */
2525 val = REG_RD_IND(sc, cpu_reg->mode);
2526 val &= ~cpu_reg->mode_value_halt;
2527 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2528 REG_WR_IND(sc, cpu_reg->mode, val);
2532 /****************************************************************************/
2533 /* Initialize the RX CPU. */
2537 /****************************************************************************/
2539 bce_init_rxp_cpu(struct bce_softc *sc)
2541 struct cpu_reg cpu_reg;
2544 cpu_reg.mode = BCE_RXP_CPU_MODE;
2545 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2546 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2547 cpu_reg.state = BCE_RXP_CPU_STATE;
2548 cpu_reg.state_value_clear = 0xffffff;
2549 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2550 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2551 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2552 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2553 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2554 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2555 cpu_reg.mips_view_base = 0x8000000;
2557 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2558 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2559 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2560 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2561 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2562 fw.start_addr = bce_RXP_b09FwStartAddr;
2564 fw.text_addr = bce_RXP_b09FwTextAddr;
2565 fw.text_len = bce_RXP_b09FwTextLen;
2567 fw.text = bce_RXP_b09FwText;
2569 fw.data_addr = bce_RXP_b09FwDataAddr;
2570 fw.data_len = bce_RXP_b09FwDataLen;
2572 fw.data = bce_RXP_b09FwData;
2574 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2575 fw.sbss_len = bce_RXP_b09FwSbssLen;
2577 fw.sbss = bce_RXP_b09FwSbss;
2579 fw.bss_addr = bce_RXP_b09FwBssAddr;
2580 fw.bss_len = bce_RXP_b09FwBssLen;
2582 fw.bss = bce_RXP_b09FwBss;
2584 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2585 fw.rodata_len = bce_RXP_b09FwRodataLen;
2586 fw.rodata_index = 0;
2587 fw.rodata = bce_RXP_b09FwRodata;
2589 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2590 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2591 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2592 fw.start_addr = bce_RXP_b06FwStartAddr;
2594 fw.text_addr = bce_RXP_b06FwTextAddr;
2595 fw.text_len = bce_RXP_b06FwTextLen;
2597 fw.text = bce_RXP_b06FwText;
2599 fw.data_addr = bce_RXP_b06FwDataAddr;
2600 fw.data_len = bce_RXP_b06FwDataLen;
2602 fw.data = bce_RXP_b06FwData;
2604 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2605 fw.sbss_len = bce_RXP_b06FwSbssLen;
2607 fw.sbss = bce_RXP_b06FwSbss;
2609 fw.bss_addr = bce_RXP_b06FwBssAddr;
2610 fw.bss_len = bce_RXP_b06FwBssLen;
2612 fw.bss = bce_RXP_b06FwBss;
2614 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2615 fw.rodata_len = bce_RXP_b06FwRodataLen;
2616 fw.rodata_index = 0;
2617 fw.rodata = bce_RXP_b06FwRodata;
2620 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2621 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2625 /****************************************************************************/
2626 /* Initialize the TX CPU. */
2630 /****************************************************************************/
2632 bce_init_txp_cpu(struct bce_softc *sc)
2634 struct cpu_reg cpu_reg;
2637 cpu_reg.mode = BCE_TXP_CPU_MODE;
2638 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2639 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2640 cpu_reg.state = BCE_TXP_CPU_STATE;
2641 cpu_reg.state_value_clear = 0xffffff;
2642 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2643 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2644 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2645 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2646 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2647 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2648 cpu_reg.mips_view_base = 0x8000000;
2650 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2651 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2652 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2653 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2654 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2655 fw.start_addr = bce_TXP_b09FwStartAddr;
2657 fw.text_addr = bce_TXP_b09FwTextAddr;
2658 fw.text_len = bce_TXP_b09FwTextLen;
2660 fw.text = bce_TXP_b09FwText;
2662 fw.data_addr = bce_TXP_b09FwDataAddr;
2663 fw.data_len = bce_TXP_b09FwDataLen;
2665 fw.data = bce_TXP_b09FwData;
2667 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2668 fw.sbss_len = bce_TXP_b09FwSbssLen;
2670 fw.sbss = bce_TXP_b09FwSbss;
2672 fw.bss_addr = bce_TXP_b09FwBssAddr;
2673 fw.bss_len = bce_TXP_b09FwBssLen;
2675 fw.bss = bce_TXP_b09FwBss;
2677 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2678 fw.rodata_len = bce_TXP_b09FwRodataLen;
2679 fw.rodata_index = 0;
2680 fw.rodata = bce_TXP_b09FwRodata;
2682 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2683 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2684 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2685 fw.start_addr = bce_TXP_b06FwStartAddr;
2687 fw.text_addr = bce_TXP_b06FwTextAddr;
2688 fw.text_len = bce_TXP_b06FwTextLen;
2690 fw.text = bce_TXP_b06FwText;
2692 fw.data_addr = bce_TXP_b06FwDataAddr;
2693 fw.data_len = bce_TXP_b06FwDataLen;
2695 fw.data = bce_TXP_b06FwData;
2697 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2698 fw.sbss_len = bce_TXP_b06FwSbssLen;
2700 fw.sbss = bce_TXP_b06FwSbss;
2702 fw.bss_addr = bce_TXP_b06FwBssAddr;
2703 fw.bss_len = bce_TXP_b06FwBssLen;
2705 fw.bss = bce_TXP_b06FwBss;
2707 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2708 fw.rodata_len = bce_TXP_b06FwRodataLen;
2709 fw.rodata_index = 0;
2710 fw.rodata = bce_TXP_b06FwRodata;
2713 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2714 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2718 /****************************************************************************/
2719 /* Initialize the TPAT CPU. */
2723 /****************************************************************************/
2725 bce_init_tpat_cpu(struct bce_softc *sc)
2727 struct cpu_reg cpu_reg;
2730 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2731 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2732 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2733 cpu_reg.state = BCE_TPAT_CPU_STATE;
2734 cpu_reg.state_value_clear = 0xffffff;
2735 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2736 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2737 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2738 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2739 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2740 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2741 cpu_reg.mips_view_base = 0x8000000;
2743 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2744 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2745 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2746 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2747 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2748 fw.start_addr = bce_TPAT_b09FwStartAddr;
2750 fw.text_addr = bce_TPAT_b09FwTextAddr;
2751 fw.text_len = bce_TPAT_b09FwTextLen;
2753 fw.text = bce_TPAT_b09FwText;
2755 fw.data_addr = bce_TPAT_b09FwDataAddr;
2756 fw.data_len = bce_TPAT_b09FwDataLen;
2758 fw.data = bce_TPAT_b09FwData;
2760 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2761 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2763 fw.sbss = bce_TPAT_b09FwSbss;
2765 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2766 fw.bss_len = bce_TPAT_b09FwBssLen;
2768 fw.bss = bce_TPAT_b09FwBss;
2770 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2771 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2772 fw.rodata_index = 0;
2773 fw.rodata = bce_TPAT_b09FwRodata;
2775 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2776 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2777 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2778 fw.start_addr = bce_TPAT_b06FwStartAddr;
2780 fw.text_addr = bce_TPAT_b06FwTextAddr;
2781 fw.text_len = bce_TPAT_b06FwTextLen;
2783 fw.text = bce_TPAT_b06FwText;
2785 fw.data_addr = bce_TPAT_b06FwDataAddr;
2786 fw.data_len = bce_TPAT_b06FwDataLen;
2788 fw.data = bce_TPAT_b06FwData;
2790 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2791 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2793 fw.sbss = bce_TPAT_b06FwSbss;
2795 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2796 fw.bss_len = bce_TPAT_b06FwBssLen;
2798 fw.bss = bce_TPAT_b06FwBss;
2800 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2801 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2802 fw.rodata_index = 0;
2803 fw.rodata = bce_TPAT_b06FwRodata;
2806 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2807 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2811 /****************************************************************************/
2812 /* Initialize the CP CPU. */
2816 /****************************************************************************/
2818 bce_init_cp_cpu(struct bce_softc *sc)
2820 struct cpu_reg cpu_reg;
2823 cpu_reg.mode = BCE_CP_CPU_MODE;
2824 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2825 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2826 cpu_reg.state = BCE_CP_CPU_STATE;
2827 cpu_reg.state_value_clear = 0xffffff;
2828 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2829 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2830 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2831 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2832 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2833 cpu_reg.spad_base = BCE_CP_SCRATCH;
2834 cpu_reg.mips_view_base = 0x8000000;
2836 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2837 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2838 fw.ver_major = bce_CP_b09FwReleaseMajor;
2839 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2840 fw.ver_fix = bce_CP_b09FwReleaseFix;
2841 fw.start_addr = bce_CP_b09FwStartAddr;
2843 fw.text_addr = bce_CP_b09FwTextAddr;
2844 fw.text_len = bce_CP_b09FwTextLen;
2846 fw.text = bce_CP_b09FwText;
2848 fw.data_addr = bce_CP_b09FwDataAddr;
2849 fw.data_len = bce_CP_b09FwDataLen;
2851 fw.data = bce_CP_b09FwData;
2853 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2854 fw.sbss_len = bce_CP_b09FwSbssLen;
2856 fw.sbss = bce_CP_b09FwSbss;
2858 fw.bss_addr = bce_CP_b09FwBssAddr;
2859 fw.bss_len = bce_CP_b09FwBssLen;
2861 fw.bss = bce_CP_b09FwBss;
2863 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2864 fw.rodata_len = bce_CP_b09FwRodataLen;
2865 fw.rodata_index = 0;
2866 fw.rodata = bce_CP_b09FwRodata;
2868 fw.ver_major = bce_CP_b06FwReleaseMajor;
2869 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2870 fw.ver_fix = bce_CP_b06FwReleaseFix;
2871 fw.start_addr = bce_CP_b06FwStartAddr;
2873 fw.text_addr = bce_CP_b06FwTextAddr;
2874 fw.text_len = bce_CP_b06FwTextLen;
2876 fw.text = bce_CP_b06FwText;
2878 fw.data_addr = bce_CP_b06FwDataAddr;
2879 fw.data_len = bce_CP_b06FwDataLen;
2881 fw.data = bce_CP_b06FwData;
2883 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2884 fw.sbss_len = bce_CP_b06FwSbssLen;
2886 fw.sbss = bce_CP_b06FwSbss;
2888 fw.bss_addr = bce_CP_b06FwBssAddr;
2889 fw.bss_len = bce_CP_b06FwBssLen;
2891 fw.bss = bce_CP_b06FwBss;
2893 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2894 fw.rodata_len = bce_CP_b06FwRodataLen;
2895 fw.rodata_index = 0;
2896 fw.rodata = bce_CP_b06FwRodata;
2899 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2900 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2904 /****************************************************************************/
2905 /* Initialize the COM CPU. */
2909 /****************************************************************************/
2911 bce_init_com_cpu(struct bce_softc *sc)
2913 struct cpu_reg cpu_reg;
2916 cpu_reg.mode = BCE_COM_CPU_MODE;
2917 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2918 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2919 cpu_reg.state = BCE_COM_CPU_STATE;
2920 cpu_reg.state_value_clear = 0xffffff;
2921 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2922 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2923 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2924 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2925 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2926 cpu_reg.spad_base = BCE_COM_SCRATCH;
2927 cpu_reg.mips_view_base = 0x8000000;
2929 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2930 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2931 fw.ver_major = bce_COM_b09FwReleaseMajor;
2932 fw.ver_minor = bce_COM_b09FwReleaseMinor;
2933 fw.ver_fix = bce_COM_b09FwReleaseFix;
2934 fw.start_addr = bce_COM_b09FwStartAddr;
2936 fw.text_addr = bce_COM_b09FwTextAddr;
2937 fw.text_len = bce_COM_b09FwTextLen;
2939 fw.text = bce_COM_b09FwText;
2941 fw.data_addr = bce_COM_b09FwDataAddr;
2942 fw.data_len = bce_COM_b09FwDataLen;
2944 fw.data = bce_COM_b09FwData;
2946 fw.sbss_addr = bce_COM_b09FwSbssAddr;
2947 fw.sbss_len = bce_COM_b09FwSbssLen;
2949 fw.sbss = bce_COM_b09FwSbss;
2951 fw.bss_addr = bce_COM_b09FwBssAddr;
2952 fw.bss_len = bce_COM_b09FwBssLen;
2954 fw.bss = bce_COM_b09FwBss;
2956 fw.rodata_addr = bce_COM_b09FwRodataAddr;
2957 fw.rodata_len = bce_COM_b09FwRodataLen;
2958 fw.rodata_index = 0;
2959 fw.rodata = bce_COM_b09FwRodata;
2961 fw.ver_major = bce_COM_b06FwReleaseMajor;
2962 fw.ver_minor = bce_COM_b06FwReleaseMinor;
2963 fw.ver_fix = bce_COM_b06FwReleaseFix;
2964 fw.start_addr = bce_COM_b06FwStartAddr;
2966 fw.text_addr = bce_COM_b06FwTextAddr;
2967 fw.text_len = bce_COM_b06FwTextLen;
2969 fw.text = bce_COM_b06FwText;
2971 fw.data_addr = bce_COM_b06FwDataAddr;
2972 fw.data_len = bce_COM_b06FwDataLen;
2974 fw.data = bce_COM_b06FwData;
2976 fw.sbss_addr = bce_COM_b06FwSbssAddr;
2977 fw.sbss_len = bce_COM_b06FwSbssLen;
2979 fw.sbss = bce_COM_b06FwSbss;
2981 fw.bss_addr = bce_COM_b06FwBssAddr;
2982 fw.bss_len = bce_COM_b06FwBssLen;
2984 fw.bss = bce_COM_b06FwBss;
2986 fw.rodata_addr = bce_COM_b06FwRodataAddr;
2987 fw.rodata_len = bce_COM_b06FwRodataLen;
2988 fw.rodata_index = 0;
2989 fw.rodata = bce_COM_b06FwRodata;
2992 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2993 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2997 /****************************************************************************/
2998 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3000 /* Loads the firmware for each CPU and starts the CPU. */
3004 /****************************************************************************/
3006 bce_init_cpus(struct bce_softc *sc)
3008 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3009 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3010 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
3012 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
3015 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
3017 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
3021 bce_init_rxp_cpu(sc);
3022 bce_init_txp_cpu(sc);
3023 bce_init_tpat_cpu(sc);
3024 bce_init_com_cpu(sc);
3025 bce_init_cp_cpu(sc);
3029 /****************************************************************************/
3030 /* Initialize context memory. */
3032 /* Clears the memory associated with each Context ID (CID). */
3036 /****************************************************************************/
3038 bce_init_ctx(struct bce_softc *sc)
3040 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3041 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3042 /* DRC: Replace this constant value with a #define. */
3043 int i, retry_cnt = 10;
3047 * BCM5709 context memory may be cached
3048 * in host memory so prepare the host memory
3051 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3053 val |= (BCM_PAGE_BITS - 8) << 16;
3054 REG_WR(sc, BCE_CTX_COMMAND, val);
3056 /* Wait for mem init command to complete. */
3057 for (i = 0; i < retry_cnt; i++) {
3058 val = REG_RD(sc, BCE_CTX_COMMAND);
3059 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3064 for (i = 0; i < sc->ctx_pages; i++) {
3068 * Set the physical address of the context
3071 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3072 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3073 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3074 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3075 BCE_ADDR_HI(sc->ctx_paddr[i]));
3076 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3077 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3080 * Verify that the context memory write was successful.
3082 for (j = 0; j < retry_cnt; j++) {
3083 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3085 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3091 uint32_t vcid_addr, offset;
3094 * For the 5706/5708, context memory is local to
3095 * the controller, so initialize the controller
3099 vcid_addr = GET_CID_ADDR(96);
3101 vcid_addr -= PHY_CTX_SIZE;
3103 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3104 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3106 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3107 CTX_WR(sc, 0x00, offset, 0);
3109 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3110 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3116 /****************************************************************************/
3117 /* Fetch the permanent MAC address of the controller. */
3121 /****************************************************************************/
3123 bce_get_mac_addr(struct bce_softc *sc)
3125 uint32_t mac_lo = 0, mac_hi = 0;
3128 * The NetXtreme II bootcode populates various NIC
3129 * power-on and runtime configuration items in a
3130 * shared memory area. The factory configured MAC
3131 * address is available from both NVRAM and the
3132 * shared memory area so we'll read the value from
3133 * shared memory for speed.
3136 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
3137 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
3139 if (mac_lo == 0 && mac_hi == 0) {
3140 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3142 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3143 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3144 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3145 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3146 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3147 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3150 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3154 /****************************************************************************/
3155 /* Program the MAC address. */
3159 /****************************************************************************/
3161 bce_set_mac_addr(struct bce_softc *sc)
3163 const uint8_t *mac_addr = sc->eaddr;
3166 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3169 val = (mac_addr[0] << 8) | mac_addr[1];
3170 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3172 val = (mac_addr[2] << 24) |
3173 (mac_addr[3] << 16) |
3174 (mac_addr[4] << 8) |
3176 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3180 /****************************************************************************/
3181 /* Stop the controller. */
3185 /****************************************************************************/
3187 bce_stop(struct bce_softc *sc)
3189 struct ifnet *ifp = &sc->arpcom.ac_if;
3190 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3191 struct ifmedia_entry *ifm;
3194 ASSERT_SERIALIZED(ifp->if_serializer);
3196 callout_stop(&sc->bce_tick_callout);
3198 /* Disable the transmit/receive blocks. */
3199 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3200 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3203 bce_disable_intr(sc);
3205 /* Free the RX lists. */
3206 bce_free_rx_chain(sc);
3208 /* Free TX buffers. */
3209 bce_free_tx_chain(sc);
3212 * Isolate/power down the PHY, but leave the media selection
3213 * unchanged so that things will be put back to normal when
3214 * we bring the interface back up.
3216 * 'mii' may be NULL if bce_stop() is called by bce_detach().
3219 itmp = ifp->if_flags;
3220 ifp->if_flags |= IFF_UP;
3221 ifm = mii->mii_media.ifm_cur;
3222 mtmp = ifm->ifm_media;
3223 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3225 ifm->ifm_media = mtmp;
3226 ifp->if_flags = itmp;
3230 sc->bce_coalchg_mask = 0;
3232 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3238 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3243 /* Wait for pending PCI transactions to complete. */
3244 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3245 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3246 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3247 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3248 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3249 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3253 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3254 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3255 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3256 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3257 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3260 /* Assume bootcode is running. */
3261 sc->bce_fw_timed_out = 0;
3263 /* Give the firmware a chance to prepare for the reset. */
3264 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3266 if_printf(&sc->arpcom.ac_if,
3267 "Firmware is not ready for reset\n");
3271 /* Set a firmware reminder that this is a soft reset. */
3272 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3273 BCE_DRV_RESET_SIGNATURE_MAGIC);
3275 /* Dummy read to force the chip to complete all current transactions. */
3276 val = REG_RD(sc, BCE_MISC_ID);
3279 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3280 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3281 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3282 REG_RD(sc, BCE_MISC_COMMAND);
3285 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3286 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3288 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3290 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3291 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3292 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3293 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3295 /* Allow up to 30us for reset to complete. */
3296 for (i = 0; i < 10; i++) {
3297 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3298 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3299 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3304 /* Check that reset completed successfully. */
3305 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3306 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3307 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3312 /* Make sure byte swapping is properly configured. */
3313 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3314 if (val != 0x01020304) {
3315 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3319 /* Just completed a reset, assume that firmware is running again. */
3320 sc->bce_fw_timed_out = 0;
3322 /* Wait for the firmware to finish its initialization. */
3323 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3325 if_printf(&sc->arpcom.ac_if,
3326 "Firmware did not complete initialization!\n");
3333 bce_chipinit(struct bce_softc *sc)
3338 /* Make sure the interrupt is not active. */
3339 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3340 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3343 * Initialize DMA byte/word swapping, configure the number of DMA
3344 * channels and PCI clock compensation delay.
3346 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3347 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3348 #if BYTE_ORDER == BIG_ENDIAN
3349 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3351 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3352 DMA_READ_CHANS << 12 |
3353 DMA_WRITE_CHANS << 16;
3355 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3357 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3358 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3361 * This setting resolves a problem observed on certain Intel PCI
3362 * chipsets that cannot handle multiple outstanding DMA operations.
3363 * See errata E9_5706A1_65.
3365 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3366 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3367 !(sc->bce_flags & BCE_PCIX_FLAG))
3368 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3370 REG_WR(sc, BCE_DMA_CONFIG, val);
3372 /* Enable the RX_V2P and Context state machines before access. */
3373 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3374 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3375 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3376 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3378 /* Initialize context mapping and zero out the quick contexts. */
3381 /* Initialize the on-boards CPUs */
3384 /* Prepare NVRAM for access. */
3385 rc = bce_init_nvram(sc);
3389 /* Set the kernel bypass block size */
3390 val = REG_RD(sc, BCE_MQ_CONFIG);
3391 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3392 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3394 /* Enable bins used on the 5709/5716. */
3395 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3396 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3397 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3398 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3399 val |= BCE_MQ_CONFIG_HALT_DIS;
3402 REG_WR(sc, BCE_MQ_CONFIG, val);
3404 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3405 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3406 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3408 /* Set the page size and clear the RV2P processor stall bits. */
3409 val = (BCM_PAGE_BITS - 8) << 24;
3410 REG_WR(sc, BCE_RV2P_CONFIG, val);
3412 /* Configure page size. */
3413 val = REG_RD(sc, BCE_TBDR_CONFIG);
3414 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3415 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3416 REG_WR(sc, BCE_TBDR_CONFIG, val);
3418 /* Set the perfect match control register to default. */
3419 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3425 /****************************************************************************/
3426 /* Initialize the controller in preparation to send/receive traffic. */
3429 /* 0 for success, positive value for failure. */
3430 /****************************************************************************/
3432 bce_blockinit(struct bce_softc *sc)
3437 /* Load the hardware default MAC address. */
3438 bce_set_mac_addr(sc);
3440 /* Set the Ethernet backoff seed value */
3441 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3442 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3443 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3445 sc->last_status_idx = 0;
3446 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3448 /* Set up link change interrupt generation. */
3449 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3451 /* Program the physical address of the status block. */
3452 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3453 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3455 /* Program the physical address of the statistics block. */
3456 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3457 BCE_ADDR_LO(sc->stats_block_paddr));
3458 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3459 BCE_ADDR_HI(sc->stats_block_paddr));
3461 /* Program various host coalescing parameters. */
3462 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3463 (sc->bce_tx_quick_cons_trip_int << 16) |
3464 sc->bce_tx_quick_cons_trip);
3465 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3466 (sc->bce_rx_quick_cons_trip_int << 16) |
3467 sc->bce_rx_quick_cons_trip);
3468 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3469 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3470 REG_WR(sc, BCE_HC_TX_TICKS,
3471 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3472 REG_WR(sc, BCE_HC_RX_TICKS,
3473 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3474 REG_WR(sc, BCE_HC_COM_TICKS,
3475 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3476 REG_WR(sc, BCE_HC_CMD_TICKS,
3477 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3478 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3479 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3480 REG_WR(sc, BCE_HC_CONFIG,
3481 BCE_HC_CONFIG_TX_TMR_MODE |
3482 BCE_HC_CONFIG_COLLECT_STATS);
3484 /* Clear the internal statistics counters. */
3485 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3487 /* Verify that bootcode is running. */
3488 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3490 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3491 if_printf(&sc->arpcom.ac_if,
3492 "%s(%d): Simulating bootcode failure.\n",
3493 __FILE__, __LINE__);
3496 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3497 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3498 if_printf(&sc->arpcom.ac_if,
3499 "Bootcode not running! Found: 0x%08X, "
3500 "Expected: 08%08X\n",
3501 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3502 BCE_DEV_INFO_SIGNATURE_MAGIC);
3507 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3508 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3509 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3510 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3511 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3514 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3515 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3517 /* Enable link state change interrupt generation. */
3518 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3520 /* Enable all remaining blocks in the MAC. */
3521 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3522 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3523 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3524 BCE_MISC_ENABLE_DEFAULT_XI);
3526 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3528 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3531 /* Save the current host coalescing block settings. */
3532 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3538 /****************************************************************************/
3539 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3541 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3542 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3546 /* 0 for success, positive value for failure. */
3547 /****************************************************************************/
3549 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3550 uint32_t *prod_bseq, int init)
3553 bus_dma_segment_t seg;
3557 uint16_t debug_chain_prod = *chain_prod;
3560 /* Make sure the inputs are valid. */
3561 DBRUNIF((*chain_prod > MAX_RX_BD),
3562 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3563 "RX producer out of range: 0x%04X > 0x%04X\n",
3565 *chain_prod, (uint16_t)MAX_RX_BD));
3567 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3568 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3570 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3571 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3572 "Simulating mbuf allocation failure.\n",
3573 __FILE__, __LINE__);
3574 sc->mbuf_alloc_failed++;
3577 /* This is a new mbuf allocation. */
3578 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3581 DBRUNIF(1, sc->rx_mbuf_alloc++);
3583 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3585 /* Map the mbuf cluster into device memory. */
3586 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3587 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3592 if_printf(&sc->arpcom.ac_if,
3593 "Error mapping mbuf into RX chain!\n");
3595 DBRUNIF(1, sc->rx_mbuf_alloc--);
3599 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3600 bus_dmamap_unload(sc->rx_mbuf_tag,
3601 sc->rx_mbuf_map[*chain_prod]);
3604 map = sc->rx_mbuf_map[*chain_prod];
3605 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3606 sc->rx_mbuf_tmpmap = map;
3608 /* Watch for overflow. */
3609 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3610 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3611 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3612 __FILE__, __LINE__, sc->free_rx_bd,
3613 (uint16_t)USABLE_RX_BD));
3615 /* Update some debug statistic counters */
3616 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3617 sc->rx_low_watermark = sc->free_rx_bd);
3618 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3620 /* Save the mbuf and update our counter. */
3621 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3622 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3625 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3627 DBRUN(BCE_VERBOSE_RECV,
3628 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3630 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3631 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3638 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3644 paddr = sc->rx_mbuf_paddr[chain_prod];
3645 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3647 /* Setup the rx_bd for the first segment. */
3648 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3650 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3651 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3652 rxbd->rx_bd_len = htole32(len);
3653 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3656 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3660 /****************************************************************************/
3661 /* Initialize the TX context memory. */
3665 /****************************************************************************/
3667 bce_init_tx_context(struct bce_softc *sc)
3671 /* Initialize the context ID for an L2 TX chain. */
3672 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3673 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3674 /* Set the CID type to support an L2 connection. */
3675 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3676 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3677 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3678 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3680 /* Point the hardware to the first page in the chain. */
3681 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3682 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3683 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3684 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3685 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3686 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3688 /* Set the CID type to support an L2 connection. */
3689 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3690 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3691 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3692 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3694 /* Point the hardware to the first page in the chain. */
3695 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3696 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3697 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3698 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3699 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3700 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3705 /****************************************************************************/
3706 /* Allocate memory and initialize the TX data structures. */
3709 /* 0 for success, positive value for failure. */
3710 /****************************************************************************/
3712 bce_init_tx_chain(struct bce_softc *sc)
3717 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3719 /* Set the initial TX producer/consumer indices. */
3722 sc->tx_prod_bseq = 0;
3724 sc->max_tx_bd = USABLE_TX_BD;
3725 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3726 DBRUNIF(1, sc->tx_full_count = 0);
3729 * The NetXtreme II supports a linked-list structre called
3730 * a Buffer Descriptor Chain (or BD chain). A BD chain
3731 * consists of a series of 1 or more chain pages, each of which
3732 * consists of a fixed number of BD entries.
3733 * The last BD entry on each page is a pointer to the next page
3734 * in the chain, and the last pointer in the BD chain
3735 * points back to the beginning of the chain.
3738 /* Set the TX next pointer chain entries. */
3739 for (i = 0; i < TX_PAGES; i++) {
3742 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3744 /* Check if we've reached the last page. */
3745 if (i == (TX_PAGES - 1))
3750 txbd->tx_bd_haddr_hi =
3751 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3752 txbd->tx_bd_haddr_lo =
3753 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3755 bce_init_tx_context(sc);
3761 /****************************************************************************/
3762 /* Free memory and clear the TX data structures. */
3766 /****************************************************************************/
3768 bce_free_tx_chain(struct bce_softc *sc)
3772 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3774 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3775 for (i = 0; i < TOTAL_TX_BD; i++) {
3776 if (sc->tx_mbuf_ptr[i] != NULL) {
3777 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3778 m_freem(sc->tx_mbuf_ptr[i]);
3779 sc->tx_mbuf_ptr[i] = NULL;
3780 DBRUNIF(1, sc->tx_mbuf_alloc--);
3784 /* Clear each TX chain page. */
3785 for (i = 0; i < TX_PAGES; i++)
3786 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3789 /* Check if we lost any mbufs in the process. */
3790 DBRUNIF((sc->tx_mbuf_alloc),
3791 if_printf(&sc->arpcom.ac_if,
3792 "%s(%d): Memory leak! "
3793 "Lost %d mbufs from tx chain!\n",
3794 __FILE__, __LINE__, sc->tx_mbuf_alloc));
3796 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3800 /****************************************************************************/
3801 /* Initialize the RX context memory. */
3805 /****************************************************************************/
3807 bce_init_rx_context(struct bce_softc *sc)
3811 /* Initialize the context ID for an L2 RX chain. */
3812 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3813 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3816 * Set the level for generating pause frames
3817 * when the number of available rx_bd's gets
3818 * too low (the low watermark) and the level
3819 * when pause frames can be stopped (the high
3822 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3823 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3824 uint32_t lo_water, hi_water;
3826 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
3827 hi_water = USABLE_RX_BD / 4;
3829 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
3830 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
3834 else if (hi_water == 0)
3837 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
3840 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
3842 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
3843 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3844 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3845 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
3846 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
3849 /* Point the hardware to the first page in the chain. */
3850 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3851 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
3852 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3853 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
3857 /****************************************************************************/
3858 /* Allocate memory and initialize the RX data structures. */
3861 /* 0 for success, positive value for failure. */
3862 /****************************************************************************/
3864 bce_init_rx_chain(struct bce_softc *sc)
3868 uint16_t prod, chain_prod;
3871 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3873 /* Initialize the RX producer and consumer indices. */
3876 sc->rx_prod_bseq = 0;
3877 sc->free_rx_bd = USABLE_RX_BD;
3878 sc->max_rx_bd = USABLE_RX_BD;
3879 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3880 DBRUNIF(1, sc->rx_empty_count = 0);
3882 /* Initialize the RX next pointer chain entries. */
3883 for (i = 0; i < RX_PAGES; i++) {
3886 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3888 /* Check if we've reached the last page. */
3889 if (i == (RX_PAGES - 1))
3894 /* Setup the chain page pointers. */
3895 rxbd->rx_bd_haddr_hi =
3896 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3897 rxbd->rx_bd_haddr_lo =
3898 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3901 /* Allocate mbuf clusters for the rx_bd chain. */
3902 prod = prod_bseq = 0;
3903 while (prod < TOTAL_RX_BD) {
3904 chain_prod = RX_CHAIN_IDX(prod);
3905 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
3906 if_printf(&sc->arpcom.ac_if,
3907 "Error filling RX chain: rx_bd[0x%04X]!\n",
3912 prod = NEXT_RX_BD(prod);
3915 /* Save the RX chain producer index. */
3917 sc->rx_prod_bseq = prod_bseq;
3919 /* Tell the chip about the waiting rx_bd's. */
3920 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
3922 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
3925 bce_init_rx_context(sc);
3931 /****************************************************************************/
3932 /* Free memory and clear the RX data structures. */
3936 /****************************************************************************/
3938 bce_free_rx_chain(struct bce_softc *sc)
3942 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3944 /* Free any mbufs still in the RX mbuf chain. */
3945 for (i = 0; i < TOTAL_RX_BD; i++) {
3946 if (sc->rx_mbuf_ptr[i] != NULL) {
3947 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3948 m_freem(sc->rx_mbuf_ptr[i]);
3949 sc->rx_mbuf_ptr[i] = NULL;
3950 DBRUNIF(1, sc->rx_mbuf_alloc--);
3954 /* Clear each RX chain page. */
3955 for (i = 0; i < RX_PAGES; i++)
3956 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3958 /* Check if we lost any mbufs in the process. */
3959 DBRUNIF((sc->rx_mbuf_alloc),
3960 if_printf(&sc->arpcom.ac_if,
3961 "%s(%d): Memory leak! "
3962 "Lost %d mbufs from rx chain!\n",
3963 __FILE__, __LINE__, sc->rx_mbuf_alloc));
3965 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3969 /****************************************************************************/
3970 /* Set media options. */
3973 /* 0 for success, positive value for failure. */
3974 /****************************************************************************/
3976 bce_ifmedia_upd(struct ifnet *ifp)
3978 struct bce_softc *sc = ifp->if_softc;
3979 struct mii_data *mii = device_get_softc(sc->bce_miibus);
3982 * 'mii' will be NULL, when this function is called on following
3983 * code path: bce_attach() -> bce_mgmt_init()
3986 /* Make sure the MII bus has been enumerated. */
3988 if (mii->mii_instance) {
3989 struct mii_softc *miisc;
3991 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3992 mii_phy_reset(miisc);
4000 /****************************************************************************/
4001 /* Reports current media status. */
4005 /****************************************************************************/
4007 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4009 struct bce_softc *sc = ifp->if_softc;
4010 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4013 ifmr->ifm_active = mii->mii_media_active;
4014 ifmr->ifm_status = mii->mii_media_status;
4018 /****************************************************************************/
4019 /* Handles PHY generated interrupt events. */
4023 /****************************************************************************/
4025 bce_phy_intr(struct bce_softc *sc)
4027 uint32_t new_link_state, old_link_state;
4028 struct ifnet *ifp = &sc->arpcom.ac_if;
4030 ASSERT_SERIALIZED(ifp->if_serializer);
4032 new_link_state = sc->status_block->status_attn_bits &
4033 STATUS_ATTN_BITS_LINK_STATE;
4034 old_link_state = sc->status_block->status_attn_bits_ack &
4035 STATUS_ATTN_BITS_LINK_STATE;
4037 /* Handle any changes if the link state has changed. */
4038 if (new_link_state != old_link_state) { /* XXX redundant? */
4039 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4041 /* Update the status_attn_bits_ack field in the status block. */
4042 if (new_link_state) {
4043 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4044 STATUS_ATTN_BITS_LINK_STATE);
4046 if_printf(ifp, "Link is now UP.\n");
4048 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4049 STATUS_ATTN_BITS_LINK_STATE);
4051 if_printf(ifp, "Link is now DOWN.\n");
4055 * Assume link is down and allow tick routine to
4056 * update the state based on the actual media state.
4059 callout_stop(&sc->bce_tick_callout);
4060 bce_tick_serialized(sc);
4063 /* Acknowledge the link change interrupt. */
4064 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4068 /****************************************************************************/
4069 /* Reads the receive consumer value from the status block (skipping over */
4070 /* chain page pointer if necessary). */
4074 /****************************************************************************/
4075 static __inline uint16_t
4076 bce_get_hw_rx_cons(struct bce_softc *sc)
4078 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4080 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4086 /****************************************************************************/
4087 /* Handles received frame interrupt events. */
4091 /****************************************************************************/
4093 bce_rx_intr(struct bce_softc *sc, int count)
4095 struct ifnet *ifp = &sc->arpcom.ac_if;
4096 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4097 uint32_t sw_prod_bseq;
4098 struct mbuf_chain chain[MAXCPU];
4100 ASSERT_SERIALIZED(ifp->if_serializer);
4102 ether_input_chain_init(chain);
4104 DBRUNIF(1, sc->rx_interrupts++);
4106 /* Get the hardware's view of the RX consumer index. */
4107 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4109 /* Get working copies of the driver's view of the RX indices. */
4110 sw_cons = sc->rx_cons;
4111 sw_prod = sc->rx_prod;
4112 sw_prod_bseq = sc->rx_prod_bseq;
4114 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4115 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4116 __func__, sw_prod, sw_cons, sw_prod_bseq);
4118 /* Prevent speculative reads from getting ahead of the status block. */
4119 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4120 BUS_SPACE_BARRIER_READ);
4122 /* Update some debug statistics counters */
4123 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4124 sc->rx_low_watermark = sc->free_rx_bd);
4125 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4127 /* Scan through the receive chain as long as there is work to do. */
4128 while (sw_cons != hw_cons) {
4129 struct mbuf *m = NULL;
4130 struct l2_fhdr *l2fhdr = NULL;
4133 uint32_t status = 0;
4135 #ifdef DEVICE_POLLING
4136 if (count >= 0 && count-- == 0) {
4137 sc->hw_rx_cons = sw_cons;
4143 * Convert the producer/consumer indices
4144 * to an actual rx_bd index.
4146 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4147 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4149 /* Get the used rx_bd. */
4150 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4151 [RX_IDX(sw_chain_cons)];
4154 DBRUN(BCE_VERBOSE_RECV,
4155 if_printf(ifp, "%s(): ", __func__);
4156 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4158 /* The mbuf is stored with the last rx_bd entry of a packet. */
4159 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4160 /* Validate that this is the last rx_bd. */
4161 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4162 if_printf(ifp, "%s(%d): "
4163 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4164 __FILE__, __LINE__, sw_chain_cons);
4165 bce_breakpoint(sc));
4167 if (sw_chain_cons != sw_chain_prod) {
4168 if_printf(ifp, "RX cons(%d) != prod(%d), "
4169 "drop!\n", sw_chain_cons,
4173 bce_setup_rxdesc_std(sc, sw_chain_cons,
4176 goto bce_rx_int_next_rx;
4179 /* Unmap the mbuf from DMA space. */
4180 bus_dmamap_sync(sc->rx_mbuf_tag,
4181 sc->rx_mbuf_map[sw_chain_cons],
4182 BUS_DMASYNC_POSTREAD);
4184 /* Save the mbuf from the driver's chain. */
4185 m = sc->rx_mbuf_ptr[sw_chain_cons];
4188 * Frames received on the NetXteme II are prepended
4189 * with an l2_fhdr structure which provides status
4190 * information about the received frame (including
4191 * VLAN tags and checksum info). The frames are also
4192 * automatically adjusted to align the IP header
4193 * (i.e. two null bytes are inserted before the
4196 l2fhdr = mtod(m, struct l2_fhdr *);
4198 len = l2fhdr->l2_fhdr_pkt_len;
4199 status = l2fhdr->l2_fhdr_status;
4201 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4203 "Simulating l2_fhdr status error.\n");
4204 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4206 /* Watch for unusual sized frames. */
4207 DBRUNIF((len < BCE_MIN_MTU ||
4208 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4210 "%s(%d): Unusual frame size found. "
4211 "Min(%d), Actual(%d), Max(%d)\n",
4213 (int)BCE_MIN_MTU, len,
4214 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4215 bce_dump_mbuf(sc, m);
4216 bce_breakpoint(sc));
4218 len -= ETHER_CRC_LEN;
4220 /* Check the received frame for errors. */
4221 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4222 L2_FHDR_ERRORS_PHY_DECODE |
4223 L2_FHDR_ERRORS_ALIGNMENT |
4224 L2_FHDR_ERRORS_TOO_SHORT |
4225 L2_FHDR_ERRORS_GIANT_FRAME)) {
4227 DBRUNIF(1, sc->l2fhdr_status_errors++);
4229 /* Reuse the mbuf for a new frame. */
4230 bce_setup_rxdesc_std(sc, sw_chain_prod,
4233 goto bce_rx_int_next_rx;
4237 * Get a new mbuf for the rx_bd. If no new
4238 * mbufs are available then reuse the current mbuf,
4239 * log an ierror on the interface, and generate
4240 * an error in the system log.
4242 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4243 &sw_prod_bseq, 0)) {
4246 "%s(%d): Failed to allocate new mbuf, "
4247 "incoming frame dropped!\n",
4248 __FILE__, __LINE__));
4252 /* Try and reuse the exisitng mbuf. */
4253 bce_setup_rxdesc_std(sc, sw_chain_prod,
4256 goto bce_rx_int_next_rx;
4260 * Skip over the l2_fhdr when passing
4261 * the data up the stack.
4263 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4265 m->m_pkthdr.len = m->m_len = len;
4266 m->m_pkthdr.rcvif = ifp;
4268 DBRUN(BCE_VERBOSE_RECV,
4269 struct ether_header *eh;
4270 eh = mtod(m, struct ether_header *);
4271 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4272 "type: 0x%04X\n", __func__,
4273 eh->ether_dhost, ":",
4274 eh->ether_shost, ":",
4275 htons(eh->ether_type)));
4277 /* Validate the checksum if offload enabled. */
4278 if (ifp->if_capenable & IFCAP_RXCSUM) {
4279 /* Check for an IP datagram. */
4280 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4281 m->m_pkthdr.csum_flags |=
4284 /* Check if the IP checksum is valid. */
4285 if ((l2fhdr->l2_fhdr_ip_xsum ^
4287 m->m_pkthdr.csum_flags |=
4290 DBPRINT(sc, BCE_WARN_RECV,
4291 "%s(): Invalid IP checksum = 0x%04X!\n",
4292 __func__, l2fhdr->l2_fhdr_ip_xsum);
4296 /* Check for a valid TCP/UDP frame. */
4297 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4298 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4300 /* Check for a good TCP/UDP checksum. */
4302 (L2_FHDR_ERRORS_TCP_XSUM |
4303 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4304 m->m_pkthdr.csum_data =
4305 l2fhdr->l2_fhdr_tcp_udp_xsum;
4306 m->m_pkthdr.csum_flags |=
4310 DBPRINT(sc, BCE_WARN_RECV,
4311 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4312 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4319 sw_prod = NEXT_RX_BD(sw_prod);
4322 sw_cons = NEXT_RX_BD(sw_cons);
4324 /* If we have a packet, pass it up the stack */
4326 DBPRINT(sc, BCE_VERBOSE_RECV,
4327 "%s(): Passing received frame up.\n", __func__);
4329 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4330 m->m_flags |= M_VLANTAG;
4331 m->m_pkthdr.ether_vlantag =
4332 l2fhdr->l2_fhdr_vlan_tag;
4334 ether_input_chain(ifp, m, NULL, chain);
4336 DBRUNIF(1, sc->rx_mbuf_alloc--);
4340 * If polling(4) is not enabled, refresh hw_cons to see
4341 * whether there's new work.
4343 * If polling(4) is enabled, i.e count >= 0, refreshing
4344 * should not be performed, so that we would not spend
4345 * too much time in RX processing.
4347 if (count < 0 && sw_cons == hw_cons)
4348 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4351 * Prevent speculative reads from getting ahead
4352 * of the status block.
4354 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4355 BUS_SPACE_BARRIER_READ);
4358 ether_input_dispatch(chain);
4360 sc->rx_cons = sw_cons;
4361 sc->rx_prod = sw_prod;
4362 sc->rx_prod_bseq = sw_prod_bseq;
4364 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4366 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4369 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4370 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4371 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4375 /****************************************************************************/
4376 /* Reads the transmit consumer value from the status block (skipping over */
4377 /* chain page pointer if necessary). */
4381 /****************************************************************************/
4382 static __inline uint16_t
4383 bce_get_hw_tx_cons(struct bce_softc *sc)
4385 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4387 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4393 /****************************************************************************/
4394 /* Handles transmit completion interrupt events. */
4398 /****************************************************************************/
4400 bce_tx_intr(struct bce_softc *sc)
4402 struct ifnet *ifp = &sc->arpcom.ac_if;
4403 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4405 ASSERT_SERIALIZED(ifp->if_serializer);
4407 DBRUNIF(1, sc->tx_interrupts++);
4409 /* Get the hardware's view of the TX consumer index. */
4410 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4411 sw_tx_cons = sc->tx_cons;
4413 /* Prevent speculative reads from getting ahead of the status block. */
4414 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4415 BUS_SPACE_BARRIER_READ);
4417 /* Cycle through any completed TX chain page entries. */
4418 while (sw_tx_cons != hw_tx_cons) {
4420 struct tx_bd *txbd = NULL;
4422 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4424 DBPRINT(sc, BCE_INFO_SEND,
4425 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4426 "sw_tx_chain_cons = 0x%04X\n",
4427 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4429 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4430 if_printf(ifp, "%s(%d): "
4431 "TX chain consumer out of range! "
4432 " 0x%04X > 0x%04X\n",
4433 __FILE__, __LINE__, sw_tx_chain_cons,
4435 bce_breakpoint(sc));
4437 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4438 [TX_IDX(sw_tx_chain_cons)]);
4440 DBRUNIF((txbd == NULL),
4441 if_printf(ifp, "%s(%d): "
4442 "Unexpected NULL tx_bd[0x%04X]!\n",
4443 __FILE__, __LINE__, sw_tx_chain_cons);
4444 bce_breakpoint(sc));
4446 DBRUN(BCE_INFO_SEND,
4447 if_printf(ifp, "%s(): ", __func__);
4448 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4451 * Free the associated mbuf. Remember
4452 * that only the last tx_bd of a packet
4453 * has an mbuf pointer and DMA map.
4455 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4456 /* Validate that this is the last tx_bd. */
4457 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4458 if_printf(ifp, "%s(%d): "
4459 "tx_bd END flag not set but "
4460 "txmbuf == NULL!\n", __FILE__, __LINE__);
4461 bce_breakpoint(sc));
4463 DBRUN(BCE_INFO_SEND,
4464 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4465 "from tx_bd[0x%04X]\n", __func__,
4468 /* Unmap the mbuf. */
4469 bus_dmamap_unload(sc->tx_mbuf_tag,
4470 sc->tx_mbuf_map[sw_tx_chain_cons]);
4472 /* Free the mbuf. */
4473 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4474 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4475 DBRUNIF(1, sc->tx_mbuf_alloc--);
4481 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4483 if (sw_tx_cons == hw_tx_cons) {
4484 /* Refresh hw_cons to see if there's new work. */
4485 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4489 * Prevent speculative reads from getting
4490 * ahead of the status block.
4492 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4493 BUS_SPACE_BARRIER_READ);
4496 if (sc->used_tx_bd == 0) {
4497 /* Clear the TX timeout timer. */
4501 /* Clear the tx hardware queue full flag. */
4502 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4503 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4504 DBPRINT(sc, BCE_WARN_SEND,
4505 "%s(): Open TX chain! %d/%d (used/total)\n",
4506 __func__, sc->used_tx_bd, sc->max_tx_bd));
4507 ifp->if_flags &= ~IFF_OACTIVE;
4509 sc->tx_cons = sw_tx_cons;
4513 /****************************************************************************/
4514 /* Disables interrupt generation. */
4518 /****************************************************************************/
4520 bce_disable_intr(struct bce_softc *sc)
4522 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4523 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4524 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4528 /****************************************************************************/
4529 /* Enables interrupt generation. */
4533 /****************************************************************************/
4535 bce_enable_intr(struct bce_softc *sc, int coal_now)
4537 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4539 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4540 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4541 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4543 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4544 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4547 REG_WR(sc, BCE_HC_COMMAND,
4548 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4553 /****************************************************************************/
4554 /* Handles controller initialization. */
4558 /****************************************************************************/
4562 struct bce_softc *sc = xsc;
4563 struct ifnet *ifp = &sc->arpcom.ac_if;
4567 ASSERT_SERIALIZED(ifp->if_serializer);
4569 /* Check if the driver is still running and bail out if it is. */
4570 if (ifp->if_flags & IFF_RUNNING)
4575 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4577 if_printf(ifp, "Controller reset failed!\n");
4581 error = bce_chipinit(sc);
4583 if_printf(ifp, "Controller initialization failed!\n");
4587 error = bce_blockinit(sc);
4589 if_printf(ifp, "Block initialization failed!\n");
4593 /* Load our MAC address. */
4594 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4595 bce_set_mac_addr(sc);
4597 /* Calculate and program the Ethernet MTU size. */
4598 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4600 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4603 * Program the mtu, enabling jumbo frame
4604 * support if necessary. Also set the mbuf
4605 * allocation count for RX frames.
4607 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4609 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4610 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4611 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4612 sc->mbuf_alloc_size = MJUM9BYTES;
4614 panic("jumbo buffer is not supported yet\n");
4617 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4618 sc->mbuf_alloc_size = MCLBYTES;
4621 /* Calculate the RX Ethernet frame size for rx_bd's. */
4622 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4624 DBPRINT(sc, BCE_INFO,
4625 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4626 "max_frame_size = %d\n",
4627 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4628 sc->max_frame_size);
4630 /* Program appropriate promiscuous/multicast filtering. */
4631 bce_set_rx_mode(sc);
4633 /* Init RX buffer descriptor chain. */
4634 bce_init_rx_chain(sc); /* XXX return value */
4636 /* Init TX buffer descriptor chain. */
4637 bce_init_tx_chain(sc); /* XXX return value */
4639 #ifdef DEVICE_POLLING
4640 /* Disable interrupts if we are polling. */
4641 if (ifp->if_flags & IFF_POLLING) {
4642 bce_disable_intr(sc);
4644 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4645 (1 << 16) | sc->bce_rx_quick_cons_trip);
4646 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4647 (1 << 16) | sc->bce_tx_quick_cons_trip);
4650 /* Enable host interrupts. */
4651 bce_enable_intr(sc, 1);
4653 bce_ifmedia_upd(ifp);
4655 ifp->if_flags |= IFF_RUNNING;
4656 ifp->if_flags &= ~IFF_OACTIVE;
4658 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4665 /****************************************************************************/
4666 /* Initialize the controller just enough so that any management firmware */
4667 /* running on the device will continue to operate corectly. */
4671 /****************************************************************************/
4673 bce_mgmt_init(struct bce_softc *sc)
4675 struct ifnet *ifp = &sc->arpcom.ac_if;
4677 /* Bail out if management firmware is not running. */
4678 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4681 /* Enable all critical blocks in the MAC. */
4682 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4683 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4684 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4685 BCE_MISC_ENABLE_DEFAULT_XI);
4687 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4689 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4692 bce_ifmedia_upd(ifp);
4696 /****************************************************************************/
4697 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4698 /* memory visible to the controller. */
4701 /* 0 for success, positive value for failure. */
4702 /****************************************************************************/
4704 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4706 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4707 bus_dmamap_t map, tmp_map;
4708 struct mbuf *m0 = *m_head;
4709 struct tx_bd *txbd = NULL;
4710 uint16_t vlan_tag = 0, flags = 0;
4711 uint16_t chain_prod, chain_prod_start, prod;
4713 int i, error, maxsegs, nsegs;
4715 uint16_t debug_prod;
4718 /* Transfer any checksum offload flags to the bd. */
4719 if (m0->m_pkthdr.csum_flags) {
4720 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4721 flags |= TX_BD_FLAGS_IP_CKSUM;
4722 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4723 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4726 /* Transfer any VLAN tags to the bd. */
4727 if (m0->m_flags & M_VLANTAG) {
4728 flags |= TX_BD_FLAGS_VLAN_TAG;
4729 vlan_tag = m0->m_pkthdr.ether_vlantag;
4733 chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4735 /* Map the mbuf into DMAable memory. */
4736 map = sc->tx_mbuf_map[chain_prod_start];
4738 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4739 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4740 ("not enough segements %d\n", maxsegs));
4741 if (maxsegs > BCE_MAX_SEGMENTS)
4742 maxsegs = BCE_MAX_SEGMENTS;
4744 /* Map the mbuf into our DMA address space. */
4745 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4746 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4749 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4754 /* prod points to an empty tx_bd at this point. */
4755 prod_bseq = sc->tx_prod_bseq;
4758 debug_prod = chain_prod;
4761 DBPRINT(sc, BCE_INFO_SEND,
4762 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4763 "prod_bseq = 0x%08X\n",
4764 __func__, prod, chain_prod, prod_bseq);
4767 * Cycle through each mbuf segment that makes up
4768 * the outgoing frame, gathering the mapping info
4769 * for that segment and creating a tx_bd to for
4772 for (i = 0; i < nsegs; i++) {
4773 chain_prod = TX_CHAIN_IDX(prod);
4774 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4776 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4777 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4778 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4779 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4780 txbd->tx_bd_flags = htole16(flags);
4781 prod_bseq += segs[i].ds_len;
4783 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4784 prod = NEXT_TX_BD(prod);
4787 /* Set the END flag on the last TX buffer descriptor. */
4788 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4790 DBRUN(BCE_EXCESSIVE_SEND,
4791 bce_dump_tx_chain(sc, debug_prod, nsegs));
4793 DBPRINT(sc, BCE_INFO_SEND,
4794 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4795 "prod_bseq = 0x%08X\n",
4796 __func__, prod, chain_prod, prod_bseq);
4799 * Ensure that the mbuf pointer for this transmission
4800 * is placed at the array index of the last
4801 * descriptor in this chain. This is done
4802 * because a single map is used for all
4803 * segments of the mbuf and we don't want to
4804 * unload the map before all of the segments
4807 sc->tx_mbuf_ptr[chain_prod] = m0;
4809 tmp_map = sc->tx_mbuf_map[chain_prod];
4810 sc->tx_mbuf_map[chain_prod] = map;
4811 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4813 sc->used_tx_bd += nsegs;
4815 /* Update some debug statistic counters */
4816 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4817 sc->tx_hi_watermark = sc->used_tx_bd);
4818 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4819 DBRUNIF(1, sc->tx_mbuf_alloc++);
4821 DBRUN(BCE_VERBOSE_SEND,
4822 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4824 /* prod points to the next free tx_bd at this point. */
4826 sc->tx_prod_bseq = prod_bseq;
4836 /****************************************************************************/
4837 /* Main transmit routine when called from another routine with a lock. */
4841 /****************************************************************************/
4843 bce_start(struct ifnet *ifp)
4845 struct bce_softc *sc = ifp->if_softc;
4848 ASSERT_SERIALIZED(ifp->if_serializer);
4850 /* If there's no link or the transmit queue is empty then just exit. */
4851 if (!sc->bce_link) {
4852 ifq_purge(&ifp->if_snd);
4856 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4859 DBPRINT(sc, BCE_INFO_SEND,
4860 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4861 "tx_prod_bseq = 0x%08X\n",
4863 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4866 struct mbuf *m_head;
4869 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4872 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4873 ifp->if_flags |= IFF_OACTIVE;
4877 /* Check for any frames to send. */
4878 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4883 * Pack the data into the transmit ring. If we
4884 * don't have room, place the mbuf back at the
4885 * head of the queue and set the OACTIVE flag
4886 * to wait for the NIC to drain the chain.
4888 if (bce_encap(sc, &m_head)) {
4890 if (sc->used_tx_bd == 0) {
4893 ifp->if_flags |= IFF_OACTIVE;
4900 /* Send a copy of the frame to any BPF listeners. */
4901 ETHER_BPF_MTAP(ifp, m_head);
4905 /* no packets were dequeued */
4906 DBPRINT(sc, BCE_VERBOSE_SEND,
4907 "%s(): No packets were dequeued\n", __func__);
4911 DBPRINT(sc, BCE_INFO_SEND,
4912 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
4913 "tx_prod_bseq = 0x%08X\n",
4915 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4917 REG_WR(sc, BCE_MQ_COMMAND,
4918 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
4920 /* Start the transmit. */
4921 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4922 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4924 /* Set the tx timeout. */
4925 ifp->if_timer = BCE_TX_TIMEOUT;
4929 /****************************************************************************/
4930 /* Handles any IOCTL calls from the operating system. */
4933 /* 0 for success, positive value for failure. */
4934 /****************************************************************************/
4936 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4938 struct bce_softc *sc = ifp->if_softc;
4939 struct ifreq *ifr = (struct ifreq *)data;
4940 struct mii_data *mii;
4941 int mask, error = 0;
4943 ASSERT_SERIALIZED(ifp->if_serializer);
4947 /* Check that the MTU setting is supported. */
4948 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4950 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4952 ifr->ifr_mtu > ETHERMTU
4959 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4961 ifp->if_mtu = ifr->ifr_mtu;
4962 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
4967 if (ifp->if_flags & IFF_UP) {
4968 if (ifp->if_flags & IFF_RUNNING) {
4969 mask = ifp->if_flags ^ sc->bce_if_flags;
4971 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4972 bce_set_rx_mode(sc);
4976 } else if (ifp->if_flags & IFF_RUNNING) {
4979 /* If MFW is running, restart the controller a bit. */
4980 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4981 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4986 sc->bce_if_flags = ifp->if_flags;
4991 if (ifp->if_flags & IFF_RUNNING)
4992 bce_set_rx_mode(sc);
4997 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4999 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5001 mii = device_get_softc(sc->bce_miibus);
5002 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5006 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5007 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5010 if (mask & IFCAP_HWCSUM) {
5011 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5012 if (IFCAP_HWCSUM & ifp->if_capenable)
5013 ifp->if_hwassist = BCE_IF_HWASSIST;
5015 ifp->if_hwassist = 0;
5020 error = ether_ioctl(ifp, command, data);
5027 /****************************************************************************/
5028 /* Transmit timeout handler. */
5032 /****************************************************************************/
5034 bce_watchdog(struct ifnet *ifp)
5036 struct bce_softc *sc = ifp->if_softc;
5038 ASSERT_SERIALIZED(ifp->if_serializer);
5040 DBRUN(BCE_VERBOSE_SEND,
5041 bce_dump_driver_state(sc);
5042 bce_dump_status_block(sc));
5045 * If we are in this routine because of pause frames, then
5046 * don't reset the hardware.
5048 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5051 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5053 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5055 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5060 if (!ifq_is_empty(&ifp->if_snd))
5065 #ifdef DEVICE_POLLING
5068 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5070 struct bce_softc *sc = ifp->if_softc;
5071 struct status_block *sblk = sc->status_block;
5072 uint16_t hw_tx_cons, hw_rx_cons;
5074 ASSERT_SERIALIZED(ifp->if_serializer);
5078 bce_disable_intr(sc);
5080 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5081 (1 << 16) | sc->bce_rx_quick_cons_trip);
5082 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5083 (1 << 16) | sc->bce_tx_quick_cons_trip);
5085 case POLL_DEREGISTER:
5086 bce_enable_intr(sc, 1);
5088 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5089 (sc->bce_tx_quick_cons_trip_int << 16) |
5090 sc->bce_tx_quick_cons_trip);
5091 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5092 (sc->bce_rx_quick_cons_trip_int << 16) |
5093 sc->bce_rx_quick_cons_trip);
5099 if (cmd == POLL_AND_CHECK_STATUS) {
5100 uint32_t status_attn_bits;
5102 status_attn_bits = sblk->status_attn_bits;
5104 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5106 "Simulating unexpected status attention bit set.");
5107 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5109 /* Was it a link change interrupt? */
5110 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5111 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5114 /* Clear any transient status updates during link state change. */
5115 REG_WR(sc, BCE_HC_COMMAND,
5116 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5117 REG_RD(sc, BCE_HC_COMMAND);
5120 * If any other attention is asserted then
5121 * the chip is toast.
5123 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5124 (sblk->status_attn_bits_ack &
5125 ~STATUS_ATTN_BITS_LINK_STATE)) {
5126 DBRUN(1, sc->unexpected_attentions++);
5128 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5129 sblk->status_attn_bits);
5132 if (bce_debug_unexpected_attention == 0)
5133 bce_breakpoint(sc));
5140 hw_rx_cons = bce_get_hw_rx_cons(sc);
5141 hw_tx_cons = bce_get_hw_tx_cons(sc);
5143 /* Check for any completed RX frames. */
5144 if (hw_rx_cons != sc->hw_rx_cons)
5145 bce_rx_intr(sc, count);
5147 /* Check for any completed TX frames. */
5148 if (hw_tx_cons != sc->hw_tx_cons)
5151 /* Check for new frames to transmit. */
5152 if (!ifq_is_empty(&ifp->if_snd))
5156 #endif /* DEVICE_POLLING */
5160 * Interrupt handler.
5162 /****************************************************************************/
5163 /* Main interrupt entry point. Verifies that the controller generated the */
5164 /* interrupt and then calls a separate routine for handle the various */
5165 /* interrupt causes (PHY, TX, RX). */
5168 /* 0 for success, positive value for failure. */
5169 /****************************************************************************/
5173 struct bce_softc *sc = xsc;
5174 struct ifnet *ifp = &sc->arpcom.ac_if;
5175 struct status_block *sblk;
5176 uint16_t hw_rx_cons, hw_tx_cons;
5178 ASSERT_SERIALIZED(ifp->if_serializer);
5180 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5181 DBRUNIF(1, sc->interrupts_generated++);
5183 sblk = sc->status_block;
5186 * If the hardware status block index matches the last value
5187 * read by the driver and we haven't asserted our interrupt
5188 * then there's nothing to do.
5190 if (sblk->status_idx == sc->last_status_idx &&
5191 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5192 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5195 /* Ack the interrupt and stop others from occuring. */
5196 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5197 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5198 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5200 /* Check if the hardware has finished any work. */
5201 hw_rx_cons = bce_get_hw_rx_cons(sc);
5202 hw_tx_cons = bce_get_hw_tx_cons(sc);
5204 /* Keep processing data as long as there is work to do. */
5206 uint32_t status_attn_bits;
5208 status_attn_bits = sblk->status_attn_bits;
5210 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5212 "Simulating unexpected status attention bit set.");
5213 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5215 /* Was it a link change interrupt? */
5216 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5217 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5221 * Clear any transient status updates during link state
5224 REG_WR(sc, BCE_HC_COMMAND,
5225 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5226 REG_RD(sc, BCE_HC_COMMAND);
5230 * If any other attention is asserted then
5231 * the chip is toast.
5233 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5234 (sblk->status_attn_bits_ack &
5235 ~STATUS_ATTN_BITS_LINK_STATE)) {
5236 DBRUN(1, sc->unexpected_attentions++);
5238 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5239 sblk->status_attn_bits);
5242 if (bce_debug_unexpected_attention == 0)
5243 bce_breakpoint(sc));
5249 /* Check for any completed RX frames. */
5250 if (hw_rx_cons != sc->hw_rx_cons)
5251 bce_rx_intr(sc, -1);
5253 /* Check for any completed TX frames. */
5254 if (hw_tx_cons != sc->hw_tx_cons)
5258 * Save the status block index value
5259 * for use during the next interrupt.
5261 sc->last_status_idx = sblk->status_idx;
5264 * Prevent speculative reads from getting
5265 * ahead of the status block.
5267 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5268 BUS_SPACE_BARRIER_READ);
5271 * If there's no work left then exit the
5272 * interrupt service routine.
5274 hw_rx_cons = bce_get_hw_rx_cons(sc);
5275 hw_tx_cons = bce_get_hw_tx_cons(sc);
5276 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5280 /* Re-enable interrupts. */
5281 bce_enable_intr(sc, 0);
5283 if (sc->bce_coalchg_mask)
5284 bce_coal_change(sc);
5286 /* Handle any frames that arrived while handling the interrupt. */
5287 if (!ifq_is_empty(&ifp->if_snd))
5292 /****************************************************************************/
5293 /* Programs the various packet receive modes (broadcast and multicast). */
5297 /****************************************************************************/
5299 bce_set_rx_mode(struct bce_softc *sc)
5301 struct ifnet *ifp = &sc->arpcom.ac_if;
5302 struct ifmultiaddr *ifma;
5303 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5304 uint32_t rx_mode, sort_mode;
5307 ASSERT_SERIALIZED(ifp->if_serializer);
5309 /* Initialize receive mode default settings. */
5310 rx_mode = sc->rx_mode &
5311 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5312 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5313 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5316 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5319 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5320 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5321 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5324 * Check for promiscuous, all multicast, or selected
5325 * multicast address filtering.
5327 if (ifp->if_flags & IFF_PROMISC) {
5328 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5330 /* Enable promiscuous mode. */
5331 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5332 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5333 } else if (ifp->if_flags & IFF_ALLMULTI) {
5334 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5336 /* Enable all multicast addresses. */
5337 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5338 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5341 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5343 /* Accept one or more multicast(s). */
5344 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5346 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5347 if (ifma->ifma_addr->sa_family != AF_LINK)
5350 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5351 ETHER_ADDR_LEN) & 0xFF;
5352 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5355 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5356 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5359 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5362 /* Only make changes if the recive mode has actually changed. */
5363 if (rx_mode != sc->rx_mode) {
5364 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5367 sc->rx_mode = rx_mode;
5368 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5371 /* Disable and clear the exisitng sort before enabling a new sort. */
5372 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5373 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5374 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5378 /****************************************************************************/
5379 /* Called periodically to updates statistics from the controllers */
5380 /* statistics block. */
5384 /****************************************************************************/
5386 bce_stats_update(struct bce_softc *sc)
5388 struct ifnet *ifp = &sc->arpcom.ac_if;
5389 struct statistics_block *stats = sc->stats_block;
5391 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5393 ASSERT_SERIALIZED(ifp->if_serializer);
5396 * Certain controllers don't report carrier sense errors correctly.
5397 * See errata E11_5708CA0_1165.
5399 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5400 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5402 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5406 * Update the sysctl statistics from the hardware statistics.
5408 sc->stat_IfHCInOctets =
5409 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5410 (uint64_t)stats->stat_IfHCInOctets_lo;
5412 sc->stat_IfHCInBadOctets =
5413 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5414 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5416 sc->stat_IfHCOutOctets =
5417 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5418 (uint64_t)stats->stat_IfHCOutOctets_lo;
5420 sc->stat_IfHCOutBadOctets =
5421 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5422 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5424 sc->stat_IfHCInUcastPkts =
5425 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5426 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5428 sc->stat_IfHCInMulticastPkts =
5429 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5430 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5432 sc->stat_IfHCInBroadcastPkts =
5433 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5434 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5436 sc->stat_IfHCOutUcastPkts =
5437 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5438 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5440 sc->stat_IfHCOutMulticastPkts =
5441 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5442 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5444 sc->stat_IfHCOutBroadcastPkts =
5445 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5446 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5448 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5449 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5451 sc->stat_Dot3StatsCarrierSenseErrors =
5452 stats->stat_Dot3StatsCarrierSenseErrors;
5454 sc->stat_Dot3StatsFCSErrors =
5455 stats->stat_Dot3StatsFCSErrors;
5457 sc->stat_Dot3StatsAlignmentErrors =
5458 stats->stat_Dot3StatsAlignmentErrors;
5460 sc->stat_Dot3StatsSingleCollisionFrames =
5461 stats->stat_Dot3StatsSingleCollisionFrames;
5463 sc->stat_Dot3StatsMultipleCollisionFrames =
5464 stats->stat_Dot3StatsMultipleCollisionFrames;
5466 sc->stat_Dot3StatsDeferredTransmissions =
5467 stats->stat_Dot3StatsDeferredTransmissions;
5469 sc->stat_Dot3StatsExcessiveCollisions =
5470 stats->stat_Dot3StatsExcessiveCollisions;
5472 sc->stat_Dot3StatsLateCollisions =
5473 stats->stat_Dot3StatsLateCollisions;
5475 sc->stat_EtherStatsCollisions =
5476 stats->stat_EtherStatsCollisions;
5478 sc->stat_EtherStatsFragments =
5479 stats->stat_EtherStatsFragments;
5481 sc->stat_EtherStatsJabbers =
5482 stats->stat_EtherStatsJabbers;
5484 sc->stat_EtherStatsUndersizePkts =
5485 stats->stat_EtherStatsUndersizePkts;
5487 sc->stat_EtherStatsOverrsizePkts =
5488 stats->stat_EtherStatsOverrsizePkts;
5490 sc->stat_EtherStatsPktsRx64Octets =
5491 stats->stat_EtherStatsPktsRx64Octets;
5493 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5494 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5496 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5497 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5499 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5500 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5502 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5503 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5505 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5506 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5508 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5509 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5511 sc->stat_EtherStatsPktsTx64Octets =
5512 stats->stat_EtherStatsPktsTx64Octets;
5514 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5515 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5517 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5518 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5520 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5521 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5523 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5524 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5526 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5527 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5529 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5530 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5532 sc->stat_XonPauseFramesReceived =
5533 stats->stat_XonPauseFramesReceived;
5535 sc->stat_XoffPauseFramesReceived =
5536 stats->stat_XoffPauseFramesReceived;
5538 sc->stat_OutXonSent =
5539 stats->stat_OutXonSent;
5541 sc->stat_OutXoffSent =
5542 stats->stat_OutXoffSent;
5544 sc->stat_FlowControlDone =
5545 stats->stat_FlowControlDone;
5547 sc->stat_MacControlFramesReceived =
5548 stats->stat_MacControlFramesReceived;
5550 sc->stat_XoffStateEntered =
5551 stats->stat_XoffStateEntered;
5553 sc->stat_IfInFramesL2FilterDiscards =
5554 stats->stat_IfInFramesL2FilterDiscards;
5556 sc->stat_IfInRuleCheckerDiscards =
5557 stats->stat_IfInRuleCheckerDiscards;
5559 sc->stat_IfInFTQDiscards =
5560 stats->stat_IfInFTQDiscards;
5562 sc->stat_IfInMBUFDiscards =
5563 stats->stat_IfInMBUFDiscards;
5565 sc->stat_IfInRuleCheckerP4Hit =
5566 stats->stat_IfInRuleCheckerP4Hit;
5568 sc->stat_CatchupInRuleCheckerDiscards =
5569 stats->stat_CatchupInRuleCheckerDiscards;
5571 sc->stat_CatchupInFTQDiscards =
5572 stats->stat_CatchupInFTQDiscards;
5574 sc->stat_CatchupInMBUFDiscards =
5575 stats->stat_CatchupInMBUFDiscards;
5577 sc->stat_CatchupInRuleCheckerP4Hit =
5578 stats->stat_CatchupInRuleCheckerP4Hit;
5580 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5583 * Update the interface statistics from the
5584 * hardware statistics.
5586 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5588 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5589 (u_long)sc->stat_EtherStatsOverrsizePkts +
5590 (u_long)sc->stat_IfInMBUFDiscards +
5591 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5592 (u_long)sc->stat_Dot3StatsFCSErrors +
5593 (u_long)sc->stat_IfInRuleCheckerDiscards +
5594 (u_long)sc->stat_IfInFTQDiscards +
5595 (u_long)sc->com_no_buffers;
5598 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5599 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5600 (u_long)sc->stat_Dot3StatsLateCollisions;
5602 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5606 /****************************************************************************/
5607 /* Periodic function to notify the bootcode that the driver is still */
5612 /****************************************************************************/
5614 bce_pulse(void *xsc)
5616 struct bce_softc *sc = xsc;
5617 struct ifnet *ifp = &sc->arpcom.ac_if;
5620 lwkt_serialize_enter(ifp->if_serializer);
5622 /* Tell the firmware that the driver is still running. */
5623 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5624 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5626 /* Schedule the next pulse. */
5627 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5629 lwkt_serialize_exit(ifp->if_serializer);
5633 /****************************************************************************/
5634 /* Periodic function to perform maintenance tasks. */
5638 /****************************************************************************/
5640 bce_tick_serialized(struct bce_softc *sc)
5642 struct ifnet *ifp = &sc->arpcom.ac_if;
5643 struct mii_data *mii;
5645 ASSERT_SERIALIZED(ifp->if_serializer);
5647 /* Update the statistics from the hardware statistics block. */
5648 bce_stats_update(sc);
5650 /* Schedule the next tick. */
5651 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5653 /* If link is up already up then we're done. */
5657 mii = device_get_softc(sc->bce_miibus);
5660 /* Check if the link has come up. */
5661 if ((mii->mii_media_status & IFM_ACTIVE) &&
5662 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5664 /* Now that link is up, handle any outstanding TX traffic. */
5665 if (!ifq_is_empty(&ifp->if_snd))
5674 struct bce_softc *sc = xsc;
5675 struct ifnet *ifp = &sc->arpcom.ac_if;
5677 lwkt_serialize_enter(ifp->if_serializer);
5678 bce_tick_serialized(sc);
5679 lwkt_serialize_exit(ifp->if_serializer);
5684 /****************************************************************************/
5685 /* Allows the driver state to be dumped through the sysctl interface. */
5688 /* 0 for success, positive value for failure. */
5689 /****************************************************************************/
5691 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5695 struct bce_softc *sc;
5698 error = sysctl_handle_int(oidp, &result, 0, req);
5700 if (error || !req->newptr)
5704 sc = (struct bce_softc *)arg1;
5705 bce_dump_driver_state(sc);
5712 /****************************************************************************/
5713 /* Allows the hardware state to be dumped through the sysctl interface. */
5716 /* 0 for success, positive value for failure. */
5717 /****************************************************************************/
5719 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5723 struct bce_softc *sc;
5726 error = sysctl_handle_int(oidp, &result, 0, req);
5728 if (error || !req->newptr)
5732 sc = (struct bce_softc *)arg1;
5733 bce_dump_hw_state(sc);
5740 /****************************************************************************/
5741 /* Provides a sysctl interface to allows dumping the RX chain. */
5744 /* 0 for success, positive value for failure. */
5745 /****************************************************************************/
5747 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5751 struct bce_softc *sc;
5754 error = sysctl_handle_int(oidp, &result, 0, req);
5756 if (error || !req->newptr)
5760 sc = (struct bce_softc *)arg1;
5761 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5768 /****************************************************************************/
5769 /* Provides a sysctl interface to allows dumping the TX chain. */
5772 /* 0 for success, positive value for failure. */
5773 /****************************************************************************/
5775 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5779 struct bce_softc *sc;
5782 error = sysctl_handle_int(oidp, &result, 0, req);
5784 if (error || !req->newptr)
5788 sc = (struct bce_softc *)arg1;
5789 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5796 /****************************************************************************/
5797 /* Provides a sysctl interface to allow reading arbitrary registers in the */
5798 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5801 /* 0 for success, positive value for failure. */
5802 /****************************************************************************/
5804 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5806 struct bce_softc *sc;
5808 uint32_t val, result;
5811 error = sysctl_handle_int(oidp, &result, 0, req);
5812 if (error || (req->newptr == NULL))
5815 /* Make sure the register is accessible. */
5816 if (result < 0x8000) {
5817 sc = (struct bce_softc *)arg1;
5818 val = REG_RD(sc, result);
5819 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5821 } else if (result < 0x0280000) {
5822 sc = (struct bce_softc *)arg1;
5823 val = REG_RD_IND(sc, result);
5824 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5831 /****************************************************************************/
5832 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
5833 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5836 /* 0 for success, positive value for failure. */
5837 /****************************************************************************/
5839 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5841 struct bce_softc *sc;
5847 error = sysctl_handle_int(oidp, &result, 0, req);
5848 if (error || (req->newptr == NULL))
5851 /* Make sure the register is accessible. */
5852 if (result < 0x20) {
5853 sc = (struct bce_softc *)arg1;
5855 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5856 if_printf(&sc->arpcom.ac_if,
5857 "phy 0x%02X = 0x%04X\n", result, val);
5863 /****************************************************************************/
5864 /* Provides a sysctl interface to forcing the driver to dump state and */
5865 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
5868 /* 0 for success, positive value for failure. */
5869 /****************************************************************************/
5871 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5875 struct bce_softc *sc;
5878 error = sysctl_handle_int(oidp, &result, 0, req);
5880 if (error || !req->newptr)
5884 sc = (struct bce_softc *)arg1;
5893 /****************************************************************************/
5894 /* Adds any sysctl parameters for tuning or debugging purposes. */
5897 /* 0 for success, positive value for failure. */
5898 /****************************************************************************/
5900 bce_add_sysctls(struct bce_softc *sc)
5902 struct sysctl_ctx_list *ctx;
5903 struct sysctl_oid_list *children;
5905 sysctl_ctx_init(&sc->bce_sysctl_ctx);
5906 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5907 SYSCTL_STATIC_CHILDREN(_hw),
5909 device_get_nameunit(sc->bce_dev),
5911 if (sc->bce_sysctl_tree == NULL) {
5912 device_printf(sc->bce_dev, "can't add sysctl node\n");
5916 ctx = &sc->bce_sysctl_ctx;
5917 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5919 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5920 CTLTYPE_INT | CTLFLAG_RW,
5921 sc, 0, bce_sysctl_tx_bds_int, "I",
5922 "Send max coalesced BD count during interrupt");
5923 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5924 CTLTYPE_INT | CTLFLAG_RW,
5925 sc, 0, bce_sysctl_tx_bds, "I",
5926 "Send max coalesced BD count");
5927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5928 CTLTYPE_INT | CTLFLAG_RW,
5929 sc, 0, bce_sysctl_tx_ticks_int, "I",
5930 "Send coalescing ticks during interrupt");
5931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5932 CTLTYPE_INT | CTLFLAG_RW,
5933 sc, 0, bce_sysctl_tx_ticks, "I",
5934 "Send coalescing ticks");
5936 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5937 CTLTYPE_INT | CTLFLAG_RW,
5938 sc, 0, bce_sysctl_rx_bds_int, "I",
5939 "Receive max coalesced BD count during interrupt");
5940 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5941 CTLTYPE_INT | CTLFLAG_RW,
5942 sc, 0, bce_sysctl_rx_bds, "I",
5943 "Receive max coalesced BD count");
5944 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5945 CTLTYPE_INT | CTLFLAG_RW,
5946 sc, 0, bce_sysctl_rx_ticks_int, "I",
5947 "Receive coalescing ticks during interrupt");
5948 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5949 CTLTYPE_INT | CTLFLAG_RW,
5950 sc, 0, bce_sysctl_rx_ticks, "I",
5951 "Receive coalescing ticks");
5954 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5956 CTLFLAG_RD, &sc->rx_low_watermark,
5957 0, "Lowest level of free rx_bd's");
5959 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5961 CTLFLAG_RD, &sc->rx_empty_count,
5962 0, "Number of times the RX chain was empty");
5964 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5966 CTLFLAG_RD, &sc->tx_hi_watermark,
5967 0, "Highest level of used tx_bd's");
5969 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5971 CTLFLAG_RD, &sc->tx_full_count,
5972 0, "Number of times the TX chain was full");
5974 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5975 "l2fhdr_status_errors",
5976 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5977 0, "l2_fhdr status errors");
5979 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5980 "unexpected_attentions",
5981 CTLFLAG_RD, &sc->unexpected_attentions,
5982 0, "unexpected attentions");
5984 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5985 "lost_status_block_updates",
5986 CTLFLAG_RD, &sc->lost_status_block_updates,
5987 0, "lost status block updates");
5989 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5990 "mbuf_alloc_failed",
5991 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5992 0, "mbuf cluster allocation failures");
5995 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5996 "stat_IfHCInOctets",
5997 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6000 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6001 "stat_IfHCInBadOctets",
6002 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6003 "Bad bytes received");
6005 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6006 "stat_IfHCOutOctets",
6007 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6010 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6011 "stat_IfHCOutBadOctets",
6012 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6015 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6016 "stat_IfHCInUcastPkts",
6017 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6018 "Unicast packets received");
6020 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6021 "stat_IfHCInMulticastPkts",
6022 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6023 "Multicast packets received");
6025 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6026 "stat_IfHCInBroadcastPkts",
6027 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6028 "Broadcast packets received");
6030 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6031 "stat_IfHCOutUcastPkts",
6032 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6033 "Unicast packets sent");
6035 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6036 "stat_IfHCOutMulticastPkts",
6037 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6038 "Multicast packets sent");
6040 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6041 "stat_IfHCOutBroadcastPkts",
6042 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6043 "Broadcast packets sent");
6045 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6046 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6047 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6048 0, "Internal MAC transmit errors");
6050 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6051 "stat_Dot3StatsCarrierSenseErrors",
6052 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6053 0, "Carrier sense errors");
6055 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6056 "stat_Dot3StatsFCSErrors",
6057 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6058 0, "Frame check sequence errors");
6060 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6061 "stat_Dot3StatsAlignmentErrors",
6062 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6063 0, "Alignment errors");
6065 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6066 "stat_Dot3StatsSingleCollisionFrames",
6067 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6068 0, "Single Collision Frames");
6070 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6071 "stat_Dot3StatsMultipleCollisionFrames",
6072 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6073 0, "Multiple Collision Frames");
6075 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6076 "stat_Dot3StatsDeferredTransmissions",
6077 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6078 0, "Deferred Transmissions");
6080 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6081 "stat_Dot3StatsExcessiveCollisions",
6082 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6083 0, "Excessive Collisions");
6085 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6086 "stat_Dot3StatsLateCollisions",
6087 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6088 0, "Late Collisions");
6090 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6091 "stat_EtherStatsCollisions",
6092 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6095 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6096 "stat_EtherStatsFragments",
6097 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6100 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6101 "stat_EtherStatsJabbers",
6102 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6105 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6106 "stat_EtherStatsUndersizePkts",
6107 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6108 0, "Undersize packets");
6110 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6111 "stat_EtherStatsOverrsizePkts",
6112 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6113 0, "stat_EtherStatsOverrsizePkts");
6115 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6116 "stat_EtherStatsPktsRx64Octets",
6117 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6118 0, "Bytes received in 64 byte packets");
6120 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6121 "stat_EtherStatsPktsRx65Octetsto127Octets",
6122 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6123 0, "Bytes received in 65 to 127 byte packets");
6125 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6126 "stat_EtherStatsPktsRx128Octetsto255Octets",
6127 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6128 0, "Bytes received in 128 to 255 byte packets");
6130 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6131 "stat_EtherStatsPktsRx256Octetsto511Octets",
6132 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6133 0, "Bytes received in 256 to 511 byte packets");
6135 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6136 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6137 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6138 0, "Bytes received in 512 to 1023 byte packets");
6140 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6141 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6142 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6143 0, "Bytes received in 1024 t0 1522 byte packets");
6145 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6146 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6147 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6148 0, "Bytes received in 1523 to 9022 byte packets");
6150 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6151 "stat_EtherStatsPktsTx64Octets",
6152 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6153 0, "Bytes sent in 64 byte packets");
6155 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6156 "stat_EtherStatsPktsTx65Octetsto127Octets",
6157 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6158 0, "Bytes sent in 65 to 127 byte packets");
6160 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6161 "stat_EtherStatsPktsTx128Octetsto255Octets",
6162 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6163 0, "Bytes sent in 128 to 255 byte packets");
6165 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6166 "stat_EtherStatsPktsTx256Octetsto511Octets",
6167 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6168 0, "Bytes sent in 256 to 511 byte packets");
6170 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6171 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6172 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6173 0, "Bytes sent in 512 to 1023 byte packets");
6175 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6176 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6177 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6178 0, "Bytes sent in 1024 to 1522 byte packets");
6180 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6181 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6182 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6183 0, "Bytes sent in 1523 to 9022 byte packets");
6185 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6186 "stat_XonPauseFramesReceived",
6187 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6188 0, "XON pause frames receved");
6190 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6191 "stat_XoffPauseFramesReceived",
6192 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6193 0, "XOFF pause frames received");
6195 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6197 CTLFLAG_RD, &sc->stat_OutXonSent,
6198 0, "XON pause frames sent");
6200 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6202 CTLFLAG_RD, &sc->stat_OutXoffSent,
6203 0, "XOFF pause frames sent");
6205 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6206 "stat_FlowControlDone",
6207 CTLFLAG_RD, &sc->stat_FlowControlDone,
6208 0, "Flow control done");
6210 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6211 "stat_MacControlFramesReceived",
6212 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6213 0, "MAC control frames received");
6215 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6216 "stat_XoffStateEntered",
6217 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6218 0, "XOFF state entered");
6220 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6221 "stat_IfInFramesL2FilterDiscards",
6222 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6223 0, "Received L2 packets discarded");
6225 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6226 "stat_IfInRuleCheckerDiscards",
6227 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6228 0, "Received packets discarded by rule");
6230 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6231 "stat_IfInFTQDiscards",
6232 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6233 0, "Received packet FTQ discards");
6235 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6236 "stat_IfInMBUFDiscards",
6237 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6238 0, "Received packets discarded due to lack of controller buffer memory");
6240 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6241 "stat_IfInRuleCheckerP4Hit",
6242 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6243 0, "Received packets rule checker hits");
6245 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6246 "stat_CatchupInRuleCheckerDiscards",
6247 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6248 0, "Received packets discarded in Catchup path");
6250 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6251 "stat_CatchupInFTQDiscards",
6252 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6253 0, "Received packets discarded in FTQ in Catchup path");
6255 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6256 "stat_CatchupInMBUFDiscards",
6257 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6258 0, "Received packets discarded in controller buffer memory in Catchup path");
6260 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6261 "stat_CatchupInRuleCheckerP4Hit",
6262 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6263 0, "Received packets rule checker hits in Catchup path");
6265 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6267 CTLFLAG_RD, &sc->com_no_buffers,
6268 0, "Valid packets received but no RX buffers available");
6271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6272 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6274 bce_sysctl_driver_state, "I", "Drive state information");
6276 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6277 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6279 bce_sysctl_hw_state, "I", "Hardware state information");
6281 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6282 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6284 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6286 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6287 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6289 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6291 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6292 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6294 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6296 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6297 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6299 bce_sysctl_reg_read, "I", "Register read");
6301 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6302 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6304 bce_sysctl_phy_read, "I", "PHY register read");
6311 /****************************************************************************/
6312 /* BCE Debug Routines */
6313 /****************************************************************************/
6316 /****************************************************************************/
6317 /* Freezes the controller to allow for a cohesive state dump. */
6321 /****************************************************************************/
6323 bce_freeze_controller(struct bce_softc *sc)
6327 val = REG_RD(sc, BCE_MISC_COMMAND);
6328 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6329 REG_WR(sc, BCE_MISC_COMMAND, val);
6333 /****************************************************************************/
6334 /* Unfreezes the controller after a freeze operation. This may not always */
6335 /* work and the controller will require a reset! */
6339 /****************************************************************************/
6341 bce_unfreeze_controller(struct bce_softc *sc)
6345 val = REG_RD(sc, BCE_MISC_COMMAND);
6346 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6347 REG_WR(sc, BCE_MISC_COMMAND, val);
6351 /****************************************************************************/
6352 /* Prints out information about an mbuf. */
6356 /****************************************************************************/
6358 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6360 struct ifnet *ifp = &sc->arpcom.ac_if;
6361 uint32_t val_hi, val_lo;
6362 struct mbuf *mp = m;
6365 /* Index out of range. */
6366 if_printf(ifp, "mbuf: null pointer\n");
6371 val_hi = BCE_ADDR_HI(mp);
6372 val_lo = BCE_ADDR_LO(mp);
6373 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6374 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6376 if (mp->m_flags & M_EXT)
6378 if (mp->m_flags & M_PKTHDR)
6379 kprintf("M_PKTHDR ");
6380 if (mp->m_flags & M_EOR)
6383 if (mp->m_flags & M_RDONLY)
6384 kprintf("M_RDONLY ");
6387 val_hi = BCE_ADDR_HI(mp->m_data);
6388 val_lo = BCE_ADDR_LO(mp->m_data);
6389 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6391 if (mp->m_flags & M_PKTHDR) {
6392 if_printf(ifp, "- m_pkthdr: flags = ( ");
6393 if (mp->m_flags & M_BCAST)
6394 kprintf("M_BCAST ");
6395 if (mp->m_flags & M_MCAST)
6396 kprintf("M_MCAST ");
6397 if (mp->m_flags & M_FRAG)
6399 if (mp->m_flags & M_FIRSTFRAG)
6400 kprintf("M_FIRSTFRAG ");
6401 if (mp->m_flags & M_LASTFRAG)
6402 kprintf("M_LASTFRAG ");
6404 if (mp->m_flags & M_VLANTAG)
6405 kprintf("M_VLANTAG ");
6408 if (mp->m_flags & M_PROMISC)
6409 kprintf("M_PROMISC ");
6411 kprintf(") csum_flags = ( ");
6412 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6413 kprintf("CSUM_IP ");
6414 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6415 kprintf("CSUM_TCP ");
6416 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6417 kprintf("CSUM_UDP ");
6418 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6419 kprintf("CSUM_IP_FRAGS ");
6420 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6421 kprintf("CSUM_FRAGMENT ");
6423 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6424 kprintf("CSUM_TSO ");
6426 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6427 kprintf("CSUM_IP_CHECKED ");
6428 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6429 kprintf("CSUM_IP_VALID ");
6430 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6431 kprintf("CSUM_DATA_VALID ");
6435 if (mp->m_flags & M_EXT) {
6436 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6437 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6438 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6440 val_hi, val_lo, mp->m_ext.ext_size);
6447 /****************************************************************************/
6448 /* Prints out the mbufs in the TX mbuf chain. */
6452 /****************************************************************************/
6454 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6456 struct ifnet *ifp = &sc->arpcom.ac_if;
6460 "----------------------------"
6462 "----------------------------\n");
6464 for (i = 0; i < count; i++) {
6465 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6466 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6467 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6471 "----------------------------"
6473 "----------------------------\n");
6477 /****************************************************************************/
6478 /* Prints out the mbufs in the RX mbuf chain. */
6482 /****************************************************************************/
6484 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6486 struct ifnet *ifp = &sc->arpcom.ac_if;
6490 "----------------------------"
6492 "----------------------------\n");
6494 for (i = 0; i < count; i++) {
6495 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6496 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6497 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6501 "----------------------------"
6503 "----------------------------\n");
6507 /****************************************************************************/
6508 /* Prints out a tx_bd structure. */
6512 /****************************************************************************/
6514 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6516 struct ifnet *ifp = &sc->arpcom.ac_if;
6518 if (idx > MAX_TX_BD) {
6519 /* Index out of range. */
6520 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6521 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6522 /* TX Chain page pointer. */
6523 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6524 "chain page pointer\n",
6525 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6527 /* Normal tx_bd entry. */
6528 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6530 "vlan tag= 0x%04X, flags = 0x%04X (",
6531 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6532 txbd->tx_bd_mss_nbytes,
6533 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6535 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6536 kprintf(" CONN_FAULT");
6538 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6539 kprintf(" TCP_UDP_CKSUM");
6541 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6542 kprintf(" IP_CKSUM");
6544 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6547 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6548 kprintf(" COAL_NOW");
6550 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6551 kprintf(" DONT_GEN_CRC");
6553 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6556 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6559 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6562 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6563 kprintf(" OPTION_WORD");
6565 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6568 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6576 /****************************************************************************/
6577 /* Prints out a rx_bd structure. */
6581 /****************************************************************************/
6583 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6585 struct ifnet *ifp = &sc->arpcom.ac_if;
6587 if (idx > MAX_RX_BD) {
6588 /* Index out of range. */
6589 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6590 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6591 /* TX Chain page pointer. */
6592 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6593 "chain page pointer\n",
6594 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6596 /* Normal tx_bd entry. */
6597 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6598 "nbytes = 0x%08X, flags = 0x%08X\n",
6599 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6600 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6605 /****************************************************************************/
6606 /* Prints out a l2_fhdr structure. */
6610 /****************************************************************************/
6612 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6614 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6615 "pkt_len = 0x%04X, vlan = 0x%04x, "
6616 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6617 idx, l2fhdr->l2_fhdr_status,
6618 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6619 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6623 /****************************************************************************/
6624 /* Prints out the tx chain. */
6628 /****************************************************************************/
6630 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6632 struct ifnet *ifp = &sc->arpcom.ac_if;
6635 /* First some info about the tx_bd chain structure. */
6637 "----------------------------"
6639 "----------------------------\n");
6641 if_printf(ifp, "page size = 0x%08X, "
6642 "tx chain pages = 0x%08X\n",
6643 (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6645 if_printf(ifp, "tx_bd per page = 0x%08X, "
6646 "usable tx_bd per page = 0x%08X\n",
6647 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6648 (uint32_t)USABLE_TX_BD_PER_PAGE);
6650 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6653 "----------------------------"
6655 "----------------------------\n");
6657 /* Now print out the tx_bd's themselves. */
6658 for (i = 0; i < count; i++) {
6661 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6662 bce_dump_txbd(sc, tx_prod, txbd);
6663 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6667 "----------------------------"
6669 "----------------------------\n");
6673 /****************************************************************************/
6674 /* Prints out the rx chain. */
6678 /****************************************************************************/
6680 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6682 struct ifnet *ifp = &sc->arpcom.ac_if;
6685 /* First some info about the tx_bd chain structure. */
6687 "----------------------------"
6689 "----------------------------\n");
6691 if_printf(ifp, "page size = 0x%08X, "
6692 "rx chain pages = 0x%08X\n",
6693 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6695 if_printf(ifp, "rx_bd per page = 0x%08X, "
6696 "usable rx_bd per page = 0x%08X\n",
6697 (uint32_t)TOTAL_RX_BD_PER_PAGE,
6698 (uint32_t)USABLE_RX_BD_PER_PAGE);
6700 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6703 "----------------------------"
6705 "----------------------------\n");
6707 /* Now print out the rx_bd's themselves. */
6708 for (i = 0; i < count; i++) {
6711 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6712 bce_dump_rxbd(sc, rx_prod, rxbd);
6713 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6717 "----------------------------"
6719 "----------------------------\n");
6723 /****************************************************************************/
6724 /* Prints out the status block from host memory. */
6728 /****************************************************************************/
6730 bce_dump_status_block(struct bce_softc *sc)
6732 struct status_block *sblk = sc->status_block;
6733 struct ifnet *ifp = &sc->arpcom.ac_if;
6736 "----------------------------"
6738 "----------------------------\n");
6740 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
6742 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
6743 sblk->status_attn_bits_ack);
6745 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6746 sblk->status_rx_quick_consumer_index0,
6747 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6749 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6750 sblk->status_tx_quick_consumer_index0,
6751 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6753 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
6755 /* Theses indices are not used for normal L2 drivers. */
6756 if (sblk->status_rx_quick_consumer_index1) {
6757 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6758 sblk->status_rx_quick_consumer_index1,
6759 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6762 if (sblk->status_tx_quick_consumer_index1) {
6763 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6764 sblk->status_tx_quick_consumer_index1,
6765 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6768 if (sblk->status_rx_quick_consumer_index2) {
6769 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6770 sblk->status_rx_quick_consumer_index2,
6771 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6774 if (sblk->status_tx_quick_consumer_index2) {
6775 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6776 sblk->status_tx_quick_consumer_index2,
6777 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6780 if (sblk->status_rx_quick_consumer_index3) {
6781 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6782 sblk->status_rx_quick_consumer_index3,
6783 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6786 if (sblk->status_tx_quick_consumer_index3) {
6787 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6788 sblk->status_tx_quick_consumer_index3,
6789 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6792 if (sblk->status_rx_quick_consumer_index4 ||
6793 sblk->status_rx_quick_consumer_index5) {
6794 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
6795 sblk->status_rx_quick_consumer_index4,
6796 sblk->status_rx_quick_consumer_index5);
6799 if (sblk->status_rx_quick_consumer_index6 ||
6800 sblk->status_rx_quick_consumer_index7) {
6801 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
6802 sblk->status_rx_quick_consumer_index6,
6803 sblk->status_rx_quick_consumer_index7);
6806 if (sblk->status_rx_quick_consumer_index8 ||
6807 sblk->status_rx_quick_consumer_index9) {
6808 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
6809 sblk->status_rx_quick_consumer_index8,
6810 sblk->status_rx_quick_consumer_index9);
6813 if (sblk->status_rx_quick_consumer_index10 ||
6814 sblk->status_rx_quick_consumer_index11) {
6815 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
6816 sblk->status_rx_quick_consumer_index10,
6817 sblk->status_rx_quick_consumer_index11);
6820 if (sblk->status_rx_quick_consumer_index12 ||
6821 sblk->status_rx_quick_consumer_index13) {
6822 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
6823 sblk->status_rx_quick_consumer_index12,
6824 sblk->status_rx_quick_consumer_index13);
6827 if (sblk->status_rx_quick_consumer_index14 ||
6828 sblk->status_rx_quick_consumer_index15) {
6829 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
6830 sblk->status_rx_quick_consumer_index14,
6831 sblk->status_rx_quick_consumer_index15);
6834 if (sblk->status_completion_producer_index ||
6835 sblk->status_cmd_consumer_index) {
6836 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
6837 sblk->status_completion_producer_index,
6838 sblk->status_cmd_consumer_index);
6842 "----------------------------"
6844 "----------------------------\n");
6848 /****************************************************************************/
6849 /* Prints out the statistics block. */
6853 /****************************************************************************/
6855 bce_dump_stats_block(struct bce_softc *sc)
6857 struct statistics_block *sblk = sc->stats_block;
6858 struct ifnet *ifp = &sc->arpcom.ac_if;
6862 " Stats Block (All Stats Not Shown Are 0) "
6863 "---------------\n");
6865 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6866 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6867 sblk->stat_IfHCInOctets_hi,
6868 sblk->stat_IfHCInOctets_lo);
6871 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6872 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6873 sblk->stat_IfHCInBadOctets_hi,
6874 sblk->stat_IfHCInBadOctets_lo);
6877 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6878 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6879 sblk->stat_IfHCOutOctets_hi,
6880 sblk->stat_IfHCOutOctets_lo);
6883 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6884 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6885 sblk->stat_IfHCOutBadOctets_hi,
6886 sblk->stat_IfHCOutBadOctets_lo);
6889 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6890 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6891 sblk->stat_IfHCInUcastPkts_hi,
6892 sblk->stat_IfHCInUcastPkts_lo);
6895 if (sblk->stat_IfHCInBroadcastPkts_hi ||
6896 sblk->stat_IfHCInBroadcastPkts_lo) {
6897 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6898 sblk->stat_IfHCInBroadcastPkts_hi,
6899 sblk->stat_IfHCInBroadcastPkts_lo);
6902 if (sblk->stat_IfHCInMulticastPkts_hi ||
6903 sblk->stat_IfHCInMulticastPkts_lo) {
6904 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6905 sblk->stat_IfHCInMulticastPkts_hi,
6906 sblk->stat_IfHCInMulticastPkts_lo);
6909 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6910 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6911 sblk->stat_IfHCOutUcastPkts_hi,
6912 sblk->stat_IfHCOutUcastPkts_lo);
6915 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6916 sblk->stat_IfHCOutBroadcastPkts_lo) {
6917 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6918 sblk->stat_IfHCOutBroadcastPkts_hi,
6919 sblk->stat_IfHCOutBroadcastPkts_lo);
6922 if (sblk->stat_IfHCOutMulticastPkts_hi ||
6923 sblk->stat_IfHCOutMulticastPkts_lo) {
6924 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6925 sblk->stat_IfHCOutMulticastPkts_hi,
6926 sblk->stat_IfHCOutMulticastPkts_lo);
6929 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6930 if_printf(ifp, " 0x%08X : "
6931 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6932 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6935 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6936 if_printf(ifp, " 0x%08X : "
6937 "Dot3StatsCarrierSenseErrors\n",
6938 sblk->stat_Dot3StatsCarrierSenseErrors);
6941 if (sblk->stat_Dot3StatsFCSErrors) {
6942 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
6943 sblk->stat_Dot3StatsFCSErrors);
6946 if (sblk->stat_Dot3StatsAlignmentErrors) {
6947 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
6948 sblk->stat_Dot3StatsAlignmentErrors);
6951 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6952 if_printf(ifp, " 0x%08X : "
6953 "Dot3StatsSingleCollisionFrames\n",
6954 sblk->stat_Dot3StatsSingleCollisionFrames);
6957 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6958 if_printf(ifp, " 0x%08X : "
6959 "Dot3StatsMultipleCollisionFrames\n",
6960 sblk->stat_Dot3StatsMultipleCollisionFrames);
6963 if (sblk->stat_Dot3StatsDeferredTransmissions) {
6964 if_printf(ifp, " 0x%08X : "
6965 "Dot3StatsDeferredTransmissions\n",
6966 sblk->stat_Dot3StatsDeferredTransmissions);
6969 if (sblk->stat_Dot3StatsExcessiveCollisions) {
6970 if_printf(ifp, " 0x%08X : "
6971 "Dot3StatsExcessiveCollisions\n",
6972 sblk->stat_Dot3StatsExcessiveCollisions);
6975 if (sblk->stat_Dot3StatsLateCollisions) {
6976 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
6977 sblk->stat_Dot3StatsLateCollisions);
6980 if (sblk->stat_EtherStatsCollisions) {
6981 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
6982 sblk->stat_EtherStatsCollisions);
6985 if (sblk->stat_EtherStatsFragments) {
6986 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
6987 sblk->stat_EtherStatsFragments);
6990 if (sblk->stat_EtherStatsJabbers) {
6991 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
6992 sblk->stat_EtherStatsJabbers);
6995 if (sblk->stat_EtherStatsUndersizePkts) {
6996 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
6997 sblk->stat_EtherStatsUndersizePkts);
7000 if (sblk->stat_EtherStatsOverrsizePkts) {
7001 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7002 sblk->stat_EtherStatsOverrsizePkts);
7005 if (sblk->stat_EtherStatsPktsRx64Octets) {
7006 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7007 sblk->stat_EtherStatsPktsRx64Octets);
7010 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7011 if_printf(ifp, " 0x%08X : "
7012 "EtherStatsPktsRx65Octetsto127Octets\n",
7013 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7016 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7017 if_printf(ifp, " 0x%08X : "
7018 "EtherStatsPktsRx128Octetsto255Octets\n",
7019 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7022 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7023 if_printf(ifp, " 0x%08X : "
7024 "EtherStatsPktsRx256Octetsto511Octets\n",
7025 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7028 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7029 if_printf(ifp, " 0x%08X : "
7030 "EtherStatsPktsRx512Octetsto1023Octets\n",
7031 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7034 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7035 if_printf(ifp, " 0x%08X : "
7036 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7037 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7040 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7041 if_printf(ifp, " 0x%08X : "
7042 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7043 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7046 if (sblk->stat_EtherStatsPktsTx64Octets) {
7047 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7048 sblk->stat_EtherStatsPktsTx64Octets);
7051 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7052 if_printf(ifp, " 0x%08X : "
7053 "EtherStatsPktsTx65Octetsto127Octets\n",
7054 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7057 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7058 if_printf(ifp, " 0x%08X : "
7059 "EtherStatsPktsTx128Octetsto255Octets\n",
7060 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7063 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7064 if_printf(ifp, " 0x%08X : "
7065 "EtherStatsPktsTx256Octetsto511Octets\n",
7066 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7069 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7070 if_printf(ifp, " 0x%08X : "
7071 "EtherStatsPktsTx512Octetsto1023Octets\n",
7072 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7075 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7076 if_printf(ifp, " 0x%08X : "
7077 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7078 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7081 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7082 if_printf(ifp, " 0x%08X : "
7083 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7084 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7087 if (sblk->stat_XonPauseFramesReceived) {
7088 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7089 sblk->stat_XonPauseFramesReceived);
7092 if (sblk->stat_XoffPauseFramesReceived) {
7093 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7094 sblk->stat_XoffPauseFramesReceived);
7097 if (sblk->stat_OutXonSent) {
7098 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7099 sblk->stat_OutXonSent);
7102 if (sblk->stat_OutXoffSent) {
7103 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7104 sblk->stat_OutXoffSent);
7107 if (sblk->stat_FlowControlDone) {
7108 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7109 sblk->stat_FlowControlDone);
7112 if (sblk->stat_MacControlFramesReceived) {
7113 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7114 sblk->stat_MacControlFramesReceived);
7117 if (sblk->stat_XoffStateEntered) {
7118 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7119 sblk->stat_XoffStateEntered);
7122 if (sblk->stat_IfInFramesL2FilterDiscards) {
7123 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7126 if (sblk->stat_IfInRuleCheckerDiscards) {
7127 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7128 sblk->stat_IfInRuleCheckerDiscards);
7131 if (sblk->stat_IfInFTQDiscards) {
7132 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7133 sblk->stat_IfInFTQDiscards);
7136 if (sblk->stat_IfInMBUFDiscards) {
7137 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7138 sblk->stat_IfInMBUFDiscards);
7141 if (sblk->stat_IfInRuleCheckerP4Hit) {
7142 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7143 sblk->stat_IfInRuleCheckerP4Hit);
7146 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7147 if_printf(ifp, " 0x%08X : "
7148 "CatchupInRuleCheckerDiscards\n",
7149 sblk->stat_CatchupInRuleCheckerDiscards);
7152 if (sblk->stat_CatchupInFTQDiscards) {
7153 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7154 sblk->stat_CatchupInFTQDiscards);
7157 if (sblk->stat_CatchupInMBUFDiscards) {
7158 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7159 sblk->stat_CatchupInMBUFDiscards);
7162 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7163 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7164 sblk->stat_CatchupInRuleCheckerP4Hit);
7168 "----------------------------"
7170 "----------------------------\n");
7174 /****************************************************************************/
7175 /* Prints out a summary of the driver state. */
7179 /****************************************************************************/
7181 bce_dump_driver_state(struct bce_softc *sc)
7183 struct ifnet *ifp = &sc->arpcom.ac_if;
7184 uint32_t val_hi, val_lo;
7187 "-----------------------------"
7189 "-----------------------------\n");
7191 val_hi = BCE_ADDR_HI(sc);
7192 val_lo = BCE_ADDR_LO(sc);
7193 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7194 "virtual address\n", val_hi, val_lo);
7196 val_hi = BCE_ADDR_HI(sc->status_block);
7197 val_lo = BCE_ADDR_LO(sc->status_block);
7198 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7199 "virtual address\n", val_hi, val_lo);
7201 val_hi = BCE_ADDR_HI(sc->stats_block);
7202 val_lo = BCE_ADDR_LO(sc->stats_block);
7203 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7204 "virtual address\n", val_hi, val_lo);
7206 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7207 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7208 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7209 "virtual adddress\n", val_hi, val_lo);
7211 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7212 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7213 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7214 "virtual address\n", val_hi, val_lo);
7216 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7217 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7218 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7219 "virtual address\n", val_hi, val_lo);
7221 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7222 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7223 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7224 "virtual address\n", val_hi, val_lo);
7226 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7227 "h/w intrs\n", sc->interrupts_generated);
7229 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7230 "rx interrupts handled\n", sc->rx_interrupts);
7232 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7233 "tx interrupts handled\n", sc->tx_interrupts);
7235 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7236 "status block index\n", sc->last_status_idx);
7238 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7239 "tx producer index\n",
7240 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7242 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7243 "tx consumer index\n",
7244 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7246 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7247 "tx producer bseq index\n", sc->tx_prod_bseq);
7249 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7250 "rx producer index\n",
7251 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7253 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7254 "rx consumer index\n",
7255 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7257 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7258 "rx producer bseq index\n", sc->rx_prod_bseq);
7260 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7261 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7263 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7264 "free rx_bd's\n", sc->free_rx_bd);
7266 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7267 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7269 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7270 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7272 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7273 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7275 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7278 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7279 sc->tx_hi_watermark, sc->max_tx_bd);
7281 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7282 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7285 "----------------------------"
7287 "----------------------------\n");
7291 /****************************************************************************/
7292 /* Prints out the hardware state through a summary of important registers, */
7293 /* followed by a complete register dump. */
7297 /****************************************************************************/
7299 bce_dump_hw_state(struct bce_softc *sc)
7301 struct ifnet *ifp = &sc->arpcom.ac_if;
7306 "----------------------------"
7308 "----------------------------\n");
7310 if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
7312 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7313 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7314 val1, BCE_MISC_ENABLE_STATUS_BITS);
7316 val1 = REG_RD(sc, BCE_DMA_STATUS);
7317 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7319 val1 = REG_RD(sc, BCE_CTX_STATUS);
7320 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7322 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7323 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7324 val1, BCE_EMAC_STATUS);
7326 val1 = REG_RD(sc, BCE_RPM_STATUS);
7327 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7329 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7330 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7331 val1, BCE_TBDR_STATUS);
7333 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7334 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7335 val1, BCE_TDMA_STATUS);
7337 val1 = REG_RD(sc, BCE_HC_STATUS);
7338 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7340 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7341 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7342 val1, BCE_TXP_CPU_STATE);
7344 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7345 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7346 val1, BCE_TPAT_CPU_STATE);
7348 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7349 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7350 val1, BCE_RXP_CPU_STATE);
7352 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7353 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7354 val1, BCE_COM_CPU_STATE);
7356 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7357 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7358 val1, BCE_MCP_CPU_STATE);
7360 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7361 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7362 val1, BCE_CP_CPU_STATE);
7365 "----------------------------"
7367 "----------------------------\n");
7370 "----------------------------"
7372 "----------------------------\n");
7374 for (i = 0x400; i < 0x8000; i += 0x10) {
7375 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7377 REG_RD(sc, i + 0x4),
7378 REG_RD(sc, i + 0x8),
7379 REG_RD(sc, i + 0xc));
7383 "----------------------------"
7385 "----------------------------\n");
7389 /****************************************************************************/
7390 /* Prints out the TXP state. */
7394 /****************************************************************************/
7396 bce_dump_txp_state(struct bce_softc *sc)
7398 struct ifnet *ifp = &sc->arpcom.ac_if;
7403 "----------------------------"
7405 "----------------------------\n");
7407 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7408 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7409 val1, BCE_TXP_CPU_MODE);
7411 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7412 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7413 val1, BCE_TXP_CPU_STATE);
7415 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7416 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7417 val1, BCE_TXP_CPU_EVENT_MASK);
7420 "----------------------------"
7422 "----------------------------\n");
7424 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7425 /* Skip the big blank spaces */
7426 if (i < 0x454000 && i > 0x5ffff) {
7427 if_printf(ifp, "0x%04X: "
7428 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7430 REG_RD_IND(sc, i + 0x4),
7431 REG_RD_IND(sc, i + 0x8),
7432 REG_RD_IND(sc, i + 0xc));
7437 "----------------------------"
7439 "----------------------------\n");
7443 /****************************************************************************/
7444 /* Prints out the RXP state. */
7448 /****************************************************************************/
7450 bce_dump_rxp_state(struct bce_softc *sc)
7452 struct ifnet *ifp = &sc->arpcom.ac_if;
7457 "----------------------------"
7459 "----------------------------\n");
7461 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7462 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7463 val1, BCE_RXP_CPU_MODE);
7465 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7466 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7467 val1, BCE_RXP_CPU_STATE);
7469 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7470 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7471 val1, BCE_RXP_CPU_EVENT_MASK);
7474 "----------------------------"
7476 "----------------------------\n");
7478 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7479 /* Skip the big blank sapces */
7480 if (i < 0xc5400 && i > 0xdffff) {
7481 if_printf(ifp, "0x%04X: "
7482 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7484 REG_RD_IND(sc, i + 0x4),
7485 REG_RD_IND(sc, i + 0x8),
7486 REG_RD_IND(sc, i + 0xc));
7491 "----------------------------"
7493 "----------------------------\n");
7497 /****************************************************************************/
7498 /* Prints out the TPAT state. */
7502 /****************************************************************************/
7504 bce_dump_tpat_state(struct bce_softc *sc)
7506 struct ifnet *ifp = &sc->arpcom.ac_if;
7511 "----------------------------"
7513 "----------------------------\n");
7515 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7516 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7517 val1, BCE_TPAT_CPU_MODE);
7519 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7520 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7521 val1, BCE_TPAT_CPU_STATE);
7523 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7524 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7525 val1, BCE_TPAT_CPU_EVENT_MASK);
7528 "----------------------------"
7530 "----------------------------\n");
7532 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7533 /* Skip the big blank spaces */
7534 if (i < 0x854000 && i > 0x9ffff) {
7535 if_printf(ifp, "0x%04X: "
7536 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7538 REG_RD_IND(sc, i + 0x4),
7539 REG_RD_IND(sc, i + 0x8),
7540 REG_RD_IND(sc, i + 0xc));
7545 "----------------------------"
7547 "----------------------------\n");
7551 /****************************************************************************/
7552 /* Prints out the driver state and then enters the debugger. */
7556 /****************************************************************************/
7558 bce_breakpoint(struct bce_softc *sc)
7561 bce_freeze_controller(sc);
7564 bce_dump_driver_state(sc);
7565 bce_dump_status_block(sc);
7566 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7567 bce_dump_hw_state(sc);
7568 bce_dump_txp_state(sc);
7571 bce_unfreeze_controller(sc);
7574 /* Call the debugger. */
7578 #endif /* BCE_DEBUG */
7581 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7583 struct bce_softc *sc = arg1;
7585 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7586 &sc->bce_tx_quick_cons_trip_int,
7587 BCE_COALMASK_TX_BDS_INT);
7591 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7593 struct bce_softc *sc = arg1;
7595 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7596 &sc->bce_tx_quick_cons_trip,
7597 BCE_COALMASK_TX_BDS);
7601 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7603 struct bce_softc *sc = arg1;
7605 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7606 &sc->bce_tx_ticks_int,
7607 BCE_COALMASK_TX_TICKS_INT);
7611 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7613 struct bce_softc *sc = arg1;
7615 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7617 BCE_COALMASK_TX_TICKS);
7621 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7623 struct bce_softc *sc = arg1;
7625 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7626 &sc->bce_rx_quick_cons_trip_int,
7627 BCE_COALMASK_RX_BDS_INT);
7631 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7633 struct bce_softc *sc = arg1;
7635 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7636 &sc->bce_rx_quick_cons_trip,
7637 BCE_COALMASK_RX_BDS);
7641 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7643 struct bce_softc *sc = arg1;
7645 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7646 &sc->bce_rx_ticks_int,
7647 BCE_COALMASK_RX_TICKS_INT);
7651 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7653 struct bce_softc *sc = arg1;
7655 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7657 BCE_COALMASK_RX_TICKS);
7661 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7662 uint32_t coalchg_mask)
7664 struct bce_softc *sc = arg1;
7665 struct ifnet *ifp = &sc->arpcom.ac_if;
7668 lwkt_serialize_enter(ifp->if_serializer);
7671 error = sysctl_handle_int(oidp, &v, 0, req);
7672 if (!error && req->newptr != NULL) {
7677 sc->bce_coalchg_mask |= coalchg_mask;
7681 lwkt_serialize_exit(ifp->if_serializer);
7686 bce_coal_change(struct bce_softc *sc)
7688 struct ifnet *ifp = &sc->arpcom.ac_if;
7690 ASSERT_SERIALIZED(ifp->if_serializer);
7692 if ((ifp->if_flags & IFF_RUNNING) == 0) {
7693 sc->bce_coalchg_mask = 0;
7697 if (sc->bce_coalchg_mask &
7698 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7699 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7700 (sc->bce_tx_quick_cons_trip_int << 16) |
7701 sc->bce_tx_quick_cons_trip);
7703 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7704 sc->bce_tx_quick_cons_trip,
7705 sc->bce_tx_quick_cons_trip_int);
7709 if (sc->bce_coalchg_mask &
7710 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7711 REG_WR(sc, BCE_HC_TX_TICKS,
7712 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7714 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7715 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7719 if (sc->bce_coalchg_mask &
7720 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7721 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7722 (sc->bce_rx_quick_cons_trip_int << 16) |
7723 sc->bce_rx_quick_cons_trip);
7725 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7726 sc->bce_rx_quick_cons_trip,
7727 sc->bce_rx_quick_cons_trip_int);
7731 if (sc->bce_coalchg_mask &
7732 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7733 REG_WR(sc, BCE_HC_RX_TICKS,
7734 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7736 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7737 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7741 sc->bce_coalchg_mask = 0;