2 * Copyright 2011 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Christian König <deathsimple@vodafone.de>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
38 /* 1 second timeout */
39 #define UVD_IDLE_TIMEOUT_MS 1000
42 #define FIRMWARE_RV710 "radeonkmsfw_RV710_uvd"
43 #define FIRMWARE_CYPRESS "radeonkmsfw_CYPRESS_uvd"
44 #define FIRMWARE_SUMO "radeonkmsfw_SUMO_uvd"
45 #define FIRMWARE_TAHITI "radeonkmsfw_TAHITI_uvd"
46 #define FIRMWARE_BONAIRE "radeonkmsfw_BONAIRE_uvd"
48 MODULE_FIRMWARE(FIRMWARE_RV710);
49 MODULE_FIRMWARE(FIRMWARE_CYPRESS);
50 MODULE_FIRMWARE(FIRMWARE_SUMO);
51 MODULE_FIRMWARE(FIRMWARE_TAHITI);
52 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
54 static void radeon_uvd_idle_work_handler(struct work_struct *work);
56 int radeon_uvd_init(struct radeon_device *rdev)
58 unsigned long bo_size;
62 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
64 switch (rdev->family) {
68 fw_name = FIRMWARE_RV710;
76 fw_name = FIRMWARE_CYPRESS;
86 fw_name = FIRMWARE_SUMO;
94 fw_name = FIRMWARE_TAHITI;
102 fw_name = FIRMWARE_BONAIRE;
109 r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev);
111 dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n",
116 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 8) +
117 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE +
118 RADEON_GPU_PAGE_SIZE;
119 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
120 RADEON_GEM_DOMAIN_VRAM, 0, NULL, &rdev->uvd.vcpu_bo);
122 dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r);
126 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
128 radeon_bo_unref(&rdev->uvd.vcpu_bo);
129 dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r);
133 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
134 &rdev->uvd.gpu_addr);
136 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
137 radeon_bo_unref(&rdev->uvd.vcpu_bo);
138 dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r);
142 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr);
144 dev_err(rdev->dev, "(%d) UVD map failed\n", r);
148 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
150 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
151 atomic_set(&rdev->uvd.handles[i], 0);
152 rdev->uvd.filp[i] = NULL;
153 rdev->uvd.img_size[i] = 0;
159 void radeon_uvd_fini(struct radeon_device *rdev)
163 if (rdev->uvd.vcpu_bo == NULL)
166 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false);
168 radeon_bo_kunmap(rdev->uvd.vcpu_bo);
169 radeon_bo_unpin(rdev->uvd.vcpu_bo);
170 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
173 radeon_bo_unref(&rdev->uvd.vcpu_bo);
175 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
177 release_firmware(rdev->uvd_fw);
180 int radeon_uvd_suspend(struct radeon_device *rdev)
186 if (rdev->uvd.vcpu_bo == NULL)
189 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
190 if (atomic_read(&rdev->uvd.handles[i]))
193 if (i == RADEON_MAX_UVD_HANDLES)
196 size = radeon_bo_size(rdev->uvd.vcpu_bo);
197 size -= rdev->uvd_fw->datasize;
199 ptr = rdev->uvd.cpu_addr;
200 ptr += rdev->uvd_fw->datasize;
202 rdev->uvd.saved_bo = kmalloc(size, M_DRM, M_WAITOK);
203 memcpy(rdev->uvd.saved_bo, ptr, size);
208 int radeon_uvd_resume(struct radeon_device *rdev)
213 if (rdev->uvd.vcpu_bo == NULL)
216 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->datasize);
218 size = radeon_bo_size(rdev->uvd.vcpu_bo);
219 size -= rdev->uvd_fw->datasize;
221 ptr = rdev->uvd.cpu_addr;
222 ptr += rdev->uvd_fw->datasize;
224 if (rdev->uvd.saved_bo != NULL) {
225 memcpy(ptr, rdev->uvd.saved_bo, size);
226 kfree(rdev->uvd.saved_bo);
227 rdev->uvd.saved_bo = NULL;
229 memset(ptr, 0, size);
234 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo)
236 rbo->placement.fpfn = 0 >> PAGE_SHIFT;
237 rbo->placement.lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT;
240 void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp)
243 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
244 uint32_t handle = atomic_read(&rdev->uvd.handles[i]);
245 if (handle != 0 && rdev->uvd.filp[i] == filp) {
246 struct radeon_fence *fence;
248 radeon_uvd_note_usage(rdev);
250 r = radeon_uvd_get_destroy_msg(rdev,
251 R600_RING_TYPE_UVD_INDEX, handle, &fence);
253 DRM_ERROR("Error destroying UVD (%d)!\n", r);
257 radeon_fence_wait(fence, false);
258 radeon_fence_unref(&fence);
260 rdev->uvd.filp[i] = NULL;
261 atomic_set(&rdev->uvd.handles[i], 0);
266 static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[])
268 unsigned stream_type = msg[4];
269 unsigned width = msg[6];
270 unsigned height = msg[7];
271 unsigned dpb_size = msg[9];
272 unsigned pitch = msg[28];
274 unsigned width_in_mb = width / 16;
275 unsigned height_in_mb = ALIGN(height / 16, 2);
277 unsigned image_size, tmp, min_dpb_size;
279 image_size = width * height;
280 image_size += image_size / 2;
281 image_size = ALIGN(image_size, 1024);
283 switch (stream_type) {
286 /* reference picture buffer */
287 min_dpb_size = image_size * 17;
289 /* macroblock context buffer */
290 min_dpb_size += width_in_mb * height_in_mb * 17 * 192;
292 /* IT surface buffer */
293 min_dpb_size += width_in_mb * height_in_mb * 32;
298 /* reference picture buffer */
299 min_dpb_size = image_size * 3;
302 min_dpb_size += width_in_mb * height_in_mb * 128;
304 /* IT surface buffer */
305 min_dpb_size += width_in_mb * 64;
307 /* DB surface buffer */
308 min_dpb_size += width_in_mb * 128;
311 tmp = max(width_in_mb, height_in_mb);
312 min_dpb_size += ALIGN(tmp * 7 * 16, 64);
317 /* reference picture buffer */
318 min_dpb_size = image_size * 3;
323 /* reference picture buffer */
324 min_dpb_size = image_size * 3;
327 min_dpb_size += width_in_mb * height_in_mb * 64;
329 /* IT surface buffer */
330 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64);
334 DRM_ERROR("UVD codec not handled %d!\n", stream_type);
339 DRM_ERROR("Invalid UVD decoding target pitch!\n");
343 if (dpb_size < min_dpb_size) {
344 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n",
345 dpb_size, min_dpb_size);
349 buf_sizes[0x1] = dpb_size;
350 buf_sizes[0x2] = image_size;
354 static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo,
355 unsigned offset, unsigned buf_sizes[])
357 int32_t *msg, msg_type, handle;
358 unsigned img_size = 0;
364 DRM_ERROR("UVD messages must be 64 byte aligned!\n");
368 if (bo->tbo.sync_obj) {
369 r = radeon_fence_wait(bo->tbo.sync_obj, false);
371 DRM_ERROR("Failed waiting for UVD message (%d)!\n", r);
376 r = radeon_bo_kmap(bo, &ptr);
378 DRM_ERROR("Failed mapping the UVD message (%d)!\n", r);
382 msg = (uint32_t*)((uint8_t*)ptr + offset);
388 DRM_ERROR("Invalid UVD handle!\n");
393 /* it's a decode msg, calc buffer sizes */
394 r = radeon_uvd_cs_msg_decode(msg, buf_sizes);
395 /* calc image size (width * height) */
396 img_size = msg[6] * msg[7];
397 radeon_bo_kunmap(bo);
401 } else if (msg_type == 2) {
402 /* it's a destroy msg, free the handle */
403 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i)
404 atomic_cmpset(&p->rdev->uvd.handles[i], handle, 0);
405 radeon_bo_kunmap(bo);
408 /* it's a create msg, calc image size (width * height) */
409 img_size = msg[7] * msg[8];
410 radeon_bo_kunmap(bo);
413 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type);
417 /* it's a create msg, no special handling needed */
420 /* create or decode, validate the handle */
421 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
422 if (atomic_read(&p->rdev->uvd.handles[i]) == handle)
426 /* handle not found try to alloc a new one */
427 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
428 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) {
429 p->rdev->uvd.filp[i] = p->filp;
430 p->rdev->uvd.img_size[i] = img_size;
435 DRM_ERROR("No more free UVD handles!\n");
439 static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
440 int data0, int data1,
441 unsigned buf_sizes[], bool *has_msg_cmd)
443 struct radeon_cs_chunk *relocs_chunk;
444 struct radeon_cs_reloc *reloc;
445 unsigned idx, cmd, offset;
449 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
450 offset = radeon_get_ib_value(p, data0);
451 idx = radeon_get_ib_value(p, data1);
452 if (idx >= relocs_chunk->length_dw) {
453 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
454 idx, relocs_chunk->length_dw);
458 reloc = p->relocs_ptr[(idx / 4)];
459 start = reloc->gpu_offset;
460 end = start + radeon_bo_size(reloc->robj);
463 p->ib.ptr[data0] = start & 0xFFFFFFFF;
464 p->ib.ptr[data1] = start >> 32;
466 cmd = radeon_get_ib_value(p, p->idx) >> 1;
470 DRM_ERROR("invalid reloc offset %X!\n", offset);
473 if ((end - start) < buf_sizes[cmd]) {
474 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd,
475 (unsigned)(end - start), buf_sizes[cmd]);
479 } else if (cmd != 0x100) {
480 DRM_ERROR("invalid UVD command %X!\n", cmd);
484 if ((start >> 28) != ((end - 1) >> 28)) {
485 DRM_ERROR("reloc %lX-%lX crossing 256MB boundary!\n",
490 /* TODO: is this still necessary on NI+ ? */
491 if ((cmd == 0 || cmd == 0x3) &&
492 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
493 DRM_ERROR("msg/fb buffer %lX-%lX out of 256MB segment!\n",
500 DRM_ERROR("More than one message in a UVD-IB!\n");
504 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
507 } else if (!*has_msg_cmd) {
508 DRM_ERROR("Message needed before other commands are send!\n");
515 static int radeon_uvd_cs_reg(struct radeon_cs_parser *p,
516 struct radeon_cs_packet *pkt,
517 int *data0, int *data1,
518 unsigned buf_sizes[],
524 for (i = 0; i <= pkt->count; ++i) {
525 switch (pkt->reg + i*4) {
526 case UVD_GPCOM_VCPU_DATA0:
529 case UVD_GPCOM_VCPU_DATA1:
532 case UVD_GPCOM_VCPU_CMD:
533 r = radeon_uvd_cs_reloc(p, *data0, *data1,
534 buf_sizes, has_msg_cmd);
538 case UVD_ENGINE_CNTL:
541 DRM_ERROR("Invalid reg 0x%X!\n",
550 int radeon_uvd_cs_parse(struct radeon_cs_parser *p)
552 struct radeon_cs_packet pkt;
553 int r, data0 = 0, data1 = 0;
555 /* does the IB has a msg command */
556 bool has_msg_cmd = false;
558 /* minimum buffer sizes */
559 unsigned buf_sizes[] = {
561 [0x00000001] = 32 * 1024 * 1024,
562 [0x00000002] = 2048 * 1152 * 3,
566 if (p->chunks[p->chunk_ib_idx].length_dw % 16) {
567 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
568 p->chunks[p->chunk_ib_idx].length_dw);
572 if (p->chunk_relocs_idx == -1) {
573 DRM_ERROR("No relocation chunk !\n");
579 r = radeon_cs_packet_parse(p, &pkt, p->idx);
583 case RADEON_PACKET_TYPE0:
584 r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1,
585 buf_sizes, &has_msg_cmd);
589 case RADEON_PACKET_TYPE2:
590 p->idx += pkt.count + 2;
593 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
596 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
599 DRM_ERROR("UVD-IBs need a msg command!\n");
606 static int radeon_uvd_send_msg(struct radeon_device *rdev,
607 int ring, uint64_t addr,
608 struct radeon_fence **fence)
613 r = radeon_ib_get(rdev, ring, &ib, NULL, 64);
617 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
619 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
620 ib.ptr[3] = addr >> 32;
621 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
623 for (i = 6; i < 16; ++i)
624 ib.ptr[i] = PACKET2(0);
627 r = radeon_ib_schedule(rdev, &ib, NULL, false);
630 *fence = radeon_fence_ref(ib.fence);
632 radeon_ib_free(rdev, &ib);
636 /* multiple fence commands without any stream commands in between can
637 crash the vcpu so just try to emmit a dummy create/destroy msg to
639 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
640 uint32_t handle, struct radeon_fence **fence)
642 /* we use the last page of the vcpu bo for the UVD message */
643 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
644 RADEON_GPU_PAGE_SIZE;
646 uint32_t *msg = (uint32_t*)((uint8_t*)rdev->uvd.cpu_addr + offs);
647 uint64_t addr = rdev->uvd.gpu_addr + offs;
651 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
655 /* stitch together an UVD create msg */
656 msg[0] = cpu_to_le32(0x00000de4);
657 msg[1] = cpu_to_le32(0x00000000);
658 msg[2] = cpu_to_le32(handle);
659 msg[3] = cpu_to_le32(0x00000000);
660 msg[4] = cpu_to_le32(0x00000000);
661 msg[5] = cpu_to_le32(0x00000000);
662 msg[6] = cpu_to_le32(0x00000000);
663 msg[7] = cpu_to_le32(0x00000780);
664 msg[8] = cpu_to_le32(0x00000440);
665 msg[9] = cpu_to_le32(0x00000000);
666 msg[10] = cpu_to_le32(0x01b37000);
667 for (i = 11; i < 1024; ++i)
668 msg[i] = cpu_to_le32(0x0);
670 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
671 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
675 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
676 uint32_t handle, struct radeon_fence **fence)
678 /* we use the last page of the vcpu bo for the UVD message */
679 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) -
680 RADEON_GPU_PAGE_SIZE;
682 uint32_t *msg = (uint32_t*)((uint8_t*)rdev->uvd.cpu_addr + offs);
683 uint64_t addr = rdev->uvd.gpu_addr + offs;
687 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true);
691 /* stitch together an UVD destroy msg */
692 msg[0] = cpu_to_le32(0x00000de4);
693 msg[1] = cpu_to_le32(0x00000002);
694 msg[2] = cpu_to_le32(handle);
695 msg[3] = cpu_to_le32(0x00000000);
696 for (i = 4; i < 1024; ++i)
697 msg[i] = cpu_to_le32(0x0);
699 r = radeon_uvd_send_msg(rdev, ring, addr, fence);
700 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
705 * radeon_uvd_count_handles - count number of open streams
707 * @rdev: radeon_device pointer
708 * @sd: number of SD streams
709 * @hd: number of HD streams
711 * Count the number of open SD/HD streams as a hint for power mangement
713 static void radeon_uvd_count_handles(struct radeon_device *rdev,
714 unsigned *sd, unsigned *hd)
721 for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) {
722 if (!atomic_read(&rdev->uvd.handles[i]))
725 if (rdev->uvd.img_size[i] >= 720*576)
732 static void radeon_uvd_idle_work_handler(struct work_struct *work)
734 struct radeon_device *rdev =
735 container_of(work, struct radeon_device, uvd.idle_work.work);
737 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) {
738 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
739 radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd,
741 radeon_dpm_enable_uvd(rdev, false);
743 radeon_set_uvd_clocks(rdev, 0, 0);
746 schedule_delayed_work(&rdev->uvd.idle_work,
747 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
751 void radeon_uvd_note_usage(struct radeon_device *rdev)
753 bool streams_changed = false;
754 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
755 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
756 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
758 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
759 unsigned hd = 0, sd = 0;
760 radeon_uvd_count_handles(rdev, &sd, &hd);
761 if ((rdev->pm.dpm.sd != sd) ||
762 (rdev->pm.dpm.hd != hd)) {
763 rdev->pm.dpm.sd = sd;
764 rdev->pm.dpm.hd = hd;
765 /* disable this for now */
766 /*streams_changed = true;*/
770 if (set_clocks || streams_changed) {
771 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
772 radeon_dpm_enable_uvd(rdev, true);
774 radeon_set_uvd_clocks(rdev, 53300, 40000);
779 static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq,
780 unsigned target_freq,
784 unsigned post_div = vco_freq / target_freq;
786 /* adjust to post divider minimum value */
787 if (post_div < pd_min)
790 /* we alway need a frequency less than or equal the target */
791 if ((vco_freq / post_div) > target_freq)
794 /* post dividers above a certain value must be even */
795 if (post_div > pd_even && post_div % 2)
802 * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers
804 * @rdev: radeon_device pointer
807 * @vco_min: minimum VCO frequency
808 * @vco_max: maximum VCO frequency
809 * @fb_factor: factor to multiply vco freq with
810 * @fb_mask: limit and bitmask for feedback divider
811 * @pd_min: post divider minimum
812 * @pd_max: post divider maximum
813 * @pd_even: post divider must be even above this value
814 * @optimal_fb_div: resulting feedback divider
815 * @optimal_vclk_div: resulting vclk post divider
816 * @optimal_dclk_div: resulting dclk post divider
818 * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs).
819 * Returns zero on success -EINVAL on error.
821 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
822 unsigned vclk, unsigned dclk,
823 unsigned vco_min, unsigned vco_max,
824 unsigned fb_factor, unsigned fb_mask,
825 unsigned pd_min, unsigned pd_max,
827 unsigned *optimal_fb_div,
828 unsigned *optimal_vclk_div,
829 unsigned *optimal_dclk_div)
831 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;
833 /* start off with something large */
834 unsigned optimal_score = ~0;
836 /* loop through vco from low to high */
837 vco_min = max(max(vco_min, vclk), dclk);
838 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) {
840 uint64_t fb_div = (uint64_t)vco_freq * fb_factor;
841 unsigned vclk_div, dclk_div, score;
843 do_div(fb_div, ref_freq);
845 /* fb div out of range ? */
846 if (fb_div > fb_mask)
847 break; /* it can oly get worse */
851 /* calc vclk divider with current vco freq */
852 vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk,
854 if (vclk_div > pd_max)
855 break; /* vco is too big, it has to stop */
857 /* calc dclk divider with current vco freq */
858 dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk,
860 if (vclk_div > pd_max)
861 break; /* vco is too big, it has to stop */
863 /* calc score with current vco freq */
864 score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div);
866 /* determine if this vco setting is better than current optimal settings */
867 if (score < optimal_score) {
868 *optimal_fb_div = fb_div;
869 *optimal_vclk_div = vclk_div;
870 *optimal_dclk_div = dclk_div;
871 optimal_score = score;
872 if (optimal_score == 0)
873 break; /* it can't get better than this */
877 /* did we found a valid setup ? */
878 if (optimal_score == ~0)
884 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
885 unsigned cg_upll_func_cntl)
889 /* make sure UPLL_CTLREQ is deasserted */
890 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
894 /* assert UPLL_CTLREQ */
895 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
897 /* wait for CTLACK and CTLACK2 to get asserted */
898 for (i = 0; i < 100; ++i) {
899 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
900 if ((RREG32(cg_upll_func_cntl) & mask) == mask)
905 /* deassert UPLL_CTLREQ */
906 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK);
909 DRM_ERROR("Timeout setting UVD clocks!\n");