2 * Copyright (c) 2004 David O'Brien <obrien@FreeBSD.org>
3 * Copyright (c) 2003 Orlando Bassotto <orlando.bassotto@ieo-research.it>
4 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/sound/pci/emu10k1.c,v 1.55.2.1 2005/12/30 19:55:53 netchild Exp $
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <gnu/dev/sound/pci/emu10k1.h>
34 #include "emu10k1-alsa%diked.h"
36 #include <bus/pci/pcireg.h>
37 #include <bus/pci/pcivar.h>
38 #include <sys/queue.h>
40 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/emu10k1.c,v 1.14 2008/01/06 16:55:51 swildner Exp $");
42 /* -------------------------------------------------------------------- */
44 #define NUM_G 64 /* use all channels */
45 #define WAVEOUT_MAXBUFSIZE 32768
46 #define EMUPAGESIZE 4096 /* don't change */
47 #define EMUMAXPAGES (WAVEOUT_MAXBUFSIZE * NUM_G / EMUPAGESIZE)
48 #define EMU10K1_PCI_ID 0x00021102 /* 1102 => Creative Labs Vendor ID */
49 #define EMU10K2_PCI_ID 0x00041102
50 #define EMU10K3_PCI_ID 0x00081102
51 #define EMU_DEFAULT_BUFSZ 4096
52 #define EMU_MAX_CHANS 8
55 #define MAXREQVOICES 8
60 #define TMEMSIZE 256*1024
63 #define ENABLE 0xffffffff
64 #define DISABLE 0x00000000
65 #define ENV_ON DCYSUSV_CHANNELENABLE_MASK
66 #define ENV_OFF 0x00 /* XXX: should this be 1? */
68 #define A_IOCFG_GPOUT_A 0x40 /* Analog Output */
69 #define A_IOCFG_GPOUT_D 0x04 /* Digital Output */
70 #define A_IOCFG_GPOUT_AD (A_IOCFG_GPOUT_A|A_IOCFG_GPOUT_D) /* A_IOCFG_GPOUT0 */
73 SLIST_ENTRY(emu_memblk) link;
76 u_int32_t pte_start, pte_size;
80 u_int8_t bmap[EMUMAXPAGES / 8];
83 bus_addr_t silent_page_addr;
84 bus_addr_t ptb_pages_addr;
85 SLIST_HEAD(, emu_memblk) blocks;
90 int b16:1, stereo:1, busy:1, running:1, ismaster:1;
93 int fxrt1; /* FX routing */
94 int fxrt2; /* FX routing (only for audigy) */
96 struct emu_voice *slave;
97 struct pcm_channel *channel;
102 /* channel registers */
104 int spd, fmt, blksz, run;
105 struct emu_voice *master, *slave;
106 struct snd_dbuf *buffer;
107 struct pcm_channel *channel;
108 struct sc_info *parent;
112 int spd, fmt, run, blksz, num;
113 u_int32_t idxreg, basereg, sizereg, setupreg, irqmask;
114 struct snd_dbuf *buffer;
115 struct pcm_channel *channel;
116 struct sc_info *parent;
119 /* device private data */
123 u_int32_t tos_link:1, APS:1, audigy:1, audigy2:1;
124 u_int32_t addrmask; /* wider if audigy */
127 bus_space_handle_t sh;
128 bus_dma_tag_t parent_dmat;
130 struct resource *reg, *irq;
135 int timer, timerinterval;
139 struct emu_voice voice[64];
140 struct sc_pchinfo pch[EMU_MAX_CHANS];
141 struct sc_rchinfo rch[3];
144 /* -------------------------------------------------------------------- */
151 static int emu_init(struct sc_info *);
152 static void emu_intr(void *);
153 static void *emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
154 static void *emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr);
155 static int emu_memfree(struct sc_info *sc, void *buf);
156 static int emu_memstart(struct sc_info *sc, void *buf);
158 static void emu_vdump(struct sc_info *sc, struct emu_voice *v);
161 /* talk to the card */
162 static u_int32_t emu_rd(struct sc_info *, int, int);
163 static void emu_wr(struct sc_info *, int, u_int32_t, int);
165 /* -------------------------------------------------------------------- */
167 static u_int32_t emu_rfmt_ac97[] = {
169 AFMT_STEREO | AFMT_S16_LE,
173 static u_int32_t emu_rfmt_mic[] = {
178 static u_int32_t emu_rfmt_efx[] = {
179 AFMT_STEREO | AFMT_S16_LE,
183 static struct pcmchan_caps emu_reccaps[3] = {
184 {8000, 48000, emu_rfmt_ac97, 0},
185 {8000, 8000, emu_rfmt_mic, 0},
186 {48000, 48000, emu_rfmt_efx, 0},
189 static u_int32_t emu_pfmt[] = {
191 AFMT_STEREO | AFMT_U8,
193 AFMT_STEREO | AFMT_S16_LE,
197 static struct pcmchan_caps emu_playcaps = {4000, 48000, emu_pfmt, 0};
199 static int adcspeed[8] = {48000, 44100, 32000, 24000, 22050, 16000, 11025, 8000};
200 /* audigy supports 12kHz. */
201 static int audigy_adcspeed[9] = {
202 48000, 44100, 32000, 24000, 22050, 16000, 12000, 11025, 8000
205 /* -------------------------------------------------------------------- */
208 emu_rd(struct sc_info *sc, int regno, int size)
212 return bus_space_read_1(sc->st, sc->sh, regno);
214 return bus_space_read_2(sc->st, sc->sh, regno);
216 return bus_space_read_4(sc->st, sc->sh, regno);
223 emu_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
227 bus_space_write_1(sc->st, sc->sh, regno, data);
230 bus_space_write_2(sc->st, sc->sh, regno, data);
233 bus_space_write_4(sc->st, sc->sh, regno, data);
239 emu_rdptr(struct sc_info *sc, int chn, int reg)
241 u_int32_t ptr, val, mask, size, offset;
243 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
244 emu_wr(sc, PTR, ptr, 4);
245 val = emu_rd(sc, DATA, 4);
246 if (reg & 0xff000000) {
247 size = (reg >> 24) & 0x3f;
248 offset = (reg >> 16) & 0x1f;
249 mask = ((1 << size) - 1) << offset;
257 emu_wrptr(struct sc_info *sc, int chn, int reg, u_int32_t data)
259 u_int32_t ptr, mask, size, offset;
261 ptr = ((reg << 16) & sc->addrmask) | (chn & PTR_CHANNELNUM_MASK);
262 emu_wr(sc, PTR, ptr, 4);
263 if (reg & 0xff000000) {
264 size = (reg >> 24) & 0x3f;
265 offset = (reg >> 16) & 0x1f;
266 mask = ((1 << size) - 1) << offset;
269 data |= emu_rd(sc, DATA, 4) & ~mask;
271 emu_wr(sc, DATA, data, 4);
275 emu_wrefx(struct sc_info *sc, unsigned int pc, unsigned int data)
277 pc += sc->audigy ? AUDIGY_CODEBASE : MICROCODEBASE;
278 emu_wrptr(sc, 0, pc, data);
281 /* -------------------------------------------------------------------- */
283 /* no locking needed */
286 emu_rdcd(kobj_t obj, void *devinfo, int regno)
288 struct sc_info *sc = (struct sc_info *)devinfo;
290 emu_wr(sc, AC97ADDRESS, regno, 1);
291 return emu_rd(sc, AC97DATA, 2);
295 emu_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
297 struct sc_info *sc = (struct sc_info *)devinfo;
299 emu_wr(sc, AC97ADDRESS, regno, 1);
300 emu_wr(sc, AC97DATA, data, 2);
304 static kobj_method_t emu_ac97_methods[] = {
305 KOBJMETHOD(ac97_read, emu_rdcd),
306 KOBJMETHOD(ac97_write, emu_wrcd),
309 AC97_DECLARE(emu_ac97);
311 /* -------------------------------------------------------------------- */
314 emu_settimer(struct sc_info *sc)
316 struct sc_pchinfo *pch;
317 struct sc_rchinfo *rch;
321 for (i = 0; i < sc->nchans; i++) {
324 tmp = (pch->spd * sndbuf_getbps(pch->buffer))
331 for (i = 0; i < 3; i++) {
334 tmp = (rch->spd * sndbuf_getbps(rch->buffer))
340 RANGE(rate, 48, 9600);
341 sc->timerinterval = 48000 / rate;
342 emu_wr(sc, TIMER, sc->timerinterval & 0x03ff, 2);
344 return sc->timerinterval;
348 emu_enatimer(struct sc_info *sc, int go)
352 if (sc->timer++ == 0) {
353 x = emu_rd(sc, INTE, 4);
354 x |= INTE_INTERVALTIMERENB;
355 emu_wr(sc, INTE, x, 4);
359 x = emu_rd(sc, INTE, 4);
360 x &= ~INTE_INTERVALTIMERENB;
361 emu_wr(sc, INTE, x, 4);
367 emu_enastop(struct sc_info *sc, char channel, int enable)
369 int reg = (channel & 0x20) ? SOLEH : SOLEL;
372 reg |= channel << 16;
373 emu_wrptr(sc, 0, reg, enable);
377 emu_recval(int speed) {
381 while (val < 7 && speed < adcspeed[val])
387 audigy_recval(int speed) {
391 while (val < 8 && speed < audigy_adcspeed[val])
397 emu_rate_to_pitch(u_int32_t rate)
399 static u_int32_t logMagTable[128] = {
400 0x00000, 0x02dfc, 0x05b9e, 0x088e6, 0x0b5d6, 0x0e26f, 0x10eb3, 0x13aa2,
401 0x1663f, 0x1918a, 0x1bc84, 0x1e72e, 0x2118b, 0x23b9a, 0x2655d, 0x28ed5,
402 0x2b803, 0x2e0e8, 0x30985, 0x331db, 0x359eb, 0x381b6, 0x3a93d, 0x3d081,
403 0x3f782, 0x41e42, 0x444c1, 0x46b01, 0x49101, 0x4b6c4, 0x4dc49, 0x50191,
404 0x5269e, 0x54b6f, 0x57006, 0x59463, 0x5b888, 0x5dc74, 0x60029, 0x623a7,
405 0x646ee, 0x66a00, 0x68cdd, 0x6af86, 0x6d1fa, 0x6f43c, 0x7164b, 0x73829,
406 0x759d4, 0x77b4f, 0x79c9a, 0x7bdb5, 0x7dea1, 0x7ff5e, 0x81fed, 0x8404e,
407 0x86082, 0x88089, 0x8a064, 0x8c014, 0x8df98, 0x8fef1, 0x91e20, 0x93d26,
408 0x95c01, 0x97ab4, 0x9993e, 0x9b79f, 0x9d5d9, 0x9f3ec, 0xa11d8, 0xa2f9d,
409 0xa4d3c, 0xa6ab5, 0xa8808, 0xaa537, 0xac241, 0xadf26, 0xafbe7, 0xb1885,
410 0xb3500, 0xb5157, 0xb6d8c, 0xb899f, 0xba58f, 0xbc15e, 0xbdd0c, 0xbf899,
411 0xc1404, 0xc2f50, 0xc4a7b, 0xc6587, 0xc8073, 0xc9b3f, 0xcb5ed, 0xcd07c,
412 0xceaec, 0xd053f, 0xd1f73, 0xd398a, 0xd5384, 0xd6d60, 0xd8720, 0xda0c3,
413 0xdba4a, 0xdd3b4, 0xded03, 0xe0636, 0xe1f4e, 0xe384a, 0xe512c, 0xe69f3,
414 0xe829f, 0xe9b31, 0xeb3a9, 0xecc08, 0xee44c, 0xefc78, 0xf148a, 0xf2c83,
415 0xf4463, 0xf5c2a, 0xf73da, 0xf8b71, 0xfa2f0, 0xfba57, 0xfd1a7, 0xfe8df
417 static char logSlopeTable[128] = {
418 0x5c, 0x5c, 0x5b, 0x5a, 0x5a, 0x59, 0x58, 0x58,
419 0x57, 0x56, 0x56, 0x55, 0x55, 0x54, 0x53, 0x53,
420 0x52, 0x52, 0x51, 0x51, 0x50, 0x50, 0x4f, 0x4f,
421 0x4e, 0x4d, 0x4d, 0x4d, 0x4c, 0x4c, 0x4b, 0x4b,
422 0x4a, 0x4a, 0x49, 0x49, 0x48, 0x48, 0x47, 0x47,
423 0x47, 0x46, 0x46, 0x45, 0x45, 0x45, 0x44, 0x44,
424 0x43, 0x43, 0x43, 0x42, 0x42, 0x42, 0x41, 0x41,
425 0x41, 0x40, 0x40, 0x40, 0x3f, 0x3f, 0x3f, 0x3e,
426 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c, 0x3c,
427 0x3b, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39,
428 0x39, 0x39, 0x39, 0x38, 0x38, 0x38, 0x38, 0x37,
429 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x36, 0x35,
430 0x35, 0x35, 0x35, 0x34, 0x34, 0x34, 0x34, 0x34,
431 0x33, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x32,
432 0x32, 0x31, 0x31, 0x31, 0x31, 0x31, 0x30, 0x30,
433 0x30, 0x30, 0x30, 0x2f, 0x2f, 0x2f, 0x2f, 0x2f
438 return 0; /* Bail out if no leading "1" */
439 rate *= 11185; /* Scale 48000 to 0x20002380 */
440 for (i = 31; i > 0; i--) {
441 if (rate & 0x80000000) { /* Detect leading "1" */
442 return (((u_int32_t) (i - 15) << 20) +
443 logMagTable[0x7f & (rate >> 24)] +
444 (0x7f & (rate >> 17)) *
445 logSlopeTable[0x7f & (rate >> 24)]);
450 return 0; /* Should never reach this point */
454 emu_rate_to_linearpitch(u_int32_t rate)
456 rate = (rate << 8) / 375;
457 return (rate >> 1) + (rate & 1);
460 static struct emu_voice *
461 emu_valloc(struct sc_info *sc)
467 for (i = 0; i < 64 && sc->voice[i].busy; i++);
476 emu_vinit(struct sc_info *sc, struct emu_voice *m, struct emu_voice *s,
477 u_int32_t sz, struct snd_dbuf *b)
482 buf = emu_memalloc(sc, sz, &tmp_addr);
486 sndbuf_setup(b, buf, sz);
487 m->start = emu_memstart(sc, buf) * EMUPAGESIZE;
488 m->end = m->start + sz;
499 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 8 |
500 FXBUS_PCM_LEFT << 16 | FXBUS_MIDI_REVERB << 24;
501 m->fxrt2 = 0x3f3f3f3f; /* No effects on second route */
503 m->fxrt1 = FXBUS_MIDI_CHORUS | FXBUS_PCM_RIGHT << 4 |
504 FXBUS_PCM_LEFT << 8 | FXBUS_MIDI_REVERB << 12;
527 emu_vsetup(struct sc_pchinfo *ch)
529 struct emu_voice *v = ch->master;
532 v->b16 = (ch->fmt & AFMT_16BIT) ? 1 : 0;
533 v->stereo = (ch->fmt & AFMT_STEREO) ? 1 : 0;
534 if (v->slave != NULL) {
535 v->slave->b16 = v->b16;
536 v->slave->stereo = v->stereo;
541 if (v->slave != NULL)
542 v->slave->speed = v->speed;
547 emu_vwrite(struct sc_info *sc, struct emu_voice *v)
551 u_int32_t sa, ea, start, val, silent_page;
553 s = (v->stereo ? 1 : 0) + (v->b16 ? 1 : 0);
558 l = r = x = y = v->vol;
560 l = v->ismaster ? l : 0;
561 r = v->ismaster ? 0 : r;
564 emu_wrptr(sc, v->vnum, CPF, v->stereo ? CPF_STEREO_MASK : 0);
565 val = v->stereo ? 28 : 30;
566 val *= v->b16 ? 1 : 2;
570 emu_wrptr(sc, v->vnum, A_FXRT1, v->fxrt1);
571 emu_wrptr(sc, v->vnum, A_FXRT2, v->fxrt2);
572 emu_wrptr(sc, v->vnum, A_SENDAMOUNTS, 0);
575 emu_wrptr(sc, v->vnum, FXRT, v->fxrt1 << 16);
577 emu_wrptr(sc, v->vnum, PTRX, (x << 8) | r);
578 emu_wrptr(sc, v->vnum, DSL, ea | (y << 24));
579 emu_wrptr(sc, v->vnum, PSST, sa | (l << 24));
580 emu_wrptr(sc, v->vnum, CCCA, start | (v->b16 ? 0 : CCCA_8BITSELECT));
582 emu_wrptr(sc, v->vnum, Z1, 0);
583 emu_wrptr(sc, v->vnum, Z2, 0);
585 silent_page = ((u_int32_t)(sc->mem.silent_page_addr) << 1)
587 emu_wrptr(sc, v->vnum, MAPA, silent_page);
588 emu_wrptr(sc, v->vnum, MAPB, silent_page);
590 emu_wrptr(sc, v->vnum, CVCF, CVCF_CURRENTFILTER_MASK);
591 emu_wrptr(sc, v->vnum, VTFT, VTFT_FILTERTARGET_MASK);
592 emu_wrptr(sc, v->vnum, ATKHLDM, 0);
593 emu_wrptr(sc, v->vnum, DCYSUSM, DCYSUSM_DECAYTIME_MASK);
594 emu_wrptr(sc, v->vnum, LFOVAL1, 0x8000);
595 emu_wrptr(sc, v->vnum, LFOVAL2, 0x8000);
596 emu_wrptr(sc, v->vnum, FMMOD, 0);
597 emu_wrptr(sc, v->vnum, TREMFRQ, 0);
598 emu_wrptr(sc, v->vnum, FM2FRQ2, 0);
599 emu_wrptr(sc, v->vnum, ENVVAL, 0x8000);
601 emu_wrptr(sc, v->vnum, ATKHLDV,
602 ATKHLDV_HOLDTIME_MASK | ATKHLDV_ATTACKTIME_MASK);
603 emu_wrptr(sc, v->vnum, ENVVOL, 0x8000);
605 emu_wrptr(sc, v->vnum, PEFE_FILTERAMOUNT, 0x7f);
606 emu_wrptr(sc, v->vnum, PEFE_PITCHAMOUNT, 0);
608 if (v->slave != NULL)
609 emu_vwrite(sc, v->slave);
613 emu_vtrigger(struct sc_info *sc, struct emu_voice *v, int go)
615 u_int32_t pitch_target, initial_pitch;
616 u_int32_t cra, cs, ccis;
621 cs = v->stereo ? 4 : 2;
622 ccis = v->stereo ? 28 : 30;
623 ccis *= v->b16 ? 1 : 2;
624 sample = v->b16 ? 0x00000000 : 0x80808080;
626 for (i = 0; i < cs; i++)
627 emu_wrptr(sc, v->vnum, CD0 + i, sample);
628 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, 0);
629 emu_wrptr(sc, v->vnum, CCR_READADDRESS, cra);
630 emu_wrptr(sc, v->vnum, CCR_CACHEINVALIDSIZE, ccis);
632 emu_wrptr(sc, v->vnum, IFATN, 0xff00);
633 emu_wrptr(sc, v->vnum, VTFT, 0xffffffff);
634 emu_wrptr(sc, v->vnum, CVCF, 0xffffffff);
635 emu_wrptr(sc, v->vnum, DCYSUSV, 0x00007f7f);
636 emu_enastop(sc, v->vnum, 0);
638 pitch_target = emu_rate_to_linearpitch(v->speed);
639 initial_pitch = emu_rate_to_pitch(v->speed) >> 8;
640 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, pitch_target);
641 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, pitch_target);
642 emu_wrptr(sc, v->vnum, IP, initial_pitch);
644 emu_wrptr(sc, v->vnum, PTRX_PITCHTARGET, 0);
645 emu_wrptr(sc, v->vnum, CPF_CURRENTPITCH, 0);
646 emu_wrptr(sc, v->vnum, IFATN, 0xffff);
647 emu_wrptr(sc, v->vnum, VTFT, 0x0000ffff);
648 emu_wrptr(sc, v->vnum, CVCF, 0x0000ffff);
649 emu_wrptr(sc, v->vnum, IP, 0);
650 emu_enastop(sc, v->vnum, 1);
652 if (v->slave != NULL)
653 emu_vtrigger(sc, v->slave, go);
657 emu_vpos(struct sc_info *sc, struct emu_voice *v)
661 s = (v->b16 ? 1 : 0) + (v->stereo ? 1 : 0);
662 ptr = (emu_rdptr(sc, v->vnum, CCCA_CURRADDR) - (v->start >> s)) << s;
663 return ptr & ~0x0000001f;
668 emu_vdump(struct sc_info *sc, struct emu_voice *v)
671 "cpf", "ptrx", "cvcf", "vtft", "z2", "z1", "psst", "dsl",
672 "ccca", "ccr", "clp", "fxrt", "mapa", "mapb", NULL, NULL,
673 "envvol", "atkhldv", "dcysusv", "lfoval1",
674 "envval", "atkhldm", "dcysusm", "lfoval2",
675 "ip", "ifatn", "pefe", "fmmod", "tremfrq", "fmfrq2",
679 "mudata1", "mustat1", "mudata2", "mustat2",
680 "fxwc1", "fxwc2", "spdrate", NULL, NULL,
681 NULL, NULL, NULL, "fxrt2", "sndamnt", "fxrt1",
686 kprintf("voice number %d\n", v->vnum);
687 for (i = 0, x = 0; i <= 0x1e; i++) {
688 if (regname[i] == NULL)
690 kprintf("%s\t[%08x]", regname[i], emu_rdptr(sc, v->vnum, i));
691 kprintf("%s", (x == 2) ? "\n" : "\t");
697 /* Print out audigy extra registers */
699 for (i = 0; i <= 0xe; i++) {
700 if (regname2[i] == NULL)
702 kprintf("%s\t[%08x]", regname2[i],
703 emu_rdptr(sc, v->vnum, i + 0x70));
704 kprintf("%s", (x == 2)? "\n" : "\t");
714 /* channel interface */
716 emupchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
717 struct pcm_channel *c, int dir)
719 struct sc_info *sc = devinfo;
720 struct sc_pchinfo *ch;
723 KASSERT(dir == PCMDIR_PLAY, ("emupchan_init: bad direction"));
724 ch = &sc->pch[sc->pnum++];
728 ch->blksz = sc->bufsz / 2;
731 snd_mtxlock(sc->lock);
732 ch->master = emu_valloc(sc);
733 ch->slave = emu_valloc(sc);
734 snd_mtxunlock(sc->lock);
735 r = (emu_vinit(sc, ch->master, ch->slave, sc->bufsz, ch->buffer))
742 emupchan_free(kobj_t obj, void *data)
744 struct sc_pchinfo *ch = data;
745 struct sc_info *sc = ch->parent;
748 snd_mtxlock(sc->lock);
749 r = emu_memfree(sc, sndbuf_getbuf(ch->buffer));
750 snd_mtxunlock(sc->lock);
756 emupchan_setformat(kobj_t obj, void *data, u_int32_t format)
758 struct sc_pchinfo *ch = data;
765 emupchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
767 struct sc_pchinfo *ch = data;
774 emupchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
776 struct sc_pchinfo *ch = data;
777 struct sc_info *sc = ch->parent;
780 ch->blksz = blocksize;
781 snd_mtxlock(sc->lock);
783 irqrate = 48000 / sc->timerinterval;
784 snd_mtxunlock(sc->lock);
789 emupchan_trigger(kobj_t obj, void *data, int go)
791 struct sc_pchinfo *ch = data;
792 struct sc_info *sc = ch->parent;
794 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD)
797 snd_mtxlock(sc->lock);
798 if (go == PCMTRIG_START) {
800 emu_vwrite(sc, ch->master);
804 kprintf("start [%d bit, %s, %d hz]\n",
805 ch->master->b16 ? 16 : 8,
806 ch->master->stereo ? "stereo" : "mono",
808 emu_vdump(sc, ch->master);
809 emu_vdump(sc, ch->slave);
812 ch->run = (go == PCMTRIG_START) ? 1 : 0;
813 emu_vtrigger(sc, ch->master, ch->run);
814 snd_mtxunlock(sc->lock);
819 emupchan_getptr(kobj_t obj, void *data)
821 struct sc_pchinfo *ch = data;
822 struct sc_info *sc = ch->parent;
825 snd_mtxlock(sc->lock);
826 r = emu_vpos(sc, ch->master);
827 snd_mtxunlock(sc->lock);
832 static struct pcmchan_caps *
833 emupchan_getcaps(kobj_t obj, void *data)
835 return &emu_playcaps;
838 static kobj_method_t emupchan_methods[] = {
839 KOBJMETHOD(channel_init, emupchan_init),
840 KOBJMETHOD(channel_free, emupchan_free),
841 KOBJMETHOD(channel_setformat, emupchan_setformat),
842 KOBJMETHOD(channel_setspeed, emupchan_setspeed),
843 KOBJMETHOD(channel_setblocksize, emupchan_setblocksize),
844 KOBJMETHOD(channel_trigger, emupchan_trigger),
845 KOBJMETHOD(channel_getptr, emupchan_getptr),
846 KOBJMETHOD(channel_getcaps, emupchan_getcaps),
849 CHANNEL_DECLARE(emupchan);
851 /* channel interface */
853 emurchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
854 struct pcm_channel *c, int dir)
856 struct sc_info *sc = devinfo;
857 struct sc_rchinfo *ch;
859 KASSERT(dir == PCMDIR_REC, ("emurchan_init: bad direction"));
860 ch = &sc->rch[sc->rnum];
864 ch->blksz = sc->bufsz / 2;
870 ch->idxreg = sc->audigy ? A_ADCIDX : ADCIDX;
873 ch->setupreg = ADCCR;
874 ch->irqmask = INTE_ADCBUFENABLE;
882 ch->irqmask = INTE_EFXBUFENABLE;
890 ch->irqmask = INTE_MICBUFENABLE;
894 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0)
897 snd_mtxlock(sc->lock);
898 emu_wrptr(sc, 0, ch->basereg, sndbuf_getbufaddr(ch->buffer));
899 emu_wrptr(sc, 0, ch->sizereg, 0); /* off */
900 snd_mtxunlock(sc->lock);
906 emurchan_setformat(kobj_t obj, void *data, u_int32_t format)
908 struct sc_rchinfo *ch = data;
915 emurchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
917 struct sc_rchinfo *ch = data;
920 if (ch->parent->audigy)
921 speed = audigy_adcspeed[audigy_recval(speed)];
923 speed = adcspeed[emu_recval(speed)];
934 emurchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
936 struct sc_rchinfo *ch = data;
937 struct sc_info *sc = ch->parent;
940 ch->blksz = blocksize;
941 snd_mtxlock(sc->lock);
943 irqrate = 48000 / sc->timerinterval;
944 snd_mtxunlock(sc->lock);
948 /* semantic note: must start at beginning of buffer */
950 emurchan_trigger(kobj_t obj, void *data, int go)
952 struct sc_rchinfo *ch = data;
953 struct sc_info *sc = ch->parent;
958 sz = ADCBS_BUFSIZE_4096;
962 sz = ADCBS_BUFSIZE_8192;
966 sz = ADCBS_BUFSIZE_16384;
970 sz = ADCBS_BUFSIZE_32768;
974 sz = ADCBS_BUFSIZE_65536;
978 sz = ADCBS_BUFSIZE_4096;
981 snd_mtxlock(sc->lock);
985 emu_wrptr(sc, 0, ch->sizereg, sz);
988 val = A_ADCCR_LCHANENABLE;
989 if (ch->fmt & AFMT_STEREO)
990 val |= A_ADCCR_RCHANENABLE;
991 val |= audigy_recval(ch->spd);
993 val = ADCCR_LCHANENABLE;
994 if (ch->fmt & AFMT_STEREO)
995 val |= ADCCR_RCHANENABLE;
996 val |= emu_recval(ch->spd);
999 emu_wrptr(sc, 0, ch->setupreg, 0);
1000 emu_wrptr(sc, 0, ch->setupreg, val);
1002 val = emu_rd(sc, INTE, 4);
1004 emu_wr(sc, INTE, val, 4);
1010 emu_wrptr(sc, 0, ch->sizereg, 0);
1012 emu_wrptr(sc, 0, ch->setupreg, 0);
1013 val = emu_rd(sc, INTE, 4);
1014 val &= ~ch->irqmask;
1015 emu_wr(sc, INTE, val, 4);
1018 case PCMTRIG_EMLDMAWR:
1019 case PCMTRIG_EMLDMARD:
1023 snd_mtxunlock(sc->lock);
1029 emurchan_getptr(kobj_t obj, void *data)
1031 struct sc_rchinfo *ch = data;
1032 struct sc_info *sc = ch->parent;
1035 snd_mtxlock(sc->lock);
1036 r = emu_rdptr(sc, 0, ch->idxreg) & 0x0000ffff;
1037 snd_mtxunlock(sc->lock);
1042 static struct pcmchan_caps *
1043 emurchan_getcaps(kobj_t obj, void *data)
1045 struct sc_rchinfo *ch = data;
1047 return &emu_reccaps[ch->num];
1050 static kobj_method_t emurchan_methods[] = {
1051 KOBJMETHOD(channel_init, emurchan_init),
1052 KOBJMETHOD(channel_setformat, emurchan_setformat),
1053 KOBJMETHOD(channel_setspeed, emurchan_setspeed),
1054 KOBJMETHOD(channel_setblocksize, emurchan_setblocksize),
1055 KOBJMETHOD(channel_trigger, emurchan_trigger),
1056 KOBJMETHOD(channel_getptr, emurchan_getptr),
1057 KOBJMETHOD(channel_getcaps, emurchan_getcaps),
1060 CHANNEL_DECLARE(emurchan);
1062 /* -------------------------------------------------------------------- */
1063 /* The interrupt handler */
1065 emu_intr(void *data)
1067 struct sc_info *sc = data;
1068 u_int32_t stat, ack, i, x;
1070 snd_mtxlock(sc->lock);
1072 stat = emu_rd(sc, IPR, 4);
1078 if (stat & IPR_INTERVALTIMER)
1079 ack |= IPR_INTERVALTIMER;
1081 if (stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL))
1082 ack |= stat & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL);
1084 if (stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL))
1085 ack |= stat & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL);
1087 if (stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL))
1088 ack |= stat & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL);
1090 if (stat & IPR_PCIERROR) {
1091 ack |= IPR_PCIERROR;
1092 device_printf(sc->dev, "pci error\n");
1093 /* we still get an nmi with ecc ram even if we ack this */
1095 if (stat & IPR_SAMPLERATETRACKER) {
1096 ack |= IPR_SAMPLERATETRACKER;
1098 device_printf(sc->dev,
1099 "sample rate tracker lock status change\n");
1104 device_printf(sc->dev, "dodgy irq: %x (harmless)\n",
1107 emu_wr(sc, IPR, stat, 4);
1110 snd_mtxunlock(sc->lock);
1112 if (ack & IPR_INTERVALTIMER) {
1114 for (i = 0; i < sc->nchans; i++) {
1115 if (sc->pch[i].run) {
1117 chn_intr(sc->pch[i].channel);
1121 emu_enatimer(sc, 0);
1125 if (ack & (IPR_ADCBUFFULL | IPR_ADCBUFHALFFULL)) {
1126 if (sc->rch[0].channel)
1127 chn_intr(sc->rch[0].channel);
1129 if (ack & (IPR_EFXBUFFULL | IPR_EFXBUFHALFFULL)) {
1130 if (sc->rch[1].channel)
1131 chn_intr(sc->rch[1].channel);
1133 if (ack & (IPR_MICBUFFULL | IPR_MICBUFHALFFULL)) {
1134 if (sc->rch[2].channel)
1135 chn_intr(sc->rch[2].channel);
1138 snd_mtxlock(sc->lock);
1141 snd_mtxunlock(sc->lock);
1144 /* -------------------------------------------------------------------- */
1147 emu_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1149 bus_addr_t *phys = arg;
1151 *phys = error ? 0 : (bus_addr_t)segs->ds_addr;
1154 kprintf("emu: setmap (%lx, %lx), nseg=%d, error=%d\n",
1155 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
1161 emu_malloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1167 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map))
1169 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, emu_setmap, addr, 0)
1176 emu_free(struct sc_info *sc, void *buf)
1178 bus_dmamem_free(sc->parent_dmat, buf, NULL);
1182 emu_memalloc(struct sc_info *sc, u_int32_t sz, bus_addr_t *addr)
1184 u_int32_t blksz, start, idx, ofs, tmp, found;
1185 struct emu_mem *mem = &sc->mem;
1186 struct emu_memblk *blk;
1189 blksz = sz / EMUPAGESIZE;
1190 if (sz > (blksz * EMUPAGESIZE))
1192 /* find a kfree block in the bitmap */
1195 while (!found && start + blksz < EMUMAXPAGES) {
1197 for (idx = start; idx < start + blksz; idx++)
1198 if (mem->bmap[idx >> 3] & (1 << (idx & 7)))
1205 blk = kmalloc(sizeof(*blk), M_DEVBUF, M_WAITOK);
1206 buf = emu_malloc(sc, sz, &blk->buf_addr);
1207 *addr = blk->buf_addr;
1209 kfree(blk, M_DEVBUF);
1213 blk->pte_start = start;
1214 blk->pte_size = blksz;
1216 kprintf("buf %p, pte_start %d, pte_size %d\n", blk->buf,
1217 blk->pte_start, blk->pte_size);
1220 for (idx = start; idx < start + blksz; idx++) {
1221 mem->bmap[idx >> 3] |= 1 << (idx & 7);
1222 tmp = (u_int32_t)(u_long)((u_int8_t *)blk->buf_addr + ofs);
1224 kprintf("pte[%d] -> %x phys, %x virt\n", idx, tmp,
1225 ((u_int32_t)buf) + ofs);
1227 mem->ptb_pages[idx] = (tmp << 1) | idx;
1230 SLIST_INSERT_HEAD(&mem->blocks, blk, link);
1235 emu_memfree(struct sc_info *sc, void *buf)
1238 struct emu_mem *mem = &sc->mem;
1239 struct emu_memblk *blk, *i;
1242 SLIST_FOREACH(i, &mem->blocks, link) {
1248 SLIST_REMOVE(&mem->blocks, blk, emu_memblk, link);
1250 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1251 for (idx = blk->pte_start; idx < blk->pte_start + blk->pte_size; idx++) {
1252 mem->bmap[idx >> 3] &= ~(1 << (idx & 7));
1253 mem->ptb_pages[idx] = tmp | idx;
1255 kfree(blk, M_DEVBUF);
1260 emu_memstart(struct sc_info *sc, void *buf)
1262 struct emu_mem *mem = &sc->mem;
1263 struct emu_memblk *blk, *i;
1266 SLIST_FOREACH(i, &mem->blocks, link) {
1272 return blk->pte_start;
1276 emu_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1279 emu_wrefx(sc, (*pc) * 2, (x << 10) | y);
1280 emu_wrefx(sc, (*pc) * 2 + 1, (op << 20) | (z << 10) | w);
1285 audigy_addefxop(struct sc_info *sc, int op, int z, int w, int x, int y,
1288 emu_wrefx(sc, (*pc) * 2, (x << 12) | y);
1289 emu_wrefx(sc, (*pc) * 2 + 1, (op << 24) | (z << 12) | w);
1294 audigy_initefx(struct sc_info *sc)
1299 /* skip 0, 0, -1, 0 - NOPs */
1300 for (i = 0; i < 512; i++)
1301 audigy_addefxop(sc, 0x0f, 0x0c0, 0x0c0, 0x0cf, 0x0c0, &pc);
1303 for (i = 0; i < 512; i++)
1304 emu_wrptr(sc, 0, A_FXGPREGBASE + i, 0x0);
1308 /* stop fx processor */
1309 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1311 /* Audigy 2 (EMU10K2) DSP Registers:
1313 0x000-0x00f : 16 registers (???)
1315 0x040/0x041 : AC97 Codec (l/r)
1316 0x042/0x043 : ADC, S/PDIF (l/r)
1317 0x044/0x045 : Optical S/PDIF in (l/r)
1319 0x048/0x049 : Line/Mic 2 (l/r)
1320 0x04a/0x04b : RCA S/PDIF (l/r)
1321 0x04c/0x04d : Aux 2 (l/r)
1323 0x060/0x061 : Digital Front (l/r)
1324 0x062/0x063 : Digital Center/LFE
1325 0x064/0x065 : AudigyDrive Heaphone (l/r)
1326 0x066/0x067 : Digital Rear (l/r)
1327 0x068/0x069 : Analog Front (l/r)
1328 0x06a/0x06b : Analog Center/LFE
1330 0x06e/0x06f : Analog Rear (l/r)
1331 0x070/0x071 : AC97 Output (l/r)
1334 0x076/0x077 : ADC Recording Buffer (l/r)
1336 0x0c0 - 0x0c4 = 0 - 4
1337 0x0c5 = 0x8, 0x0c6 = 0x10, 0x0c7 = 0x20
1338 0x0c8 = 0x100, 0x0c9 = 0x10000, 0x0ca = 0x80000
1339 0x0cb = 0x10000000, 0x0cc = 0x20000000, 0x0cd = 0x40000000
1340 0x0ce = 0x80000000, 0x0cf = 0x7fffffff, 0x0d0 = 0xffffffff
1341 0x0d1 = 0xfffffffe, 0x0d2 = 0xc0000000, 0x0d3 = 0x41fbbcdc
1342 0x0d4 = 0x5a7ef9db, 0x0d5 = 0x00100000, 0x0dc = 0x00000001 (???)
1344 0x0d6 : Accumulator (???)
1345 0x0d7 : Condition Register
1346 0x0d8 : Noise source
1347 0x0d9 : Noise source
1348 Tank Memory Data Registers
1350 Tank Memory Address Registers
1352 General Purpose Registers
1356 /* AC97Output[l/r] = FXBus PCM[l/r] */
1357 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_L), A_C_00000000,
1358 A_C_00000000, A_FXBUS(FXBUS_PCM_LEFT), &pc);
1359 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AC97_R), A_C_00000000,
1360 A_C_00000000, A_FXBUS(FXBUS_PCM_RIGHT), &pc);
1362 /* GPR[0/1] = RCA S/PDIF[l/r] -- Master volume */
1363 audigy_addefxop(sc, iACC3, A_GPR(0), A_C_00000000,
1364 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_L), &pc);
1365 audigy_addefxop(sc, iACC3, A_GPR(1), A_C_00000000,
1366 A_C_00000000, A_EXTIN(EXTIN_COAX_SPDIF_R), &pc);
1368 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1369 audigy_addefxop(sc, iINTERP, A_GPR(2), A_GPR(1),
1370 A_C_40000000, A_GPR(0), &pc);
1372 /* Headphones[l/r] = GPR[0/1] */
1373 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_L),
1374 A_C_00000000, A_C_00000000, A_GPR(0), &pc);
1375 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_HEADPHONE_R),
1376 A_C_00000000, A_C_00000000, A_GPR(1), &pc);
1378 /* Analog Front[l/r] = GPR[0/1] */
1379 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_L), A_C_00000000,
1380 A_C_00000000, A_GPR(0), &pc);
1381 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AFRONT_R), A_C_00000000,
1382 A_C_00000000, A_GPR(1), &pc);
1384 /* Digital Front[l/r] = GPR[0/1] */
1385 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L), A_C_00000000,
1386 A_C_00000000, A_GPR(0), &pc);
1387 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_FRONT_R), A_C_00000000,
1388 A_C_00000000, A_GPR(1), &pc);
1390 /* Center and Subwoofer configuration */
1391 /* Analog Center = GPR[0] + GPR[2] */
1392 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ACENTER), A_C_00000000,
1393 A_GPR(0), A_GPR(2), &pc);
1394 /* Analog Sub = GPR[1] + GPR[2] */
1395 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ALFE), A_C_00000000,
1396 A_GPR(1), A_GPR(2), &pc);
1398 /* Digital Center = GPR[0] + GPR[2] */
1399 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_CENTER), A_C_00000000,
1400 A_GPR(0), A_GPR(2), &pc);
1401 /* Digital Sub = GPR[1] + GPR[2] */
1402 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_LFE), A_C_00000000,
1403 A_GPR(1), A_GPR(2), &pc);
1406 /* Analog Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1407 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1408 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1409 A_GPR(16), A_GPR(0), &pc);
1410 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1411 A_GPR(17), A_GPR(1), &pc);
1413 /* Digital Rear[l/r] = (GPR[0/1] * RearVolume[l/r]) >> 31 */
1414 /* RearVolume = GPR[0x10/0x11] (Will this ever be implemented?) */
1415 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1416 A_GPR(16), A_GPR(0), &pc);
1417 audigy_addefxop(sc, iMAC0, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1418 A_GPR(17), A_GPR(1), &pc);
1420 /* XXX This is just a copy to the channel, since we do not have
1421 * a patch manager, it is useful for have another output enabled.
1424 /* Analog Rear[l/r] = GPR[0/1] */
1425 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_L), A_C_00000000,
1426 A_C_00000000, A_GPR(0), &pc);
1427 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_AREAR_R), A_C_00000000,
1428 A_C_00000000, A_GPR(1), &pc);
1430 /* Digital Rear[l/r] = GPR[0/1] */
1431 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_L), A_C_00000000,
1432 A_C_00000000, A_GPR(0), &pc);
1433 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_REAR_R), A_C_00000000,
1434 A_C_00000000, A_GPR(1), &pc);
1437 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1438 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_L), A_C_00000000,
1439 A_C_00000000, A_EXTIN(A_EXTIN_AC97_L), &pc);
1440 audigy_addefxop(sc, iACC3, A_EXTOUT(A_EXTOUT_ADC_CAP_R), A_C_00000000,
1441 A_C_00000000, A_EXTIN(A_EXTIN_AC97_R), &pc);
1443 /* resume normal operations */
1444 emu_wrptr(sc, 0, A_DBG, 0);
1448 emu_initefx(struct sc_info *sc)
1453 /* acc3 0,0,0,0 - NOPs */
1454 for (i = 0; i < 512; i++) {
1455 emu_wrefx(sc, i * 2, 0x10040);
1456 emu_wrefx(sc, i * 2 + 1, 0x610040);
1459 for (i = 0; i < 256; i++)
1460 emu_wrptr(sc, 0, FXGPREGBASE + i, 0);
1462 /* FX-8010 DSP Registers:
1464 0x000-0x00f : 16 registers
1466 0x010/0x011 : AC97 Codec (l/r)
1467 0x012/0x013 : ADC, S/PDIF (l/r)
1468 0x014/0x015 : Mic(left), Zoom (l/r)
1469 0x016/0x017 : TOS link in (l/r)
1470 0x018/0x019 : Line/Mic 1 (l/r)
1471 0x01a/0x01b : COAX S/PDIF (l/r)
1472 0x01c/0x01d : Line/Mic 2 (l/r)
1474 0x020/0x021 : AC97 Output (l/r)
1475 0x022/0x023 : TOS link out (l/r)
1476 0x024/0x025 : Center/LFE
1477 0x026/0x027 : LiveDrive Headphone (l/r)
1478 0x028/0x029 : Rear Channel (l/r)
1479 0x02a/0x02b : ADC Recording Buffer (l/r)
1480 0x02c : Mic Recording Buffer
1481 0x031/0x032 : Analog Center/LFE
1483 0x040 - 0x044 = 0 - 4
1484 0x045 = 0x8, 0x046 = 0x10, 0x047 = 0x20
1485 0x048 = 0x100, 0x049 = 0x10000, 0x04a = 0x80000
1486 0x04b = 0x10000000, 0x04c = 0x20000000, 0x04d = 0x40000000
1487 0x04e = 0x80000000, 0x04f = 0x7fffffff, 0x050 = 0xffffffff
1488 0x051 = 0xfffffffe, 0x052 = 0xc0000000, 0x053 = 0x41fbbcdc
1489 0x054 = 0x5a7ef9db, 0x055 = 0x00100000
1492 0x057 : Condition Register
1493 0x058 : Noise source
1494 0x059 : Noise source
1495 0x05a : IRQ Register
1496 0x05b : TRAM Delay Base Address Count
1497 General Purpose Registers
1499 Tank Memory Data Registers
1501 Tank Memory Address Registers
1505 /* Routing - this will be configurable in later version */
1507 /* GPR[0/1] = FX * 4 + SPDIF-in */
1508 emu_addefxop(sc, iMACINT0, GPR(0), EXTIN(EXTIN_SPDIF_CD_L),
1509 FXBUS(FXBUS_PCM_LEFT), C_00000004, &pc);
1510 emu_addefxop(sc, iMACINT0, GPR(1), EXTIN(EXTIN_SPDIF_CD_R),
1511 FXBUS(FXBUS_PCM_RIGHT), C_00000004, &pc);
1513 /* GPR[0/1] += APS-input */
1514 emu_addefxop(sc, iACC3, GPR(0), GPR(0), C_00000000,
1515 sc->APS ? EXTIN(EXTIN_TOSLINK_L) : C_00000000, &pc);
1516 emu_addefxop(sc, iACC3, GPR(1), GPR(1), C_00000000,
1517 sc->APS ? EXTIN(EXTIN_TOSLINK_R) : C_00000000, &pc);
1519 /* FrontOut (AC97) = GPR[0/1] */
1520 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_L), C_00000000,
1521 C_00000000, GPR(0), &pc);
1522 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_AC97_R), C_00000000,
1523 C_00000001, GPR(1), &pc);
1525 /* GPR[2] = GPR[0] (Left) / 2 + GPR[1] (Right) / 2 -- Central volume */
1526 emu_addefxop(sc, iINTERP, GPR(2), GPR(1), C_40000000, GPR(0), &pc);
1529 /* RearOut = (GPR[0/1] * RearVolume) >> 31 */
1530 /* RearVolume = GPR[0x10/0x11] */
1531 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_L), C_00000000,
1532 GPR(16), GPR(0), &pc);
1533 emu_addefxop(sc, iMAC0, EXTOUT(EXTOUT_REAR_R), C_00000000,
1534 GPR(17), GPR(1), &pc);
1536 /* XXX This is just a copy to the channel, since we do not have
1537 * a patch manager, it is useful for have another output enabled.
1540 /* Rear[l/r] = GPR[0/1] */
1541 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_L), C_00000000,
1542 C_00000000, GPR(0), &pc);
1543 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_REAR_R), C_00000000,
1544 C_00000000, GPR(1), &pc);
1547 /* TOS out[l/r] = GPR[0/1] */
1548 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_L), C_00000000,
1549 C_00000000, GPR(0), &pc);
1550 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_TOSLINK_R), C_00000000,
1551 C_00000000, GPR(1), &pc);
1553 /* Center and Subwoofer configuration */
1554 /* Analog Center = GPR[0] + GPR[2] */
1555 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ACENTER), C_00000000,
1556 GPR(0), GPR(2), &pc);
1557 /* Analog Sub = GPR[1] + GPR[2] */
1558 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ALFE), C_00000000,
1559 GPR(1), GPR(2), &pc);
1560 /* Digital Center = GPR[0] + GPR[2] */
1561 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_CENTER), C_00000000,
1562 GPR(0), GPR(2), &pc);
1563 /* Digital Sub = GPR[1] + GPR[2] */
1564 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_LFE), C_00000000,
1565 GPR(1), GPR(2), &pc);
1567 /* Headphones[l/r] = GPR[0/1] */
1568 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_L), C_00000000,
1569 C_00000000, GPR(0), &pc);
1570 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_HEADPHONE_R), C_00000000,
1571 C_00000000, GPR(1), &pc);
1573 /* ADC Recording buffer[l/r] = AC97Input[l/r] */
1574 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_L), C_00000000,
1575 C_00000000, EXTIN(EXTIN_AC97_L), &pc);
1576 emu_addefxop(sc, iACC3, EXTOUT(EXTOUT_ADC_CAP_R), C_00000000,
1577 C_00000000, EXTIN(EXTIN_AC97_R), &pc);
1579 /* resume normal operations */
1580 emu_wrptr(sc, 0, DBG, 0);
1583 /* Probe and attach the card */
1585 emu_init(struct sc_info *sc)
1587 u_int32_t spcs, ch, tmp, i;
1590 /* enable additional AC97 slots */
1591 emu_wrptr(sc, 0, AC97SLOT, AC97SLOT_CNTR | AC97SLOT_LFE);
1594 /* disable audio and lock cache */
1596 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
1599 /* reset recording buffers */
1600 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1601 emu_wrptr(sc, 0, MICBA, 0);
1602 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1603 emu_wrptr(sc, 0, FXBA, 0);
1604 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1605 emu_wrptr(sc, 0, ADCBA, 0);
1607 /* disable channel interrupt */
1609 INTE_INTERVALTIMERENB | INTE_SAMPLERATETRACKER | INTE_PCIERRORENABLE,
1611 emu_wrptr(sc, 0, CLIEL, 0);
1612 emu_wrptr(sc, 0, CLIEH, 0);
1613 emu_wrptr(sc, 0, SOLEL, 0);
1614 emu_wrptr(sc, 0, SOLEH, 0);
1616 /* wonder what these do... */
1618 emu_wrptr(sc, 0, SPBYPASS, 0xf00);
1619 emu_wrptr(sc, 0, AC97SLOT, 0x3);
1622 /* init envelope engine */
1623 for (ch = 0; ch < NUM_G; ch++) {
1624 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1625 emu_wrptr(sc, ch, IP, 0);
1626 emu_wrptr(sc, ch, VTFT, 0xffff);
1627 emu_wrptr(sc, ch, CVCF, 0xffff);
1628 emu_wrptr(sc, ch, PTRX, 0);
1629 emu_wrptr(sc, ch, CPF, 0);
1630 emu_wrptr(sc, ch, CCR, 0);
1632 emu_wrptr(sc, ch, PSST, 0);
1633 emu_wrptr(sc, ch, DSL, 0x10);
1634 emu_wrptr(sc, ch, CCCA, 0);
1635 emu_wrptr(sc, ch, Z1, 0);
1636 emu_wrptr(sc, ch, Z2, 0);
1637 emu_wrptr(sc, ch, FXRT, 0xd01c0000);
1639 emu_wrptr(sc, ch, ATKHLDM, 0);
1640 emu_wrptr(sc, ch, DCYSUSM, 0);
1641 emu_wrptr(sc, ch, IFATN, 0xffff);
1642 emu_wrptr(sc, ch, PEFE, 0);
1643 emu_wrptr(sc, ch, FMMOD, 0);
1644 emu_wrptr(sc, ch, TREMFRQ, 24); /* 1 Hz */
1645 emu_wrptr(sc, ch, FM2FRQ2, 24); /* 1 Hz */
1646 emu_wrptr(sc, ch, TEMPENV, 0);
1648 /*** these are last so OFF prevents writing ***/
1649 emu_wrptr(sc, ch, LFOVAL2, 0);
1650 emu_wrptr(sc, ch, LFOVAL1, 0);
1651 emu_wrptr(sc, ch, ATKHLDV, 0);
1652 emu_wrptr(sc, ch, ENVVOL, 0);
1653 emu_wrptr(sc, ch, ENVVAL, 0);
1656 /* audigy cards need this to initialize correctly */
1657 emu_wrptr(sc, ch, 0x4c, 0);
1658 emu_wrptr(sc, ch, 0x4d, 0);
1659 emu_wrptr(sc, ch, 0x4e, 0);
1660 emu_wrptr(sc, ch, 0x4f, 0);
1661 /* set default routing */
1662 emu_wrptr(sc, ch, A_FXRT1, 0x03020100);
1663 emu_wrptr(sc, ch, A_FXRT2, 0x3f3f3f3f);
1664 emu_wrptr(sc, ch, A_SENDAMOUNTS, 0);
1667 sc->voice[ch].vnum = ch;
1668 sc->voice[ch].slave = NULL;
1669 sc->voice[ch].busy = 0;
1670 sc->voice[ch].ismaster = 0;
1671 sc->voice[ch].running = 0;
1672 sc->voice[ch].b16 = 0;
1673 sc->voice[ch].stereo = 0;
1674 sc->voice[ch].speed = 0;
1675 sc->voice[ch].start = 0;
1676 sc->voice[ch].end = 0;
1677 sc->voice[ch].channel = NULL;
1679 sc->pnum = sc->rnum = 0;
1682 * Init to 0x02109204 :
1683 * Clock accuracy = 0 (1000ppm)
1684 * Sample Rate = 2 (48kHz)
1685 * Audio Channel = 1 (Left of 2)
1686 * Source Number = 0 (Unspecified)
1687 * Generation Status = 1 (Original for Cat Code 12)
1688 * Cat Code = 12 (Digital Signal Mixer)
1690 * Emphasis = 0 (None)
1691 * CP = 1 (Copyright unasserted)
1692 * AN = 0 (Audio data)
1695 spcs = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1696 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1697 SPCS_GENERATIONSTATUS | 0x00001200 | 0x00000000 |
1698 SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1699 emu_wrptr(sc, 0, SPCS0, spcs);
1700 emu_wrptr(sc, 0, SPCS1, spcs);
1701 emu_wrptr(sc, 0, SPCS2, spcs);
1705 else if (sc->audigy2) { /* Audigy 2 */
1706 /* from ALSA initialization code: */
1708 /* Hack for Alice3 to work independent of haP16V driver */
1711 /* Setup SRCMulti_I2S SamplingRate */
1712 tmp = emu_rdptr(sc, 0, A_SPDIF_SAMPLERATE) & 0xfffff1ff;
1713 emu_wrptr(sc, 0, A_SPDIF_SAMPLERATE, tmp | 0x400);
1715 /* Setup SRCSel (Enable SPDIF, I2S SRCMulti) */
1716 emu_wr(sc, 0x20, 0x00600000, 4);
1717 emu_wr(sc, 0x24, 0x00000014, 4);
1719 /* Setup SRCMulti Input Audio Enable */
1720 emu_wr(sc, 0x20, 0x006e0000, 4);
1721 emu_wr(sc, 0x24, 0xff00ff00, 4);
1724 SLIST_INIT(&sc->mem.blocks);
1725 sc->mem.ptb_pages = emu_malloc(sc, EMUMAXPAGES * sizeof(u_int32_t),
1726 &sc->mem.ptb_pages_addr);
1727 if (sc->mem.ptb_pages == NULL)
1730 sc->mem.silent_page = emu_malloc(sc, EMUPAGESIZE,
1731 &sc->mem.silent_page_addr);
1732 if (sc->mem.silent_page == NULL) {
1733 emu_free(sc, sc->mem.ptb_pages);
1736 /* Clear page with silence & setup all pointers to this page */
1737 bzero(sc->mem.silent_page, EMUPAGESIZE);
1738 tmp = (u_int32_t)(sc->mem.silent_page_addr) << 1;
1739 for (i = 0; i < EMUMAXPAGES; i++)
1740 sc->mem.ptb_pages[i] = tmp | i;
1742 emu_wrptr(sc, 0, PTB, (sc->mem.ptb_pages_addr));
1743 emu_wrptr(sc, 0, TCB, 0); /* taken from original driver */
1744 emu_wrptr(sc, 0, TCBS, 0); /* taken from original driver */
1746 for (ch = 0; ch < NUM_G; ch++) {
1747 emu_wrptr(sc, ch, MAPA, tmp | MAP_PTI_MASK);
1748 emu_wrptr(sc, ch, MAPB, tmp | MAP_PTI_MASK);
1751 /* emu_memalloc(sc, EMUPAGESIZE); */
1753 * Hokay, now enable the AUD bit
1756 * Enable Audio = 0 (enabled after fx processor initialization)
1757 * Mute Disable Audio = 0
1762 * Mute Disable Audio = 0
1764 * GP S/PDIF AC3 Enable = 1
1765 * CD S/PDIF AC3 Enable = 1
1769 * Mute Disable Audio = 0
1770 * Lock Tank Memory = 1
1771 * Lock Sound Memory = 0
1776 tmp = HCFG_AUTOMUTE | HCFG_JOYENABLE;
1777 if (sc->audigy2) /* Audigy 2 */
1778 tmp = HCFG_AUDIOENABLE | HCFG_AC3ENABLE_CDSPDIF |
1779 HCFG_AC3ENABLE_GPSPDIF;
1780 emu_wr(sc, HCFG, tmp, 4);
1784 /* from ALSA initialization code: */
1786 /* enable audio and disable both audio/digital outputs */
1787 emu_wr(sc, HCFG, emu_rd(sc, HCFG, 4) | HCFG_AUDIOENABLE, 4);
1788 emu_wr(sc, A_IOCFG, emu_rd(sc, A_IOCFG, 4) & ~A_IOCFG_GPOUT_AD,
1790 if (sc->audigy2) { /* Audigy 2 */
1792 * Set GPO6 to 1 for Apollo. This has to be done after
1793 * init Alice3 I2SOut beyond 48kHz.
1794 * So, sequence is important.
1797 emu_rd(sc, A_IOCFG, 4) | A_IOCFG_GPOUT_A, 4);
1800 /* EMU10K1 initialization code */
1801 tmp = HCFG_AUDIOENABLE | HCFG_LOCKTANKCACHE_MASK
1804 tmp |= HCFG_JOYENABLE;
1806 emu_wr(sc, HCFG, tmp, 4);
1808 /* TOSLink detection */
1810 tmp = emu_rd(sc, HCFG, 4);
1811 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
1812 emu_wr(sc, HCFG, tmp | HCFG_GPOUT1, 4);
1814 if (tmp != (emu_rd(sc, HCFG, 4) & ~HCFG_GPOUT1)) {
1816 emu_wr(sc, HCFG, tmp, 4);
1825 emu_uninit(struct sc_info *sc)
1829 emu_wr(sc, INTE, 0, 4);
1830 for (ch = 0; ch < NUM_G; ch++)
1831 emu_wrptr(sc, ch, DCYSUSV, ENV_OFF);
1832 for (ch = 0; ch < NUM_G; ch++) {
1833 emu_wrptr(sc, ch, VTFT, 0);
1834 emu_wrptr(sc, ch, CVCF, 0);
1835 emu_wrptr(sc, ch, PTRX, 0);
1836 emu_wrptr(sc, ch, CPF, 0);
1839 if (sc->audigy) { /* stop fx processor */
1840 emu_wrptr(sc, 0, A_DBG, A_DBG_SINGLE_STEP);
1843 /* disable audio and lock cache */
1845 HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
1848 emu_wrptr(sc, 0, PTB, 0);
1849 /* reset recording buffers */
1850 emu_wrptr(sc, 0, MICBS, ADCBS_BUFSIZE_NONE);
1851 emu_wrptr(sc, 0, MICBA, 0);
1852 emu_wrptr(sc, 0, FXBS, ADCBS_BUFSIZE_NONE);
1853 emu_wrptr(sc, 0, FXBA, 0);
1854 emu_wrptr(sc, 0, FXWC, 0);
1855 emu_wrptr(sc, 0, ADCBS, ADCBS_BUFSIZE_NONE);
1856 emu_wrptr(sc, 0, ADCBA, 0);
1857 emu_wrptr(sc, 0, TCB, 0);
1858 emu_wrptr(sc, 0, TCBS, 0);
1860 /* disable channel interrupt */
1861 emu_wrptr(sc, 0, CLIEL, 0);
1862 emu_wrptr(sc, 0, CLIEH, 0);
1863 emu_wrptr(sc, 0, SOLEL, 0);
1864 emu_wrptr(sc, 0, SOLEH, 0);
1866 /* init envelope engine */
1867 if (!SLIST_EMPTY(&sc->mem.blocks))
1868 device_printf(sc->dev, "warning: memblock list not empty\n");
1869 emu_free(sc, sc->mem.ptb_pages);
1870 emu_free(sc, sc->mem.silent_page);
1876 emu_pci_probe(device_t dev)
1880 switch (pci_get_devid(dev)) {
1881 case EMU10K1_PCI_ID:
1882 s = "Creative EMU10K1";
1885 case EMU10K2_PCI_ID:
1886 if (pci_get_revid(dev) == 0x04)
1887 s = "Creative Audigy 2 (EMU10K2)";
1889 s = "Creative Audigy (EMU10K2)";
1892 case EMU10K3_PCI_ID:
1893 s = "Creative Audigy 2 (EMU10K3)";
1900 device_set_desc(dev, s);
1901 return BUS_PROBE_DEFAULT;
1905 emu_pci_attach(device_t dev)
1907 struct ac97_info *codec = NULL;
1911 char status[SND_STATUSLEN];
1913 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
1915 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc");
1917 sc->type = pci_get_devid(dev);
1918 sc->rev = pci_get_revid(dev);
1919 sc->audigy = sc->type == EMU10K2_PCI_ID || sc->type == EMU10K3_PCI_ID;
1920 sc->audigy2 = (sc->audigy && sc->rev == 0x04);
1921 sc->nchans = sc->audigy ? 8 : 4;
1922 sc->addrmask = sc->audigy ? A_PTR_ADDRESS_MASK : PTR_ADDRESS_MASK;
1924 data = pci_read_config(dev, PCIR_COMMAND, 2);
1925 data |= (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN);
1926 pci_write_config(dev, PCIR_COMMAND, data, 2);
1927 data = pci_read_config(dev, PCIR_COMMAND, 2);
1930 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &i, RF_ACTIVE);
1931 if (sc->reg == NULL) {
1932 device_printf(dev, "unable to map register space\n");
1935 sc->st = rman_get_bustag(sc->reg);
1936 sc->sh = rman_get_bushandle(sc->reg);
1938 sc->bufsz = pcm_getbuffersize(dev, 4096, EMU_DEFAULT_BUFSZ, 65536);
1940 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1941 /*lowaddr*/1 << 31, /* can only access 0-2gb */
1942 /*highaddr*/BUS_SPACE_MAXADDR,
1943 /*filter*/NULL, /*filterarg*/NULL,
1944 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
1946 &sc->parent_dmat) != 0) {
1947 device_printf(dev, "unable to create dma tag\n");
1951 if (emu_init(sc) == -1) {
1952 device_printf(dev, "unable to initialize the card\n");
1956 codec = AC97_CREATE(dev, sc, emu_ac97);
1957 if (codec == NULL) goto bad;
1958 gotmic = (ac97_getcaps(codec) & AC97_CAP_MICCHANNEL) ? 1 : 0;
1959 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1) goto bad;
1962 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &i,
1963 RF_ACTIVE | RF_SHAREABLE);
1965 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, emu_intr, sc, &sc->ih)) {
1966 device_printf(dev, "unable to map interrupt\n");
1970 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
1971 rman_get_start(sc->reg), rman_get_start(sc->irq),
1972 PCM_KLDSTRING(snd_emu10k1));
1974 if (pcm_register(dev, sc, sc->nchans, gotmic ? 3 : 2)) goto bad;
1975 for (i = 0; i < sc->nchans; i++)
1976 pcm_addchan(dev, PCMDIR_PLAY, &emupchan_class, sc);
1977 for (i = 0; i < (gotmic ? 3 : 2); i++)
1978 pcm_addchan(dev, PCMDIR_REC, &emurchan_class, sc);
1980 pcm_setstatus(dev, status);
1985 if (codec) ac97_destroy(codec);
1986 if (sc->reg) bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
1987 if (sc->ih) bus_teardown_intr(dev, sc->irq, sc->ih);
1988 if (sc->irq) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
1989 if (sc->parent_dmat) bus_dma_tag_destroy(sc->parent_dmat);
1990 if (sc->lock) snd_mtxfree(sc->lock);
1991 kfree(sc, M_DEVBUF);
1996 emu_pci_detach(device_t dev)
2001 r = pcm_unregister(dev);
2005 sc = pcm_getdevinfo(dev);
2009 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), sc->reg);
2010 bus_teardown_intr(dev, sc->irq, sc->ih);
2011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
2012 bus_dma_tag_destroy(sc->parent_dmat);
2013 snd_mtxfree(sc->lock);
2014 kfree(sc, M_DEVBUF);
2019 /* add suspend, resume */
2020 static device_method_t emu_methods[] = {
2021 /* Device interface */
2022 DEVMETHOD(device_probe, emu_pci_probe),
2023 DEVMETHOD(device_attach, emu_pci_attach),
2024 DEVMETHOD(device_detach, emu_pci_detach),
2029 static driver_t emu_driver = {
2035 DRIVER_MODULE(snd_emu10k1, pci, emu_driver, pcm_devclass, NULL, NULL);
2036 DRIVER_MODULE(snd_emu10k1, cardbus, emu_driver, pcm_devclass, NULL, NULL);
2037 MODULE_DEPEND(snd_emu10k1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
2038 MODULE_VERSION(snd_emu10k1, 1);
2040 /* dummy driver to silence the joystick device */
2042 emujoy_pci_probe(device_t dev)
2046 switch (pci_get_devid(dev)) {
2048 s = "Creative EMU10K1 Joystick";
2052 s = "Creative EMU10K2 Joystick";
2057 if (s) device_set_desc(dev, s);
2058 return s ? -1000 : ENXIO;
2062 emujoy_pci_attach(device_t dev)
2068 emujoy_pci_detach(device_t dev)
2073 static device_method_t emujoy_methods[] = {
2074 DEVMETHOD(device_probe, emujoy_pci_probe),
2075 DEVMETHOD(device_attach, emujoy_pci_attach),
2076 DEVMETHOD(device_detach, emujoy_pci_detach),
2081 static driver_t emujoy_driver = {
2087 static devclass_t emujoy_devclass;
2089 DRIVER_MODULE(emujoy, pci, emujoy_driver, emujoy_devclass, NULL, NULL);