2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.53.2.12 2007/07/12 06:39:38 ariff Exp $
28 * $DragonFly: src/sys/dev/sound/pci/ich.c,v 1.17 2007/11/30 07:48:57 hasso Exp $
31 #include <dev/sound/pcm/sound.h>
32 #include <dev/sound/pcm/ac97.h>
33 #include <dev/sound/pci/ich.h>
35 #include <bus/pci/pcireg.h>
36 #include <bus/pci/pcivar.h>
38 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/ich.c,v 1.17 2007/11/30 07:48:57 hasso Exp $");
40 /* -------------------------------------------------------------------- */
42 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
43 #define ICH_DTBL_LENGTH 32
44 #define ICH_DEFAULT_BUFSZ 16384
45 #define ICH_MAX_BUFSZ 65536
46 #define ICH_MIN_BUFSZ 4096
47 #define ICH_DEFAULT_BLKCNT 2
48 #define ICH_MAX_BLKCNT 32
49 #define ICH_MIN_BLKCNT 2
50 #define ICH_MIN_BLKSZ 64
52 #define INTEL_VENDORID 0x8086
53 #define SIS_VENDORID 0x1039
54 #define NVIDIA_VENDORID 0x10de
55 #define AMD_VENDORID 0x1022
57 #define INTEL_82440MX 0x7195
58 #define INTEL_82801AA 0x2415
59 #define INTEL_82801AB 0x2425
60 #define INTEL_82801BA 0x2445
61 #define INTEL_82801CA 0x2485
62 #define INTEL_82801DB 0x24c5 /* ICH4 needs special handling */
63 #define INTEL_82801EB 0x24d5 /* ICH5 needs to be treated as ICH4 */
64 #define INTEL_6300ESB 0x25a6 /* 6300ESB needs to be treated as ICH4 */
65 #define INTEL_82801FB 0x266e /* ICH6 needs to be treated as ICH4 */
66 #define INTEL_82801GB 0x27de /* ICH7 needs to be treated as ICH4 */
67 #define SIS_7012 0x7012 /* SiS 7012 needs special handling */
68 #define NVIDIA_NFORCE 0x01b1
69 #define NVIDIA_NFORCE2 0x006a
70 #define NVIDIA_NFORCE2_400 0x008a
71 #define NVIDIA_NFORCE3 0x00da
72 #define NVIDIA_NFORCE3_250 0x00ea
73 #define NVIDIA_NFORCE4 0x0059
74 #define NVIDIA_NFORCE_410_MCP 0x026b
75 #define NVIDIA_NFORCE4_MCP 0x003a
76 #define AMD_768 0x7445
77 #define AMD_8111 0x746d
79 #define ICH_LOCK(sc) snd_mtxlock((sc)->ich_lock)
80 #define ICH_UNLOCK(sc) snd_mtxunlock((sc)->ich_lock)
81 #define ICH_LOCK_ASSERT(sc) snd_mtxassert((sc)->ich_lock)
84 #define ICH_DEBUG(stmt) do { \
88 #define ICH_DEBUG(...)
91 #define ICH_CALIBRATE_DONE (1 << 0)
92 #define ICH_IGNORE_PCR (1 << 1)
93 #define ICH_IGNORE_RESET (1 << 2)
94 #define ICH_FIXED_RATE (1 << 3)
95 #define ICH_DMA_NOCACHE (1 << 4)
96 #define ICH_HIGH_LATENCY (1 << 5)
98 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
99 #include <machine/specialreg.h>
100 #define ICH_DMA_ATTR(sc, v, s, attr) do { \
101 vm_offset_t va = (vm_offset_t)(v); \
102 vm_size_t sz = (vm_size_t)(s); \
103 if ((sc) != NULL && ((sc)->flags & ICH_DMA_NOCACHE) && \
104 va != 0 && sz != 0) \
105 (void)pmap_change_attr(va, sz, (attr)); \
108 #define ICH_DMA_ATTR(...)
111 static const struct ich_type {
115 #define PROBE_LOW 0x01
118 { INTEL_VENDORID, INTEL_82440MX, 0,
120 { INTEL_VENDORID, INTEL_82801AA, 0,
121 "Intel ICH (82801AA)" },
122 { INTEL_VENDORID, INTEL_82801AB, 0,
123 "Intel ICH (82801AB)" },
124 { INTEL_VENDORID, INTEL_82801BA, 0,
125 "Intel ICH2 (82801BA)" },
126 { INTEL_VENDORID, INTEL_82801CA, 0,
127 "Intel ICH3 (82801CA)" },
128 { INTEL_VENDORID, INTEL_82801DB, PROBE_LOW,
129 "Intel ICH4 (82801DB)" },
130 { INTEL_VENDORID, INTEL_82801EB, PROBE_LOW,
131 "Intel ICH5 (82801EB)" },
132 { INTEL_VENDORID, INTEL_6300ESB, PROBE_LOW,
134 { INTEL_VENDORID, INTEL_82801FB, PROBE_LOW,
135 "Intel ICH6 (82801FB)" },
136 { INTEL_VENDORID, INTEL_82801GB, PROBE_LOW,
137 "Intel ICH7 (82801GB)" },
138 { SIS_VENDORID, SIS_7012, 0,
140 { NVIDIA_VENDORID, NVIDIA_NFORCE, 0,
142 { NVIDIA_VENDORID, NVIDIA_NFORCE2, 0,
144 { NVIDIA_VENDORID, NVIDIA_NFORCE2_400, 0,
145 "nVidia nForce2 400" },
146 { NVIDIA_VENDORID, NVIDIA_NFORCE3, 0,
148 { NVIDIA_VENDORID, NVIDIA_NFORCE3_250, 0,
149 "nVidia nForce3 250" },
150 { NVIDIA_VENDORID, NVIDIA_NFORCE4, 0,
152 { NVIDIA_VENDORID, NVIDIA_NFORCE_410_MCP, 0,
153 "nVidia nForce 410 MCP" },
154 { NVIDIA_VENDORID, NVIDIA_NFORCE4_MCP, 0,
155 "nVidia nForce 4 MCP" },
156 { AMD_VENDORID, AMD_768, 0,
158 { AMD_VENDORID, AMD_8111, 0,
162 /* buffer descriptor */
164 volatile uint32_t buffer;
165 volatile uint32_t length;
170 /* channel registers */
172 uint32_t num:8, run:1, run_save:1;
173 uint32_t blksz, blkcnt, spd;
174 uint32_t regbase, spdreg;
178 struct snd_dbuf *buffer;
179 struct pcm_channel *channel;
180 struct sc_info *parent;
182 struct ich_desc *dtbl;
183 bus_addr_t desc_addr;
186 /* device private data */
189 int hasvra, hasvrm, hasmic;
190 unsigned int chnum, bufsz, blkcnt;
191 int sample_size, swap_reg;
193 struct resource *nambar, *nabmbar, *irq;
194 int regtype, nambarid, nabmbarid, irqid;
195 bus_space_tag_t nambart, nabmbart;
196 bus_space_handle_t nambarh, nabmbarh;
197 bus_dma_tag_t dmat, chan_dmat;
201 struct ac97_info *codec;
202 struct sc_chinfo ch[3];
204 struct ich_desc *dtbl;
205 unsigned int dtbl_size;
206 bus_addr_t desc_addr;
207 struct intr_config_hook intrhook;
214 #define IGNORE_PCR 0x01
216 /* -------------------------------------------------------------------- */
218 static uint32_t ich_fmt[] = {
219 AFMT_STEREO | AFMT_S16_LE,
222 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
223 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
225 /* -------------------------------------------------------------------- */
227 static __inline uint32_t
228 ich_rd(struct sc_info *sc, int regno, int size)
232 return (bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno));
234 return (bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno));
236 return (bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno));
243 ich_wr(struct sc_info *sc, int regno, uint32_t data, int size)
247 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
250 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
253 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
260 ich_waitcd(void *devinfo)
262 struct sc_info *sc = (struct sc_info *)devinfo;
266 for (i = 0; i < ICH_TIMEOUT; i++) {
267 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
268 if ((data & 0x01) == 0)
272 if ((sc->flags & ICH_IGNORE_PCR) != 0)
274 device_printf(sc->dev, "CODEC semaphore timeout\n");
279 ich_rdcd(kobj_t obj, void *devinfo, int regno)
281 struct sc_info *sc = (struct sc_info *)devinfo;
286 return (bus_space_read_2(sc->nambart, sc->nambarh, regno));
290 ich_wrcd(kobj_t obj, void *devinfo, int regno, uint16_t data)
292 struct sc_info *sc = (struct sc_info *)devinfo;
296 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
301 static kobj_method_t ich_ac97_methods[] = {
302 KOBJMETHOD(ac97_read, ich_rdcd),
303 KOBJMETHOD(ac97_write, ich_wrcd),
306 AC97_DECLARE(ich_ac97);
308 /* -------------------------------------------------------------------- */
309 /* common routines */
312 ich_filldtbl(struct sc_chinfo *ch)
314 struct sc_info *sc = ch->parent;
318 base = sndbuf_getbufaddr(ch->buffer);
319 if ((ch->blksz * ch->blkcnt) > sndbuf_getmaxsize(ch->buffer))
320 ch->blksz = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
321 if ((sndbuf_getblksz(ch->buffer) != ch->blksz ||
322 sndbuf_getblkcnt(ch->buffer) != ch->blkcnt) &&
323 sndbuf_resize(ch->buffer, ch->blkcnt, ch->blksz) != 0)
324 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
325 __func__, ch->blksz, ch->blkcnt);
326 ch->blksz = sndbuf_getblksz(ch->buffer);
328 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
329 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
330 ch->dtbl[i].length = ICH_BDC_IOC
331 | (ch->blksz / ch->parent->sample_size);
336 ich_resetchan(struct sc_info *sc, int num)
341 regbase = ICH_REG_PO_BASE;
343 regbase = ICH_REG_PI_BASE;
345 regbase = ICH_REG_MC_BASE;
349 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
351 /* This may result in no sound output on NForce 2 MBs, see PR 73987 */
354 (void)ich_rd(sc, regbase + ICH_REG_X_CR, 1);
356 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
357 for (i = 0; i < ICH_TIMEOUT; i++) {
358 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
364 if (sc->flags & ICH_IGNORE_RESET)
367 else if (sc->vendor == NVIDIA_VENDORID) {
368 sc->flags |= ICH_IGNORE_RESET;
369 device_printf(sc->dev, "ignoring reset failure!\n");
374 device_printf(sc->dev, "cannot reset channel %d\n", num);
378 /* -------------------------------------------------------------------- */
379 /* channel interface */
382 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
384 struct sc_info *sc = devinfo;
385 struct sc_chinfo *ch;
396 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
397 ch->desc_addr = sc->desc_addr +
398 (ch->num * ICH_DTBL_LENGTH * sizeof(struct ich_desc));
399 ch->blkcnt = sc->blkcnt;
400 ch->blksz = sc->bufsz / ch->blkcnt;
404 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
405 ch->regbase = ICH_REG_PO_BASE;
406 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_FDACRATE : 0;
407 ch->imask = ICH_GLOB_STA_POINT;
411 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
412 ch->regbase = ICH_REG_PI_BASE;
413 ch->spdreg = (sc->hasvra) ? AC97_REGEXT_LADCRATE : 0;
414 ch->imask = ICH_GLOB_STA_PIINT;
418 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
419 ch->regbase = ICH_REG_MC_BASE;
420 ch->spdreg = (sc->hasvrm) ? AC97_REGEXT_MADCRATE : 0;
421 ch->imask = ICH_GLOB_STA_MINT;
428 if (sc->flags & ICH_FIXED_RATE)
432 if (sndbuf_alloc(ch->buffer, sc->chan_dmat, sc->bufsz) != 0)
435 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer),
436 sndbuf_getmaxsize(ch->buffer), PAT_UNCACHEABLE);
439 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
446 ichchan_free(kobj_t obj, void *data)
448 struct sc_chinfo *ch;
451 ch = (struct sc_chinfo *)data;
452 sc = (ch != NULL) ? ch->parent : NULL;
453 if (ch != NULL && sc != NULL) {
454 ICH_DMA_ATTR(sc, sndbuf_getbuf(ch->buffer),
455 sndbuf_getmaxsize(ch->buffer), PAT_WRITE_BACK);
462 ichchan_setformat(kobj_t obj, void *data, uint32_t format)
466 struct sc_chinfo *ch = data;
467 struct sc_info *sc = ch->parent;
468 if (!(sc->flags & ICH_CALIBRATE_DONE))
469 device_printf(sc->dev,
470 "WARNING: %s() called before calibration!\n",
478 ichchan_setspeed(kobj_t obj, void *data, uint32_t speed)
480 struct sc_chinfo *ch = data;
481 struct sc_info *sc = ch->parent;
484 if (!(sc->flags & ICH_CALIBRATE_DONE))
485 device_printf(sc->dev,
486 "WARNING: %s() called before calibration!\n",
494 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
495 sc->ac97rate = 48000;
496 ac97rate = sc->ac97rate;
498 r = (speed * 48000) / ac97rate;
500 * Cast the return value of ac97_setrate() to uint64 so that
501 * the math don't overflow into the negative range.
503 ch->spd = ((uint64_t)ac97_setrate(sc->codec, ch->spdreg, r) *
512 ichchan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
514 struct sc_chinfo *ch = data;
515 struct sc_info *sc = ch->parent;
518 if (!(sc->flags & ICH_CALIBRATE_DONE))
519 device_printf(sc->dev,
520 "WARNING: %s() called before calibration!\n",
524 if (sc->flags & ICH_HIGH_LATENCY)
525 blocksize = sndbuf_getmaxsize(ch->buffer) / ch->blkcnt;
527 if (blocksize < ICH_MIN_BLKSZ)
528 blocksize = ICH_MIN_BLKSZ;
529 blocksize &= ~(ICH_MIN_BLKSZ - 1);
530 ch->blksz = blocksize;
533 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
540 ichchan_trigger(kobj_t obj, void *data, int go)
542 struct sc_chinfo *ch = data;
543 struct sc_info *sc = ch->parent;
546 if (!(sc->flags & ICH_CALIBRATE_DONE))
547 device_printf(sc->dev,
548 "WARNING: %s() called before calibration!\n",
556 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
557 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
563 ich_resetchan(sc, ch->num);
574 ichchan_getptr(kobj_t obj, void *data)
576 struct sc_chinfo *ch = data;
577 struct sc_info *sc = ch->parent;
581 if (!(sc->flags & ICH_CALIBRATE_DONE))
582 device_printf(sc->dev,
583 "WARNING: %s() called before calibration!\n",
588 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
591 pos = ch->civ * ch->blksz;
596 static struct pcmchan_caps *
597 ichchan_getcaps(kobj_t obj, void *data)
599 struct sc_chinfo *ch = data;
602 struct sc_info *sc = ch->parent;
604 if (!(sc->flags & ICH_CALIBRATE_DONE))
605 device_printf(ch->parent->dev,
606 "WARNING: %s() called before calibration!\n",
610 return ((ch->spdreg) ? &ich_vrcaps : &ich_caps);
613 static kobj_method_t ichchan_methods[] = {
614 KOBJMETHOD(channel_init, ichchan_init),
615 KOBJMETHOD(channel_free, ichchan_free),
616 KOBJMETHOD(channel_setformat, ichchan_setformat),
617 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
618 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
619 KOBJMETHOD(channel_trigger, ichchan_trigger),
620 KOBJMETHOD(channel_getptr, ichchan_getptr),
621 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
624 CHANNEL_DECLARE(ichchan);
626 /* -------------------------------------------------------------------- */
627 /* The interrupt handler */
632 struct sc_info *sc = (struct sc_info *)p;
633 struct sc_chinfo *ch;
634 uint32_t cbi, lbi, lvi, st, gs;
640 if (!(sc->flags & ICH_CALIBRATE_DONE))
641 device_printf(sc->dev,
642 "WARNING: %s() called before calibration!\n",
646 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
647 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
648 /* Clear resume interrupt(s) - nothing doing with them */
649 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
651 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
653 for (i = 0; i < 3; i++) {
655 if ((ch->imask & gs) == 0)
658 st = ich_rd(sc, ch->regbase +
659 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
661 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
662 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
663 /* block complete - update buffer */
666 chn_intr(ch->channel);
669 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
670 cbi = ch->civ % ch->blkcnt;
672 cbi = ch->blkcnt - 1;
675 lbi = lvi % ch->blkcnt;
679 lvi += cbi + ch->blkcnt - lbi;
680 lvi %= ICH_DTBL_LENGTH;
681 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
684 /* clear status bit */
685 ich_wr(sc, ch->regbase +
686 ((sc->swap_reg) ? ICH_REG_X_PICB : ICH_REG_X_SR),
691 device_printf(sc->dev,
692 "Unhandled interrupt, gs_intr = %x\n", gs);
696 /* ------------------------------------------------------------------------- */
697 /* Sysctl to control ac97 speed (some boards appear to end up using
698 * XTAL_IN rather than BIT_CLK for link timing).
702 ich_initsys(struct sc_info* sc)
705 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
706 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
707 OID_AUTO, "ac97rate", CTLFLAG_RW,
708 &sc->ac97rate, 48000,
709 "AC97 link rate (default = 48000)");
710 #endif /* SND_DYNSYSCTL */
715 ich_setstatus(struct sc_info *sc)
717 char status[SND_STATUSLEN];
719 ksnprintf(status, SND_STATUSLEN,
720 "at io 0x%lx, 0x%lx irq %ld bufsz %u %s",
721 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar),
722 rman_get_start(sc->irq), sc->bufsz,PCM_KLDSTRING(snd_ich));
724 if (bootverbose && (sc->flags & ICH_DMA_NOCACHE))
725 device_printf(sc->dev,
726 "PCI Master abort workaround enabled\n");
728 pcm_setstatus(sc->dev, status);
731 /* -------------------------------------------------------------------- */
732 /* Calibrate card to determine the clock source. The source maybe a
733 * function of the ac97 codec initialization code (to be investigated).
737 ich_calibrate(void *arg)
740 struct sc_chinfo *ch;
741 struct timeval t1, t2;
743 uint32_t wait_us, actual_48k_rate, oblkcnt;
745 sc = (struct sc_info *)arg;
749 if (sc->intrhook.ich_func != NULL) {
750 config_intrhook_disestablish(&sc->intrhook);
751 sc->intrhook.ich_func = NULL;
755 * Grab audio from input for fixed interval and compare how
756 * much we actually get with what we expect. Interval needs
757 * to be sufficiently short that no interrupts are
761 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
763 oblkcnt = ch->blkcnt;
765 sc->flags |= ICH_CALIBRATE_DONE;
767 ichchan_setblocksize(0, ch, sndbuf_getmaxsize(ch->buffer) >> 1);
769 sc->flags &= ~ICH_CALIBRATE_DONE;
772 * our data format is stereo, 16 bit so each sample is 4 bytes.
773 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
774 * we're going to start recording with interrupts disabled and measure
775 * the time taken for one block to complete. we know the block size,
776 * we know the time in microseconds, we calculate the sample rate:
778 * actual_rate [bps] = bytes / (time [s] * 4)
779 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
780 * actual_rate [Hz] = (bytes * 250000) / time [us]
784 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
786 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (uint32_t)(ch->desc_addr), 4);
790 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
795 if (t2.tv_sec - t1.tv_sec > 1)
797 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
798 } while (nciv == ociv);
801 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
805 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
806 ch->blkcnt = oblkcnt;
808 /* turn time delta into us */
809 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
812 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
813 sc->flags |= ICH_CALIBRATE_DONE;
819 /* Just in case the timecounter screwed. It is possible, really. */
821 actual_48k_rate = ((uint64_t)ch->blksz * 250000) / wait_us;
823 actual_48k_rate = 48000;
825 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
826 sc->ac97rate = actual_48k_rate;
828 sc->ac97rate = 48000;
831 if (bootverbose || sc->ac97rate != 48000) {
832 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
833 if (sc->ac97rate != actual_48k_rate)
834 kprintf(", will use %d Hz", sc->ac97rate);
837 sc->flags |= ICH_CALIBRATE_DONE;
845 /* -------------------------------------------------------------------- */
846 /* Probe and attach the card */
849 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
851 struct sc_info *sc = (struct sc_info *)arg;
852 sc->desc_addr = segs->ds_addr;
857 ich_init(struct sc_info *sc)
861 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
863 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
865 if ((stat & ICH_GLOB_STA_PCR) == 0) {
866 /* ICH4/ICH5 may fail when busmastering is enabled. Continue */
867 if (sc->vendor == INTEL_VENDORID && (
868 sc->devid == INTEL_82801DB || sc->devid == INTEL_82801EB ||
869 sc->devid == INTEL_6300ESB || sc->devid == INTEL_82801FB ||
870 sc->devid == INTEL_82801GB)) {
871 sc->flags |= ICH_IGNORE_PCR;
872 device_printf(sc->dev, "primary codec not ready!\n");
877 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
879 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
882 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
884 if (sc->hasmic && ich_resetchan(sc, 2))
891 ich_pci_probe(device_t dev)
894 uint16_t devid, vendor;
896 vendor = pci_get_vendor(dev);
897 devid = pci_get_device(dev);
898 for (i = 0; i < sizeof(ich_devs)/sizeof(ich_devs[0]); i++) {
899 if (vendor == ich_devs[i].vendor &&
900 devid == ich_devs[i].devid) {
901 device_set_desc(dev, ich_devs[i].name);
902 /* allow a better driver to override us */
903 if ((ich_devs[i].options & PROBE_LOW) != 0)
904 return (BUS_PROBE_LOW_PRIORITY);
905 return (BUS_PROBE_DEFAULT);
912 ich_pci_attach(device_t dev)
916 uint16_t devid, vendor;
920 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
921 sc->ich_lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ich softc");
924 vendor = sc->vendor = pci_get_vendor(dev);
925 devid = sc->devid = pci_get_device(dev);
926 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
928 * The SiS 7012 register set isn't quite like the standard ich.
929 * There really should be a general "quirks" mechanism.
931 if (vendor == SIS_VENDORID && devid == SIS_7012) {
940 * Intel 440MX Errata #36
941 * - AC97 Soft Audio and Soft Modem Master Abort Errata
943 * http://www.intel.com/design/chipsets/specupdt/245051.htm
945 if (vendor == INTEL_VENDORID && devid == INTEL_82440MX)
946 sc->flags |= ICH_DMA_NOCACHE;
949 * Enable bus master. On ich4/5 this may prevent the detection of
950 * the primary codec becoming ready in ich_init().
952 pci_enable_busmaster(dev);
955 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
956 * read-only. Need to enable "legacy support", by poking into
957 * pci config space. The driver should use MMBAR and MBBAR,
958 * but doing so will mess things up here. ich4 has enough new
959 * features it warrants it's own driver.
961 if (vendor == INTEL_VENDORID && (devid == INTEL_82801DB ||
962 devid == INTEL_82801EB || devid == INTEL_6300ESB ||
963 devid == INTEL_82801FB || devid == INTEL_82801GB)) {
964 sc->nambarid = PCIR_MMBAR;
965 sc->nabmbarid = PCIR_MBBAR;
966 sc->regtype = SYS_RES_MEMORY;
967 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
969 sc->nambarid = PCIR_NAMBAR;
970 sc->nabmbarid = PCIR_NABMBAR;
971 sc->regtype = SYS_RES_IOPORT;
974 sc->nambar = bus_alloc_resource_any(dev, sc->regtype,
975 &sc->nambarid, RF_ACTIVE);
976 sc->nabmbar = bus_alloc_resource_any(dev, sc->regtype,
977 &sc->nabmbarid, RF_ACTIVE);
979 if (!sc->nambar || !sc->nabmbar) {
980 device_printf(dev, "unable to map IO port space\n");
984 sc->nambart = rman_get_bustag(sc->nambar);
985 sc->nambarh = rman_get_bushandle(sc->nambar);
986 sc->nabmbart = rman_get_bustag(sc->nabmbar);
987 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
989 sc->bufsz = pcm_getbuffersize(dev,
990 ICH_MIN_BUFSZ, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
992 if (resource_int_value(device_get_name(dev),
993 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
994 sc->blkcnt = sc->bufsz / i;
996 while (sc->blkcnt >> i)
998 sc->blkcnt = 1 << (i - 1);
999 if (sc->blkcnt < ICH_MIN_BLKCNT)
1000 sc->blkcnt = ICH_MIN_BLKCNT;
1001 else if (sc->blkcnt > ICH_MAX_BLKCNT)
1002 sc->blkcnt = ICH_MAX_BLKCNT;
1004 sc->blkcnt = ICH_DEFAULT_BLKCNT;
1006 if (resource_int_value(device_get_name(dev),
1007 device_get_unit(dev), "highlatency", &i) == 0 && i != 0) {
1008 sc->flags |= ICH_HIGH_LATENCY;
1009 sc->blkcnt = ICH_MIN_BLKCNT;
1012 if (resource_int_value(device_get_name(dev),
1013 device_get_unit(dev), "fixedrate", &i) == 0 && i != 0)
1014 sc->flags |= ICH_FIXED_RATE;
1017 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1018 RF_ACTIVE | RF_SHAREABLE);
1019 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr,
1021 device_printf(dev, "unable to map interrupt\n");
1026 device_printf(dev, "unable to initialize the card\n");
1030 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
1031 if (sc->codec == NULL)
1035 * Turn on inverted external amplifier sense flags for few
1039 case 0x202f161f: /* Gateway 7326GZ */
1040 case 0x203a161f: /* Gateway 4028GZ */
1041 case 0x204c161f: /* Kvazar-Micro Senator 3592XT */
1042 case 0x8144104d: /* Sony VAIO PCG-TR* */
1043 case 0x8197104d: /* Sony S1XP */
1044 case 0x81c0104d: /* Sony VAIO type T */
1045 case 0x81c5104d: /* Sony VAIO VGN B1VP/B1XP */
1046 case 0x3089103c: /* Compaq Presario B3800 */
1047 case 0x309a103c: /* HP Compaq nx4300 */
1048 case 0x82131033: /* NEC VersaPro VJ10F/BH */
1049 case 0x82be1033: /* NEC VersaPro VJ12F/CH */
1050 ac97_setflags(sc->codec, ac97_getflags(sc->codec) | AC97_F_EAPD_INV);
1056 mixer_init(dev, ac97_getmixerclass(), sc->codec);
1058 /* check and set VRA function */
1059 extcaps = ac97_getextcaps(sc->codec);
1060 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
1061 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
1062 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
1063 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1065 sc->dtbl_size = sizeof(struct ich_desc) * ICH_DTBL_LENGTH *
1066 ((sc->hasmic) ? 3 : 2);
1069 if (bus_dma_tag_create(NULL, 8, 0,
1070 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1071 sc->dtbl_size, 1, 0x3ffff, 0, &sc->dmat) != 0) {
1072 device_printf(dev, "unable to create dma tag\n");
1076 /* PCM channel tag */
1077 if (bus_dma_tag_create(NULL, ICH_MIN_BLKSZ, 0,
1078 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1079 sc->bufsz, 1, 0x3ffff, 0, &sc->chan_dmat) != 0) {
1080 device_printf(dev, "unable to create dma tag\n");
1083 #if 0 /* TODO: No uncacheable DMA support in DragonFly. */
1084 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT |
1085 ((sc->flags & ICH_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1088 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT,
1093 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sc->dtbl_size,
1097 if (pcm_register(dev, sc, 1, (sc->hasmic) ? 2 : 1))
1100 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
1101 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
1103 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
1105 if (sc->flags & ICH_FIXED_RATE) {
1106 sc->flags |= ICH_CALIBRATE_DONE;
1111 sc->intrhook.ich_func = ich_calibrate;
1112 sc->intrhook.ich_arg = sc;
1114 config_intrhook_establish(&sc->intrhook) != 0) {
1115 sc->intrhook.ich_func = NULL;
1124 ac97_destroy(sc->codec);
1126 bus_teardown_intr(dev, sc->irq, sc->ih);
1128 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1130 bus_release_resource(dev, sc->regtype,
1131 sc->nambarid, sc->nambar);
1133 bus_release_resource(dev, sc->regtype,
1134 sc->nabmbarid, sc->nabmbar);
1136 bus_dmamap_unload(sc->dmat, sc->dtmap);
1138 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1140 bus_dma_tag_destroy(sc->chan_dmat);
1142 bus_dma_tag_destroy(sc->dmat);
1144 snd_mtxfree(sc->ich_lock);
1145 kfree(sc, M_DEVBUF);
1150 ich_pci_detach(device_t dev)
1155 r = pcm_unregister(dev);
1158 sc = pcm_getdevinfo(dev);
1160 bus_teardown_intr(dev, sc->irq, sc->ih);
1161 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1162 bus_release_resource(dev, sc->regtype, sc->nambarid, sc->nambar);
1163 bus_release_resource(dev, sc->regtype, sc->nabmbarid, sc->nabmbar);
1164 bus_dmamap_unload(sc->dmat, sc->dtmap);
1165 bus_dmamem_free(sc->dmat, sc->dtbl, sc->dtmap);
1166 bus_dma_tag_destroy(sc->chan_dmat);
1167 bus_dma_tag_destroy(sc->dmat);
1168 snd_mtxfree(sc->ich_lock);
1169 kfree(sc, M_DEVBUF);
1174 ich_pci_codec_reset(struct sc_info *sc)
1179 control = ich_rd(sc, ICH_REG_GLOB_CNT, 4);
1180 control &= ~(ICH_GLOB_CTL_SHUT);
1181 control |= (control & ICH_GLOB_CTL_COLD) ?
1182 ICH_GLOB_CTL_WARM : ICH_GLOB_CTL_COLD;
1183 ich_wr(sc, ICH_REG_GLOB_CNT, control, 4);
1185 for (i = 500000; i; i--) {
1186 if (ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_PCR)
1187 break; /* or ICH_SCR? */
1192 kprintf("%s: time out\n", __func__);
1196 ich_pci_suspend(device_t dev)
1201 sc = pcm_getdevinfo(dev);
1203 for (i = 0 ; i < 3; i++) {
1204 sc->ch[i].run_save = sc->ch[i].run;
1205 if (sc->ch[i].run) {
1207 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
1216 ich_pci_resume(device_t dev)
1221 sc = pcm_getdevinfo(dev);
1223 if (sc->regtype == SYS_RES_IOPORT)
1224 pci_enable_io(dev, SYS_RES_IOPORT);
1226 pci_enable_io(dev, SYS_RES_MEMORY);
1227 pci_enable_busmaster(dev);
1230 /* Reinit audio device */
1231 if (ich_init(sc) == -1) {
1232 device_printf(dev, "unable to reinitialize the card\n");
1237 ich_pci_codec_reset(sc);
1239 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
1240 if (mixer_reinit(dev) == -1) {
1241 device_printf(dev, "unable to reinitialize the mixer\n");
1244 /* Re-start DMA engines */
1245 for (i = 0 ; i < 3; i++) {
1246 struct sc_chinfo *ch = &sc->ch[i];
1247 if (sc->ch[i].run_save) {
1248 ichchan_setblocksize(0, ch, ch->blksz);
1249 ichchan_setspeed(0, ch, ch->spd);
1250 ichchan_trigger(0, ch, PCMTRIG_START);
1256 static device_method_t ich_methods[] = {
1257 /* Device interface */
1258 DEVMETHOD(device_probe, ich_pci_probe),
1259 DEVMETHOD(device_attach, ich_pci_attach),
1260 DEVMETHOD(device_detach, ich_pci_detach),
1261 DEVMETHOD(device_suspend, ich_pci_suspend),
1262 DEVMETHOD(device_resume, ich_pci_resume),
1266 static driver_t ich_driver = {
1272 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
1273 MODULE_DEPEND(snd_ich, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1274 MODULE_VERSION(snd_ich, 1);