2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $
33 #include "opt_compat_oldpci.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
39 #include <sys/linker.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/sysctl.h>
45 #include <sys/endian.h>
46 #include <sys/machintr.h>
48 #include <machine/msi_machdep.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 extern struct dev_ops pcic_ops; /* XXX */
75 typedef void (*pci_read_cap_t)(device_t, int, int, pcicfgregs *);
77 static uint32_t pci_mapbase(unsigned mapreg);
78 static const char *pci_maptype(unsigned mapreg);
79 static int pci_mapsize(unsigned testval);
80 static int pci_maprange(unsigned mapreg);
81 static void pci_fixancient(pcicfgregs *cfg);
83 static int pci_porten(device_t pcib, int b, int s, int f);
84 static int pci_memen(device_t pcib, int b, int s, int f);
85 static void pci_assign_interrupt(device_t bus, device_t dev,
87 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
88 int b, int s, int f, int reg,
89 struct resource_list *rl, int force, int prefetch);
90 static int pci_probe(device_t dev);
91 static int pci_attach(device_t dev);
92 static void pci_child_detached(device_t, device_t);
93 static void pci_load_vendor_data(void);
94 static int pci_describe_parse_line(char **ptr, int *vendor,
95 int *device, char **desc);
96 static char *pci_describe_device(device_t dev);
97 static int pci_modevent(module_t mod, int what, void *arg);
98 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
100 static void pci_read_capabilities(device_t pcib, pcicfgregs *cfg);
101 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
102 int reg, uint32_t *data);
104 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
105 int reg, uint32_t data);
107 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
108 static void pci_disable_msi(device_t dev);
109 static void pci_enable_msi(device_t dev, uint64_t address,
111 static void pci_enable_msix(device_t dev, u_int index,
112 uint64_t address, uint32_t data);
113 static void pci_mask_msix(device_t dev, u_int index);
114 static void pci_unmask_msix(device_t dev, u_int index);
115 static int pci_msi_blacklisted(void);
116 static void pci_resume_msi(device_t dev);
117 static void pci_resume_msix(device_t dev);
118 static int pcie_slotimpl(const pcicfgregs *);
119 static void pci_print_verbose_expr(const pcicfgregs *);
121 static void pci_read_cap_pmgt(device_t, int, int, pcicfgregs *);
122 static void pci_read_cap_ht(device_t, int, int, pcicfgregs *);
123 static void pci_read_cap_msi(device_t, int, int, pcicfgregs *);
124 static void pci_read_cap_msix(device_t, int, int, pcicfgregs *);
125 static void pci_read_cap_vpd(device_t, int, int, pcicfgregs *);
126 static void pci_read_cap_subvendor(device_t, int, int,
128 static void pci_read_cap_pcix(device_t, int, int, pcicfgregs *);
129 static void pci_read_cap_express(device_t, int, int, pcicfgregs *);
131 static device_method_t pci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, pci_probe),
134 DEVMETHOD(device_attach, pci_attach),
135 DEVMETHOD(device_detach, bus_generic_detach),
136 DEVMETHOD(device_shutdown, bus_generic_shutdown),
137 DEVMETHOD(device_suspend, pci_suspend),
138 DEVMETHOD(device_resume, pci_resume),
141 DEVMETHOD(bus_print_child, pci_print_child),
142 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
143 DEVMETHOD(bus_read_ivar, pci_read_ivar),
144 DEVMETHOD(bus_write_ivar, pci_write_ivar),
145 DEVMETHOD(bus_driver_added, pci_driver_added),
146 DEVMETHOD(bus_child_detached, pci_child_detached),
147 DEVMETHOD(bus_setup_intr, pci_setup_intr),
148 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
150 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
151 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
152 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
153 DEVMETHOD(bus_delete_resource, pci_delete_resource),
154 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
155 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
156 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
157 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
158 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
159 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
162 DEVMETHOD(pci_read_config, pci_read_config_method),
163 DEVMETHOD(pci_write_config, pci_write_config_method),
164 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
165 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
166 DEVMETHOD(pci_enable_io, pci_enable_io_method),
167 DEVMETHOD(pci_disable_io, pci_disable_io_method),
168 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
169 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
170 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
171 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
172 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
173 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
174 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
175 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
176 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
177 DEVMETHOD(pci_release_msi, pci_release_msi_method),
178 DEVMETHOD(pci_msi_count, pci_msi_count_method),
179 DEVMETHOD(pci_msix_count, pci_msix_count_method),
184 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
186 static devclass_t pci_devclass;
187 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, NULL);
188 MODULE_VERSION(pci, 1);
190 static char *pci_vendordata;
191 static size_t pci_vendordata_size;
194 static const struct pci_read_cap {
196 pci_read_cap_t read_cap;
197 } pci_read_caps[] = {
198 { PCIY_PMG, pci_read_cap_pmgt },
199 { PCIY_HT, pci_read_cap_ht },
200 { PCIY_MSI, pci_read_cap_msi },
201 { PCIY_MSIX, pci_read_cap_msix },
202 { PCIY_VPD, pci_read_cap_vpd },
203 { PCIY_SUBVENDOR, pci_read_cap_subvendor },
204 { PCIY_PCIX, pci_read_cap_pcix },
205 { PCIY_EXPRESS, pci_read_cap_express },
206 { 0, NULL } /* required last entry */
210 uint32_t devid; /* Vendor/device of the card */
212 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
213 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
218 struct pci_quirk pci_quirks[] = {
219 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
220 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
221 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
222 /* As does the Serverworks OSB4 (the SMBus mapping register) */
223 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
226 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
227 * or the CMIC-SL (AKA ServerWorks GC_LE).
229 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
230 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
233 * MSI doesn't work on earlier Intel chipsets including
234 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
236 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
237 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
238 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
239 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
240 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
241 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
242 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
245 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
248 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
253 /* map register information */
254 #define PCI_MAPMEM 0x01 /* memory map */
255 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
256 #define PCI_MAPPORT 0x04 /* port map */
258 struct devlist pci_devq;
259 uint32_t pci_generation;
260 uint32_t pci_numdevs = 0;
261 static int pcie_chipset, pcix_chipset;
264 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
266 static int pci_enable_io_modes = 1;
267 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
268 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
269 &pci_enable_io_modes, 1,
270 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
271 enable these bits correctly. We'd like to do this all the time, but there\n\
272 are some peripherals that this causes problems with.");
274 static int pci_do_power_nodriver = 0;
275 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
276 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
277 &pci_do_power_nodriver, 0,
278 "Place a function into D3 state when no driver attaches to it. 0 means\n\
279 disable. 1 means conservatively place devices into D3 state. 2 means\n\
280 aggressively place devices into D3 state. 3 means put absolutely everything\n\
283 static int pci_do_power_resume = 1;
284 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
285 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
286 &pci_do_power_resume, 1,
287 "Transition from D3 -> D0 on resume.");
289 static int pci_do_msi = 1;
290 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
291 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
292 "Enable support for MSI interrupts");
294 static int pci_do_msix = 1;
295 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
296 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
297 "Enable support for MSI-X interrupts");
299 static int pci_honor_msi_blacklist = 1;
300 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
301 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
302 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
304 /* Find a device_t by bus/slot/function in domain 0 */
307 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
310 return (pci_find_dbsf(0, bus, slot, func));
313 /* Find a device_t by domain/bus/slot/function */
316 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
318 struct pci_devinfo *dinfo;
320 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
321 if ((dinfo->cfg.domain == domain) &&
322 (dinfo->cfg.bus == bus) &&
323 (dinfo->cfg.slot == slot) &&
324 (dinfo->cfg.func == func)) {
325 return (dinfo->cfg.dev);
332 /* Find a device_t by vendor/device ID */
335 pci_find_device(uint16_t vendor, uint16_t device)
337 struct pci_devinfo *dinfo;
339 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
340 if ((dinfo->cfg.vendor == vendor) &&
341 (dinfo->cfg.device == device)) {
342 return (dinfo->cfg.dev);
349 /* return base address of memory or port map */
352 pci_mapbase(uint32_t mapreg)
355 if (PCI_BAR_MEM(mapreg))
356 return (mapreg & PCIM_BAR_MEM_BASE);
358 return (mapreg & PCIM_BAR_IO_BASE);
361 /* return map type of memory or port map */
364 pci_maptype(unsigned mapreg)
367 if (PCI_BAR_IO(mapreg))
369 if (mapreg & PCIM_BAR_MEM_PREFETCH)
370 return ("Prefetchable Memory");
374 /* return log2 of map size decoded for memory or port map */
377 pci_mapsize(uint32_t testval)
381 testval = pci_mapbase(testval);
384 while ((testval & 1) == 0)
393 /* return log2 of address range supported by map register */
396 pci_maprange(unsigned mapreg)
400 if (PCI_BAR_IO(mapreg))
403 switch (mapreg & PCIM_BAR_MEM_TYPE) {
404 case PCIM_BAR_MEM_32:
407 case PCIM_BAR_MEM_1MB:
410 case PCIM_BAR_MEM_64:
417 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
420 pci_fixancient(pcicfgregs *cfg)
422 if (cfg->hdrtype != 0)
425 /* PCI to PCI bridges use header type 1 */
426 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
430 /* extract header type specific config data */
433 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
435 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
436 switch (cfg->hdrtype) {
438 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
439 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
440 cfg->nummaps = PCI_MAXMAPS_0;
443 cfg->nummaps = PCI_MAXMAPS_1;
445 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
449 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
450 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
451 cfg->nummaps = PCI_MAXMAPS_2;
453 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
460 /* read configuration header into pcicfgregs structure */
462 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
464 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
465 pcicfgregs *cfg = NULL;
466 struct pci_devinfo *devlist_entry;
467 struct devlist *devlist_head;
469 devlist_head = &pci_devq;
471 devlist_entry = NULL;
473 if (REG(PCIR_DEVVENDOR, 4) != -1) {
474 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
476 cfg = &devlist_entry->cfg;
482 cfg->vendor = REG(PCIR_VENDOR, 2);
483 cfg->device = REG(PCIR_DEVICE, 2);
484 cfg->cmdreg = REG(PCIR_COMMAND, 2);
485 cfg->statreg = REG(PCIR_STATUS, 2);
486 cfg->baseclass = REG(PCIR_CLASS, 1);
487 cfg->subclass = REG(PCIR_SUBCLASS, 1);
488 cfg->progif = REG(PCIR_PROGIF, 1);
489 cfg->revid = REG(PCIR_REVID, 1);
490 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
491 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
492 cfg->lattimer = REG(PCIR_LATTIMER, 1);
493 cfg->intpin = REG(PCIR_INTPIN, 1);
494 cfg->intline = REG(PCIR_INTLINE, 1);
496 cfg->mingnt = REG(PCIR_MINGNT, 1);
497 cfg->maxlat = REG(PCIR_MAXLAT, 1);
499 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
500 cfg->hdrtype &= ~PCIM_MFDEV;
503 pci_hdrtypedata(pcib, b, s, f, cfg);
505 pci_read_capabilities(pcib, cfg);
507 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
509 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
510 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
511 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
512 devlist_entry->conf.pc_sel.pc_func = cfg->func;
513 devlist_entry->conf.pc_hdr = cfg->hdrtype;
515 devlist_entry->conf.pc_subvendor = cfg->subvendor;
516 devlist_entry->conf.pc_subdevice = cfg->subdevice;
517 devlist_entry->conf.pc_vendor = cfg->vendor;
518 devlist_entry->conf.pc_device = cfg->device;
520 devlist_entry->conf.pc_class = cfg->baseclass;
521 devlist_entry->conf.pc_subclass = cfg->subclass;
522 devlist_entry->conf.pc_progif = cfg->progif;
523 devlist_entry->conf.pc_revid = cfg->revid;
528 return (devlist_entry);
533 pci_fixup_nextptr(int *nextptr0)
535 int nextptr = *nextptr0;
537 /* "Next pointer" is only one byte */
538 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
542 * PCI local bus spec 3.0:
544 * "... The bottom two bits of all pointers are reserved
545 * and must be implemented as 00b although software must
546 * mask them to allow for future uses of these bits ..."
549 kprintf("Illegal PCI extended capability "
550 "offset, fixup 0x%02x -> 0x%02x\n",
551 nextptr, nextptr & ~0x3);
557 if (nextptr < 0x40) {
559 kprintf("Illegal PCI extended capability "
560 "offset 0x%02x", nextptr);
568 pci_read_cap_pmgt(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
571 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
573 struct pcicfg_pp *pp = &cfg->pp;
578 pp->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
579 pp->pp_status = ptr + PCIR_POWER_STATUS;
580 pp->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
582 if ((nextptr - ptr) > PCIR_POWER_DATA) {
585 * We should write to data_select and read back from
586 * data_scale to determine whether data register is
590 pp->pp_data = ptr + PCIR_POWER_DATA;
600 pci_read_cap_ht(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
602 #if defined(__i386__) || defined(__x86_64__)
605 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
607 struct pcicfg_ht *ht = &cfg->ht;
611 /* Determine HT-specific capability type. */
612 val = REG(ptr + PCIR_HT_COMMAND, 2);
614 if ((val & 0xe000) == PCIM_HTCAP_SLAVE)
615 cfg->ht.ht_slave = ptr;
617 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_MSI_MAPPING)
620 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
621 /* Sanity check the mapping window. */
622 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI, 4);
624 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO, 4);
625 if (addr != MSI_X86_ADDR_BASE) {
626 device_printf(pcib, "HT Bridge at pci%d:%d:%d:%d "
627 "has non-default MSI window 0x%llx\n",
628 cfg->domain, cfg->bus, cfg->slot, cfg->func,
632 addr = MSI_X86_ADDR_BASE;
636 ht->ht_msictrl = val;
637 ht->ht_msiaddr = addr;
641 #endif /* __i386__ || __x86_64__ */
645 pci_read_cap_msi(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
648 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
650 struct pcicfg_msi *msi = &cfg->msi;
652 msi->msi_location = ptr;
653 msi->msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
654 msi->msi_msgnum = 1 << ((msi->msi_ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
660 pci_read_cap_msix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
663 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
665 struct pcicfg_msix *msix = &cfg->msix;
668 msix->msix_location = ptr;
669 msix->msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
670 msix->msix_msgnum = (msix->msix_ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
672 val = REG(ptr + PCIR_MSIX_TABLE, 4);
673 msix->msix_table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
674 msix->msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
676 val = REG(ptr + PCIR_MSIX_PBA, 4);
677 msix->msix_pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
678 msix->msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
684 pci_read_cap_vpd(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
686 cfg->vpd.vpd_reg = ptr;
690 pci_read_cap_subvendor(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
693 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
695 /* Should always be true. */
696 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
699 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
700 cfg->subvendor = val & 0xffff;
701 cfg->subdevice = val >> 16;
708 pci_read_cap_pcix(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
711 * Assume we have a PCI-X chipset if we have
712 * at least one PCI-PCI bridge with a PCI-X
713 * capability. Note that some systems with
714 * PCI-express or HT chipsets might match on
715 * this check as well.
717 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
720 cfg->pcix.pcix_ptr = ptr;
724 pcie_slotimpl(const pcicfgregs *cfg)
726 const struct pcicfg_expr *expr = &cfg->expr;
730 * Only version 1 can be parsed currently
732 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
736 * - Slot implemented bit is meaningful iff current port is
737 * root port or down stream port.
738 * - Testing for root port or down stream port is meanningful
739 * iff PCI configure has type 1 header.
742 if (cfg->hdrtype != 1)
745 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
746 if (port_type != PCIE_ROOT_PORT && port_type != PCIE_DOWN_STREAM_PORT)
749 if (!(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
756 pci_read_cap_express(device_t pcib, int ptr, int nextptr, pcicfgregs *cfg)
759 PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
761 struct pcicfg_expr *expr = &cfg->expr;
764 * Assume we have a PCI-express chipset if we have
765 * at least one PCI-express device.
769 expr->expr_ptr = ptr;
770 expr->expr_cap = REG(ptr + PCIER_CAPABILITY, 2);
773 * Only version 1 can be parsed currently
775 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
779 * Read slot capabilities. Slot capabilities exists iff
780 * current port's slot is implemented
782 if (pcie_slotimpl(cfg))
783 expr->expr_slotcap = REG(ptr + PCIER_SLOTCAP, 4);
789 pci_read_capabilities(device_t pcib, pcicfgregs *cfg)
791 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
792 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
797 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
798 /* No capabilities */
802 switch (cfg->hdrtype & PCIM_HDRTYPE) {
805 ptrptr = PCIR_CAP_PTR;
808 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
811 return; /* no capabilities support */
813 nextptr = REG(ptrptr, 1); /* sanity check? */
816 * Read capability entries.
818 while (pci_fixup_nextptr(&nextptr)) {
819 const struct pci_read_cap *rc;
822 /* Find the next entry */
823 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
825 /* Process this entry */
826 val = REG(ptr + PCICAP_ID, 1);
827 for (rc = pci_read_caps; rc->read_cap != NULL; ++rc) {
828 if (rc->cap == val) {
829 rc->read_cap(pcib, ptr, nextptr, cfg);
835 #if defined(__i386__) || defined(__x86_64__)
837 * Enable the MSI mapping window for all HyperTransport
838 * slaves. PCI-PCI bridges have their windows enabled via
841 if (cfg->ht.ht_slave != 0 && cfg->ht.ht_msimap != 0 &&
842 !(cfg->ht.ht_msictrl & PCIM_HTCMD_MSI_ENABLE)) {
844 "Enabling MSI window for HyperTransport slave at pci%d:%d:%d:%d\n",
845 cfg->domain, cfg->bus, cfg->slot, cfg->func);
846 cfg->ht.ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
847 WREG(cfg->ht.ht_msimap + PCIR_HT_COMMAND, cfg->ht.ht_msictrl,
852 /* REG and WREG use carry through to next functions */
856 * PCI Vital Product Data
859 #define PCI_VPD_TIMEOUT 1000000
862 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
864 int count = PCI_VPD_TIMEOUT;
866 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
868 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
870 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
873 DELAY(1); /* limit looping */
875 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
882 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
884 int count = PCI_VPD_TIMEOUT;
886 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
888 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
889 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
890 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
893 DELAY(1); /* limit looping */
900 #undef PCI_VPD_TIMEOUT
902 struct vpd_readstate {
912 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
917 if (vrs->bytesinval == 0) {
918 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
920 vrs->val = le32toh(reg);
922 byte = vrs->val & 0xff;
925 vrs->val = vrs->val >> 8;
926 byte = vrs->val & 0xff;
936 pcie_slot_implemented(device_t dev)
938 struct pci_devinfo *dinfo = device_get_ivars(dev);
940 return pcie_slotimpl(&dinfo->cfg);
944 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
949 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
950 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
951 panic("%s: invalid max read request size 0x%02x\n",
952 device_get_nameunit(dev), rqsize);
955 expr_ptr = pci_get_pciecap_ptr(dev);
957 panic("%s: not PCIe device\n", device_get_nameunit(dev));
959 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
960 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
962 device_printf(dev, "adjust device control 0x%04x", val);
964 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
966 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
969 kprintf(" -> 0x%04x\n", val);
974 pcie_get_max_readrq(device_t dev)
979 expr_ptr = pci_get_pciecap_ptr(dev);
981 panic("%s: not PCIe device\n", device_get_nameunit(dev));
983 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
984 return (val & PCIEM_DEVCTL_MAX_READRQ_MASK);
988 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
990 struct vpd_readstate vrs;
995 int alloc, off; /* alloc/off for RO/W arrays */
1001 /* init vpd reader */
1009 name = remain = i = 0; /* shut up stupid gcc */
1010 alloc = off = 0; /* shut up stupid gcc */
1011 dflen = 0; /* shut up stupid gcc */
1013 while (state >= 0) {
1014 if (vpd_nextbyte(&vrs, &byte)) {
1019 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
1020 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
1021 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
1024 case 0: /* item name */
1026 if (vpd_nextbyte(&vrs, &byte2)) {
1031 if (vpd_nextbyte(&vrs, &byte2)) {
1035 remain |= byte2 << 8;
1036 if (remain > (0x7f*4 - vrs.off)) {
1039 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
1040 cfg->domain, cfg->bus, cfg->slot,
1045 remain = byte & 0x7;
1046 name = (byte >> 3) & 0xf;
1049 case 0x2: /* String */
1050 cfg->vpd.vpd_ident = kmalloc(remain + 1,
1051 M_DEVBUF, M_WAITOK);
1058 case 0x10: /* VPD-R */
1061 cfg->vpd.vpd_ros = kmalloc(alloc *
1062 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
1066 case 0x11: /* VPD-W */
1069 cfg->vpd.vpd_w = kmalloc(alloc *
1070 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
1074 default: /* Invalid data, abort */
1080 case 1: /* Identifier String */
1081 cfg->vpd.vpd_ident[i++] = byte;
1084 cfg->vpd.vpd_ident[i] = '\0';
1089 case 2: /* VPD-R Keyword Header */
1091 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1092 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
1093 M_DEVBUF, M_WAITOK | M_ZERO);
1095 cfg->vpd.vpd_ros[off].keyword[0] = byte;
1096 if (vpd_nextbyte(&vrs, &byte2)) {
1100 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
1101 if (vpd_nextbyte(&vrs, &byte2)) {
1107 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
1110 * if this happens, we can't trust the rest
1114 "pci%d:%d:%d:%d: bad keyword length: %d\n",
1115 cfg->domain, cfg->bus, cfg->slot,
1120 } else if (dflen == 0) {
1121 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
1122 sizeof(*cfg->vpd.vpd_ros[off].value),
1123 M_DEVBUF, M_WAITOK);
1124 cfg->vpd.vpd_ros[off].value[0] = '\x00';
1126 cfg->vpd.vpd_ros[off].value = kmalloc(
1128 sizeof(*cfg->vpd.vpd_ros[off].value),
1129 M_DEVBUF, M_WAITOK);
1132 /* keep in sync w/ state 3's transistions */
1133 if (dflen == 0 && remain == 0)
1135 else if (dflen == 0)
1141 case 3: /* VPD-R Keyword Value */
1142 cfg->vpd.vpd_ros[off].value[i++] = byte;
1143 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
1144 "RV", 2) == 0 && cksumvalid == -1) {
1150 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
1151 cfg->domain, cfg->bus,
1152 cfg->slot, cfg->func,
1161 /* keep in sync w/ state 2's transistions */
1163 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
1164 if (dflen == 0 && remain == 0) {
1165 cfg->vpd.vpd_rocnt = off;
1166 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
1167 off * sizeof(*cfg->vpd.vpd_ros),
1168 M_DEVBUF, M_WAITOK | M_ZERO);
1170 } else if (dflen == 0)
1180 case 5: /* VPD-W Keyword Header */
1182 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1183 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
1184 M_DEVBUF, M_WAITOK | M_ZERO);
1186 cfg->vpd.vpd_w[off].keyword[0] = byte;
1187 if (vpd_nextbyte(&vrs, &byte2)) {
1191 cfg->vpd.vpd_w[off].keyword[1] = byte2;
1192 if (vpd_nextbyte(&vrs, &byte2)) {
1196 cfg->vpd.vpd_w[off].len = dflen = byte2;
1197 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
1198 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
1199 sizeof(*cfg->vpd.vpd_w[off].value),
1200 M_DEVBUF, M_WAITOK);
1203 /* keep in sync w/ state 6's transistions */
1204 if (dflen == 0 && remain == 0)
1206 else if (dflen == 0)
1212 case 6: /* VPD-W Keyword Value */
1213 cfg->vpd.vpd_w[off].value[i++] = byte;
1216 /* keep in sync w/ state 5's transistions */
1218 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1219 if (dflen == 0 && remain == 0) {
1220 cfg->vpd.vpd_wcnt = off;
1221 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1222 off * sizeof(*cfg->vpd.vpd_w),
1223 M_DEVBUF, M_WAITOK | M_ZERO);
1225 } else if (dflen == 0)
1230 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1231 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1238 if (cksumvalid == 0 || state < -1) {
1239 /* read-only data bad, clean up */
1240 if (cfg->vpd.vpd_ros != NULL) {
1241 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1242 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1243 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1244 cfg->vpd.vpd_ros = NULL;
1248 /* I/O error, clean up */
1249 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1250 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1251 if (cfg->vpd.vpd_ident != NULL) {
1252 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1253 cfg->vpd.vpd_ident = NULL;
1255 if (cfg->vpd.vpd_w != NULL) {
1256 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1257 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1258 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1259 cfg->vpd.vpd_w = NULL;
1262 cfg->vpd.vpd_cached = 1;
1268 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1270 struct pci_devinfo *dinfo = device_get_ivars(child);
1271 pcicfgregs *cfg = &dinfo->cfg;
1273 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1274 pci_read_vpd(device_get_parent(dev), cfg);
1276 *identptr = cfg->vpd.vpd_ident;
1278 if (*identptr == NULL)
1285 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1288 struct pci_devinfo *dinfo = device_get_ivars(child);
1289 pcicfgregs *cfg = &dinfo->cfg;
1292 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1293 pci_read_vpd(device_get_parent(dev), cfg);
1295 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1296 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1297 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1298 *vptr = cfg->vpd.vpd_ros[i].value;
1301 if (i != cfg->vpd.vpd_rocnt)
1309 * Return the offset in configuration space of the requested extended
1310 * capability entry or 0 if the specified capability was not found.
1313 pci_find_extcap_method(device_t dev, device_t child, int capability,
1316 struct pci_devinfo *dinfo = device_get_ivars(child);
1317 pcicfgregs *cfg = &dinfo->cfg;
1322 * Check the CAP_LIST bit of the PCI status register first.
1324 status = pci_read_config(child, PCIR_STATUS, 2);
1325 if (!(status & PCIM_STATUS_CAPPRESENT))
1329 * Determine the start pointer of the capabilities list.
1331 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1337 ptr = PCIR_CAP_PTR_2;
1341 return (ENXIO); /* no extended capabilities support */
1343 ptr = pci_read_config(child, ptr, 1);
1346 * Traverse the capabilities list.
1349 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1354 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1361 * Support for MSI-X message interrupts.
1364 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1366 struct pci_devinfo *dinfo = device_get_ivars(dev);
1367 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1370 KASSERT(msix->msix_table_len > index, ("bogus index"));
1371 offset = msix->msix_table_offset + index * 16;
1372 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1373 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1374 bus_write_4(msix->msix_table_res, offset + 8, data);
1376 /* Enable MSI -> HT mapping. */
1377 pci_ht_map_msi(dev, address);
1381 pci_mask_msix(device_t dev, u_int index)
1383 struct pci_devinfo *dinfo = device_get_ivars(dev);
1384 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1385 uint32_t offset, val;
1387 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1388 offset = msix->msix_table_offset + index * 16 + 12;
1389 val = bus_read_4(msix->msix_table_res, offset);
1390 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1391 val |= PCIM_MSIX_VCTRL_MASK;
1392 bus_write_4(msix->msix_table_res, offset, val);
1397 pci_unmask_msix(device_t dev, u_int index)
1399 struct pci_devinfo *dinfo = device_get_ivars(dev);
1400 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1401 uint32_t offset, val;
1403 KASSERT(msix->msix_table_len > index, ("bogus index"));
1404 offset = msix->msix_table_offset + index * 16 + 12;
1405 val = bus_read_4(msix->msix_table_res, offset);
1406 if (val & PCIM_MSIX_VCTRL_MASK) {
1407 val &= ~PCIM_MSIX_VCTRL_MASK;
1408 bus_write_4(msix->msix_table_res, offset, val);
1413 pci_pending_msix(device_t dev, u_int index)
1415 struct pci_devinfo *dinfo = device_get_ivars(dev);
1416 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1417 uint32_t offset, bit;
1419 KASSERT(msix->msix_table_len > index, ("bogus index"));
1420 offset = msix->msix_pba_offset + (index / 32) * 4;
1421 bit = 1 << index % 32;
1422 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1426 * Restore MSI-X registers and table during resume. If MSI-X is
1427 * enabled then walk the virtual table to restore the actual MSI-X
1431 pci_resume_msix(device_t dev)
1433 struct pci_devinfo *dinfo = device_get_ivars(dev);
1434 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1435 struct msix_table_entry *mte;
1436 struct msix_vector *mv;
1439 if (msix->msix_alloc > 0) {
1440 /* First, mask all vectors. */
1441 for (i = 0; i < msix->msix_msgnum; i++)
1442 pci_mask_msix(dev, i);
1444 /* Second, program any messages with at least one handler. */
1445 for (i = 0; i < msix->msix_table_len; i++) {
1446 mte = &msix->msix_table[i];
1447 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1449 mv = &msix->msix_vectors[mte->mte_vector - 1];
1450 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1451 pci_unmask_msix(dev, i);
1454 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1455 msix->msix_ctrl, 2);
1459 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1460 * returned in *count. After this function returns, each message will be
1461 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1464 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1466 struct pci_devinfo *dinfo = device_get_ivars(child);
1467 pcicfgregs *cfg = &dinfo->cfg;
1468 struct resource_list_entry *rle;
1469 int actual, error, i, irq, max;
1471 /* Don't let count == 0 get us into trouble. */
1475 /* If rid 0 is allocated, then fail. */
1476 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1477 if (rle != NULL && rle->res != NULL)
1480 /* Already have allocated messages? */
1481 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1484 /* If MSI is blacklisted for this system, fail. */
1485 if (pci_msi_blacklisted())
1488 /* MSI-X capability present? */
1489 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1492 /* Make sure the appropriate BARs are mapped. */
1493 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1494 cfg->msix.msix_table_bar);
1495 if (rle == NULL || rle->res == NULL ||
1496 !(rman_get_flags(rle->res) & RF_ACTIVE))
1498 cfg->msix.msix_table_res = rle->res;
1499 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1500 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1501 cfg->msix.msix_pba_bar);
1502 if (rle == NULL || rle->res == NULL ||
1503 !(rman_get_flags(rle->res) & RF_ACTIVE))
1506 cfg->msix.msix_pba_res = rle->res;
1509 device_printf(child,
1510 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1511 *count, cfg->msix.msix_msgnum);
1512 max = min(*count, cfg->msix.msix_msgnum);
1513 for (i = 0; i < max; i++) {
1514 /* Allocate a message. */
1515 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1518 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1525 device_printf(child,
1526 "could not allocate any MSI-X vectors\n");
1532 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1534 device_printf(child, "using IRQ %lu for MSI-X\n",
1540 * Be fancy and try to print contiguous runs of
1541 * IRQ values as ranges. 'irq' is the previous IRQ.
1542 * 'run' is true if we are in a range.
1544 device_printf(child, "using IRQs %lu", rle->start);
1547 for (i = 1; i < actual; i++) {
1548 rle = resource_list_find(&dinfo->resources,
1549 SYS_RES_IRQ, i + 1);
1551 /* Still in a run? */
1552 if (rle->start == irq + 1) {
1558 /* Finish previous range. */
1560 kprintf("-%d", irq);
1564 /* Start new range. */
1565 kprintf(",%lu", rle->start);
1569 /* Unfinished range? */
1571 kprintf("-%d", irq);
1572 kprintf(" for MSI-X\n");
1576 /* Mask all vectors. */
1577 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1578 pci_mask_msix(child, i);
1580 /* Allocate and initialize vector data and virtual table. */
1581 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1582 M_DEVBUF, M_WAITOK | M_ZERO);
1583 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1584 M_DEVBUF, M_WAITOK | M_ZERO);
1585 for (i = 0; i < actual; i++) {
1586 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1587 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1588 cfg->msix.msix_table[i].mte_vector = i + 1;
1591 /* Update control register to enable MSI-X. */
1592 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1593 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1594 cfg->msix.msix_ctrl, 2);
1596 /* Update counts of alloc'd messages. */
1597 cfg->msix.msix_alloc = actual;
1598 cfg->msix.msix_table_len = actual;
1604 * By default, pci_alloc_msix() will assign the allocated IRQ
1605 * resources consecutively to the first N messages in the MSI-X table.
1606 * However, device drivers may want to use different layouts if they
1607 * either receive fewer messages than they asked for, or they wish to
1608 * populate the MSI-X table sparsely. This method allows the driver
1609 * to specify what layout it wants. It must be called after a
1610 * successful pci_alloc_msix() but before any of the associated
1611 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1613 * The 'vectors' array contains 'count' message vectors. The array
1614 * maps directly to the MSI-X table in that index 0 in the array
1615 * specifies the vector for the first message in the MSI-X table, etc.
1616 * The vector value in each array index can either be 0 to indicate
1617 * that no vector should be assigned to a message slot, or it can be a
1618 * number from 1 to N (where N is the count returned from a
1619 * succcessful call to pci_alloc_msix()) to indicate which message
1620 * vector (IRQ) to be used for the corresponding message.
1622 * On successful return, each message with a non-zero vector will have
1623 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1624 * 1. Additionally, if any of the IRQs allocated via the previous
1625 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1626 * will be kfreed back to the system automatically.
1628 * For example, suppose a driver has a MSI-X table with 6 messages and
1629 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1630 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1631 * C. After the call to pci_alloc_msix(), the device will be setup to
1632 * have an MSI-X table of ABC--- (where - means no vector assigned).
1633 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1634 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1635 * be kfreed back to the system. This device will also have valid
1636 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1638 * In any case, the SYS_RES_IRQ rid X will always map to the message
1639 * at MSI-X table index X - 1 and will only be valid if a vector is
1640 * assigned to that table entry.
1643 pci_remap_msix_method(device_t dev, device_t child, int count,
1644 const u_int *vectors)
1646 struct pci_devinfo *dinfo = device_get_ivars(child);
1647 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1648 struct resource_list_entry *rle;
1649 int i, irq, j, *used;
1652 * Have to have at least one message in the table but the
1653 * table can't be bigger than the actual MSI-X table in the
1656 if (count == 0 || count > msix->msix_msgnum)
1659 /* Sanity check the vectors. */
1660 for (i = 0; i < count; i++)
1661 if (vectors[i] > msix->msix_alloc)
1665 * Make sure there aren't any holes in the vectors to be used.
1666 * It's a big pain to support it, and it doesn't really make
1667 * sense anyway. Also, at least one vector must be used.
1669 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1671 for (i = 0; i < count; i++)
1672 if (vectors[i] != 0)
1673 used[vectors[i] - 1] = 1;
1674 for (i = 0; i < msix->msix_alloc - 1; i++)
1675 if (used[i] == 0 && used[i + 1] == 1) {
1676 kfree(used, M_DEVBUF);
1680 kfree(used, M_DEVBUF);
1684 /* Make sure none of the resources are allocated. */
1685 for (i = 0; i < msix->msix_table_len; i++) {
1686 if (msix->msix_table[i].mte_vector == 0)
1688 if (msix->msix_table[i].mte_handlers > 0)
1690 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1691 KASSERT(rle != NULL, ("missing resource"));
1692 if (rle->res != NULL)
1696 /* Free the existing resource list entries. */
1697 for (i = 0; i < msix->msix_table_len; i++) {
1698 if (msix->msix_table[i].mte_vector == 0)
1700 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1704 * Build the new virtual table keeping track of which vectors are
1707 kfree(msix->msix_table, M_DEVBUF);
1708 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1709 M_DEVBUF, M_WAITOK | M_ZERO);
1710 for (i = 0; i < count; i++)
1711 msix->msix_table[i].mte_vector = vectors[i];
1712 msix->msix_table_len = count;
1714 /* Free any unused IRQs and resize the vectors array if necessary. */
1715 j = msix->msix_alloc - 1;
1717 struct msix_vector *vec;
1719 while (used[j] == 0) {
1720 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1721 msix->msix_vectors[j].mv_irq);
1724 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1726 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1728 kfree(msix->msix_vectors, M_DEVBUF);
1729 msix->msix_vectors = vec;
1730 msix->msix_alloc = j + 1;
1732 kfree(used, M_DEVBUF);
1734 /* Map the IRQs onto the rids. */
1735 for (i = 0; i < count; i++) {
1736 if (vectors[i] == 0)
1738 irq = msix->msix_vectors[vectors[i]].mv_irq;
1739 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1744 device_printf(child, "Remapped MSI-X IRQs as: ");
1745 for (i = 0; i < count; i++) {
1748 if (vectors[i] == 0)
1752 msix->msix_vectors[vectors[i]].mv_irq);
1761 pci_release_msix(device_t dev, device_t child)
1763 struct pci_devinfo *dinfo = device_get_ivars(child);
1764 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1765 struct resource_list_entry *rle;
1768 /* Do we have any messages to release? */
1769 if (msix->msix_alloc == 0)
1772 /* Make sure none of the resources are allocated. */
1773 for (i = 0; i < msix->msix_table_len; i++) {
1774 if (msix->msix_table[i].mte_vector == 0)
1776 if (msix->msix_table[i].mte_handlers > 0)
1778 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1779 KASSERT(rle != NULL, ("missing resource"));
1780 if (rle->res != NULL)
1784 /* Update control register to disable MSI-X. */
1785 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1786 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1787 msix->msix_ctrl, 2);
1789 /* Free the resource list entries. */
1790 for (i = 0; i < msix->msix_table_len; i++) {
1791 if (msix->msix_table[i].mte_vector == 0)
1793 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1795 kfree(msix->msix_table, M_DEVBUF);
1796 msix->msix_table_len = 0;
1798 /* Release the IRQs. */
1799 for (i = 0; i < msix->msix_alloc; i++)
1800 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1801 msix->msix_vectors[i].mv_irq);
1802 kfree(msix->msix_vectors, M_DEVBUF);
1803 msix->msix_alloc = 0;
1808 * Return the max supported MSI-X messages this device supports.
1809 * Basically, assuming the MD code can alloc messages, this function
1810 * should return the maximum value that pci_alloc_msix() can return.
1811 * Thus, it is subject to the tunables, etc.
1814 pci_msix_count_method(device_t dev, device_t child)
1816 struct pci_devinfo *dinfo = device_get_ivars(child);
1817 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1819 if (pci_do_msix && msix->msix_location != 0)
1820 return (msix->msix_msgnum);
1825 * HyperTransport MSI mapping control
1828 pci_ht_map_msi(device_t dev, uint64_t addr)
1830 struct pci_devinfo *dinfo = device_get_ivars(dev);
1831 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1836 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1837 ht->ht_msiaddr >> 20 == addr >> 20) {
1838 /* Enable MSI -> HT mapping. */
1839 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1840 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1844 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1845 /* Disable MSI -> HT mapping. */
1846 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1847 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1853 * Support for MSI message signalled interrupts.
1856 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1858 struct pci_devinfo *dinfo = device_get_ivars(dev);
1859 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1861 /* Write data and address values. */
1862 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1863 address & 0xffffffff, 4);
1864 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1865 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1867 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1870 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1873 /* Enable MSI in the control register. */
1874 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1875 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1878 /* Enable MSI -> HT mapping. */
1879 pci_ht_map_msi(dev, address);
1883 pci_disable_msi(device_t dev)
1885 struct pci_devinfo *dinfo = device_get_ivars(dev);
1886 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1888 /* Disable MSI -> HT mapping. */
1889 pci_ht_map_msi(dev, 0);
1891 /* Disable MSI in the control register. */
1892 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1893 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1898 * Restore MSI registers during resume. If MSI is enabled then
1899 * restore the data and address registers in addition to the control
1903 pci_resume_msi(device_t dev)
1905 struct pci_devinfo *dinfo = device_get_ivars(dev);
1906 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1910 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1911 address = msi->msi_addr;
1912 data = msi->msi_data;
1913 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1914 address & 0xffffffff, 4);
1915 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1916 pci_write_config(dev, msi->msi_location +
1917 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1918 pci_write_config(dev, msi->msi_location +
1919 PCIR_MSI_DATA_64BIT, data, 2);
1921 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1924 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1929 pci_remap_msi_irq(device_t dev, u_int irq)
1931 struct pci_devinfo *dinfo = device_get_ivars(dev);
1932 pcicfgregs *cfg = &dinfo->cfg;
1933 struct resource_list_entry *rle;
1934 struct msix_table_entry *mte;
1935 struct msix_vector *mv;
1941 bus = device_get_parent(dev);
1944 * Handle MSI first. We try to find this IRQ among our list
1945 * of MSI IRQs. If we find it, we request updated address and
1946 * data registers and apply the results.
1948 if (cfg->msi.msi_alloc > 0) {
1950 /* If we don't have any active handlers, nothing to do. */
1951 if (cfg->msi.msi_handlers == 0)
1953 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1954 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1956 if (rle->start == irq) {
1957 error = PCIB_MAP_MSI(device_get_parent(bus),
1958 dev, irq, &addr, &data);
1961 pci_disable_msi(dev);
1962 dinfo->cfg.msi.msi_addr = addr;
1963 dinfo->cfg.msi.msi_data = data;
1964 pci_enable_msi(dev, addr, data);
1972 * For MSI-X, we check to see if we have this IRQ. If we do,
1973 * we request the updated mapping info. If that works, we go
1974 * through all the slots that use this IRQ and update them.
1976 if (cfg->msix.msix_alloc > 0) {
1977 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1978 mv = &cfg->msix.msix_vectors[i];
1979 if (mv->mv_irq == irq) {
1980 error = PCIB_MAP_MSI(device_get_parent(bus),
1981 dev, irq, &addr, &data);
1984 mv->mv_address = addr;
1986 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1987 mte = &cfg->msix.msix_table[j];
1988 if (mte->mte_vector != i + 1)
1990 if (mte->mte_handlers == 0)
1992 pci_mask_msix(dev, j);
1993 pci_enable_msix(dev, j, addr, data);
1994 pci_unmask_msix(dev, j);
2005 * Returns true if the specified device is blacklisted because MSI
2009 pci_msi_device_blacklisted(device_t dev)
2011 struct pci_quirk *q;
2013 if (!pci_honor_msi_blacklist)
2016 for (q = &pci_quirks[0]; q->devid; q++) {
2017 if (q->devid == pci_get_devid(dev) &&
2018 q->type == PCI_QUIRK_DISABLE_MSI)
2025 * Determine if MSI is blacklisted globally on this sytem. Currently,
2026 * we just check for blacklisted chipsets as represented by the
2027 * host-PCI bridge at device 0:0:0. In the future, it may become
2028 * necessary to check other system attributes, such as the kenv values
2029 * that give the motherboard manufacturer and model number.
2032 pci_msi_blacklisted(void)
2036 if (!pci_honor_msi_blacklist)
2039 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
2040 if (!(pcie_chipset || pcix_chipset))
2043 dev = pci_find_bsf(0, 0, 0);
2045 return (pci_msi_device_blacklisted(dev));
2050 * Attempt to allocate *count MSI messages. The actual number allocated is
2051 * returned in *count. After this function returns, each message will be
2052 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
2055 pci_alloc_msi_method(device_t dev, device_t child, int *count)
2057 struct pci_devinfo *dinfo = device_get_ivars(child);
2058 pcicfgregs *cfg = &dinfo->cfg;
2059 struct resource_list_entry *rle;
2060 int actual, error, i, irqs[32];
2063 /* Don't let count == 0 get us into trouble. */
2067 /* If rid 0 is allocated, then fail. */
2068 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
2069 if (rle != NULL && rle->res != NULL)
2072 /* Already have allocated messages? */
2073 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
2076 /* If MSI is blacklisted for this system, fail. */
2077 if (pci_msi_blacklisted())
2080 /* MSI capability present? */
2081 if (cfg->msi.msi_location == 0 || !pci_do_msi)
2085 device_printf(child,
2086 "attempting to allocate %d MSI vectors (%d supported)\n",
2087 *count, cfg->msi.msi_msgnum);
2089 /* Don't ask for more than the device supports. */
2090 actual = min(*count, cfg->msi.msi_msgnum);
2092 /* Don't ask for more than 32 messages. */
2093 actual = min(actual, 32);
2095 /* MSI requires power of 2 number of messages. */
2096 if (!powerof2(actual))
2100 /* Try to allocate N messages. */
2101 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
2102 cfg->msi.msi_msgnum, irqs);
2113 * We now have N actual messages mapped onto SYS_RES_IRQ
2114 * resources in the irqs[] array, so add new resources
2115 * starting at rid 1.
2117 for (i = 0; i < actual; i++)
2118 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
2119 irqs[i], irqs[i], 1, -1);
2123 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
2128 * Be fancy and try to print contiguous runs
2129 * of IRQ values as ranges. 'run' is true if
2130 * we are in a range.
2132 device_printf(child, "using IRQs %d", irqs[0]);
2134 for (i = 1; i < actual; i++) {
2136 /* Still in a run? */
2137 if (irqs[i] == irqs[i - 1] + 1) {
2142 /* Finish previous range. */
2144 kprintf("-%d", irqs[i - 1]);
2148 /* Start new range. */
2149 kprintf(",%d", irqs[i]);
2152 /* Unfinished range? */
2154 kprintf("-%d", irqs[actual - 1]);
2155 kprintf(" for MSI\n");
2159 /* Update control register with actual count. */
2160 ctrl = cfg->msi.msi_ctrl;
2161 ctrl &= ~PCIM_MSICTRL_MME_MASK;
2162 ctrl |= (ffs(actual) - 1) << 4;
2163 cfg->msi.msi_ctrl = ctrl;
2164 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
2166 /* Update counts of alloc'd messages. */
2167 cfg->msi.msi_alloc = actual;
2168 cfg->msi.msi_handlers = 0;
2173 /* Release the MSI messages associated with this device. */
2175 pci_release_msi_method(device_t dev, device_t child)
2177 struct pci_devinfo *dinfo = device_get_ivars(child);
2178 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2179 struct resource_list_entry *rle;
2180 int error, i, irqs[32];
2182 /* Try MSI-X first. */
2183 error = pci_release_msix(dev, child);
2184 if (error != ENODEV)
2187 /* Do we have any messages to release? */
2188 if (msi->msi_alloc == 0)
2190 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
2192 /* Make sure none of the resources are allocated. */
2193 if (msi->msi_handlers > 0)
2195 for (i = 0; i < msi->msi_alloc; i++) {
2196 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
2197 KASSERT(rle != NULL, ("missing MSI resource"));
2198 if (rle->res != NULL)
2200 irqs[i] = rle->start;
2203 /* Update control register with 0 count. */
2204 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
2205 ("%s: MSI still enabled", __func__));
2206 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
2207 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
2210 /* Release the messages. */
2211 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
2212 for (i = 0; i < msi->msi_alloc; i++)
2213 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
2215 /* Update alloc count. */
2223 * Return the max supported MSI messages this device supports.
2224 * Basically, assuming the MD code can alloc messages, this function
2225 * should return the maximum value that pci_alloc_msi() can return.
2226 * Thus, it is subject to the tunables, etc.
2229 pci_msi_count_method(device_t dev, device_t child)
2231 struct pci_devinfo *dinfo = device_get_ivars(child);
2232 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2234 if (pci_do_msi && msi->msi_location != 0)
2235 return (msi->msi_msgnum);
2239 /* kfree pcicfgregs structure and all depending data structures */
2242 pci_freecfg(struct pci_devinfo *dinfo)
2244 struct devlist *devlist_head;
2247 devlist_head = &pci_devq;
2249 if (dinfo->cfg.vpd.vpd_reg) {
2250 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2251 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2252 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2253 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2254 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2255 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2256 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2258 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2259 kfree(dinfo, M_DEVBUF);
2261 /* increment the generation count */
2264 /* we're losing one device */
2270 * PCI power manangement
2273 pci_set_powerstate_method(device_t dev, device_t child, int state)
2275 struct pci_devinfo *dinfo = device_get_ivars(child);
2276 pcicfgregs *cfg = &dinfo->cfg;
2278 int result, oldstate, highest, delay;
2280 if (cfg->pp.pp_cap == 0)
2281 return (EOPNOTSUPP);
2284 * Optimize a no state change request away. While it would be OK to
2285 * write to the hardware in theory, some devices have shown odd
2286 * behavior when going from D3 -> D3.
2288 oldstate = pci_get_powerstate(child);
2289 if (oldstate == state)
2293 * The PCI power management specification states that after a state
2294 * transition between PCI power states, system software must
2295 * guarantee a minimal delay before the function accesses the device.
2296 * Compute the worst case delay that we need to guarantee before we
2297 * access the device. Many devices will be responsive much more
2298 * quickly than this delay, but there are some that don't respond
2299 * instantly to state changes. Transitions to/from D3 state require
2300 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2301 * is done below with DELAY rather than a sleeper function because
2302 * this function can be called from contexts where we cannot sleep.
2304 highest = (oldstate > state) ? oldstate : state;
2305 if (highest == PCI_POWERSTATE_D3)
2307 else if (highest == PCI_POWERSTATE_D2)
2311 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2312 & ~PCIM_PSTAT_DMASK;
2315 case PCI_POWERSTATE_D0:
2316 status |= PCIM_PSTAT_D0;
2318 case PCI_POWERSTATE_D1:
2319 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2320 return (EOPNOTSUPP);
2321 status |= PCIM_PSTAT_D1;
2323 case PCI_POWERSTATE_D2:
2324 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2325 return (EOPNOTSUPP);
2326 status |= PCIM_PSTAT_D2;
2328 case PCI_POWERSTATE_D3:
2329 status |= PCIM_PSTAT_D3;
2337 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2338 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2339 dinfo->cfg.func, oldstate, state);
2341 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2348 pci_get_powerstate_method(device_t dev, device_t child)
2350 struct pci_devinfo *dinfo = device_get_ivars(child);
2351 pcicfgregs *cfg = &dinfo->cfg;
2355 if (cfg->pp.pp_cap != 0) {
2356 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2357 switch (status & PCIM_PSTAT_DMASK) {
2359 result = PCI_POWERSTATE_D0;
2362 result = PCI_POWERSTATE_D1;
2365 result = PCI_POWERSTATE_D2;
2368 result = PCI_POWERSTATE_D3;
2371 result = PCI_POWERSTATE_UNKNOWN;
2375 /* No support, device is always at D0 */
2376 result = PCI_POWERSTATE_D0;
2382 * Some convenience functions for PCI device drivers.
2385 static __inline void
2386 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2390 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2392 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2395 static __inline void
2396 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2400 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2402 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2406 pci_enable_busmaster_method(device_t dev, device_t child)
2408 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2413 pci_disable_busmaster_method(device_t dev, device_t child)
2415 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2420 pci_enable_io_method(device_t dev, device_t child, int space)
2430 case SYS_RES_IOPORT:
2431 bit = PCIM_CMD_PORTEN;
2434 case SYS_RES_MEMORY:
2435 bit = PCIM_CMD_MEMEN;
2441 pci_set_command_bit(dev, child, bit);
2442 /* Some devices seem to need a brief stall here, what do to? */
2443 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2446 device_printf(child, "failed to enable %s mapping!\n", error);
2451 pci_disable_io_method(device_t dev, device_t child, int space)
2461 case SYS_RES_IOPORT:
2462 bit = PCIM_CMD_PORTEN;
2465 case SYS_RES_MEMORY:
2466 bit = PCIM_CMD_MEMEN;
2472 pci_clear_command_bit(dev, child, bit);
2473 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2474 if (command & bit) {
2475 device_printf(child, "failed to disable %s mapping!\n", error);
2482 * New style pci driver. Parent device is either a pci-host-bridge or a
2483 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2487 pci_print_verbose(struct pci_devinfo *dinfo)
2491 pcicfgregs *cfg = &dinfo->cfg;
2493 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2494 cfg->vendor, cfg->device, cfg->revid);
2495 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2496 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2497 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2498 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2500 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2501 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2502 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2503 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2504 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2505 if (cfg->intpin > 0)
2506 kprintf("\tintpin=%c, irq=%d\n",
2507 cfg->intpin +'a' -1, cfg->intline);
2508 if (cfg->pp.pp_cap) {
2511 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2512 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2513 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2514 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2515 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2516 status & PCIM_PSTAT_DMASK);
2518 if (cfg->msi.msi_location) {
2521 ctrl = cfg->msi.msi_ctrl;
2522 kprintf("\tMSI supports %d message%s%s%s\n",
2523 cfg->msi.msi_msgnum,
2524 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2525 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2526 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2528 if (cfg->msix.msix_location) {
2529 kprintf("\tMSI-X supports %d message%s ",
2530 cfg->msix.msix_msgnum,
2531 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2532 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2533 kprintf("in map 0x%x\n",
2534 cfg->msix.msix_table_bar);
2536 kprintf("in maps 0x%x and 0x%x\n",
2537 cfg->msix.msix_table_bar,
2538 cfg->msix.msix_pba_bar);
2540 pci_print_verbose_expr(cfg);
2545 pci_print_verbose_expr(const pcicfgregs *cfg)
2547 const struct pcicfg_expr *expr = &cfg->expr;
2548 const char *port_name;
2554 if (expr->expr_ptr == 0) /* No PCI Express capability */
2557 kprintf("\tPCI Express ver.%d cap=0x%04x",
2558 expr->expr_cap & PCIEM_CAP_VER_MASK, expr->expr_cap);
2559 if ((expr->expr_cap & PCIEM_CAP_VER_MASK) != PCIEM_CAP_VER_1)
2562 port_type = expr->expr_cap & PCIEM_CAP_PORT_TYPE;
2564 switch (port_type) {
2565 case PCIE_END_POINT:
2566 port_name = "DEVICE";
2568 case PCIE_LEG_END_POINT:
2569 port_name = "LEGDEV";
2571 case PCIE_ROOT_PORT:
2574 case PCIE_UP_STREAM_PORT:
2575 port_name = "UPSTREAM";
2577 case PCIE_DOWN_STREAM_PORT:
2578 port_name = "DOWNSTRM";
2580 case PCIE_PCIE2PCI_BRIDGE:
2581 port_name = "PCIE2PCI";
2583 case PCIE_PCI2PCIE_BRIDGE:
2584 port_name = "PCI2PCIE";
2590 if ((port_type == PCIE_ROOT_PORT ||
2591 port_type == PCIE_DOWN_STREAM_PORT) &&
2592 !(expr->expr_cap & PCIEM_CAP_SLOT_IMPL))
2594 if (port_name != NULL)
2595 kprintf("[%s]", port_name);
2597 if (pcie_slotimpl(cfg)) {
2598 kprintf(", slotcap=0x%08x", expr->expr_slotcap);
2599 if (expr->expr_slotcap & PCIEM_SLTCAP_HP_CAP)
2600 kprintf("[HOTPLUG]");
2607 pci_porten(device_t pcib, int b, int s, int f)
2609 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2610 & PCIM_CMD_PORTEN) != 0;
2614 pci_memen(device_t pcib, int b, int s, int f)
2616 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2617 & PCIM_CMD_MEMEN) != 0;
2621 * Add a resource based on a pci map register. Return 1 if the map
2622 * register is a 32bit map register or 2 if it is a 64bit register.
2625 pci_add_map(device_t pcib, device_t bus, device_t dev,
2626 int b, int s, int f, int reg, struct resource_list *rl, int force,
2631 pci_addr_t start, end, count;
2638 struct resource *res;
2640 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2641 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2642 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2643 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2645 if (PCI_BAR_MEM(map)) {
2646 type = SYS_RES_MEMORY;
2647 if (map & PCIM_BAR_MEM_PREFETCH)
2650 type = SYS_RES_IOPORT;
2651 ln2size = pci_mapsize(testval);
2652 ln2range = pci_maprange(testval);
2653 base = pci_mapbase(map);
2654 barlen = ln2range == 64 ? 2 : 1;
2657 * For I/O registers, if bottom bit is set, and the next bit up
2658 * isn't clear, we know we have a BAR that doesn't conform to the
2659 * spec, so ignore it. Also, sanity check the size of the data
2660 * areas to the type of memory involved. Memory must be at least
2661 * 16 bytes in size, while I/O ranges must be at least 4.
2663 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2665 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2666 (type == SYS_RES_IOPORT && ln2size < 2))
2670 /* Read the other half of a 64bit map register */
2671 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2673 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2674 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2675 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2676 kprintf(", port disabled\n");
2677 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2678 kprintf(", memory disabled\n");
2680 kprintf(", enabled\n");
2684 * If base is 0, then we have problems. It is best to ignore
2685 * such entries for the moment. These will be allocated later if
2686 * the driver specifically requests them. However, some
2687 * removable busses look better when all resources are allocated,
2688 * so allow '0' to be overriden.
2690 * Similarly treat maps whose values is the same as the test value
2691 * read back. These maps have had all f's written to them by the
2692 * BIOS in an attempt to disable the resources.
2694 if (!force && (base == 0 || map == testval))
2696 if ((u_long)base != base) {
2698 "pci%d:%d:%d:%d bar %#x too many address bits",
2699 pci_get_domain(dev), b, s, f, reg);
2704 * This code theoretically does the right thing, but has
2705 * undesirable side effects in some cases where peripherals
2706 * respond oddly to having these bits enabled. Let the user
2707 * be able to turn them off (since pci_enable_io_modes is 1 by
2710 if (pci_enable_io_modes) {
2711 /* Turn on resources that have been left off by a lazy BIOS */
2712 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2713 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2714 cmd |= PCIM_CMD_PORTEN;
2715 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2717 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2718 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2719 cmd |= PCIM_CMD_MEMEN;
2720 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2723 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2725 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2729 count = 1 << ln2size;
2730 if (base == 0 || base == pci_mapbase(testval)) {
2731 start = 0; /* Let the parent decide. */
2735 end = base + (1 << ln2size) - 1;
2737 resource_list_add(rl, type, reg, start, end, count, -1);
2740 * Try to allocate the resource for this BAR from our parent
2741 * so that this resource range is already reserved. The
2742 * driver for this device will later inherit this resource in
2743 * pci_alloc_resource().
2745 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2746 prefetch ? RF_PREFETCHABLE : 0, -1);
2749 * If the allocation fails, delete the resource list
2750 * entry to force pci_alloc_resource() to allocate
2751 * resources from the parent.
2753 resource_list_delete(rl, type, reg);
2754 #ifdef PCI_BAR_CLEAR
2757 #else /* !PCI_BAR_CLEAR */
2759 * Don't clear BAR here. Some BIOS lists HPET as a
2760 * PCI function, clearing the BAR causes HPET timer
2764 kprintf("pci:%d:%d:%d: resource reservation failed "
2765 "%#jx - %#jx\n", b, s, f,
2766 (intmax_t)start, (intmax_t)end);
2769 #endif /* PCI_BAR_CLEAR */
2771 start = rman_get_start(res);
2773 pci_write_config(dev, reg, start, 4);
2775 pci_write_config(dev, reg + 4, start >> 32, 4);
2780 * For ATA devices we need to decide early what addressing mode to use.
2781 * Legacy demands that the primary and secondary ATA ports sits on the
2782 * same addresses that old ISA hardware did. This dictates that we use
2783 * those addresses and ignore the BAR's if we cannot set PCI native
2787 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2788 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2790 int rid, type, progif;
2792 /* if this device supports PCI native addressing use it */
2793 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2794 if ((progif & 0x8a) == 0x8a) {
2795 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2796 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2797 kprintf("Trying ATA native PCI addressing mode\n");
2798 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2802 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2803 type = SYS_RES_IOPORT;
2804 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2805 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2806 prefetchmask & (1 << 0));
2807 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2808 prefetchmask & (1 << 1));
2811 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8, -1);
2812 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2815 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1, -1);
2816 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2819 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2820 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2821 prefetchmask & (1 << 2));
2822 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2823 prefetchmask & (1 << 3));
2826 resource_list_add(rl, type, rid, 0x170, 0x177, 8, -1);
2827 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2830 resource_list_add(rl, type, rid, 0x376, 0x376, 1, -1);
2831 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2834 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2835 prefetchmask & (1 << 4));
2836 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2837 prefetchmask & (1 << 5));
2841 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2843 struct pci_devinfo *dinfo = device_get_ivars(dev);
2844 pcicfgregs *cfg = &dinfo->cfg;
2845 char tunable_name[64];
2848 /* Has to have an intpin to have an interrupt. */
2849 if (cfg->intpin == 0)
2852 /* Let the user override the IRQ with a tunable. */
2853 irq = PCI_INVALID_IRQ;
2854 ksnprintf(tunable_name, sizeof(tunable_name),
2855 "hw.pci%d.%d.%d.INT%c.irq",
2856 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2857 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2858 irq = PCI_INVALID_IRQ;
2861 * If we didn't get an IRQ via the tunable, then we either use the
2862 * IRQ value in the intline register or we ask the bus to route an
2863 * interrupt for us. If force_route is true, then we only use the
2864 * value in the intline register if the bus was unable to assign an
2867 if (!PCI_INTERRUPT_VALID(irq)) {
2868 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2869 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2870 if (!PCI_INTERRUPT_VALID(irq))
2874 /* If after all that we don't have an IRQ, just bail. */
2875 if (!PCI_INTERRUPT_VALID(irq))
2878 /* Update the config register if it changed. */
2879 if (irq != cfg->intline) {
2881 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2884 /* Add this IRQ as rid 0 interrupt resource. */
2885 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1,
2886 machintr_intr_cpuid(irq));
2890 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2892 struct pci_devinfo *dinfo = device_get_ivars(dev);
2893 pcicfgregs *cfg = &dinfo->cfg;
2894 struct resource_list *rl = &dinfo->resources;
2895 struct pci_quirk *q;
2902 /* ATA devices needs special map treatment */
2903 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2904 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2905 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2906 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2907 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2908 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2910 for (i = 0; i < cfg->nummaps;)
2911 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2912 rl, force, prefetchmask & (1 << i));
2915 * Add additional, quirked resources.
2917 for (q = &pci_quirks[0]; q->devid; q++) {
2918 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2919 && q->type == PCI_QUIRK_MAP_REG)
2920 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2924 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2926 * Try to re-route interrupts. Sometimes the BIOS or
2927 * firmware may leave bogus values in these registers.
2928 * If the re-route fails, then just stick with what we
2931 pci_assign_interrupt(bus, dev, 1);
2936 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2938 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2939 device_t pcib = device_get_parent(dev);
2940 struct pci_devinfo *dinfo;
2942 int s, f, pcifunchigh;
2945 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2946 ("dinfo_size too small"));
2947 maxslots = PCIB_MAXSLOTS(pcib);
2948 for (s = 0; s <= maxslots; s++) {
2952 hdrtype = REG(PCIR_HDRTYPE, 1);
2953 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2955 if (hdrtype & PCIM_MFDEV)
2956 pcifunchigh = PCI_FUNCMAX;
2957 for (f = 0; f <= pcifunchigh; f++) {
2958 dinfo = pci_read_device(pcib, domain, busno, s, f,
2960 if (dinfo != NULL) {
2961 pci_add_child(dev, dinfo);
2969 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2973 pcib = device_get_parent(bus);
2974 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2975 device_set_ivars(dinfo->cfg.dev, dinfo);
2976 resource_list_init(&dinfo->resources);
2977 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2978 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2979 pci_print_verbose(dinfo);
2980 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2984 pci_probe(device_t dev)
2986 device_set_desc(dev, "PCI bus");
2988 /* Allow other subclasses to override this driver. */
2993 pci_attach(device_t dev)
2998 * Since there can be multiple independantly numbered PCI
2999 * busses on systems with multiple PCI domains, we can't use
3000 * the unit number to decide which bus we are probing. We ask
3001 * the parent pcib what our domain and bus numbers are.
3003 domain = pcib_get_domain(dev);
3004 busno = pcib_get_bus(dev);
3006 device_printf(dev, "domain=%d, physical bus=%d\n",
3009 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
3011 return (bus_generic_attach(dev));
3015 pci_suspend(device_t dev)
3017 int dstate, error, i, numdevs;
3018 device_t acpi_dev, child, *devlist;
3019 struct pci_devinfo *dinfo;
3022 * Save the PCI configuration space for each child and set the
3023 * device in the appropriate power state for this sleep state.
3026 if (pci_do_power_resume)
3027 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3028 device_get_children(dev, &devlist, &numdevs);
3029 for (i = 0; i < numdevs; i++) {
3031 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3032 pci_cfg_save(child, dinfo, 0);
3035 /* Suspend devices before potentially powering them down. */
3036 error = bus_generic_suspend(dev);
3038 kfree(devlist, M_TEMP);
3043 * Always set the device to D3. If ACPI suggests a different
3044 * power state, use it instead. If ACPI is not present, the
3045 * firmware is responsible for managing device power. Skip
3046 * children who aren't attached since they are powered down
3047 * separately. Only manage type 0 devices for now.
3049 for (i = 0; acpi_dev && i < numdevs; i++) {
3051 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3052 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
3053 dstate = PCI_POWERSTATE_D3;
3054 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
3055 pci_set_powerstate(child, dstate);
3058 kfree(devlist, M_TEMP);
3063 pci_resume(device_t dev)
3066 device_t acpi_dev, child, *devlist;
3067 struct pci_devinfo *dinfo;
3070 * Set each child to D0 and restore its PCI configuration space.
3073 if (pci_do_power_resume)
3074 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
3075 device_get_children(dev, &devlist, &numdevs);
3076 for (i = 0; i < numdevs; i++) {
3078 * Notify ACPI we're going to D0 but ignore the result. If
3079 * ACPI is not present, the firmware is responsible for
3080 * managing device power. Only manage type 0 devices for now.
3083 dinfo = (struct pci_devinfo *) device_get_ivars(child);
3084 if (acpi_dev && device_is_attached(child) &&
3085 dinfo->cfg.hdrtype == 0) {
3086 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
3087 pci_set_powerstate(child, PCI_POWERSTATE_D0);
3090 /* Now the device is powered up, restore its config space. */
3091 pci_cfg_restore(child, dinfo);
3093 kfree(devlist, M_TEMP);
3094 return (bus_generic_resume(dev));
3098 pci_load_vendor_data(void)
3100 caddr_t vendordata, info;
3102 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
3103 info = preload_search_info(vendordata, MODINFO_ADDR);
3104 pci_vendordata = *(char **)info;
3105 info = preload_search_info(vendordata, MODINFO_SIZE);
3106 pci_vendordata_size = *(size_t *)info;
3107 /* terminate the database */
3108 pci_vendordata[pci_vendordata_size] = '\n';
3113 pci_driver_added(device_t dev, driver_t *driver)
3118 struct pci_devinfo *dinfo;
3122 device_printf(dev, "driver added\n");
3123 DEVICE_IDENTIFY(driver, dev);
3124 device_get_children(dev, &devlist, &numdevs);
3125 for (i = 0; i < numdevs; i++) {
3127 if (device_get_state(child) != DS_NOTPRESENT)
3129 dinfo = device_get_ivars(child);
3130 pci_print_verbose(dinfo);
3132 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
3133 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
3135 pci_cfg_restore(child, dinfo);
3136 if (device_probe_and_attach(child) != 0)
3137 pci_cfg_save(child, dinfo, 1);
3139 kfree(devlist, M_TEMP);
3143 pci_child_detached(device_t parent __unused, device_t child)
3145 /* Turn child's power off */
3146 pci_cfg_save(child, device_get_ivars(child), 1);
3150 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
3151 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
3154 struct pci_devinfo *dinfo;
3155 struct msix_table_entry *mte;
3156 struct msix_vector *mv;
3163 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
3164 arg, &cookie, serializer);
3168 /* If this is not a direct child, just bail out. */
3169 if (device_get_parent(child) != dev) {
3174 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3176 rid = rman_get_rid(irq);
3178 /* Make sure that INTx is enabled */
3179 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
3182 * Check to see if the interrupt is MSI or MSI-X.
3183 * Ask our parent to map the MSI and give
3184 * us the address and data register values.
3185 * If we fail for some reason, teardown the
3186 * interrupt handler.
3188 dinfo = device_get_ivars(child);
3189 if (dinfo->cfg.msi.msi_alloc > 0) {
3190 if (dinfo->cfg.msi.msi_addr == 0) {
3191 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
3192 ("MSI has handlers, but vectors not mapped"));
3193 error = PCIB_MAP_MSI(device_get_parent(dev),
3194 child, rman_get_start(irq), &addr, &data);
3197 dinfo->cfg.msi.msi_addr = addr;
3198 dinfo->cfg.msi.msi_data = data;
3199 pci_enable_msi(child, addr, data);
3201 dinfo->cfg.msi.msi_handlers++;
3203 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3204 ("No MSI or MSI-X interrupts allocated"));
3205 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3206 ("MSI-X index too high"));
3207 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3208 KASSERT(mte->mte_vector != 0, ("no message vector"));
3209 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
3210 KASSERT(mv->mv_irq == rman_get_start(irq),
3212 if (mv->mv_address == 0) {
3213 KASSERT(mte->mte_handlers == 0,
3214 ("MSI-X table entry has handlers, but vector not mapped"));
3215 error = PCIB_MAP_MSI(device_get_parent(dev),
3216 child, rman_get_start(irq), &addr, &data);
3219 mv->mv_address = addr;
3222 if (mte->mte_handlers == 0) {
3223 pci_enable_msix(child, rid - 1, mv->mv_address,
3225 pci_unmask_msix(child, rid - 1);
3227 mte->mte_handlers++;
3230 /* Make sure that INTx is disabled if we are using MSI/MSIX */
3231 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3234 (void)bus_generic_teardown_intr(dev, child, irq,
3245 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
3249 struct msix_table_entry *mte;
3250 struct resource_list_entry *rle;
3251 struct pci_devinfo *dinfo;
3256 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
3259 /* If this isn't a direct child, just bail out */
3260 if (device_get_parent(child) != dev)
3261 return(bus_generic_teardown_intr(dev, child, irq, cookie));
3263 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3265 rid = rman_get_rid(irq);
3268 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
3271 * Check to see if the interrupt is MSI or MSI-X. If so,
3272 * decrement the appropriate handlers count and mask the
3273 * MSI-X message, or disable MSI messages if the count
3276 dinfo = device_get_ivars(child);
3277 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
3278 if (rle->res != irq)
3280 if (dinfo->cfg.msi.msi_alloc > 0) {
3281 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
3282 ("MSI-X index too high"));
3283 if (dinfo->cfg.msi.msi_handlers == 0)
3285 dinfo->cfg.msi.msi_handlers--;
3286 if (dinfo->cfg.msi.msi_handlers == 0)
3287 pci_disable_msi(child);
3289 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
3290 ("No MSI or MSI-X interrupts allocated"));
3291 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
3292 ("MSI-X index too high"));
3293 mte = &dinfo->cfg.msix.msix_table[rid - 1];
3294 if (mte->mte_handlers == 0)
3296 mte->mte_handlers--;
3297 if (mte->mte_handlers == 0)
3298 pci_mask_msix(child, rid - 1);
3301 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3304 ("%s: generic teardown failed for MSI/MSI-X", __func__));
3306 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3311 pci_print_child(device_t dev, device_t child)
3313 struct pci_devinfo *dinfo;
3314 struct resource_list *rl;
3317 dinfo = device_get_ivars(child);
3318 rl = &dinfo->resources;
3320 retval += bus_print_child_header(dev, child);
3322 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3323 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3324 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3325 if (device_get_flags(dev))
3326 retval += kprintf(" flags %#x", device_get_flags(dev));
3328 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3329 pci_get_function(child));
3331 retval += bus_print_child_footer(dev, child);
3341 } pci_nomatch_tab[] = {
3342 {PCIC_OLD, -1, "old"},
3343 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3344 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3345 {PCIC_STORAGE, -1, "mass storage"},
3346 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3347 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3348 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3349 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3350 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3351 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3352 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3353 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3354 {PCIC_NETWORK, -1, "network"},
3355 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3356 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3357 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3358 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3359 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3360 {PCIC_DISPLAY, -1, "display"},
3361 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3362 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3363 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3364 {PCIC_MULTIMEDIA, -1, "multimedia"},
3365 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3366 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3367 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3368 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3369 {PCIC_MEMORY, -1, "memory"},
3370 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3371 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3372 {PCIC_BRIDGE, -1, "bridge"},
3373 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3374 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3375 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3376 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3377 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3378 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3379 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3380 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3381 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3382 {PCIC_SIMPLECOMM, -1, "simple comms"},
3383 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3384 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3385 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3386 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3387 {PCIC_BASEPERIPH, -1, "base peripheral"},
3388 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3389 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3390 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3391 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3392 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3393 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3394 {PCIC_INPUTDEV, -1, "input device"},
3395 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3396 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3397 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3398 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3399 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3400 {PCIC_DOCKING, -1, "docking station"},
3401 {PCIC_PROCESSOR, -1, "processor"},
3402 {PCIC_SERIALBUS, -1, "serial bus"},
3403 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3404 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3405 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3406 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3407 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3408 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3409 {PCIC_WIRELESS, -1, "wireless controller"},
3410 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3411 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3412 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3413 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3414 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3415 {PCIC_SATCOM, -1, "satellite communication"},
3416 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3417 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3418 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3419 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3420 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3421 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3422 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3423 {PCIC_DASP, -1, "dasp"},
3424 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3429 pci_probe_nomatch(device_t dev, device_t child)
3432 char *cp, *scp, *device;
3435 * Look for a listing for this device in a loaded device database.
3437 if ((device = pci_describe_device(child)) != NULL) {
3438 device_printf(dev, "<%s>", device);
3439 kfree(device, M_DEVBUF);
3442 * Scan the class/subclass descriptions for a general
3447 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3448 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3449 if (pci_nomatch_tab[i].subclass == -1) {
3450 cp = pci_nomatch_tab[i].desc;
3451 } else if (pci_nomatch_tab[i].subclass ==
3452 pci_get_subclass(child)) {
3453 scp = pci_nomatch_tab[i].desc;
3457 device_printf(dev, "<%s%s%s>",
3459 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3462 kprintf(" (vendor 0x%04x, dev 0x%04x) at device %d.%d",
3463 pci_get_vendor(child), pci_get_device(child),
3464 pci_get_slot(child), pci_get_function(child));
3465 if (pci_get_intpin(child) > 0) {
3468 irq = pci_get_irq(child);
3469 if (PCI_INTERRUPT_VALID(irq))
3470 kprintf(" irq %d", irq);
3474 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3478 * Parse the PCI device database, if loaded, and return a pointer to a
3479 * description of the device.
3481 * The database is flat text formatted as follows:
3483 * Any line not in a valid format is ignored.
3484 * Lines are terminated with newline '\n' characters.
3486 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3489 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3490 * - devices cannot be listed without a corresponding VENDOR line.
3491 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3492 * another TAB, then the device name.
3496 * Assuming (ptr) points to the beginning of a line in the database,
3497 * return the vendor or device and description of the next entry.
3498 * The value of (vendor) or (device) inappropriate for the entry type
3499 * is set to -1. Returns nonzero at the end of the database.
3501 * Note that this is slightly unrobust in the face of corrupt data;
3502 * we attempt to safeguard against this by spamming the end of the
3503 * database with a newline when we initialise.
3506 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3515 left = pci_vendordata_size - (cp - pci_vendordata);
3523 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3527 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3530 /* skip to next line */
3531 while (*cp != '\n' && left > 0) {
3540 /* skip to next line */
3541 while (*cp != '\n' && left > 0) {
3545 if (*cp == '\n' && left > 0)
3552 pci_describe_device(device_t dev)
3555 char *desc, *vp, *dp, *line;
3557 desc = vp = dp = NULL;
3560 * If we have no vendor data, we can't do anything.
3562 if (pci_vendordata == NULL)
3566 * Scan the vendor data looking for this device
3568 line = pci_vendordata;
3569 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3572 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3574 if (vendor == pci_get_vendor(dev))
3577 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3580 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3588 if (device == pci_get_device(dev))
3592 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3593 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3595 ksprintf(desc, "%s, %s", vp, dp);
3598 kfree(vp, M_DEVBUF);
3600 kfree(dp, M_DEVBUF);
3605 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3607 struct pci_devinfo *dinfo;
3610 dinfo = device_get_ivars(child);
3614 case PCI_IVAR_ETHADDR:
3616 * The generic accessor doesn't deal with failure, so
3617 * we set the return value, then return an error.
3619 *((uint8_t **) result) = NULL;
3621 case PCI_IVAR_SUBVENDOR:
3622 *result = cfg->subvendor;
3624 case PCI_IVAR_SUBDEVICE:
3625 *result = cfg->subdevice;
3627 case PCI_IVAR_VENDOR:
3628 *result = cfg->vendor;
3630 case PCI_IVAR_DEVICE:
3631 *result = cfg->device;
3633 case PCI_IVAR_DEVID:
3634 *result = (cfg->device << 16) | cfg->vendor;
3636 case PCI_IVAR_CLASS:
3637 *result = cfg->baseclass;
3639 case PCI_IVAR_SUBCLASS:
3640 *result = cfg->subclass;
3642 case PCI_IVAR_PROGIF:
3643 *result = cfg->progif;
3645 case PCI_IVAR_REVID:
3646 *result = cfg->revid;
3648 case PCI_IVAR_INTPIN:
3649 *result = cfg->intpin;
3652 *result = cfg->intline;
3654 case PCI_IVAR_DOMAIN:
3655 *result = cfg->domain;
3661 *result = cfg->slot;
3663 case PCI_IVAR_FUNCTION:
3664 *result = cfg->func;
3666 case PCI_IVAR_CMDREG:
3667 *result = cfg->cmdreg;
3669 case PCI_IVAR_CACHELNSZ:
3670 *result = cfg->cachelnsz;
3672 case PCI_IVAR_MINGNT:
3673 *result = cfg->mingnt;
3675 case PCI_IVAR_MAXLAT:
3676 *result = cfg->maxlat;
3678 case PCI_IVAR_LATTIMER:
3679 *result = cfg->lattimer;
3681 case PCI_IVAR_PCIXCAP_PTR:
3682 *result = cfg->pcix.pcix_ptr;
3684 case PCI_IVAR_PCIECAP_PTR:
3685 *result = cfg->expr.expr_ptr;
3687 case PCI_IVAR_VPDCAP_PTR:
3688 *result = cfg->vpd.vpd_reg;
3697 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3699 struct pci_devinfo *dinfo;
3701 dinfo = device_get_ivars(child);
3704 case PCI_IVAR_INTPIN:
3705 dinfo->cfg.intpin = value;
3707 case PCI_IVAR_ETHADDR:
3708 case PCI_IVAR_SUBVENDOR:
3709 case PCI_IVAR_SUBDEVICE:
3710 case PCI_IVAR_VENDOR:
3711 case PCI_IVAR_DEVICE:
3712 case PCI_IVAR_DEVID:
3713 case PCI_IVAR_CLASS:
3714 case PCI_IVAR_SUBCLASS:
3715 case PCI_IVAR_PROGIF:
3716 case PCI_IVAR_REVID:
3718 case PCI_IVAR_DOMAIN:
3721 case PCI_IVAR_FUNCTION:
3722 return (EINVAL); /* disallow for now */
3729 #include "opt_ddb.h"
3731 #include <ddb/ddb.h>
3732 #include <sys/cons.h>
3735 * List resources based on pci map registers, used for within ddb
3738 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3740 struct pci_devinfo *dinfo;
3741 struct devlist *devlist_head;
3744 int i, error, none_count;
3747 /* get the head of the device queue */
3748 devlist_head = &pci_devq;
3751 * Go through the list of devices and print out devices
3753 for (error = 0, i = 0,
3754 dinfo = STAILQ_FIRST(devlist_head);
3755 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3756 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3758 /* Populate pd_name and pd_unit */
3761 name = device_get_name(dinfo->cfg.dev);
3764 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3765 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3766 (name && *name) ? name : "none",
3767 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3769 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3770 p->pc_sel.pc_func, (p->pc_class << 16) |
3771 (p->pc_subclass << 8) | p->pc_progif,
3772 (p->pc_subdevice << 16) | p->pc_subvendor,
3773 (p->pc_device << 16) | p->pc_vendor,
3774 p->pc_revid, p->pc_hdr);
3780 static struct resource *
3781 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3782 u_long start, u_long end, u_long count, u_int flags)
3784 struct pci_devinfo *dinfo = device_get_ivars(child);
3785 struct resource_list *rl = &dinfo->resources;
3786 struct resource_list_entry *rle;
3787 struct resource *res;
3788 pci_addr_t map, testval;
3792 * Weed out the bogons, and figure out how large the BAR/map
3793 * is. Bars that read back 0 here are bogus and unimplemented.
3794 * Note: atapci in legacy mode are special and handled elsewhere
3795 * in the code. If you have a atapci device in legacy mode and
3796 * it fails here, that other code is broken.
3799 map = pci_read_config(child, *rid, 4);
3800 pci_write_config(child, *rid, 0xffffffff, 4);
3801 testval = pci_read_config(child, *rid, 4);
3802 if (pci_maprange(testval) == 64)
3803 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3804 if (pci_mapbase(testval) == 0)
3808 * Restore the original value of the BAR. We may have reprogrammed
3809 * the BAR of the low-level console device and when booting verbose,
3810 * we need the console device addressable.
3812 pci_write_config(child, *rid, map, 4);
3814 if (PCI_BAR_MEM(testval)) {
3815 if (type != SYS_RES_MEMORY) {
3818 "child %s requested type %d for rid %#x,"
3819 " but the BAR says it is an memio\n",
3820 device_get_nameunit(child), type, *rid);
3824 if (type != SYS_RES_IOPORT) {
3827 "child %s requested type %d for rid %#x,"
3828 " but the BAR says it is an ioport\n",
3829 device_get_nameunit(child), type, *rid);
3834 * For real BARs, we need to override the size that
3835 * the driver requests, because that's what the BAR
3836 * actually uses and we would otherwise have a
3837 * situation where we might allocate the excess to
3838 * another driver, which won't work.
3840 mapsize = pci_mapsize(testval);
3841 count = 1UL << mapsize;
3842 if (RF_ALIGNMENT(flags) < mapsize)
3843 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3844 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3845 flags |= RF_PREFETCHABLE;
3848 * Allocate enough resource, and then write back the
3849 * appropriate bar for that resource.
3851 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3852 start, end, count, flags, -1);
3854 device_printf(child,
3855 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3856 count, *rid, type, start, end);
3859 resource_list_add(rl, type, *rid, start, end, count, -1);
3860 rle = resource_list_find(rl, type, *rid);
3862 panic("pci_alloc_map: unexpectedly can't find resource.");
3864 rle->start = rman_get_start(res);
3865 rle->end = rman_get_end(res);
3868 device_printf(child,
3869 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3870 count, *rid, type, rman_get_start(res));
3871 map = rman_get_start(res);
3873 pci_write_config(child, *rid, map, 4);
3874 if (pci_maprange(testval) == 64)
3875 pci_write_config(child, *rid + 4, map >> 32, 4);
3881 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3882 u_long start, u_long end, u_long count, u_int flags, int cpuid)
3884 struct pci_devinfo *dinfo = device_get_ivars(child);
3885 struct resource_list *rl = &dinfo->resources;
3886 struct resource_list_entry *rle;
3887 pcicfgregs *cfg = &dinfo->cfg;
3890 * Perform lazy resource allocation
3892 if (device_get_parent(child) == dev) {
3896 * Can't alloc legacy interrupt once MSI messages
3897 * have been allocated.
3900 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3901 cfg->msix.msix_alloc > 0))
3905 * If the child device doesn't have an
3906 * interrupt routed and is deserving of an
3907 * interrupt, try to assign it one.
3909 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3911 pci_assign_interrupt(dev, child, 0);
3913 case SYS_RES_IOPORT:
3914 case SYS_RES_MEMORY:
3915 if (*rid < PCIR_BAR(cfg->nummaps)) {
3917 * Enable the I/O mode. We should
3918 * also be assigning resources too
3919 * when none are present. The
3920 * resource_list_alloc kind of sorta does
3923 if (PCI_ENABLE_IO(dev, child, type))
3926 rle = resource_list_find(rl, type, *rid);
3928 return (pci_alloc_map(dev, child, type, rid,
3929 start, end, count, flags));
3933 * If we've already allocated the resource, then
3934 * return it now. But first we may need to activate
3935 * it, since we don't allocate the resource as active
3936 * above. Normally this would be done down in the
3937 * nexus, but since we short-circuit that path we have
3938 * to do its job here. Not sure if we should kfree the
3939 * resource if it fails to activate.
3941 rle = resource_list_find(rl, type, *rid);
3942 if (rle != NULL && rle->res != NULL) {
3944 device_printf(child,
3945 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3946 rman_get_size(rle->res), *rid, type,
3947 rman_get_start(rle->res));
3948 if ((flags & RF_ACTIVE) &&
3949 bus_generic_activate_resource(dev, child, type,
3950 *rid, rle->res) != 0)
3955 return (resource_list_alloc(rl, dev, child, type, rid,
3956 start, end, count, flags, cpuid));
3960 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3962 struct pci_devinfo *dinfo;
3963 struct resource_list *rl;
3964 struct resource_list_entry *rle;
3966 if (device_get_parent(child) != dev)
3969 dinfo = device_get_ivars(child);
3970 rl = &dinfo->resources;
3971 rle = resource_list_find(rl, type, rid);
3974 if (rman_get_device(rle->res) != dev ||
3975 rman_get_flags(rle->res) & RF_ACTIVE) {
3976 device_printf(dev, "delete_resource: "
3977 "Resource still owned by child, oops. "
3978 "(type=%d, rid=%d, addr=%lx)\n",
3979 rle->type, rle->rid,
3980 rman_get_start(rle->res));
3983 bus_release_resource(dev, type, rid, rle->res);
3985 resource_list_delete(rl, type, rid);
3988 * Why do we turn off the PCI configuration BAR when we delete a
3991 pci_write_config(child, rid, 0, 4);
3992 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3995 struct resource_list *
3996 pci_get_resource_list (device_t dev, device_t child)
3998 struct pci_devinfo *dinfo = device_get_ivars(child);
4003 return (&dinfo->resources);
4007 pci_read_config_method(device_t dev, device_t child, int reg, int width)
4009 struct pci_devinfo *dinfo = device_get_ivars(child);
4010 pcicfgregs *cfg = &dinfo->cfg;
4012 return (PCIB_READ_CONFIG(device_get_parent(dev),
4013 cfg->bus, cfg->slot, cfg->func, reg, width));
4017 pci_write_config_method(device_t dev, device_t child, int reg,
4018 uint32_t val, int width)
4020 struct pci_devinfo *dinfo = device_get_ivars(child);
4021 pcicfgregs *cfg = &dinfo->cfg;
4023 PCIB_WRITE_CONFIG(device_get_parent(dev),
4024 cfg->bus, cfg->slot, cfg->func, reg, val, width);
4028 pci_child_location_str_method(device_t dev, device_t child, char *buf,
4032 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
4033 pci_get_function(child));
4038 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
4041 struct pci_devinfo *dinfo;
4044 dinfo = device_get_ivars(child);
4046 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
4047 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
4048 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
4054 pci_assign_interrupt_method(device_t dev, device_t child)
4056 struct pci_devinfo *dinfo = device_get_ivars(child);
4057 pcicfgregs *cfg = &dinfo->cfg;
4059 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
4064 pci_modevent(module_t mod, int what, void *arg)
4066 static struct cdev *pci_cdev;
4070 STAILQ_INIT(&pci_devq);
4072 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
4074 pci_load_vendor_data();
4078 destroy_dev(pci_cdev);
4086 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
4091 * Only do header type 0 devices. Type 1 devices are bridges,
4092 * which we know need special treatment. Type 2 devices are
4093 * cardbus bridges which also require special treatment.
4094 * Other types are unknown, and we err on the side of safety
4097 if (dinfo->cfg.hdrtype != 0)
4101 * Restore the device to full power mode. We must do this
4102 * before we restore the registers because moving from D3 to
4103 * D0 will cause the chip's BARs and some other registers to
4104 * be reset to some unknown power on reset values. Cut down
4105 * the noise on boot by doing nothing if we are already in
4108 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
4109 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4111 for (i = 0; i < dinfo->cfg.nummaps; i++)
4112 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
4113 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
4114 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
4115 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
4116 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
4117 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
4118 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
4119 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
4120 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
4121 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
4122 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
4124 /* Restore MSI and MSI-X configurations if they are present. */
4125 if (dinfo->cfg.msi.msi_location != 0)
4126 pci_resume_msi(dev);
4127 if (dinfo->cfg.msix.msix_location != 0)
4128 pci_resume_msix(dev);
4132 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
4139 * Only do header type 0 devices. Type 1 devices are bridges, which
4140 * we know need special treatment. Type 2 devices are cardbus bridges
4141 * which also require special treatment. Other types are unknown, and
4142 * we err on the side of safety by ignoring them. Powering down
4143 * bridges should not be undertaken lightly.
4145 if (dinfo->cfg.hdrtype != 0)
4147 for (i = 0; i < dinfo->cfg.nummaps; i++)
4148 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
4149 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
4152 * Some drivers apparently write to these registers w/o updating our
4153 * cached copy. No harm happens if we update the copy, so do so here
4154 * so we can restore them. The COMMAND register is modified by the
4155 * bus w/o updating the cache. This should represent the normally
4156 * writable portion of the 'defined' part of type 0 headers. In
4157 * theory we also need to save/restore the PCI capability structures
4158 * we know about, but apart from power we don't know any that are
4161 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
4162 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
4163 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
4164 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
4165 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
4166 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
4167 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
4168 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
4169 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
4170 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
4171 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
4172 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
4173 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
4174 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
4175 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
4178 * don't set the state for display devices, base peripherals and
4179 * memory devices since bad things happen when they are powered down.
4180 * We should (a) have drivers that can easily detach and (b) use
4181 * generic drivers for these devices so that some device actually
4182 * attaches. We need to make sure that when we implement (a) we don't
4183 * power the device down on a reattach.
4185 cls = pci_get_class(dev);
4188 switch (pci_do_power_nodriver)
4190 case 0: /* NO powerdown at all */
4192 case 1: /* Conservative about what to power down */
4193 if (cls == PCIC_STORAGE)
4196 case 2: /* Agressive about what to power down */
4197 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
4198 cls == PCIC_BASEPERIPH)
4201 case 3: /* Power down everything */
4205 * PCI spec says we can only go into D3 state from D0 state.
4206 * Transition from D[12] into D0 before going to D3 state.
4208 ps = pci_get_powerstate(dev);
4209 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
4210 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
4211 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
4212 pci_set_powerstate(dev, PCI_POWERSTATE_D3);
4215 #ifdef COMPAT_OLDPCI
4218 * Locate the parent of a PCI device by scanning the PCI devlist
4219 * and return the entry for the parent.
4220 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
4221 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
4224 pci_devlist_get_parent(pcicfgregs *cfg)
4226 struct devlist *devlist_head;
4227 struct pci_devinfo *dinfo;
4228 pcicfgregs *bridge_cfg;
4231 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
4233 /* If the device is on PCI bus 0, look for the host */
4234 if (cfg->bus == 0) {
4235 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4236 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4237 bridge_cfg = &dinfo->cfg;
4238 if (bridge_cfg->baseclass == PCIC_BRIDGE
4239 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
4240 && bridge_cfg->bus == cfg->bus) {
4246 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
4248 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
4249 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
4250 bridge_cfg = &dinfo->cfg;
4251 if (bridge_cfg->baseclass == PCIC_BRIDGE
4252 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
4253 && bridge_cfg->secondarybus == cfg->bus) {
4262 #endif /* COMPAT_OLDPCI */