sys/bus/firewire/fwohci.c

   1 /*
   2  * Copyright (c) 2003 Hidetoshi Shimokawa
   3  * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the acknowledgement as bellow:
  16  *
  17  *    This product includes software developed by K. Kobayashi and H. Shimokawa
  18  *
  19  * 4. The name of the author may not be used to endorse or promote products
  20  *    derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  30  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  31  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/firewire/fwohci.c,v 1.1.2.19 2003/05/01 06:24:37 simokawa Exp $
  35  * $DragonFly: src/sys/bus/firewire/fwohci.c,v 1.4 2003/08/27 11:42:34 rob Exp $
  36  *
  37  */
  38
  39 #define ATRQ_CH 0
  40 #define ATRS_CH 1
  41 #define ARRQ_CH 2
  42 #define ARRS_CH 3
  43 #define ITX_CH 4
  44 #define IRX_CH 0x24
  45
  46 #include <sys/param.h>
  47 #include <sys/proc.h>
  48 #include <sys/systm.h>
  49 #include <sys/types.h>
  50 #include <sys/mbuf.h>
  51 #include <sys/mman.h>
  52 #include <sys/socket.h>
  53 #include <sys/socketvar.h>
  54 #include <sys/signalvar.h>
  55 #include <sys/malloc.h>
  56 #include <sys/sockio.h>
  57 #include <sys/bus.h>
  58 #include <sys/kernel.h>
  59 #include <sys/conf.h>
  60 #include <sys/endian.h>
  61
  62 #include <machine/bus.h>
  63 #include <machine/resource.h>
  64 #include <sys/rman.h>
  65
  66 #include <machine/cpufunc.h>            /* for rdtsc proto for clock.h below */
  67 #include <machine/clock.h>
  68 #include <bus/pci/pcivar.h>
  69 #include <bus/pci/pcireg.h>
  70
  71 #include "firewire.h"
  72 #include "firewirereg.h"
  73 #include "fwdma.h"
  74 #include "fwohcireg.h"
  75 #include "fwohcivar.h"
  76 #include "firewire_phy.h"
  77
  78 #include "iec68113.h"
  79
  80 #undef OHCI_DEBUG
  81
  82 static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL",
  83                 "STOR","LOAD","NOP ","STOP",};
  84
  85 static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3",
  86                 "UNDEF","REG","SYS","DEV"};
  87 static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"};
  88 char fwohcicode[32][0x20]={
  89         "No stat","Undef","long","miss Ack err",
  90         "underrun","overrun","desc err", "data read err",
  91         "data write err","bus reset","timeout","tcode err",
  92         "Undef","Undef","unknown event","flushed",
  93         "Undef","ack complete","ack pend","Undef",
  94         "ack busy_X","ack busy_A","ack busy_B","Undef",
  95         "Undef","Undef","Undef","ack tardy",
  96         "Undef","ack data_err","ack type_err",""};
  97
  98 #define MAX_SPEED 2
  99 extern char linkspeed[MAX_SPEED+1][0x10];
 100 u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
 101
 102 static struct tcode_info tinfo[] = {
 103 /*              hdr_len block   flag*/
 104 /* 0 WREQQ  */ {16,     FWTI_REQ | FWTI_TLABEL},
 105 /* 1 WREQB  */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
 106 /* 2 WRES   */ {12,     FWTI_RES},
 107 /* 3 XXX    */ { 0,     0},
 108 /* 4 RREQQ  */ {12,     FWTI_REQ | FWTI_TLABEL},
 109 /* 5 RREQB  */ {16,     FWTI_REQ | FWTI_TLABEL},
 110 /* 6 RRESQ  */ {16,     FWTI_RES},
 111 /* 7 RRESB  */ {16,     FWTI_RES | FWTI_BLOCK_ASY},
 112 /* 8 CYCS   */ { 0,     0},
 113 /* 9 LREQ   */ {16,     FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
 114 /* a STREAM */ { 4,     FWTI_REQ | FWTI_BLOCK_STR},
 115 /* b LRES   */ {16,     FWTI_RES | FWTI_BLOCK_ASY},
 116 /* c XXX    */ { 0,     0},
 117 /* d XXX    */ { 0,     0},
 118 /* e PHY    */ {12,     FWTI_REQ},
 119 /* f XXX    */ { 0,     0}
 120 };
 121
 122 #define OHCI_WRITE_SIGMASK 0xffff0000
 123 #define OHCI_READ_SIGMASK 0xffff0000
 124
 125 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
 126 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
 127
 128 static void fwohci_ibr (struct firewire_comm *);
 129 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
 130 static void fwohci_db_free (struct fwohci_dbch *);
 131 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
 132 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
 133 static void fwohci_start_atq (struct firewire_comm *);
 134 static void fwohci_start_ats (struct firewire_comm *);
 135 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
 136 static u_int32_t fwphy_wrdata ( struct fwohci_softc *, u_int32_t, u_int32_t);
 137 static u_int32_t fwphy_rddata ( struct fwohci_softc *, u_int32_t);
 138 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
 139 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
 140 static int fwohci_irx_enable (struct firewire_comm *, int);
 141 static int fwohci_irx_disable (struct firewire_comm *, int);
 142 #if BYTE_ORDER == BIG_ENDIAN
 143 static void fwohci_irx_post (struct firewire_comm *, u_int32_t *);
 144 #endif
 145 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
 146 static int fwohci_itx_disable (struct firewire_comm *, int);
 147 static void fwohci_timeout (void *);
 148 static void fwohci_poll (struct firewire_comm *, int, int);
 149 static void fwohci_set_intr (struct firewire_comm *, int);
 150
 151 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
 152 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
 153 static void     dump_db (struct fwohci_softc *, u_int32_t);
 154 static void     print_db (struct fwohcidb_tr *, volatile struct fwohcidb *, u_int32_t , u_int32_t);
 155 static void     dump_dma (struct fwohci_softc *, u_int32_t);
 156 static u_int32_t fwohci_cyctimer (struct firewire_comm *);
 157 static void fwohci_rbuf_update (struct fwohci_softc *, int);
 158 static void fwohci_tbuf_update (struct fwohci_softc *, int);
 159 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
 160 #if FWOHCI_TASKQUEUE
 161 static void fwohci_complete(void *, int);
 162 #endif
 163
 164 /*
 165  * memory allocated for DMA programs
 166  */
 167 #define DMA_PROG_ALLOC          (8 * PAGE_SIZE)
 168
 169 /* #define NDB 1024 */
 170 #define NDB FWMAXQUEUE
 171 #define NDVDB (DVBUF * NDB)
 172
 173 #define OHCI_VERSION            0x00
 174 #define OHCI_ATRETRY            0x08
 175 #define OHCI_CROMHDR            0x18
 176 #define OHCI_BUS_OPT            0x20
 177 #define OHCI_BUSIRMC            (1 << 31)
 178 #define OHCI_BUSCMC             (1 << 30)
 179 #define OHCI_BUSISC             (1 << 29)
 180 #define OHCI_BUSBMC             (1 << 28)
 181 #define OHCI_BUSPMC             (1 << 27)
 182 #define OHCI_BUSFNC             OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
 183                                 OHCI_BUSBMC | OHCI_BUSPMC
 184
 185 #define OHCI_EUID_HI            0x24
 186 #define OHCI_EUID_LO            0x28
 187
 188 #define OHCI_CROMPTR            0x34
 189 #define OHCI_HCCCTL             0x50
 190 #define OHCI_HCCCTLCLR          0x54
 191 #define OHCI_AREQHI             0x100
 192 #define OHCI_AREQHICLR          0x104
 193 #define OHCI_AREQLO             0x108
 194 #define OHCI_AREQLOCLR          0x10c
 195 #define OHCI_PREQHI             0x110
 196 #define OHCI_PREQHICLR          0x114
 197 #define OHCI_PREQLO             0x118
 198 #define OHCI_PREQLOCLR          0x11c
 199 #define OHCI_PREQUPPER          0x120
 200
 201 #define OHCI_SID_BUF            0x64
 202 #define OHCI_SID_CNT            0x68
 203 #define OHCI_SID_ERR            (1 << 31)
 204 #define OHCI_SID_CNT_MASK       0xffc
 205
 206 #define OHCI_IT_STAT            0x90
 207 #define OHCI_IT_STATCLR         0x94
 208 #define OHCI_IT_MASK            0x98
 209 #define OHCI_IT_MASKCLR         0x9c
 210
 211 #define OHCI_IR_STAT            0xa0
 212 #define OHCI_IR_STATCLR         0xa4
 213 #define OHCI_IR_MASK            0xa8
 214 #define OHCI_IR_MASKCLR         0xac
 215
 216 #define OHCI_LNKCTL             0xe0
 217 #define OHCI_LNKCTLCLR          0xe4
 218
 219 #define OHCI_PHYACCESS          0xec
 220 #define OHCI_CYCLETIMER         0xf0
 221
 222 #define OHCI_DMACTL(off)        (off)
 223 #define OHCI_DMACTLCLR(off)     (off + 4)
 224 #define OHCI_DMACMD(off)        (off + 0xc)
 225 #define OHCI_DMAMATCH(off)      (off + 0x10)
 226
 227 #define OHCI_ATQOFF             0x180
 228 #define OHCI_ATQCTL             OHCI_ATQOFF
 229 #define OHCI_ATQCTLCLR          (OHCI_ATQOFF + 4)
 230 #define OHCI_ATQCMD             (OHCI_ATQOFF + 0xc)
 231 #define OHCI_ATQMATCH           (OHCI_ATQOFF + 0x10)
 232
 233 #define OHCI_ATSOFF             0x1a0
 234 #define OHCI_ATSCTL             OHCI_ATSOFF
 235 #define OHCI_ATSCTLCLR          (OHCI_ATSOFF + 4)
 236 #define OHCI_ATSCMD             (OHCI_ATSOFF + 0xc)
 237 #define OHCI_ATSMATCH           (OHCI_ATSOFF + 0x10)
 238
 239 #define OHCI_ARQOFF             0x1c0
 240 #define OHCI_ARQCTL             OHCI_ARQOFF
 241 #define OHCI_ARQCTLCLR          (OHCI_ARQOFF + 4)
 242 #define OHCI_ARQCMD             (OHCI_ARQOFF + 0xc)
 243 #define OHCI_ARQMATCH           (OHCI_ARQOFF + 0x10)
 244
 245 #define OHCI_ARSOFF             0x1e0
 246 #define OHCI_ARSCTL             OHCI_ARSOFF
 247 #define OHCI_ARSCTLCLR          (OHCI_ARSOFF + 4)
 248 #define OHCI_ARSCMD             (OHCI_ARSOFF + 0xc)
 249 #define OHCI_ARSMATCH           (OHCI_ARSOFF + 0x10)
 250
 251 #define OHCI_ITOFF(CH)          (0x200 + 0x10 * (CH))
 252 #define OHCI_ITCTL(CH)          (OHCI_ITOFF(CH))
 253 #define OHCI_ITCTLCLR(CH)       (OHCI_ITOFF(CH) + 4)
 254 #define OHCI_ITCMD(CH)          (OHCI_ITOFF(CH) + 0xc)
 255
 256 #define OHCI_IROFF(CH)          (0x400 + 0x20 * (CH))
 257 #define OHCI_IRCTL(CH)          (OHCI_IROFF(CH))
 258 #define OHCI_IRCTLCLR(CH)       (OHCI_IROFF(CH) + 4)
 259 #define OHCI_IRCMD(CH)          (OHCI_IROFF(CH) + 0xc)
 260 #define OHCI_IRMATCH(CH)        (OHCI_IROFF(CH) + 0x10)
 261
 262 d_ioctl_t fwohci_ioctl;
 263
 264 /*
 265  * Communication with PHY device
 266  */
 267 static u_int32_t
 268 fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data)
 269 {
 270         u_int32_t fun;
 271
 272         addr &= 0xf;
 273         data &= 0xff;
 274
 275         fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
 276         OWRITE(sc, OHCI_PHYACCESS, fun);
 277         DELAY(100);
 278
 279         return(fwphy_rddata( sc, addr));
 280 }
 281
 282 static u_int32_t
 283 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
 284 {
 285         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 286         int i;
 287         u_int32_t bm;
 288
 289 #define OHCI_CSR_DATA   0x0c
 290 #define OHCI_CSR_COMP   0x10
 291 #define OHCI_CSR_CONT   0x14
 292 #define OHCI_BUS_MANAGER_ID     0
 293
 294         OWRITE(sc, OHCI_CSR_DATA, node);
 295         OWRITE(sc, OHCI_CSR_COMP, 0x3f);
 296         OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
 297         for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
 298                 DELAY(10);
 299         bm = OREAD(sc, OHCI_CSR_DATA);
 300         if((bm & 0x3f) == 0x3f)
 301                 bm = node;
 302         if (bootverbose)
 303                 device_printf(sc->fc.dev,
 304                         "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
 305
 306         return(bm);
 307 }
 308
 309 static u_int32_t
 310 fwphy_rddata(struct fwohci_softc *sc,  u_int addr)
 311 {
 312         u_int32_t fun, stat;
 313         u_int i, retry = 0;
 314
 315         addr &= 0xf;
 316 #define MAX_RETRY 100
 317 again:
 318         OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
 319         fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
 320         OWRITE(sc, OHCI_PHYACCESS, fun);
 321         for ( i = 0 ; i < MAX_RETRY ; i ++ ){
 322                 fun = OREAD(sc, OHCI_PHYACCESS);
 323                 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
 324                         break;
 325                 DELAY(100);
 326         }
 327         if(i >= MAX_RETRY) {
 328                 if (bootverbose)
 329                         device_printf(sc->fc.dev, "phy read failed(1).\n");
 330                 if (++retry < MAX_RETRY) {
 331                         DELAY(100);
 332                         goto again;
 333                 }
 334         }
 335         /* Make sure that SCLK is started */
 336         stat = OREAD(sc, FWOHCI_INTSTAT);
 337         if ((stat & OHCI_INT_REG_FAIL) != 0 ||
 338                         ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
 339                 if (bootverbose)
 340                         device_printf(sc->fc.dev, "phy read failed(2).\n");
 341                 if (++retry < MAX_RETRY) {
 342                         DELAY(100);
 343                         goto again;
 344                 }
 345         }
 346         if (bootverbose || retry >= MAX_RETRY)
 347                 device_printf(sc->fc.dev,
 348                         "fwphy_rddata: loop=%d, retry=%d\n", i, retry);
 349 #undef MAX_RETRY
 350         return((fun >> PHYDEV_RDDATA )& 0xff);
 351 }
 352 /* Device specific ioctl. */
 353 int
 354 fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td)
 355 {
 356         struct firewire_softc *sc;
 357         struct fwohci_softc *fc;
 358         int unit = DEV2UNIT(dev);
 359         int err = 0;
 360         struct fw_reg_req_t *reg  = (struct fw_reg_req_t *) data;
 361         u_int32_t *dmach = (u_int32_t *) data;
 362
 363         sc = devclass_get_softc(firewire_devclass, unit);
 364         if(sc == NULL){
 365                 return(EINVAL);
 366         }
 367         fc = (struct fwohci_softc *)sc->fc;
 368
 369         if (!data)
 370                 return(EINVAL);
 371
 372         switch (cmd) {
 373         case FWOHCI_WRREG:
 374 #define OHCI_MAX_REG 0x800
 375                 if(reg->addr <= OHCI_MAX_REG){
 376                         OWRITE(fc, reg->addr, reg->data);
 377                         reg->data = OREAD(fc, reg->addr);
 378                 }else{
 379                         err = EINVAL;
 380                 }
 381                 break;
 382         case FWOHCI_RDREG:
 383                 if(reg->addr <= OHCI_MAX_REG){
 384                         reg->data = OREAD(fc, reg->addr);
 385                 }else{
 386                         err = EINVAL;
 387                 }
 388                 break;
 389 /* Read DMA descriptors for debug  */
 390         case DUMPDMA:
 391                 if(*dmach <= OHCI_MAX_DMA_CH ){
 392                         dump_dma(fc, *dmach);
 393                         dump_db(fc, *dmach);
 394                 }else{
 395                         err = EINVAL;
 396                 }
 397                 break;
 398         default:
 399                 break;
 400         }
 401         return err;
 402 }
 403
 404 static int
 405 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
 406 {
 407         u_int32_t reg, reg2;
 408         int e1394a = 1;
 409 /*
 410  * probe PHY parameters
 411  * 0. to prove PHY version, whether compliance of 1394a.
 412  * 1. to probe maximum speed supported by the PHY and
 413  *    number of port supported by core-logic.
 414  *    It is not actually available port on your PC .
 415  */
 416         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
 417         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
 418
 419         if((reg >> 5) != 7 ){
 420                 sc->fc.mode &= ~FWPHYASYST;
 421                 sc->fc.nport = reg & FW_PHY_NP;
 422                 sc->fc.speed = reg & FW_PHY_SPD >> 6;
 423                 if (sc->fc.speed > MAX_SPEED) {
 424                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
 425                                 sc->fc.speed, MAX_SPEED);
 426                         sc->fc.speed = MAX_SPEED;
 427                 }
 428                 device_printf(dev,
 429                         "Phy 1394 only %s, %d ports.\n",
 430                         linkspeed[sc->fc.speed], sc->fc.nport);
 431         }else{
 432                 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
 433                 sc->fc.mode |= FWPHYASYST;
 434                 sc->fc.nport = reg & FW_PHY_NP;
 435                 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
 436                 if (sc->fc.speed > MAX_SPEED) {
 437                         device_printf(dev, "invalid speed %d (fixed to %d).\n",
 438                                 sc->fc.speed, MAX_SPEED);
 439                         sc->fc.speed = MAX_SPEED;
 440                 }
 441                 device_printf(dev,
 442                         "Phy 1394a available %s, %d ports.\n",
 443                         linkspeed[sc->fc.speed], sc->fc.nport);
 444
 445                 /* check programPhyEnable */
 446                 reg2 = fwphy_rddata(sc, 5);
 447 #if 0
 448                 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
 449 #else   /* XXX force to enable 1394a */
 450                 if (e1394a) {
 451 #endif
 452                         if (bootverbose)
 453                                 device_printf(dev,
 454                                         "Enable 1394a Enhancements\n");
 455                         /* enable EAA EMC */
 456                         reg2 |= 0x03;
 457                         /* set aPhyEnhanceEnable */
 458                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
 459                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
 460                 } else {
 461                         /* for safe */
 462                         reg2 &= ~0x83;
 463                 }
 464                 reg2 = fwphy_wrdata(sc, 5, reg2);
 465         }
 466
 467         reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
 468         if((reg >> 5) == 7 ){
 469                 reg = fwphy_rddata(sc, 4);
 470                 reg |= 1 << 6;
 471                 fwphy_wrdata(sc, 4, reg);
 472                 reg = fwphy_rddata(sc, 4);
 473         }
 474         return 0;
 475 }
 476
 477
 478 void
 479 fwohci_reset(struct fwohci_softc *sc, device_t dev)
 480 {
 481         int i, max_rec, speed;
 482         u_int32_t reg, reg2;
 483         struct fwohcidb_tr *db_tr;
 484
 485         /* Disable interrupt */
 486         OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
 487
 488         /* Now stopping all DMA channel */
 489         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
 490         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
 491         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
 492         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
 493
 494         OWRITE(sc,  OHCI_IR_MASKCLR, ~0);
 495         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 496                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
 497                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
 498         }
 499
 500         /* FLUSH FIFO and reset Transmitter/Reciever */
 501         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
 502         if (bootverbose)
 503                 device_printf(dev, "resetting OHCI...");
 504         i = 0;
 505         while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
 506                 if (i++ > 100) break;
 507                 DELAY(1000);
 508         }
 509         if (bootverbose)
 510                 printf("done (loop=%d)\n", i);
 511
 512         /* Probe phy */
 513         fwohci_probe_phy(sc, dev);
 514
 515         /* Probe link */
 516         reg = OREAD(sc,  OHCI_BUS_OPT);
 517         reg2 = reg | OHCI_BUSFNC;
 518         max_rec = (reg & 0x0000f000) >> 12;
 519         speed = (reg & 0x00000007);
 520         device_printf(dev, "Link %s, max_rec %d bytes.\n",
 521                         linkspeed[speed], MAXREC(max_rec));
 522         /* XXX fix max_rec */
 523         sc->fc.maxrec = sc->fc.speed + 8;
 524         if (max_rec != sc->fc.maxrec) {
 525                 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
 526                 device_printf(dev, "max_rec %d -> %d\n",
 527                                 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
 528         }
 529         if (bootverbose)
 530                 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
 531         OWRITE(sc,  OHCI_BUS_OPT, reg2);
 532
 533         /* Initialize registers */
 534         OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
 535         OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
 536         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
 537         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
 538         OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
 539         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
 540         fw_busreset(&sc->fc);
 541
 542         /* Enable link */
 543         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
 544
 545         /* Force to start async RX DMA */
 546         sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
 547         sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
 548         fwohci_rx_enable(sc, &sc->arrq);
 549         fwohci_rx_enable(sc, &sc->arrs);
 550
 551         /* Initialize async TX */
 552         OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
 553         OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
 554         /* AT Retries */
 555         OWRITE(sc, FWOHCI_RETRY,
 556                 /* CycleLimit   PhyRespRetries ATRespRetries ATReqRetries */
 557                 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
 558         for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
 559                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
 560                 db_tr->xfer = NULL;
 561         }
 562         for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
 563                                 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
 564                 db_tr->xfer = NULL;
 565         }
 566
 567
 568         /* Enable interrupt */
 569         OWRITE(sc, FWOHCI_INTMASK,
 570                         OHCI_INT_ERR  | OHCI_INT_PHY_SID
 571                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
 572                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
 573                         | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
 574         fwohci_set_intr(&sc->fc, 1);
 575
 576 }
 577
 578 int
 579 fwohci_init(struct fwohci_softc *sc, device_t dev)
 580 {
 581         int i;
 582         u_int32_t reg;
 583         u_int8_t ui[8];
 584
 585 #if FWOHCI_TASKQUEUE
 586         TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
 587 #endif
 588
 589         reg = OREAD(sc, OHCI_VERSION);
 590         device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
 591                         (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1);
 592
 593 /* Available Isochrounous DMA channel probe */
 594         OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
 595         OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
 596         reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
 597         OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
 598         OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
 599         for (i = 0; i < 0x20; i++)
 600                 if ((reg & (1 << i)) == 0)
 601                         break;
 602         sc->fc.nisodma = i;
 603         device_printf(dev, "No. of Isochronous channel is %d.\n", i);
 604
 605         sc->fc.arq = &sc->arrq.xferq;
 606         sc->fc.ars = &sc->arrs.xferq;
 607         sc->fc.atq = &sc->atrq.xferq;
 608         sc->fc.ats = &sc->atrs.xferq;
 609
 610         sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 611         sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 612         sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 613         sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
 614
 615         sc->arrq.xferq.start = NULL;
 616         sc->arrs.xferq.start = NULL;
 617         sc->atrq.xferq.start = fwohci_start_atq;
 618         sc->atrs.xferq.start = fwohci_start_ats;
 619
 620         sc->arrq.xferq.buf = NULL;
 621         sc->arrs.xferq.buf = NULL;
 622         sc->atrq.xferq.buf = NULL;
 623         sc->atrs.xferq.buf = NULL;
 624
 625         sc->arrq.ndesc = 1;
 626         sc->arrs.ndesc = 1;
 627         sc->atrq.ndesc = 8;     /* equal to maximum of mbuf chains */
 628         sc->atrs.ndesc = 2;
 629
 630         sc->arrq.ndb = NDB;
 631         sc->arrs.ndb = NDB / 2;
 632         sc->atrq.ndb = NDB;
 633         sc->atrs.ndb = NDB / 2;
 634
 635         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 636                 sc->fc.it[i] = &sc->it[i].xferq;
 637                 sc->fc.ir[i] = &sc->ir[i].xferq;
 638                 sc->it[i].ndb = 0;
 639                 sc->ir[i].ndb = 0;
 640         }
 641
 642         sc->fc.tcode = tinfo;
 643         sc->fc.dev = dev;
 644
 645         sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
 646                                                 &sc->crom_dma, BUS_DMA_WAITOK);
 647         if(sc->fc.config_rom == NULL){
 648                 device_printf(dev, "config_rom alloc failed.");
 649                 return ENOMEM;
 650         }
 651
 652 #if 1
 653         sc->fc.config_rom[1] = 0x31333934;
 654         sc->fc.config_rom[2] = 0xf000a002;
 655         sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
 656         sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
 657         sc->fc.config_rom[5] = 0;
 658         sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
 659
 660         sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
 661 #endif
 662
 663
 664 /* SID recieve buffer must allign 2^11 */
 665 #define OHCI_SIDSIZE    (1 << 11)
 666         sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
 667                                                 &sc->sid_dma, BUS_DMA_WAITOK);
 668         if (sc->sid_buf == NULL) {
 669                 device_printf(dev, "sid_buf alloc failed.");
 670                 return ENOMEM;
 671         }
 672
 673         fwdma_malloc(&sc->fc, sizeof(u_int32_t), sizeof(u_int32_t),
 674                                         &sc->dummy_dma, BUS_DMA_WAITOK);
 675
 676         if (sc->dummy_dma.v_addr == NULL) {
 677                 device_printf(dev, "dummy_dma alloc failed.");
 678                 return ENOMEM;
 679         }
 680
 681         fwohci_db_init(sc, &sc->arrq);
 682         if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
 683                 return ENOMEM;
 684
 685         fwohci_db_init(sc, &sc->arrs);
 686         if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
 687                 return ENOMEM;
 688
 689         fwohci_db_init(sc, &sc->atrq);
 690         if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
 691                 return ENOMEM;
 692
 693         fwohci_db_init(sc, &sc->atrs);
 694         if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
 695                 return ENOMEM;
 696
 697         sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
 698         sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
 699         for( i = 0 ; i < 8 ; i ++)
 700                 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
 701         device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
 702                 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
 703
 704         sc->fc.ioctl = fwohci_ioctl;
 705         sc->fc.cyctimer = fwohci_cyctimer;
 706         sc->fc.set_bmr = fwohci_set_bus_manager;
 707         sc->fc.ibr = fwohci_ibr;
 708         sc->fc.irx_enable = fwohci_irx_enable;
 709         sc->fc.irx_disable = fwohci_irx_disable;
 710
 711         sc->fc.itx_enable = fwohci_itxbuf_enable;
 712         sc->fc.itx_disable = fwohci_itx_disable;
 713 #if BYTE_ORDER == BIG_ENDIAN
 714         sc->fc.irx_post = fwohci_irx_post;
 715 #else
 716         sc->fc.irx_post = NULL;
 717 #endif
 718         sc->fc.itx_post = NULL;
 719         sc->fc.timeout = fwohci_timeout;
 720         sc->fc.poll = fwohci_poll;
 721         sc->fc.set_intr = fwohci_set_intr;
 722
 723         sc->intmask = sc->irstat = sc->itstat = 0;
 724
 725         fw_init(&sc->fc);
 726         fwohci_reset(sc, dev);
 727
 728         return 0;
 729 }
 730
 731 void
 732 fwohci_timeout(void *arg)
 733 {
 734         struct fwohci_softc *sc;
 735
 736         sc = (struct fwohci_softc *)arg;
 737 }
 738
 739 u_int32_t
 740 fwohci_cyctimer(struct firewire_comm *fc)
 741 {
 742         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 743         return(OREAD(sc, OHCI_CYCLETIMER));
 744 }
 745
 746 int
 747 fwohci_detach(struct fwohci_softc *sc, device_t dev)
 748 {
 749         int i;
 750
 751         if (sc->sid_buf != NULL)
 752                 fwdma_free(&sc->fc, &sc->sid_dma);
 753         if (sc->fc.config_rom != NULL)
 754                 fwdma_free(&sc->fc, &sc->crom_dma);
 755
 756         fwohci_db_free(&sc->arrq);
 757         fwohci_db_free(&sc->arrs);
 758
 759         fwohci_db_free(&sc->atrq);
 760         fwohci_db_free(&sc->atrs);
 761
 762         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
 763                 fwohci_db_free(&sc->it[i]);
 764                 fwohci_db_free(&sc->ir[i]);
 765         }
 766
 767         return 0;
 768 }
 769
 770 #define LAST_DB(dbtr, db) do {                                          \
 771         struct fwohcidb_tr *_dbtr = (dbtr);                             \
 772         int _cnt = _dbtr->dbcnt;                                        \
 773         db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0];                   \
 774 } while (0)
 775
 776 static void
 777 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 778 {
 779         struct fwohcidb_tr *db_tr;
 780         volatile struct fwohcidb *db;
 781         bus_dma_segment_t *s;
 782         int i;
 783
 784         db_tr = (struct fwohcidb_tr *)arg;
 785         db = &db_tr->db[db_tr->dbcnt];
 786         if (error) {
 787                 if (firewire_debug || error != EFBIG)
 788                         printf("fwohci_execute_db: error=%d\n", error);
 789                 return;
 790         }
 791         for (i = 0; i < nseg; i++) {
 792                 s = &segs[i];
 793                 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
 794                 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
 795                 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
 796                 db++;
 797                 db_tr->dbcnt++;
 798         }
 799 }
 800
 801 static void
 802 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
 803                                                 bus_size_t size, int error)
 804 {
 805         fwohci_execute_db(arg, segs, nseg, error);
 806 }
 807
 808 static void
 809 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
 810 {
 811         int i, s;
 812         int tcode, hdr_len, pl_off, pl_len;
 813         int fsegment = -1;
 814         u_int32_t off;
 815         struct fw_xfer *xfer;
 816         struct fw_pkt *fp;
 817         volatile struct fwohci_txpkthdr *ohcifp;
 818         struct fwohcidb_tr *db_tr;
 819         volatile struct fwohcidb *db;
 820         struct tcode_info *info;
 821         static int maxdesc=0;
 822
 823         if(&sc->atrq == dbch){
 824                 off = OHCI_ATQOFF;
 825         }else if(&sc->atrs == dbch){
 826                 off = OHCI_ATSOFF;
 827         }else{
 828                 return;
 829         }
 830
 831         if (dbch->flags & FWOHCI_DBCH_FULL)
 832                 return;
 833
 834         s = splfw();
 835         db_tr = dbch->top;
 836 txloop:
 837         xfer = STAILQ_FIRST(&dbch->xferq.q);
 838         if(xfer == NULL){
 839                 goto kick;
 840         }
 841         if(dbch->xferq.queued == 0 ){
 842                 device_printf(sc->fc.dev, "TX queue empty\n");
 843         }
 844         STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
 845         db_tr->xfer = xfer;
 846         xfer->state = FWXF_START;
 847
 848         fp = (struct fw_pkt *)xfer->send.buf;
 849         tcode = fp->mode.common.tcode;
 850
 851         ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
 852         info = &tinfo[tcode];
 853         hdr_len = pl_off = info->hdr_len;
 854         for( i = 0 ; i < pl_off ; i+= 4){
 855                 ohcifp->mode.ld[i/4] = fp->mode.ld[i/4];
 856         }
 857         ohcifp->mode.common.spd = xfer->spd;
 858         if (tcode == FWTCODE_STREAM ){
 859                 hdr_len = 8;
 860                 ohcifp->mode.stream.len = fp->mode.stream.len;
 861         } else if (tcode == FWTCODE_PHY) {
 862                 hdr_len = 12;
 863                 ohcifp->mode.ld[1] = fp->mode.ld[1];
 864                 ohcifp->mode.ld[2] = fp->mode.ld[2];
 865                 ohcifp->mode.common.spd = 0;
 866                 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
 867         } else {
 868                 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
 869                 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
 870                 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
 871         }
 872         db = &db_tr->db[0];
 873         FWOHCI_DMA_WRITE(db->db.desc.cmd,
 874                         OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
 875         FWOHCI_DMA_WRITE(db->db.desc.res, 0);
 876 /* Specify bound timer of asy. responce */
 877         if(&sc->atrs == dbch){
 878                 FWOHCI_DMA_WRITE(db->db.desc.res,
 879                          (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
 880         }
 881 #if BYTE_ORDER == BIG_ENDIAN
 882         if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
 883                 hdr_len = 12;
 884         for (i = 0; i < hdr_len/4; i ++)
 885                 FWOHCI_DMA_WRITE(ohcifp->mode.ld[i], ohcifp->mode.ld[i]);
 886 #endif
 887
 888 again:
 889         db_tr->dbcnt = 2;
 890         db = &db_tr->db[db_tr->dbcnt];
 891         pl_len = xfer->send.len - pl_off;
 892         if (pl_len > 0) {
 893                 int err;
 894                 /* handle payload */
 895                 if (xfer->mbuf == NULL) {
 896                         caddr_t pl_addr;
 897
 898                         pl_addr = xfer->send.buf + pl_off;
 899                         err = bus_dmamap_load(dbch->dmat, db_tr->dma_map,
 900                                 pl_addr, pl_len,
 901                                 fwohci_execute_db, db_tr,
 902                                 /*flags*/0);
 903                 } else {
 904                         /* XXX we can handle only 6 (=8-2) mbuf chains */
 905                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
 906                                 xfer->mbuf,
 907                                 fwohci_execute_db2, db_tr,
 908                                 /* flags */0);
 909                         if (err == EFBIG) {
 910                                 struct mbuf *m0;
 911
 912                                 if (firewire_debug)
 913                                         device_printf(sc->fc.dev, "EFBIG.\n");
 914                                 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 915                                 if (m0 != NULL) {
 916                                         m_copydata(xfer->mbuf, 0,
 917                                                 xfer->mbuf->m_pkthdr.len,
 918                                                 mtod(m0, caddr_t));
 919                                         m0->m_len = m0->m_pkthdr.len =
 920                                                 xfer->mbuf->m_pkthdr.len;
 921                                         m_freem(xfer->mbuf);
 922                                         xfer->mbuf = m0;
 923                                         goto again;
 924                                 }
 925                                 device_printf(sc->fc.dev, "m_getcl failed.\n");
 926                         }
 927                 }
 928                 if (err)
 929                         printf("dmamap_load: err=%d\n", err);
 930                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
 931                                                 BUS_DMASYNC_PREWRITE);
 932 #if 0 /* OHCI_OUTPUT_MODE == 0 */
 933                 for (i = 2; i < db_tr->dbcnt; i++)
 934                         FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
 935                                                 OHCI_OUTPUT_MORE);
 936 #endif
 937         }
 938         if (maxdesc < db_tr->dbcnt) {
 939                 maxdesc = db_tr->dbcnt;
 940                 if (bootverbose)
 941                         device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
 942         }
 943         /* last db */
 944         LAST_DB(db_tr, db);
 945         FWOHCI_DMA_SET(db->db.desc.cmd,
 946                 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
 947         FWOHCI_DMA_WRITE(db->db.desc.depend,
 948                         STAILQ_NEXT(db_tr, link)->bus_addr);
 949
 950         if(fsegment == -1 )
 951                 fsegment = db_tr->dbcnt;
 952         if (dbch->pdb_tr != NULL) {
 953                 LAST_DB(dbch->pdb_tr, db);
 954                 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
 955         }
 956         dbch->pdb_tr = db_tr;
 957         db_tr = STAILQ_NEXT(db_tr, link);
 958         if(db_tr != dbch->bottom){
 959                 goto txloop;
 960         } else {
 961                 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
 962                 dbch->flags |= FWOHCI_DBCH_FULL;
 963         }
 964 kick:
 965         /* kick asy q */
 966         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
 967         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
 968
 969         if(dbch->xferq.flag & FWXFERQ_RUNNING) {
 970                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
 971         } else {
 972                 if (bootverbose)
 973                         device_printf(sc->fc.dev, "start AT DMA status=%x\n",
 974                                         OREAD(sc, OHCI_DMACTL(off)));
 975                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
 976                 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
 977                 dbch->xferq.flag |= FWXFERQ_RUNNING;
 978         }
 979
 980         dbch->top = db_tr;
 981         splx(s);
 982         return;
 983 }
 984
 985 static void
 986 fwohci_start_atq(struct firewire_comm *fc)
 987 {
 988         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 989         fwohci_start( sc, &(sc->atrq));
 990         return;
 991 }
 992
 993 static void
 994 fwohci_start_ats(struct firewire_comm *fc)
 995 {
 996         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
 997         fwohci_start( sc, &(sc->atrs));
 998         return;
 999 }
1000
1001 void
1002 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1003 {
1004         int s, ch, err = 0;
1005         struct fwohcidb_tr *tr;
1006         volatile struct fwohcidb *db;
1007         struct fw_xfer *xfer;
1008         u_int32_t off;
1009         u_int stat, status;
1010         int     packets;
1011         struct firewire_comm *fc = (struct firewire_comm *)sc;
1012
1013         if(&sc->atrq == dbch){
1014                 off = OHCI_ATQOFF;
1015                 ch = ATRQ_CH;
1016         }else if(&sc->atrs == dbch){
1017                 off = OHCI_ATSOFF;
1018                 ch = ATRS_CH;
1019         }else{
1020                 return;
1021         }
1022         s = splfw();
1023         tr = dbch->bottom;
1024         packets = 0;
1025         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
1026         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
1027         while(dbch->xferq.queued > 0){
1028                 LAST_DB(tr, db);
1029                 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1030                 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1031                         if (fc->status != FWBUSRESET)
1032                                 /* maybe out of order?? */
1033                                 goto out;
1034                 }
1035                 bus_dmamap_sync(dbch->dmat, tr->dma_map,
1036                         BUS_DMASYNC_POSTWRITE);
1037                 bus_dmamap_unload(dbch->dmat, tr->dma_map);
1038 #if 0
1039                 dump_db(sc, ch);
1040 #endif
1041                 if(status & OHCI_CNTL_DMA_DEAD) {
1042                         /* Stop DMA */
1043                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1044                         device_printf(sc->fc.dev, "force reset AT FIFO\n");
1045                         OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1046                         OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1047                         OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1048                 }
1049                 stat = status & FWOHCIEV_MASK;
1050                 switch(stat){
1051                 case FWOHCIEV_ACKPEND:
1052                 case FWOHCIEV_ACKCOMPL:
1053                         err = 0;
1054                         break;
1055                 case FWOHCIEV_ACKBSA:
1056                 case FWOHCIEV_ACKBSB:
1057                 case FWOHCIEV_ACKBSX:
1058                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1059                         err = EBUSY;
1060                         break;
1061                 case FWOHCIEV_FLUSHED:
1062                 case FWOHCIEV_ACKTARD:
1063                         device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1064                         err = EAGAIN;
1065                         break;
1066                 case FWOHCIEV_MISSACK:
1067                 case FWOHCIEV_UNDRRUN:
1068                 case FWOHCIEV_OVRRUN:
1069                 case FWOHCIEV_DESCERR:
1070                 case FWOHCIEV_DTRDERR:
1071                 case FWOHCIEV_TIMEOUT:
1072                 case FWOHCIEV_TCODERR:
1073                 case FWOHCIEV_UNKNOWN:
1074                 case FWOHCIEV_ACKDERR:
1075                 case FWOHCIEV_ACKTERR:
1076                 default:
1077                         device_printf(sc->fc.dev, "txd err=%2x %s\n",
1078                                                         stat, fwohcicode[stat]);
1079                         err = EINVAL;
1080                         break;
1081                 }
1082                 if (tr->xfer != NULL) {
1083                         xfer = tr->xfer;
1084                         if (xfer->state == FWXF_RCVD) {
1085                                 if (firewire_debug)
1086                                         printf("already rcvd\n");
1087                                 fw_xfer_done(xfer);
1088                         } else {
1089                                 xfer->state = FWXF_SENT;
1090                                 if (err == EBUSY && fc->status != FWBUSRESET) {
1091                                         xfer->state = FWXF_BUSY;
1092                                         xfer->resp = err;
1093                                         if (xfer->retry_req != NULL)
1094                                                 xfer->retry_req(xfer);
1095                                         else {
1096                                                 xfer->recv.len = 0;
1097                                                 fw_xfer_done(xfer);
1098                                         }
1099                                 } else if (stat != FWOHCIEV_ACKPEND) {
1100                                         if (stat != FWOHCIEV_ACKCOMPL)
1101                                                 xfer->state = FWXF_SENTERR;
1102                                         xfer->resp = err;
1103                                         xfer->recv.len = 0;
1104                                         fw_xfer_done(xfer);
1105                                 }
1106                         }
1107                         /*
1108                          * The watchdog timer takes care of split
1109                          * transcation timeout for ACKPEND case.
1110                          */
1111                 } else {
1112                         printf("this shouldn't happen\n");
1113                 }
1114                 dbch->xferq.queued --;
1115                 tr->xfer = NULL;
1116
1117                 packets ++;
1118                 tr = STAILQ_NEXT(tr, link);
1119                 dbch->bottom = tr;
1120                 if (dbch->bottom == dbch->top) {
1121                         /* we reaches the end of context program */
1122                         if (firewire_debug && dbch->xferq.queued > 0)
1123                                 printf("queued > 0\n");
1124                         break;
1125                 }
1126         }
1127 out:
1128         if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1129                 printf("make free slot\n");
1130                 dbch->flags &= ~FWOHCI_DBCH_FULL;
1131                 fwohci_start(sc, dbch);
1132         }
1133         splx(s);
1134 }
1135
1136 static void
1137 fwohci_db_free(struct fwohci_dbch *dbch)
1138 {
1139         struct fwohcidb_tr *db_tr;
1140         int idb;
1141
1142         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1143                 return;
1144
1145         for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1146                         db_tr = STAILQ_NEXT(db_tr, link), idb++){
1147                 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1148                                         db_tr->buf != NULL) {
1149                         fwdma_free_size(dbch->dmat, db_tr->dma_map,
1150                                         db_tr->buf, dbch->xferq.psize);
1151                         db_tr->buf = NULL;
1152                 } else if (db_tr->dma_map != NULL)
1153                         bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1154         }
1155         dbch->ndb = 0;
1156         db_tr = STAILQ_FIRST(&dbch->db_trq);
1157         fwdma_free_multiseg(dbch->am);
1158         free(db_tr, M_FW);
1159         STAILQ_INIT(&dbch->db_trq);
1160         dbch->flags &= ~FWOHCI_DBCH_INIT;
1161 }
1162
1163 static void
1164 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1165 {
1166         int     idb;
1167         struct fwohcidb_tr *db_tr;
1168
1169         if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1170                 goto out;
1171
1172         /* create dma_tag for buffers */
1173 #define MAX_REQCOUNT    0xffff
1174         if (bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1175                         /*alignment*/ 1, /*boundary*/ 0,
1176                         /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1177                         /*highaddr*/ BUS_SPACE_MAXADDR,
1178                         /*filter*/NULL, /*filterarg*/NULL,
1179                         /*maxsize*/ dbch->xferq.psize,
1180                         /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1181                         /*maxsegsz*/ MAX_REQCOUNT,
1182                         /*flags*/ 0, &dbch->dmat))
1183                 return;
1184
1185         /* allocate DB entries and attach one to each DMA channels */
1186         /* DB entry must start at 16 bytes bounary. */
1187         STAILQ_INIT(&dbch->db_trq);
1188         db_tr = (struct fwohcidb_tr *)
1189                 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1190                 M_FW, M_WAITOK | M_ZERO);
1191         if(db_tr == NULL){
1192                 printf("fwohci_db_init: malloc(1) failed\n");
1193                 return;
1194         }
1195
1196 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1197         dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1198                 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK);
1199         if (dbch->am == NULL) {
1200                 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1201                 return;
1202         }
1203         /* Attach DB to DMA ch. */
1204         for(idb = 0 ; idb < dbch->ndb ; idb++){
1205                 db_tr->dbcnt = 0;
1206                 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1207                 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1208                 /* create dmamap for buffers */
1209                 /* XXX do we need 4bytes alignment tag? */
1210                 /* XXX don't alloc dma_map for AR */
1211                 if (bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1212                         printf("bus_dmamap_create failed\n");
1213                         dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1214                         fwohci_db_free(dbch);
1215                         return;
1216                 }
1217                 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1218                 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1219                         if (idb % dbch->xferq.bnpacket == 0)
1220                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1221                                                 ].start = (caddr_t)db_tr;
1222                         if ((idb + 1) % dbch->xferq.bnpacket == 0)
1223                                 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1224                                                 ].end = (caddr_t)db_tr;
1225                 }
1226                 db_tr++;
1227         }
1228         STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1229                         = STAILQ_FIRST(&dbch->db_trq);
1230 out:
1231         dbch->xferq.queued = 0;
1232         dbch->pdb_tr = NULL;
1233         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1234         dbch->bottom = dbch->top;
1235         dbch->flags = FWOHCI_DBCH_INIT;
1236 }
1237
1238 static int
1239 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1240 {
1241         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1242         int sleepch;
1243
1244         OWRITE(sc, OHCI_ITCTLCLR(dmach),
1245                         OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1246         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1247         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1248         /* XXX we cannot free buffers until the DMA really stops */
1249         tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1250         fwohci_db_free(&sc->it[dmach]);
1251         sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1252         return 0;
1253 }
1254
1255 static int
1256 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1257 {
1258         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1259         int sleepch;
1260
1261         OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1262         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1263         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1264         /* XXX we cannot free buffers until the DMA really stops */
1265         tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1266         fwohci_db_free(&sc->ir[dmach]);
1267         sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1268         return 0;
1269 }
1270
1271 #if BYTE_ORDER == BIG_ENDIAN
1272 static void
1273 fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld)
1274 {
1275         qld[0] = FWOHCI_DMA_READ(qld[0]);
1276         return;
1277 }
1278 #endif
1279
1280 static int
1281 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1282 {
1283         int err = 0;
1284         int idb, z, i, dmach = 0, ldesc;
1285         u_int32_t off = NULL;
1286         struct fwohcidb_tr *db_tr;
1287         volatile struct fwohcidb *db;
1288
1289         if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1290                 err = EINVAL;
1291                 return err;
1292         }
1293         z = dbch->ndesc;
1294         for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1295                 if( &sc->it[dmach] == dbch){
1296                         off = OHCI_ITOFF(dmach);
1297                         break;
1298                 }
1299         }
1300         if(off == NULL){
1301                 err = EINVAL;
1302                 return err;
1303         }
1304         if(dbch->xferq.flag & FWXFERQ_RUNNING)
1305                 return err;
1306         dbch->xferq.flag |= FWXFERQ_RUNNING;
1307         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1308                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1309         }
1310         db_tr = dbch->top;
1311         for (idb = 0; idb < dbch->ndb; idb ++) {
1312                 fwohci_add_tx_buf(dbch, db_tr, idb);
1313                 if(STAILQ_NEXT(db_tr, link) == NULL){
1314                         break;
1315                 }
1316                 db = db_tr->db;
1317                 ldesc = db_tr->dbcnt - 1;
1318                 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1319                                 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1320                 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1321                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1322                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1323                                 FWOHCI_DMA_SET(
1324                                         db[ldesc].db.desc.cmd,
1325                                         OHCI_INTERRUPT_ALWAYS);
1326                                 /* OHCI 1.1 and above */
1327                                 FWOHCI_DMA_SET(
1328                                         db[0].db.desc.cmd,
1329                                         OHCI_INTERRUPT_ALWAYS);
1330                         }
1331                 }
1332                 db_tr = STAILQ_NEXT(db_tr, link);
1333         }
1334         FWOHCI_DMA_CLEAR(
1335                 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1336         return err;
1337 }
1338
1339 static int
1340 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1341 {
1342         int err = 0;
1343         int idb, z, i, dmach = 0, ldesc;
1344         u_int32_t off = NULL;
1345         struct fwohcidb_tr *db_tr;
1346         volatile struct fwohcidb *db;
1347
1348         z = dbch->ndesc;
1349         if(&sc->arrq == dbch){
1350                 off = OHCI_ARQOFF;
1351         }else if(&sc->arrs == dbch){
1352                 off = OHCI_ARSOFF;
1353         }else{
1354                 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1355                         if( &sc->ir[dmach] == dbch){
1356                                 off = OHCI_IROFF(dmach);
1357                                 break;
1358                         }
1359                 }
1360         }
1361         if(off == NULL){
1362                 err = EINVAL;
1363                 return err;
1364         }
1365         if(dbch->xferq.flag & FWXFERQ_STREAM){
1366                 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1367                         return err;
1368         }else{
1369                 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1370                         err = EBUSY;
1371                         return err;
1372                 }
1373         }
1374         dbch->xferq.flag |= FWXFERQ_RUNNING;
1375         dbch->top = STAILQ_FIRST(&dbch->db_trq);
1376         for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1377                 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1378         }
1379         db_tr = dbch->top;
1380         for (idb = 0; idb < dbch->ndb; idb ++) {
1381                 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1382                 if (STAILQ_NEXT(db_tr, link) == NULL)
1383                         break;
1384                 db = db_tr->db;
1385                 ldesc = db_tr->dbcnt - 1;
1386                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1387                         STAILQ_NEXT(db_tr, link)->bus_addr | z);
1388                 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1389                         if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1390                                 FWOHCI_DMA_SET(
1391                                         db[ldesc].db.desc.cmd,
1392                                         OHCI_INTERRUPT_ALWAYS);
1393                                 FWOHCI_DMA_CLEAR(
1394                                         db[ldesc].db.desc.depend,
1395                                         0xf);
1396                         }
1397                 }
1398                 db_tr = STAILQ_NEXT(db_tr, link);
1399         }
1400         FWOHCI_DMA_CLEAR(
1401                 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1402         dbch->buf_offset = 0;
1403         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1404         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1405         if(dbch->xferq.flag & FWXFERQ_STREAM){
1406                 return err;
1407         }else{
1408                 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1409         }
1410         OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1411         return err;
1412 }
1413
1414 static int
1415 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1416 {
1417         int sec, cycle, cycle_match;
1418
1419         cycle = cycle_now & 0x1fff;
1420         sec = cycle_now >> 13;
1421 #define CYCLE_MOD       0x10
1422 #if 1
1423 #define CYCLE_DELAY     8       /* min delay to start DMA */
1424 #else
1425 #define CYCLE_DELAY     7000    /* min delay to start DMA */
1426 #endif
1427         cycle = cycle + CYCLE_DELAY;
1428         if (cycle >= 8000) {
1429                 sec ++;
1430                 cycle -= 8000;
1431         }
1432         cycle = roundup2(cycle, CYCLE_MOD);
1433         if (cycle >= 8000) {
1434                 sec ++;
1435                 if (cycle == 8000)
1436                         cycle = 0;
1437                 else
1438                         cycle = CYCLE_MOD;
1439         }
1440         cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1441
1442         return(cycle_match);
1443 }
1444
1445 static int
1446 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1447 {
1448         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1449         int err = 0;
1450         unsigned short tag, ich;
1451         struct fwohci_dbch *dbch;
1452         int cycle_match, cycle_now, s, ldesc;
1453         u_int32_t stat;
1454         struct fw_bulkxfer *first, *chunk, *prev;
1455         struct fw_xferq *it;
1456
1457         dbch = &sc->it[dmach];
1458         it = &dbch->xferq;
1459
1460         tag = (it->flag >> 6) & 3;
1461         ich = it->flag & 0x3f;
1462         if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1463                 dbch->ndb = it->bnpacket * it->bnchunk;
1464                 dbch->ndesc = 3;
1465                 fwohci_db_init(sc, dbch);
1466                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1467                         return ENOMEM;
1468                 err = fwohci_tx_enable(sc, dbch);
1469         }
1470         if(err)
1471                 return err;
1472
1473         ldesc = dbch->ndesc - 1;
1474         s = splfw();
1475         prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1476         while  ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1477                 volatile struct fwohcidb *db;
1478
1479                 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1480                                         BUS_DMASYNC_PREWRITE);
1481                 fwohci_txbufdb(sc, dmach, chunk);
1482                 if (prev != NULL) {
1483                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1484 #if 0 /* XXX necessary? */
1485                         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1486                                                 OHCI_BRANCH_ALWAYS);
1487 #endif
1488 #if 0 /* if bulkxfer->npacket changes */
1489                         db[ldesc].db.desc.depend = db[0].db.desc.depend =
1490                                 ((struct fwohcidb_tr *)
1491                                 (chunk->start))->bus_addr | dbch->ndesc;
1492 #else
1493                         FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1494                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1495 #endif
1496                 }
1497                 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1498                 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1499                 prev = chunk;
1500         }
1501         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1502         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1503         splx(s);
1504         stat = OREAD(sc, OHCI_ITCTL(dmach));
1505         if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1506                 printf("stat 0x%x\n", stat);
1507
1508         if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1509                 return 0;
1510
1511 #if 0
1512         OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1513 #endif
1514         OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1515         OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1516         OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1517         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1518
1519         first = STAILQ_FIRST(&it->stdma);
1520         OWRITE(sc, OHCI_ITCMD(dmach),
1521                 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1522         if (firewire_debug) {
1523                 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1524 #if 1
1525                 dump_dma(sc, ITX_CH + dmach);
1526 #endif
1527         }
1528         if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1529 #if 1
1530                 /* Don't start until all chunks are buffered */
1531                 if (STAILQ_FIRST(&it->stfree) != NULL)
1532                         goto out;
1533 #endif
1534 #if 1
1535                 /* Clear cycle match counter bits */
1536                 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1537
1538                 /* 2bit second + 13bit cycle */
1539                 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1540                 cycle_match = fwohci_next_cycle(fc, cycle_now);
1541
1542                 OWRITE(sc, OHCI_ITCTL(dmach),
1543                                 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1544                                 | OHCI_CNTL_DMA_RUN);
1545 #else
1546                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1547 #endif
1548                 if (firewire_debug) {
1549                         printf("cycle_match: 0x%04x->0x%04x\n",
1550                                                 cycle_now, cycle_match);
1551                         dump_dma(sc, ITX_CH + dmach);
1552                         dump_db(sc, ITX_CH + dmach);
1553                 }
1554         } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1555                 device_printf(sc->fc.dev,
1556                         "IT DMA underrun (0x%08x)\n", stat);
1557                 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1558         }
1559 out:
1560         return err;
1561 }
1562
1563 static int
1564 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1565 {
1566         struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1567         int err = 0, s, ldesc;
1568         unsigned short tag, ich;
1569         u_int32_t stat;
1570         struct fwohci_dbch *dbch;
1571         struct fwohcidb_tr *db_tr;
1572         struct fw_bulkxfer *first, *prev, *chunk;
1573         struct fw_xferq *ir;
1574
1575         dbch = &sc->ir[dmach];
1576         ir = &dbch->xferq;
1577
1578         if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1579                 tag = (ir->flag >> 6) & 3;
1580                 ich = ir->flag & 0x3f;
1581                 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1582
1583                 ir->queued = 0;
1584                 dbch->ndb = ir->bnpacket * ir->bnchunk;
1585                 dbch->ndesc = 2;
1586                 fwohci_db_init(sc, dbch);
1587                 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1588                         return ENOMEM;
1589                 err = fwohci_rx_enable(sc, dbch);
1590         }
1591         if(err)
1592                 return err;
1593
1594         first = STAILQ_FIRST(&ir->stfree);
1595         if (first == NULL) {
1596                 device_printf(fc->dev, "IR DMA no free chunk\n");
1597                 return 0;
1598         }
1599
1600         ldesc = dbch->ndesc - 1;
1601         s = splfw();
1602         prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1603         while  ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1604                 volatile struct fwohcidb *db;
1605
1606 #if 1 /* XXX for if_fwe */
1607                 if (chunk->mbuf != NULL) {
1608                         db_tr = (struct fwohcidb_tr *)(chunk->start);
1609                         db_tr->dbcnt = 1;
1610                         err = bus_dmamap_load_mbuf(dbch->dmat, db_tr->dma_map,
1611                                         chunk->mbuf, fwohci_execute_db2, db_tr,
1612                                         /* flags */0);
1613                         FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1614                                 OHCI_UPDATE | OHCI_INPUT_LAST |
1615                                 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1616                 }
1617 #endif
1618                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1619                 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1620                 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1621                 if (prev != NULL) {
1622                         db = ((struct fwohcidb_tr *)(prev->end))->db;
1623                         FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1624                 }
1625                 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1626                 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1627                 prev = chunk;
1628         }
1629         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
1630         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1631         splx(s);
1632         stat = OREAD(sc, OHCI_IRCTL(dmach));
1633         if (stat & OHCI_CNTL_DMA_ACTIVE)
1634                 return 0;
1635         if (stat & OHCI_CNTL_DMA_RUN) {
1636                 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1637                 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1638         }
1639
1640         if (firewire_debug)
1641                 printf("start IR DMA 0x%x\n", stat);
1642         OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1643         OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1644         OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1645         OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1646         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1647         OWRITE(sc, OHCI_IRCMD(dmach),
1648                 ((struct fwohcidb_tr *)(first->start))->bus_addr
1649                                                         | dbch->ndesc);
1650         OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1651         OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1652 #if 0
1653         dump_db(sc, IRX_CH + dmach);
1654 #endif
1655         return err;
1656 }
1657
1658 int
1659 fwohci_stop(struct fwohci_softc *sc, device_t dev)
1660 {
1661         u_int i;
1662
1663 /* Now stopping all DMA channel */
1664         OWRITE(sc,  OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1665         OWRITE(sc,  OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1666         OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1667         OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1668
1669         for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1670                 OWRITE(sc,  OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1671                 OWRITE(sc,  OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1672         }
1673
1674 /* FLUSH FIFO and reset Transmitter/Reciever */
1675         OWRITE(sc,  OHCI_HCCCTL, OHCI_HCC_RESET);
1676
1677 /* Stop interrupt */
1678         OWRITE(sc, FWOHCI_INTMASKCLR,
1679                         OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1680                         | OHCI_INT_PHY_INT
1681                         | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1682                         | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1683                         | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1684                         | OHCI_INT_PHY_BUS_R);
1685 /* XXX Link down?  Bus reset? */
1686         return 0;
1687 }
1688
1689 int
1690 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1691 {
1692         int i;
1693
1694         fwohci_reset(sc, dev);
1695         /* XXX resume isochronus receive automatically. (how about TX?) */
1696         for(i = 0; i < sc->fc.nisodma; i ++) {
1697                 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) {
1698                         device_printf(sc->fc.dev,
1699                                 "resume iso receive ch: %d\n", i);
1700                         sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING;
1701                         sc->fc.irx_enable(&sc->fc, i);
1702                 }
1703         }
1704
1705         bus_generic_resume(dev);
1706         sc->fc.ibr(&sc->fc);
1707         return 0;
1708 }
1709
1710 #define ACK_ALL
1711 static void
1712 fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
1713 {
1714         u_int32_t irstat, itstat;
1715         u_int i;
1716         struct firewire_comm *fc = (struct firewire_comm *)sc;
1717
1718 #ifdef OHCI_DEBUG
1719         if(stat & OREAD(sc, FWOHCI_INTMASK))
1720                 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1721                         stat & OHCI_INT_EN ? "DMA_EN ":"",
1722                         stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1723                         stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1724                         stat & OHCI_INT_ERR ? "INT_ERR ":"",
1725                         stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1726                         stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1727                         stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1728                         stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1729                         stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1730                         stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1731                         stat & OHCI_INT_PHY_SID ? "SID ":"",
1732                         stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1733                         stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1734                         stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1735                         stat & OHCI_INT_DMA_IT  ? "DMA_IT " :"",
1736                         stat & OHCI_INT_DMA_PRRS  ? "DMA_PRRS " :"",
1737                         stat & OHCI_INT_DMA_PRRQ  ? "DMA_PRRQ " :"",
1738                         stat & OHCI_INT_DMA_ARRS  ? "DMA_ARRS " :"",
1739                         stat & OHCI_INT_DMA_ARRQ  ? "DMA_ARRQ " :"",
1740                         stat & OHCI_INT_DMA_ATRS  ? "DMA_ATRS " :"",
1741                         stat & OHCI_INT_DMA_ATRQ  ? "DMA_ATRQ " :"",
1742                         stat, OREAD(sc, FWOHCI_INTMASK)
1743                 );
1744 #endif
1745 /* Bus reset */
1746         if(stat & OHCI_INT_PHY_BUS_R ){
1747                 if (fc->status == FWBUSRESET)
1748                         goto busresetout;
1749                 /* Disable bus reset interrupt until sid recv. */
1750                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_PHY_BUS_R);
1751
1752                 device_printf(fc->dev, "BUS reset\n");
1753                 OWRITE(sc, FWOHCI_INTMASKCLR,  OHCI_INT_CYC_LOST);
1754                 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1755
1756                 OWRITE(sc,  OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1757                 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1758                 OWRITE(sc,  OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1759                 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1760
1761 #ifndef ACK_ALL
1762                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1763 #endif
1764                 fw_busreset(fc);
1765         }
1766 busresetout:
1767         if((stat & OHCI_INT_DMA_IR )){
1768 #ifndef ACK_ALL
1769                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1770 #endif
1771 #if __FreeBSD_version >= 500000
1772                 irstat = atomic_readandclear_int(&sc->irstat);
1773 #else
1774                 irstat = sc->irstat;
1775                 sc->irstat = 0;
1776 #endif
1777                 for(i = 0; i < fc->nisodma ; i++){
1778                         struct fwohci_dbch *dbch;
1779
1780                         if((irstat & (1 << i)) != 0){
1781                                 dbch = &sc->ir[i];
1782                                 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1783                                         device_printf(sc->fc.dev,
1784                                                 "dma(%d) not active\n", i);
1785                                         continue;
1786                                 }
1787                                 fwohci_rbuf_update(sc, i);
1788                         }
1789                 }
1790         }
1791         if((stat & OHCI_INT_DMA_IT )){
1792 #ifndef ACK_ALL
1793                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1794 #endif
1795 #if __FreeBSD_version >= 500000
1796                 itstat = atomic_readandclear_int(&sc->itstat);
1797 #else
1798                 itstat = sc->itstat;
1799                 sc->itstat = 0;
1800 #endif
1801                 for(i = 0; i < fc->nisodma ; i++){
1802                         if((itstat & (1 << i)) != 0){
1803                                 fwohci_tbuf_update(sc, i);
1804                         }
1805                 }
1806         }
1807         if((stat & OHCI_INT_DMA_PRRS )){
1808 #ifndef ACK_ALL
1809                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1810 #endif
1811 #if 0
1812                 dump_dma(sc, ARRS_CH);
1813                 dump_db(sc, ARRS_CH);
1814 #endif
1815                 fwohci_arcv(sc, &sc->arrs, count);
1816         }
1817         if((stat & OHCI_INT_DMA_PRRQ )){
1818 #ifndef ACK_ALL
1819                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1820 #endif
1821 #if 0
1822                 dump_dma(sc, ARRQ_CH);
1823                 dump_db(sc, ARRQ_CH);
1824 #endif
1825                 fwohci_arcv(sc, &sc->arrq, count);
1826         }
1827         if(stat & OHCI_INT_PHY_SID){
1828                 u_int32_t *buf, node_id;
1829                 int plen;
1830
1831 #ifndef ACK_ALL
1832                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
1833 #endif
1834                 /* Enable bus reset interrupt */
1835                 OWRITE(sc, FWOHCI_INTMASK,  OHCI_INT_PHY_BUS_R);
1836                 /* Allow async. request to us */
1837                 OWRITE(sc, OHCI_AREQHI, 1 << 31);
1838                 /* XXX insecure ?? */
1839                 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
1840                 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
1841                 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
1842                 /* Set ATRetries register */
1843                 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
1844 /*
1845 ** Checking whether the node is root or not. If root, turn on
1846 ** cycle master.
1847 */
1848                 node_id = OREAD(sc, FWOHCI_NODEID);
1849                 plen = OREAD(sc, OHCI_SID_CNT);
1850
1851                 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
1852                         node_id, (plen >> 16) & 0xff);
1853                 if (!(node_id & OHCI_NODE_VALID)) {
1854                         printf("Bus reset failure\n");
1855                         goto sidout;
1856                 }
1857                 if (node_id & OHCI_NODE_ROOT) {
1858                         printf("CYCLEMASTER mode\n");
1859                         OWRITE(sc, OHCI_LNKCTL,
1860                                 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
1861                 } else {
1862                         printf("non CYCLEMASTER mode\n");
1863                         OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
1864                         OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
1865                 }
1866                 fc->nodeid = node_id & 0x3f;
1867
1868                 if (plen & OHCI_SID_ERR) {
1869                         device_printf(fc->dev, "SID Error\n");
1870                         goto sidout;
1871                 }
1872                 plen &= OHCI_SID_CNT_MASK;
1873                 if (plen < 4 || plen > OHCI_SIDSIZE) {
1874                         device_printf(fc->dev, "invalid SID len = %d\n", plen);
1875                         goto sidout;
1876                 }
1877                 plen -= 4; /* chop control info */
1878                 buf = (u_int32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
1879                 if (buf == NULL) {
1880                         device_printf(fc->dev, "malloc failed\n");
1881                         goto sidout;
1882                 }
1883                 for (i = 0; i < plen / 4; i ++)
1884                         buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
1885 #if 1
1886                 /* pending all pre-bus_reset packets */
1887                 fwohci_txd(sc, &sc->atrq);
1888                 fwohci_txd(sc, &sc->atrs);
1889                 fwohci_arcv(sc, &sc->arrs, -1);
1890                 fwohci_arcv(sc, &sc->arrq, -1);
1891                 fw_drain_txq(fc);
1892 #endif
1893                 fw_sidrcv(fc, buf, plen);
1894                 free(buf, M_FW);
1895         }
1896 sidout:
1897         if((stat & OHCI_INT_DMA_ATRQ )){
1898 #ifndef ACK_ALL
1899                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
1900 #endif
1901                 fwohci_txd(sc, &(sc->atrq));
1902         }
1903         if((stat & OHCI_INT_DMA_ATRS )){
1904 #ifndef ACK_ALL
1905                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
1906 #endif
1907                 fwohci_txd(sc, &(sc->atrs));
1908         }
1909         if((stat & OHCI_INT_PW_ERR )){
1910 #ifndef ACK_ALL
1911                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
1912 #endif
1913                 device_printf(fc->dev, "posted write error\n");
1914         }
1915         if((stat & OHCI_INT_ERR )){
1916 #ifndef ACK_ALL
1917                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
1918 #endif
1919                 device_printf(fc->dev, "unrecoverable error\n");
1920         }
1921         if((stat & OHCI_INT_PHY_INT)) {
1922 #ifndef ACK_ALL
1923                 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
1924 #endif
1925                 device_printf(fc->dev, "phy int\n");
1926         }
1927
1928         return;
1929 }
1930
1931 #if FWOHCI_TASKQUEUE
1932 static void
1933 fwohci_complete(void *arg, int pending)
1934 {
1935         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1936         u_int32_t stat;
1937
1938 again:
1939         stat = atomic_readandclear_int(&sc->intstat);
1940         if (stat)
1941                 fwohci_intr_body(sc, stat, -1);
1942         else
1943                 return;
1944         goto again;
1945 }
1946 #endif
1947
1948 static u_int32_t
1949 fwochi_check_stat(struct fwohci_softc *sc)
1950 {
1951         u_int32_t stat, irstat, itstat;
1952
1953         stat = OREAD(sc, FWOHCI_INTSTAT);
1954         if (stat == 0xffffffff) {
1955                 device_printf(sc->fc.dev,
1956                         "device physically ejected?\n");
1957                 return(stat);
1958         }
1959 #ifdef ACK_ALL
1960         if (stat)
1961                 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
1962 #endif
1963         if (stat & OHCI_INT_DMA_IR) {
1964                 irstat = OREAD(sc, OHCI_IR_STAT);
1965                 OWRITE(sc, OHCI_IR_STATCLR, irstat);
1966                 atomic_set_int(&sc->irstat, irstat);
1967         }
1968         if (stat & OHCI_INT_DMA_IT) {
1969                 itstat = OREAD(sc, OHCI_IT_STAT);
1970                 OWRITE(sc, OHCI_IT_STATCLR, itstat);
1971                 atomic_set_int(&sc->itstat, itstat);
1972         }
1973         return(stat);
1974 }
1975
1976 void
1977 fwohci_intr(void *arg)
1978 {
1979         struct fwohci_softc *sc = (struct fwohci_softc *)arg;
1980         u_int32_t stat;
1981 #if !FWOHCI_TASKQUEUE
1982         u_int32_t bus_reset = 0;
1983 #endif
1984
1985         if (!(sc->intmask & OHCI_INT_EN)) {
1986                 /* polling mode */
1987                 return;
1988         }
1989
1990 #if !FWOHCI_TASKQUEUE
1991 again:
1992 #endif
1993         stat = fwochi_check_stat(sc);
1994         if (stat == 0 || stat == 0xffffffff)
1995                 return;
1996 #if FWOHCI_TASKQUEUE
1997         atomic_set_int(&sc->intstat, stat);
1998         /* XXX mask bus reset intr. during bus reset phase */
1999         if (stat)
2000                 taskqueue_enqueue(taskqueue_swi_giant, &sc->fwohci_task_complete);
2001 #else
2002         /* We cannot clear bus reset event during bus reset phase */
2003         if ((stat & ~bus_reset) == 0)
2004                 return;
2005         bus_reset = stat & OHCI_INT_PHY_BUS_R;
2006         fwohci_intr_body(sc, stat, -1);
2007         goto again;
2008 #endif
2009 }
2010
2011 static void
2012 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2013 {
2014         int s;
2015         u_int32_t stat;
2016         struct fwohci_softc *sc;
2017
2018
2019         sc = (struct fwohci_softc *)fc;
2020         stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2021                 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2022                 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2023 #if 0
2024         if (!quick) {
2025 #else
2026         if (1) {
2027 #endif
2028                 stat = fwochi_check_stat(sc);
2029                 if (stat == 0 || stat == 0xffffffff)
2030                         return;
2031         }
2032         s = splfw();
2033         fwohci_intr_body(sc, stat, count);
2034         splx(s);
2035 }
2036
2037 static void
2038 fwohci_set_intr(struct firewire_comm *fc, int enable)
2039 {
2040         struct fwohci_softc *sc;
2041
2042         sc = (struct fwohci_softc *)fc;
2043         if (bootverbose)
2044                 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2045         if (enable) {
2046                 sc->intmask |= OHCI_INT_EN;
2047                 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2048         } else {
2049                 sc->intmask &= ~OHCI_INT_EN;
2050                 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2051         }
2052 }
2053
2054 static void
2055 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2056 {
2057         struct firewire_comm *fc = &sc->fc;
2058         volatile struct fwohcidb *db;
2059         struct fw_bulkxfer *chunk;
2060         struct fw_xferq *it;
2061         u_int32_t stat, count;
2062         int s, w=0, ldesc;
2063
2064         it = fc->it[dmach];
2065         ldesc = sc->it[dmach].ndesc - 1;
2066         s = splfw(); /* unnecessary ? */
2067         fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2068         while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2069                 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2070                 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2071                                 >> OHCI_STATUS_SHIFT;
2072                 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2073                 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2074                                 & OHCI_COUNT_MASK;
2075                 if (stat == 0)
2076                         break;
2077                 STAILQ_REMOVE_HEAD(&it->stdma, link);
2078                 switch (stat & FWOHCIEV_MASK){
2079                 case FWOHCIEV_ACKCOMPL:
2080 #if 0
2081                         device_printf(fc->dev, "0x%08x\n", count);
2082 #endif
2083                         break;
2084                 default:
2085                         device_printf(fc->dev,
2086                                 "Isochronous transmit err %02x(%s)\n",
2087                                         stat, fwohcicode[stat & 0x1f]);
2088                 }
2089                 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2090                 w++;
2091         }
2092         splx(s);
2093         if (w)
2094                 wakeup(it);
2095 }
2096
2097 static void
2098 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2099 {
2100         struct firewire_comm *fc = &sc->fc;
2101         volatile struct fwohcidb_tr *db_tr;
2102         struct fw_bulkxfer *chunk;
2103         struct fw_xferq *ir;
2104         u_int32_t stat;
2105         int s, w=0, ldesc;
2106
2107         ir = fc->ir[dmach];
2108         ldesc = sc->ir[dmach].ndesc - 1;
2109 #if 0
2110         dump_db(sc, dmach);
2111 #endif
2112         s = splfw();
2113         fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2114         while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2115                 db_tr = (struct fwohcidb_tr *)chunk->end;
2116                 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2117                                 >> OHCI_STATUS_SHIFT;
2118                 if (stat == 0)
2119                         break;
2120
2121                 if (chunk->mbuf != NULL) {
2122                         bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2123                                                 BUS_DMASYNC_POSTREAD);
2124                         bus_dmamap_unload(sc->ir[dmach].dmat, db_tr->dma_map);
2125                 } else if (ir->buf != NULL) {
2126                         fwdma_sync_multiseg(ir->buf, chunk->poffset,
2127                                 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2128                 } else {
2129                         /* XXX */
2130                         printf("fwohci_rbuf_update: this shouldn't happend\n");
2131                 }
2132
2133                 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2134                 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2135                 switch (stat & FWOHCIEV_MASK) {
2136                 case FWOHCIEV_ACKCOMPL:
2137                         chunk->resp = 0;
2138                         break;
2139                 default:
2140                         chunk->resp = EINVAL;
2141                         device_printf(fc->dev,
2142                                 "Isochronous receive err %02x(%s)\n",
2143                                         stat, fwohcicode[stat & 0x1f]);
2144                 }
2145                 w++;
2146         }
2147         splx(s);
2148         if (w) {
2149                 if (ir->flag & FWXFERQ_HANDLER)
2150                         ir->hand(ir);
2151                 else
2152                         wakeup(ir);
2153         }
2154 }
2155
2156 void
2157 dump_dma(struct fwohci_softc *sc, u_int32_t ch)
2158 {
2159         u_int32_t off, cntl, stat, cmd, match;
2160
2161         if(ch == 0){
2162                 off = OHCI_ATQOFF;
2163         }else if(ch == 1){
2164                 off = OHCI_ATSOFF;
2165         }else if(ch == 2){
2166                 off = OHCI_ARQOFF;
2167         }else if(ch == 3){
2168                 off = OHCI_ARSOFF;
2169         }else if(ch < IRX_CH){
2170                 off = OHCI_ITCTL(ch - ITX_CH);
2171         }else{
2172                 off = OHCI_IRCTL(ch - IRX_CH);
2173         }
2174         cntl = stat = OREAD(sc, off);
2175         cmd = OREAD(sc, off + 0xc);
2176         match = OREAD(sc, off + 0x10);
2177
2178         device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2179                 ch,
2180                 cntl,
2181                 cmd,
2182                 match);
2183         stat &= 0xffff ;
2184         if (stat) {
2185                 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2186                         ch,
2187                         stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2188                         stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2189                         stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2190                         stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2191                         stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2192                         stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2193                         fwohcicode[stat & 0x1f],
2194                         stat & 0x1f
2195                 );
2196         }else{
2197                 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2198         }
2199 }
2200
2201 void
2202 dump_db(struct fwohci_softc *sc, u_int32_t ch)
2203 {
2204         struct fwohci_dbch *dbch;
2205         struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2206         volatile struct fwohcidb *curr = NULL, *prev, *next = NULL;
2207         int idb, jdb;
2208         u_int32_t cmd, off;
2209         if(ch == 0){
2210                 off = OHCI_ATQOFF;
2211                 dbch = &sc->atrq;
2212         }else if(ch == 1){
2213                 off = OHCI_ATSOFF;
2214                 dbch = &sc->atrs;
2215         }else if(ch == 2){
2216                 off = OHCI_ARQOFF;
2217                 dbch = &sc->arrq;
2218         }else if(ch == 3){
2219                 off = OHCI_ARSOFF;
2220                 dbch = &sc->arrs;
2221         }else if(ch < IRX_CH){
2222                 off = OHCI_ITCTL(ch - ITX_CH);
2223                 dbch = &sc->it[ch - ITX_CH];
2224         }else {
2225                 off = OHCI_IRCTL(ch - IRX_CH);
2226                 dbch = &sc->ir[ch - IRX_CH];
2227         }
2228         cmd = OREAD(sc, off + 0xc);
2229
2230         if( dbch->ndb == 0 ){
2231                 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2232                 return;
2233         }
2234         pp = dbch->top;
2235         prev = pp->db;
2236         for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2237                 if(pp == NULL){
2238                         curr = NULL;
2239                         goto outdb;
2240                 }
2241                 cp = STAILQ_NEXT(pp, link);
2242                 if(cp == NULL){
2243                         curr = NULL;
2244                         goto outdb;
2245                 }
2246                 np = STAILQ_NEXT(cp, link);
2247                 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2248                         if ((cmd  & 0xfffffff0) == cp->bus_addr) {
2249                                 curr = cp->db;
2250                                 if(np != NULL){
2251                                         next = np->db;
2252                                 }else{
2253                                         next = NULL;
2254                                 }
2255                                 goto outdb;
2256                         }
2257                 }
2258                 pp = STAILQ_NEXT(pp, link);
2259                 prev = pp->db;
2260         }
2261 outdb:
2262         if( curr != NULL){
2263 #if 0
2264                 printf("Prev DB %d\n", ch);
2265                 print_db(pp, prev, ch, dbch->ndesc);
2266 #endif
2267                 printf("Current DB %d\n", ch);
2268                 print_db(cp, curr, ch, dbch->ndesc);
2269 #if 0
2270                 printf("Next DB %d\n", ch);
2271                 print_db(np, next, ch, dbch->ndesc);
2272 #endif
2273         }else{
2274                 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2275         }
2276         return;
2277 }
2278
2279 void
2280 print_db(struct fwohcidb_tr *db_tr, volatile struct fwohcidb *db,
2281                 u_int32_t ch, u_int32_t max)
2282 {
2283         fwohcireg_t stat;
2284         int i, key;
2285         u_int32_t cmd, res;
2286
2287         if(db == NULL){
2288                 printf("No Descriptor is found\n");
2289                 return;
2290         }
2291
2292         printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2293                 ch,
2294                 "Current",
2295                 "OP  ",
2296                 "KEY",
2297                 "INT",
2298                 "BR ",
2299                 "len",
2300                 "Addr",
2301                 "Depend",
2302                 "Stat",
2303                 "Cnt");
2304         for( i = 0 ; i <= max ; i ++){
2305                 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2306                 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2307                 key = cmd & OHCI_KEY_MASK;
2308                 stat = res >> OHCI_STATUS_SHIFT;
2309 #if __FreeBSD_version >= 500000
2310                 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2311                                 (uintmax_t)db_tr->bus_addr,
2312 #else
2313                 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2314                                 db_tr->bus_addr,
2315 #endif
2316                                 dbcode[(cmd >> 28) & 0xf],
2317                                 dbkey[(cmd >> 24) & 0x7],
2318                                 dbcond[(cmd >> 20) & 0x3],
2319                                 dbcond[(cmd >> 18) & 0x3],
2320                                 cmd & OHCI_COUNT_MASK,
2321                                 FWOHCI_DMA_READ(db[i].db.desc.addr),
2322                                 FWOHCI_DMA_READ(db[i].db.desc.depend),
2323                                 stat,
2324                                 res & OHCI_COUNT_MASK);
2325                 if(stat & 0xff00){
2326                         printf(" %s%s%s%s%s%s %s(%x)\n",
2327                                 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2328                                 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2329                                 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2330                                 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2331                                 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2332                                 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2333                                 fwohcicode[stat & 0x1f],
2334                                 stat & 0x1f
2335                         );
2336                 }else{
2337                         printf(" Nostat\n");
2338                 }
2339                 if(key == OHCI_KEY_ST2 ){
2340                         printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2341                                 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2342                                 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2343                                 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2344                                 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2345                 }
2346                 if(key == OHCI_KEY_DEVICE){
2347                         return;
2348                 }
2349                 if((cmd & OHCI_BRANCH_MASK)
2350                                 == OHCI_BRANCH_ALWAYS){
2351                         return;
2352                 }
2353                 if((cmd & OHCI_CMD_MASK)
2354                                 == OHCI_OUTPUT_LAST){
2355                         return;
2356                 }
2357                 if((cmd & OHCI_CMD_MASK)
2358                                 == OHCI_INPUT_LAST){
2359                         return;
2360                 }
2361                 if(key == OHCI_KEY_ST2 ){
2362                         i++;
2363                 }
2364         }
2365         return;
2366 }
2367
2368 void
2369 fwohci_ibr(struct firewire_comm *fc)
2370 {
2371         struct fwohci_softc *sc;
2372         u_int32_t fun;
2373
2374         device_printf(fc->dev, "Initiate bus reset\n");
2375         sc = (struct fwohci_softc *)fc;
2376
2377         /*
2378          * Set root hold-off bit so that non cyclemaster capable node
2379          * shouldn't became the root node.
2380          */
2381 #if 1
2382         fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2383         fun |= FW_PHY_IBR | FW_PHY_RHB;
2384         fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2385 #else   /* Short bus reset */
2386         fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2387         fun |= FW_PHY_ISBR | FW_PHY_RHB;
2388         fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2389 #endif
2390 }
2391
2392 void
2393 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2394 {
2395         struct fwohcidb_tr *db_tr, *fdb_tr;
2396         struct fwohci_dbch *dbch;
2397         volatile struct fwohcidb *db;
2398         struct fw_pkt *fp;
2399         volatile struct fwohci_txpkthdr *ohcifp;
2400         unsigned short chtag;
2401         int idb;
2402
2403         dbch = &sc->it[dmach];
2404         chtag = sc->it[dmach].xferq.flag & 0xff;
2405
2406         db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2407         fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2408 /*
2409 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2410 */
2411         for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2412                 db = db_tr->db;
2413                 fp = (struct fw_pkt *)db_tr->buf;
2414                 ohcifp = (volatile struct fwohci_txpkthdr *) db[1].db.immed;
2415                 ohcifp->mode.ld[0] = fp->mode.ld[0];
2416                 ohcifp->mode.stream.len = fp->mode.stream.len;
2417                 ohcifp->mode.stream.chtag = chtag;
2418                 ohcifp->mode.stream.tcode = 0xa;
2419                 ohcifp->mode.stream.spd = 0;
2420 #if BYTE_ORDER == BIG_ENDIAN
2421                 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2422                 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2423 #endif
2424
2425                 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2426                 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2427                 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2428 #if 0 /* if bulkxfer->npackets changes */
2429                 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2430                         | OHCI_UPDATE
2431                         | OHCI_BRANCH_ALWAYS;
2432                 db[0].db.desc.depend =
2433                         = db[dbch->ndesc - 1].db.desc.depend
2434                         = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2435 #else
2436                 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2437                 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2438 #endif
2439                 bulkxfer->end = (caddr_t)db_tr;
2440                 db_tr = STAILQ_NEXT(db_tr, link);
2441         }
2442         db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2443         FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2444         FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2445 #if 0 /* if bulkxfer->npackets changes */
2446         db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2447         /* OHCI 1.1 and above */
2448         db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2449 #endif
2450 /*
2451         db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2452         fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2453 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2454 */
2455         return;
2456 }
2457
2458 static int
2459 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2460                                                                 int poffset)
2461 {
2462         volatile struct fwohcidb *db = db_tr->db;
2463         struct fw_xferq *it;
2464         int err = 0;
2465
2466         it = &dbch->xferq;
2467         if(it->buf == 0){
2468                 err = EINVAL;
2469                 return err;
2470         }
2471         db_tr->buf = fwdma_v_addr(it->buf, poffset);
2472         db_tr->dbcnt = 3;
2473
2474         FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2475                 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2476         FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2477         fwdma_bus_addr(it->buf, poffset) + sizeof(u_int32_t));
2478
2479         FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2480                 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2481 #if 1
2482         FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2483         FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2484 #endif
2485         return 0;
2486 }
2487
2488 int
2489 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2490                 int poffset, struct fwdma_alloc *dummy_dma)
2491 {
2492         volatile struct fwohcidb *db = db_tr->db;
2493         struct fw_xferq *ir;
2494         int i, ldesc;
2495         bus_addr_t dbuf[2];
2496         int dsiz[2];
2497
2498         ir = &dbch->xferq;
2499         if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2500                 db_tr->buf = fwdma_malloc_size(dbch->dmat, &db_tr->dma_map,
2501                         ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2502                 if (db_tr->buf == NULL)
2503                         return(ENOMEM);
2504                 db_tr->dbcnt = 1;
2505                 dsiz[0] = ir->psize;
2506                 bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2507                         BUS_DMASYNC_PREREAD);
2508         } else {
2509                 db_tr->dbcnt = 0;
2510                 if (dummy_dma != NULL) {
2511                         dsiz[db_tr->dbcnt] = sizeof(u_int32_t);
2512                         dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2513                 }
2514                 dsiz[db_tr->dbcnt] = ir->psize;
2515                 if (ir->buf != NULL) {
2516                         db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2517                         dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2518                 }
2519                 db_tr->dbcnt++;
2520         }
2521         for(i = 0 ; i < db_tr->dbcnt ; i++){
2522                 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2523                 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2524                 if (ir->flag & FWXFERQ_STREAM) {
2525                         FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2526                 }
2527                 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2528         }
2529         ldesc = db_tr->dbcnt - 1;
2530         if (ir->flag & FWXFERQ_STREAM) {
2531                 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2532         }
2533         FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2534         return 0;
2535 }
2536
2537
2538 static int
2539 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2540 {
2541         struct fw_pkt *fp0;
2542         u_int32_t ld0;
2543         int slen;
2544 #if BYTE_ORDER == BIG_ENDIAN
2545         int i;
2546 #endif
2547
2548         ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2549 #if 0
2550         printf("ld0: x%08x\n", ld0);
2551 #endif
2552         fp0 = (struct fw_pkt *)&ld0;
2553         switch (fp0->mode.common.tcode) {
2554         case FWTCODE_RREQQ:
2555         case FWTCODE_WRES:
2556         case FWTCODE_WREQQ:
2557         case FWTCODE_RRESQ:
2558         case FWOHCITCODE_PHY:
2559                 slen = 12;
2560                 break;
2561         case FWTCODE_RREQB:
2562         case FWTCODE_WREQB:
2563         case FWTCODE_LREQ:
2564         case FWTCODE_RRESB:
2565         case FWTCODE_LRES:
2566                 slen = 16;
2567                 break;
2568         default:
2569                 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2570                 return(0);
2571         }
2572         if (slen > len) {
2573                 if (firewire_debug)
2574                         printf("splitted header\n");
2575                 return(-slen);
2576         }
2577 #if BYTE_ORDER == BIG_ENDIAN
2578         for(i = 0; i < slen/4; i ++)
2579                 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2580 #endif
2581         return(slen);
2582 }
2583
2584 #define PLEN(x) roundup2(x, sizeof(u_int32_t))
2585 static int
2586 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2587 {
2588         int r;
2589
2590         switch(fp->mode.common.tcode){
2591         case FWTCODE_RREQQ:
2592                 r = sizeof(fp->mode.rreqq) + sizeof(u_int32_t);
2593                 break;
2594         case FWTCODE_WRES:
2595                 r = sizeof(fp->mode.wres) + sizeof(u_int32_t);
2596                 break;
2597         case FWTCODE_WREQQ:
2598                 r = sizeof(fp->mode.wreqq) + sizeof(u_int32_t);
2599                 break;
2600         case FWTCODE_RREQB:
2601                 r = sizeof(fp->mode.rreqb) + sizeof(u_int32_t);
2602                 break;
2603         case FWTCODE_RRESQ:
2604                 r = sizeof(fp->mode.rresq) + sizeof(u_int32_t);
2605                 break;
2606         case FWTCODE_WREQB:
2607                 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len)
2608                                                 + sizeof(u_int32_t);
2609                 break;
2610         case FWTCODE_LREQ:
2611                 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len)
2612                                                 + sizeof(u_int32_t);
2613                 break;
2614         case FWTCODE_RRESB:
2615                 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len)
2616                                                 + sizeof(u_int32_t);
2617                 break;
2618         case FWTCODE_LRES:
2619                 r = sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len)
2620                                                 + sizeof(u_int32_t);
2621                 break;
2622         case FWOHCITCODE_PHY:
2623                 r = 16;
2624                 break;
2625         default:
2626                 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2627                                                 fp->mode.common.tcode);
2628                 r = 0;
2629         }
2630         if (r > dbch->xferq.psize) {
2631                 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2632                 /* panic ? */
2633         }
2634         return r;
2635 }
2636
2637 static void
2638 fwohci_arcv_free_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr)
2639 {
2640         volatile struct fwohcidb *db = &db_tr->db[0];
2641
2642         FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2643         FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2644         FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2645         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREWRITE);
2646         dbch->bottom = db_tr;
2647 }
2648
2649 static void
2650 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2651 {
2652         struct fwohcidb_tr *db_tr;
2653         struct iovec vec[2];
2654         struct fw_pkt pktbuf;
2655         int nvec;
2656         struct fw_pkt *fp;
2657         u_int8_t *ld;
2658         u_int32_t stat, off, status;
2659         u_int spd;
2660         int len, plen, hlen, pcnt, offset;
2661         int s;
2662         caddr_t buf;
2663         int resCount;
2664
2665         if(&sc->arrq == dbch){
2666                 off = OHCI_ARQOFF;
2667         }else if(&sc->arrs == dbch){
2668                 off = OHCI_ARSOFF;
2669         }else{
2670                 return;
2671         }
2672
2673         s = splfw();
2674         db_tr = dbch->top;
2675         pcnt = 0;
2676         /* XXX we cannot handle a packet which lies in more than two buf */
2677         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTREAD);
2678         fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_POSTWRITE);
2679         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2680         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2681 #if 0
2682         printf("status 0x%04x, resCount 0x%04x\n", status, resCount);
2683 #endif
2684         while (status & OHCI_CNTL_DMA_ACTIVE) {
2685                 len = dbch->xferq.psize - resCount;
2686                 ld = (u_int8_t *)db_tr->buf;
2687                 if (dbch->pdb_tr == NULL) {
2688                         len -= dbch->buf_offset;
2689                         ld += dbch->buf_offset;
2690                 }
2691                 if (len > 0)
2692                         bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2693                                         BUS_DMASYNC_POSTREAD);
2694                 while (len > 0 ) {
2695                         if (count >= 0 && count-- == 0)
2696                                 goto out;
2697                         if(dbch->pdb_tr != NULL){
2698                                 /* we have a fragment in previous buffer */
2699                                 int rlen;
2700
2701                                 offset = dbch->buf_offset;
2702                                 if (offset < 0)
2703                                         offset = - offset;
2704                                 buf = dbch->pdb_tr->buf + offset;
2705                                 rlen = dbch->xferq.psize - offset;
2706                                 if (firewire_debug)
2707                                         printf("rlen=%d, offset=%d\n",
2708                                                 rlen, dbch->buf_offset);
2709                                 if (dbch->buf_offset < 0) {
2710                                         /* splitted in header, pull up */
2711                                         char *p;
2712
2713                                         p = (char *)&pktbuf;
2714                                         bcopy(buf, p, rlen);
2715                                         p += rlen;
2716                                         /* this must be too long but harmless */
2717                                         rlen = sizeof(pktbuf) - rlen;
2718                                         if (rlen < 0)
2719                                                 printf("why rlen < 0\n");
2720                                         bcopy(db_tr->buf, p, rlen);
2721                                         ld += rlen;
2722                                         len -= rlen;
2723                                         hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2724                                         if (hlen < 0) {
2725                                                 printf("hlen < 0 shouldn't happen");
2726                                         }
2727                                         offset = sizeof(pktbuf);
2728                                         vec[0].iov_base = (char *)&pktbuf;
2729                                         vec[0].iov_len = offset;
2730                                 } else {
2731                                         /* splitted in payload */
2732                                         offset = rlen;
2733                                         vec[0].iov_base = buf;
2734                                         vec[0].iov_len = rlen;
2735                                 }
2736                                 fp=(struct fw_pkt *)vec[0].iov_base;
2737                                 nvec = 1;
2738                         } else {
2739                                 /* no fragment in previous buffer */
2740                                 fp=(struct fw_pkt *)ld;
2741                                 hlen = fwohci_arcv_swap(fp, len);
2742                                 if (hlen == 0)
2743                                         /* XXX need reset */
2744                                         goto out;
2745                                 if (hlen < 0) {
2746                                         dbch->pdb_tr = db_tr;
2747                                         dbch->buf_offset = - dbch->buf_offset;
2748                                         /* sanity check */
2749                                         if (resCount != 0)
2750                                                 printf("resCount != 0 !?\n");
2751                                         goto out;
2752                                 }
2753                                 offset = 0;
2754                                 nvec = 0;
2755                         }
2756                         plen = fwohci_get_plen(sc, dbch, fp) - offset;
2757                         if (plen < 0) {
2758                                 /* minimum header size + trailer
2759                                 = sizeof(fw_pkt) so this shouldn't happens */
2760                                 printf("plen is negative! offset=%d\n", offset);
2761                                 goto out;
2762                         }
2763                         if (plen > 0) {
2764                                 len -= plen;
2765                                 if (len < 0) {
2766                                         dbch->pdb_tr = db_tr;
2767                                         if (firewire_debug)
2768                                                 printf("splitted payload\n");
2769                                         /* sanity check */
2770                                         if (resCount != 0)
2771                                                 printf("resCount != 0 !?\n");
2772                                         goto out;
2773                                 }
2774                                 vec[nvec].iov_base = ld;
2775                                 vec[nvec].iov_len = plen;
2776                                 nvec ++;
2777                                 ld += plen;
2778                         }
2779                         dbch->buf_offset = ld - (u_int8_t *)db_tr->buf;
2780                         if (nvec == 0)
2781                                 printf("nvec == 0\n");
2782
2783 /* DMA result-code will be written at the tail of packet */
2784 #if BYTE_ORDER == BIG_ENDIAN
2785                         stat = FWOHCI_DMA_READ(((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat) >> 16;
2786 #else
2787                         stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat;
2788 #endif
2789 #if 0
2790                         printf("plen: %d, stat %x\n", plen ,stat);
2791 #endif
2792                         spd = (stat >> 5) & 0x3;
2793                         stat &= 0x1f;
2794                         switch(stat){
2795                         case FWOHCIEV_ACKPEND:
2796 #if 0
2797                                 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
2798 #endif
2799                                 /* fall through */
2800                         case FWOHCIEV_ACKCOMPL:
2801                                 if ((vec[nvec-1].iov_len -=
2802                                         sizeof(struct fwohci_trailer)) == 0)
2803                                         nvec--;
2804                                 fw_rcv(&sc->fc, vec, nvec, 0, spd);
2805                                         break;
2806                         case FWOHCIEV_BUSRST:
2807                                 if (sc->fc.status != FWBUSRESET)
2808                                         printf("got BUSRST packet!?\n");
2809                                 break;
2810                         default:
2811                                 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]);
2812 #if 0 /* XXX */
2813                                 goto out;
2814 #endif
2815                                 break;
2816                         }
2817                         pcnt ++;
2818                         if (dbch->pdb_tr != NULL) {
2819                                 fwohci_arcv_free_buf(dbch, dbch->pdb_tr);
2820                                 dbch->pdb_tr = NULL;
2821                         }
2822
2823                 }
2824 out:
2825                 if (resCount == 0) {
2826                         /* done on this buffer */
2827                         if (dbch->pdb_tr == NULL) {
2828                                 fwohci_arcv_free_buf(dbch, db_tr);
2829                                 dbch->buf_offset = 0;
2830                         } else
2831                                 if (dbch->pdb_tr != db_tr)
2832                                         printf("pdb_tr != db_tr\n");
2833                         db_tr = STAILQ_NEXT(db_tr, link);
2834                         status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2835                                                 >> OHCI_STATUS_SHIFT;
2836                         resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
2837                                                 & OHCI_COUNT_MASK;
2838                         /* XXX check buffer overrun */
2839                         dbch->top = db_tr;
2840                 } else {
2841                         dbch->buf_offset = dbch->xferq.psize - resCount;
2842                         break;
2843                 }
2844                 /* XXX make sure DMA is not dead */
2845         }
2846 #if 0
2847         if (pcnt < 1)
2848                 printf("fwohci_arcv: no packets\n");
2849 #endif
2850         splx(s);
2851 }