2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.23 2005/06/14 11:08:40 joerg Exp $
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/syslog.h>
50 #include <sys/thread2.h>
52 #include <sys/module.h>
55 #include <machine/bus.h>
57 #include <machine/resource.h>
59 #include <net/ethernet.h>
61 #include <net/ifq_var.h>
62 #include <net/if_arp.h>
63 #include <net/if_dl.h>
64 #include <net/if_mib.h>
65 #include <net/if_media.h>
68 #include <dev/netif/mii_layer/mii.h>
69 #include <dev/netif/mii_layer/miivar.h>
74 #include <net/bridge/bridge.h>
76 #include <machine/md_var.h>
81 devclass_t ed_devclass;
83 static void ed_init (void *);
84 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
85 static void ed_start (struct ifnet *);
86 static void ed_reset (struct ifnet *);
87 static void ed_watchdog (struct ifnet *);
89 static void ed_tick (void *);
92 static void ds_getmcaf (struct ed_softc *, u_int32_t *);
94 static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int);
96 static __inline void ed_rint (struct ed_softc *);
97 static __inline void ed_xmit (struct ed_softc *);
98 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
100 static void ed_hpp_set_physical_link (struct ed_softc *);
101 static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *,
103 static void ed_hpp_writemem (struct ed_softc *, unsigned char *,
104 /* u_short */ int, /* u_short */ int);
105 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *,
108 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *,
111 static void ed_setrcr (struct ed_softc *);
113 static uint32_t ds_mchash (const uint8_t *);
115 DECLARE_DUMMY_MODULE(if_ed);
118 * Interrupt conversion table for WD/SMC ASIC/83C584
120 static unsigned short ed_intr_val[] = {
132 * Interrupt conversion table for 83C790
134 static unsigned short ed_790_intr_val[] = {
146 * Interrupt conversion table for the HP PC LAN+
149 static unsigned short ed_hpp_intr_val[] = {
169 * Generic probe routine for testing for the existance of a DS8390.
170 * Must be called after the NIC has just been reset. This routine
171 * works by looking at certain register values that are guaranteed
172 * to be initialized a certain way after power-up or reset. Seems
173 * not to currently work on the 83C690.
177 * Register reset bits set bits
178 * Command Register (CR) TXP, STA RD2, STP
179 * Interrupt Status (ISR) RST
180 * Interrupt Mask (IMR) All bits
181 * Data Control (DCR) LAS
182 * Transmit Config. (TCR) LB1, LB0
184 * We only look at the CR and ISR registers, however, because looking at
185 * the others would require changing register pages (which would be
186 * intrusive if this isn't an 8390).
188 * Return 1 if 8390 was found, 0 if not.
192 ed_probe_generic8390(sc)
195 if ((ed_nic_inb(sc, ED_P0_CR) &
196 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
197 (ED_CR_RD2 | ED_CR_STP))
199 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
206 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
209 ed_probe_WD80x3_generic(dev, flags, intr_vals)
212 unsigned short *intr_vals[];
214 struct ed_softc *sc = device_get_softc(dev);
217 u_int memsize, maddr;
218 u_char iptr, isa16bit, sum, totalsum;
219 u_long conf_maddr, conf_msize, irq, junk;
221 sc->chip_type = ED_CHIP_TYPE_DP8390;
223 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
224 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
225 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
229 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
232 * Attempt to do a checksum over the station address PROM. If it
233 * fails, it's probably not a SMC/WD board. There is a problem with
234 * this, though: some clone WD boards don't pass the checksum test.
235 * Danpex boards for one.
237 for (sum = 0, i = 0; i < 8; ++i)
238 sum += ed_asic_inb(sc, ED_WD_PROM + i);
240 if (sum != totalsum) {
243 * Checksum is invalid. This often happens with cheap WD8003E
244 * clones. In this case, the checksum byte (the eighth byte)
245 * seems to always be zero.
247 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
248 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
251 /* reset card to force it into a known state. */
252 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
253 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
255 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
258 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
259 /* wait in the case this card is reading its EEROM */
262 sc->vendor = ED_VENDOR_WD_SMC;
263 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
266 * Set initial values for width/size.
271 case ED_TYPE_WD8003S:
272 sc->type_str = "WD8003S";
274 case ED_TYPE_WD8003E:
275 sc->type_str = "WD8003E";
277 case ED_TYPE_WD8003EB:
278 sc->type_str = "WD8003EB";
280 case ED_TYPE_WD8003W:
281 sc->type_str = "WD8003W";
283 case ED_TYPE_WD8013EBT:
284 sc->type_str = "WD8013EBT";
288 case ED_TYPE_WD8013W:
289 sc->type_str = "WD8013W";
293 case ED_TYPE_WD8013EP: /* also WD8003EP */
294 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
297 sc->type_str = "WD8013EP";
299 sc->type_str = "WD8003EP";
302 case ED_TYPE_WD8013WC:
303 sc->type_str = "WD8013WC";
307 case ED_TYPE_WD8013EBP:
308 sc->type_str = "WD8013EBP";
312 case ED_TYPE_WD8013EPC:
313 sc->type_str = "WD8013EPC";
317 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
318 case ED_TYPE_SMC8216T:
319 if (sc->type == ED_TYPE_SMC8216C) {
320 sc->type_str = "SMC8216/SMC8216C";
322 sc->type_str = "SMC8216T";
325 ed_asic_outb(sc, ED_WD790_HWR,
326 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
327 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
328 case ED_WD790_RAR_SZ64:
331 case ED_WD790_RAR_SZ32:
334 case ED_WD790_RAR_SZ16:
337 case ED_WD790_RAR_SZ8:
338 /* 8216 has 16K shared mem -- 8416 has 8K */
339 if (sc->type == ED_TYPE_SMC8216C) {
340 sc->type_str = "SMC8416C/SMC8416BT";
342 sc->type_str = "SMC8416T";
347 ed_asic_outb(sc, ED_WD790_HWR,
348 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
351 sc->chip_type = ED_CHIP_TYPE_WD790;
353 case ED_TYPE_TOSHIBA1:
354 sc->type_str = "Toshiba1";
358 case ED_TYPE_TOSHIBA4:
359 sc->type_str = "Toshiba4";
369 * Make some adjustments to initial values depending on what is found
372 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
373 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
374 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
379 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
380 &conf_maddr, &conf_msize);
385 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
386 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
387 for (i = 0; i < 8; i++)
388 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
392 * Allow the user to override the autoconfiguration
395 memsize = conf_msize;
398 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
399 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
400 maddr, maddr + memsize);
405 * (note that if the user specifies both of the following flags that
406 * '8bit' mode intentionally has precedence)
408 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
410 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
414 * If possible, get the assigned interrupt number from the card and
417 if ((sc->type & ED_WD_SOFTCONFIG) &&
418 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
421 * Assemble together the encoded interrupt number.
423 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
424 ((ed_asic_inb(sc, ED_WD_IRR) &
425 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
428 * If no interrupt specified (or "?"), use what the board tells us.
430 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
432 if (error && intr_vals[0] != NULL) {
433 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
434 intr_vals[0][iptr], 1);
440 * Enable the interrupt.
442 ed_asic_outb(sc, ED_WD_IRR,
443 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
445 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
446 ed_asic_outb(sc, ED_WD790_HWR,
447 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
448 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
449 (ed_asic_inb(sc, ED_WD790_GCR) &
450 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
451 ed_asic_outb(sc, ED_WD790_HWR,
452 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
455 * If no interrupt specified (or "?"), use what the board tells us.
457 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
459 if (error && intr_vals[1] != NULL) {
460 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
461 intr_vals[1][iptr], 1);
469 ed_asic_outb(sc, ED_WD790_ICR,
470 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
472 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
475 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
479 sc->isa16bit = isa16bit;
482 error = ed_alloc_memory(dev, 0, memsize);
484 printf("*** ed_alloc_memory() failed! (%d)\n", error);
487 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
490 * allocate one xmit buffer if < 16k, two buffers otherwise
492 if ((memsize < 16384) ||
493 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
498 sc->tx_page_start = ED_WD_PAGE_OFFSET;
499 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
500 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
501 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
502 sc->mem_size = memsize;
503 sc->mem_end = sc->mem_start + memsize;
506 * Get station address from on-board ROM
508 for (i = 0; i < ETHER_ADDR_LEN; ++i)
509 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
512 * Set upper address bits and 8/16 bit access to shared memory.
515 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
516 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
518 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
519 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
522 * Enable 16bit access
524 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
527 if (((sc->type & ED_WD_SOFTCONFIG) ||
528 (sc->type == ED_TYPE_TOSHIBA1) ||
529 (sc->type == ED_TYPE_TOSHIBA4) ||
530 (sc->type == ED_TYPE_WD8013EBT)) &&
531 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
532 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
534 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
539 * Set address and enable interface shared memory.
541 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
542 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
543 ed_asic_outb(sc, ED_WD_MSR + 1,
544 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
545 ed_asic_outb(sc, ED_WD_MSR + 2,
546 ((kvtop(sc->mem_start) >> 16) & 0x0f));
547 ed_asic_outb(sc, ED_WD_MSR,
548 ED_WD_MSR_MENB | ED_WD_MSR_POW);
550 ed_asic_outb(sc, ED_WD_MSR,
551 ((kvtop(sc->mem_start) >> 13) &
552 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
554 sc->cr_proto = ED_CR_RD2;
556 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
557 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
558 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
559 ((kvtop(sc->mem_start) >> 11) & 0x40) |
560 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
561 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
566 printf("starting memory performance test at 0x%x, size %d...\n",
567 sc->mem_start, memsize*16384);
568 for (i = 0; i < 16384; i++)
569 bzero(sc->mem_start, memsize);
570 printf("***DONE***\n");
574 * Now zero memory and verify that it is clear
576 bzero(sc->mem_start, memsize);
578 for (i = 0; i < memsize; ++i) {
579 if (sc->mem_start[i]) {
580 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
581 (long long)kvtop(sc->mem_start + i));
584 * Disable 16 bit access to shared memory
587 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
588 ed_asic_outb(sc, ED_WD_MSR, 0x00);
590 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
598 * Disable 16bit access to shared memory - we leave it
599 * disabled so that 1) machines reboot properly when the board
600 * is set 16 bit mode and there are conflicting 8bit
601 * devices/ROMS in the same 128k address space as this boards
602 * shared memory. and 2) so that other 8 bit devices with
603 * shared memory can be used in this 128k region, too.
606 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
607 ed_asic_outb(sc, ED_WD_MSR, 0x00);
609 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
616 ed_probe_WD80x3(dev, port_rid, flags)
621 struct ed_softc *sc = device_get_softc(dev);
623 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
625 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
629 sc->asic_offset = ED_WD_ASIC_OFFSET;
630 sc->nic_offset = ED_WD_NIC_OFFSET;
632 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
636 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
639 ed_probe_3Com(dev, port_rid, flags)
644 struct ed_softc *sc = device_get_softc(dev);
649 u_long conf_maddr, conf_msize, irq, junk;
651 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
655 sc->asic_offset = ED_3COM_ASIC_OFFSET;
656 sc->nic_offset = ED_3COM_NIC_OFFSET;
659 * Verify that the kernel configured I/O address matches the board
662 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
663 case ED_3COM_BCFR_300:
664 if (rman_get_start(sc->port_res) != 0x300)
667 case ED_3COM_BCFR_310:
668 if (rman_get_start(sc->port_res) != 0x310)
671 case ED_3COM_BCFR_330:
672 if (rman_get_start(sc->port_res) != 0x330)
675 case ED_3COM_BCFR_350:
676 if (rman_get_start(sc->port_res) != 0x350)
679 case ED_3COM_BCFR_250:
680 if (rman_get_start(sc->port_res) != 0x250)
683 case ED_3COM_BCFR_280:
684 if (rman_get_start(sc->port_res) != 0x280)
687 case ED_3COM_BCFR_2A0:
688 if (rman_get_start(sc->port_res) != 0x2a0)
691 case ED_3COM_BCFR_2E0:
692 if (rman_get_start(sc->port_res) != 0x2e0)
699 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
700 &conf_maddr, &conf_msize);
705 * Verify that the kernel shared memory address matches the board
706 * configured address.
708 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
709 case ED_3COM_PCFR_DC000:
710 if (conf_maddr != 0xdc000)
713 case ED_3COM_PCFR_D8000:
714 if (conf_maddr != 0xd8000)
717 case ED_3COM_PCFR_CC000:
718 if (conf_maddr != 0xcc000)
721 case ED_3COM_PCFR_C8000:
722 if (conf_maddr != 0xc8000)
731 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
732 * sequence because it'll lock up if the cable isn't connected if we
735 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
738 * Wait for a while, then un-reset it
743 * The 3Com ASIC defaults to rather strange settings for the CR after
744 * a reset - it's important to set it again after the following outb
745 * (this is done when we map the PROM below).
747 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
750 * Wait a bit for the NIC to recover from the reset
754 sc->vendor = ED_VENDOR_3COM;
755 sc->type_str = "3c503";
757 sc->cr_proto = ED_CR_RD2;
760 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
766 * Get station address from on-board ROM
770 * First, map ethernet address PROM over the top of where the NIC
771 * registers normally appear.
773 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
775 for (i = 0; i < ETHER_ADDR_LEN; ++i)
776 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
779 * Unmap PROM - select NIC registers. The proper setting of the
780 * tranceiver is set in ed_init so that the attach code is given a
781 * chance to set the default based on a compile-time config option
783 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
786 * Determine if this is an 8bit or 16bit board
790 * select page 0 registers
792 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
795 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
798 ed_nic_outb(sc, ED_P0_DCR, 0);
801 * select page 2 registers
803 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
806 * The 3c503 forces the WTS bit to a one if this is a 16bit board
808 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
814 * select page 0 registers
816 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
818 error = ed_alloc_memory(dev, 0, memsize);
822 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
823 sc->mem_size = memsize;
824 sc->mem_end = sc->mem_start + memsize;
827 * We have an entire 8k window to put the transmit buffers on the
828 * 16bit boards. But since the 16bit 3c503's shared memory is only
829 * fast enough to overlap the loading of one full-size packet, trying
830 * to load more than 2 buffers can actually leave the transmitter idle
831 * during the load. So 2 seems the best value. (Although a mix of
832 * variable-sized packets might change this assumption. Nonetheless,
833 * we optimize for linear transfers of same-size packets.)
836 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
841 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
842 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
843 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
844 ED_3COM_RX_PAGE_OFFSET_16BIT;
845 sc->mem_ring = sc->mem_start;
848 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
849 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
850 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
851 ED_3COM_TX_PAGE_OFFSET_8BIT;
852 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
855 sc->isa16bit = isa16bit;
858 * Initialize GA page start/stop registers. Probably only needed if
859 * doing DMA, but what the hell.
861 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
862 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
865 * Set IRQ. 3c503 only allows a choice of irq 2-5.
867 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
874 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
877 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
880 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
883 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
886 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
892 * Initialize GA configuration register. Set bank and enable shared
895 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
899 * Initialize "Vector Pointer" registers. These gawd-awful things are
900 * compared to 20 bits of the address on ISA, and if they match, the
901 * shared memory is disabled. We set them to 0xffff0...allegedly the
904 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
905 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
906 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
909 * Zero memory and verify that it is clear
911 bzero(sc->mem_start, memsize);
913 for (i = 0; i < memsize; ++i)
914 if (sc->mem_start[i]) {
915 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
916 (unsigned long long)kvtop(sc->mem_start + i));
923 * Probe and vendor-specific initialization routine for SIC boards
926 ed_probe_SIC(dev, port_rid, flags)
931 struct ed_softc *sc = device_get_softc(dev);
935 u_long conf_maddr, conf_msize;
938 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
942 sc->asic_offset = ED_SIC_ASIC_OFFSET;
943 sc->nic_offset = ED_SIC_NIC_OFFSET;
945 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
946 &conf_maddr, &conf_msize);
952 memsize = conf_msize;
954 error = ed_alloc_memory(dev, 0, memsize);
958 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
959 sc->mem_size = memsize;
961 /* Reset card to force it into a known state. */
962 ed_asic_outb(sc, 0, 0x00);
966 * Here we check the card ROM, if the checksum passes, and the
967 * type code and ethernet address check out, then we know we have
970 ed_asic_outb(sc, 0, 0x81);
973 sum = sc->mem_start[6];
974 for (i = 0; i < ETHER_ADDR_LEN; i++) {
975 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
978 device_printf(dev, "ed_probe_sic: got address %6D\n",
979 sc->arpcom.ac_enaddr, ":");
984 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
985 sc->arpcom.ac_enaddr[2]) == 0) {
989 sc->vendor = ED_VENDOR_SIC;
990 sc->type_str = "SIC";
995 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
997 ed_asic_outb(sc, 0, 0x80);
1001 * Now zero memory and verify that it is clear
1003 bzero(sc->mem_start, sc->mem_size);
1005 for (i = 0; i < sc->mem_size; i++) {
1006 if (sc->mem_start[i]) {
1007 device_printf(dev, "failed to clear shared memory "
1008 "at %llx - check configuration\n",
1009 (long long)kvtop(sc->mem_start + i));
1016 sc->mem_end = sc->mem_start + sc->mem_size;
1019 * allocate one xmit buffer if < 16k, two buffers otherwise
1021 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1026 sc->tx_page_start = 0;
1028 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1029 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1031 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1037 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1040 ed_probe_Novell_generic(dev, flags)
1044 struct ed_softc *sc = device_get_softc(dev);
1046 u_char romdata[16], tmp;
1047 static char test_pattern[32] = "THIS is A memory TEST pattern";
1048 char test_buffer[32];
1050 /* XXX - do Novell-specific probe here */
1052 /* Reset the board */
1053 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1054 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1057 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1060 * I don't know if this is necessary; probably cruft leftover from
1061 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1062 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1063 * non-invasive...but some boards don't seem to reset and I don't have
1064 * complete documentation on what the 'right' thing to do is...so we
1065 * do the invasive thing for now. Yuck.]
1067 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1071 * This is needed because some NE clones apparently don't reset the
1072 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1073 * - this makes the probe invasive! ...Done against my better
1076 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1080 /* Make sure that we really have an 8390 based board */
1081 if (!ed_probe_generic8390(sc))
1084 sc->vendor = ED_VENDOR_NOVELL;
1086 sc->cr_proto = ED_CR_RD2;
1089 * Test the ability to read and write to the NIC memory. This has the
1090 * side affect of determining if this is an NE1000 or an NE2000.
1094 * This prevents packets from being stored in the NIC memory when the
1095 * readmem routine turns on the start bit in the CR.
1097 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1099 /* Temporarily initialize DCR for byte operations */
1100 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1102 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1103 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1108 * Write a test pattern in byte mode. If this fails, then there
1109 * probably isn't any memory at 8k - which likely means that the board
1112 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1113 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1115 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1116 sc->type = ED_TYPE_NE1000;
1117 sc->type_str = "NE1000";
1120 /* neither an NE1000 nor a Linksys - try NE2000 */
1121 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1122 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1123 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1128 * Write a test pattern in word mode. If this also fails, then
1129 * we don't know what this board is.
1131 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1132 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1133 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1134 sc->type = ED_TYPE_NE2000;
1135 sc->type_str = "NE2000";
1142 /* 8k of memory plus an additional 8k if 16bit */
1143 memsize = 8192 + sc->isa16bit * 8192;
1145 #if 0 /* probably not useful - NE boards only come two ways */
1146 /* allow kernel config file overrides */
1147 if (isa_dev->id_msize)
1148 memsize = isa_dev->id_msize;
1151 sc->mem_size = memsize;
1153 /* NIC memory doesn't start at zero on an NE board */
1154 /* The start address is tied to the bus width */
1155 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1156 sc->mem_end = sc->mem_start + memsize;
1157 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1159 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1160 int x, i, mstart = 0, msize = 0;
1161 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1163 for (i = 0; i < ED_PAGE_SIZE; i++)
1166 /* Clear all the memory. */
1167 for (x = 1; x < 256; x++)
1168 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1170 /* Search for the start of RAM. */
1171 for (x = 1; x < 256; x++) {
1172 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1173 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1174 for (i = 0; i < ED_PAGE_SIZE; i++)
1176 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1177 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1178 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1179 mstart = x * ED_PAGE_SIZE;
1180 msize = ED_PAGE_SIZE;
1187 device_printf(dev, "Cannot find start of RAM.\n");
1190 /* Search for the start of RAM. */
1191 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1192 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1193 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1194 for (i = 0; i < ED_PAGE_SIZE; i++)
1196 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1197 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1198 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1199 msize += ED_PAGE_SIZE;
1209 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1212 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1214 sc->mem_size = msize;
1215 sc->mem_start = (caddr_t) mstart;
1216 sc->mem_end = (caddr_t) (msize + mstart);
1217 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1221 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1224 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1229 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1230 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1232 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1234 ed_pio_readmem(sc, 0, romdata, 16);
1235 for (n = 0; n < ETHER_ADDR_LEN; n++)
1236 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1238 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1239 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1240 sc->type_str = "Gateway AT";
1243 /* clear any pending interrupts that might have occurred above */
1244 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1250 ed_probe_Novell(dev, port_rid, flags)
1255 struct ed_softc *sc = device_get_softc(dev);
1258 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1262 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1263 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1265 return ed_probe_Novell_generic(dev, flags);
1268 #define ED_HPP_TEST_SIZE 16
1271 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1272 * (HP Part nos: 27247B and 27252A).
1274 * The card has an asic wrapper around a DS8390 core. The asic handles
1275 * host accesses and offers both standard register IO and memory mapped
1276 * IO. Memory mapped I/O allows better performance at the expense of greater
1277 * chance of an incompatibility with existing ISA cards.
1279 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1280 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1281 * don't allow 32 bit accesses; these are indicated by a bit in the software
1282 * ID register (see if_edreg.h).
1284 * Other caveats are: we should read the MAC address only when the card
1287 * For more information; please consult the CRYNWR packet driver.
1289 * The AUI port is turned on using the "link2" option on the ifconfig
1293 ed_probe_HP_pclanp(dev, port_rid, flags)
1298 struct ed_softc *sc = device_get_softc(dev);
1300 int n; /* temp var */
1301 int memsize; /* mem on board */
1302 u_char checksum; /* checksum of board address */
1303 u_char irq; /* board configured IRQ */
1304 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1305 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1306 u_long conf_maddr, conf_msize, conf_irq, junk;
1308 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1312 /* Fill in basic information */
1313 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1314 sc->nic_offset = ED_HPP_NIC_OFFSET;
1316 sc->chip_type = ED_CHIP_TYPE_DP8390;
1317 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1320 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1323 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1324 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1325 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1326 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1330 * Read the MAC address and verify checksum on the address.
1333 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1334 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1335 checksum += (sc->arpcom.ac_enaddr[n] =
1336 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1338 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1340 if (checksum != 0xFF)
1344 * Verify that the software model number is 0.
1347 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1348 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1349 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1353 * Read in and save the current options configured on card.
1356 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1358 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1359 ED_HPP_OPTION_CHIP_RESET |
1360 ED_HPP_OPTION_ENABLE_IRQ);
1363 * Reset the chip. This requires writing to the option register
1364 * so take care to preserve the other bits.
1367 ed_asic_outw(sc, ED_HPP_OPTION,
1368 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1369 ED_HPP_OPTION_CHIP_RESET)));
1371 DELAY(5000); /* wait for chip reset to complete */
1373 ed_asic_outw(sc, ED_HPP_OPTION,
1374 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1375 ED_HPP_OPTION_CHIP_RESET |
1376 ED_HPP_OPTION_ENABLE_IRQ)));
1380 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1381 return ENXIO; /* reset did not complete */
1384 * Read out configuration information.
1387 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1389 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1392 * Check for impossible IRQ.
1395 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1399 * If the kernel IRQ was specified with a '?' use the cards idea
1400 * of the IRQ. If the kernel IRQ was explicitly specified, it
1401 * should match that of the hardware.
1403 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1406 bus_set_resource(dev, SYS_RES_IRQ, 0,
1407 ed_hpp_intr_val[irq], 1);
1409 if (conf_irq != ed_hpp_intr_val[irq])
1414 * Fill in softconfig info.
1417 sc->vendor = ED_VENDOR_HP;
1418 sc->type = ED_TYPE_HP_PCLANPLUS;
1419 sc->type_str = "HP-PCLAN+";
1421 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1422 sc->mem_start = 0; /* we use offsets inside the card RAM */
1424 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1427 * The board has 32KB of memory. Is there a way to determine
1428 * this programmatically?
1434 * Check if memory mapping of the I/O registers possible.
1437 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1442 * determine the memory address from the board.
1445 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1446 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1449 * Check that the kernel specified start of memory and
1450 * hardware's idea of it match.
1452 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1453 &conf_maddr, &conf_msize);
1457 if (mem_addr != conf_maddr)
1460 error = ed_alloc_memory(dev, 0, memsize);
1464 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1468 * Fill in the rest of the soft config structure.
1472 * The transmit page index.
1475 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1477 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1483 * Memory description
1486 sc->mem_size = memsize;
1487 sc->mem_ring = sc->mem_start +
1488 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1489 sc->mem_end = sc->mem_start + sc->mem_size;
1492 * Receive area starts after the transmit area and
1493 * continues till the end of memory.
1496 sc->rec_page_start = sc->tx_page_start +
1497 (sc->txb_cnt * ED_TXBUF_SIZE);
1498 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1501 sc->cr_proto = 0; /* value works */
1504 * Set the wrap registers for string I/O reads.
1507 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1508 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1509 ((sc->rec_page_start / ED_PAGE_SIZE) |
1510 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1513 * Reset the register page to normal operation.
1516 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1519 * Verify that we can read/write from adapter memory.
1520 * Create test pattern.
1523 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1525 test_pattern[n] = (n*n) ^ ~n;
1528 #undef ED_HPP_TEST_SIZE
1531 * Check that the memory is accessible thru the I/O ports.
1532 * Write out the contents of "test_pattern", read back
1533 * into "test_buffer" and compare the two for any
1537 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1539 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1540 sizeof(test_pattern));
1541 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1542 test_buffer, sizeof(test_pattern));
1544 if (bcmp(test_pattern, test_buffer,
1545 sizeof(test_pattern)))
1554 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1558 ed_hpp_set_physical_link(struct ed_softc *sc)
1560 struct ifnet *ifp = &sc->arpcom.ac_if;
1563 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1564 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1566 if (ifp->if_flags & IFF_ALTPHYS) {
1572 lan_page |= ED_HPP_LAN_AUI;
1574 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1575 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1581 * Use the ThinLan interface
1584 lan_page &= ~ED_HPP_LAN_AUI;
1586 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1587 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1592 * Wait for the lan card to re-initialize itself
1595 DELAY(150000); /* wait 150 ms */
1598 * Restore normal pages.
1601 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1606 * Allocate a port resource with the given resource id.
1609 ed_alloc_port(dev, rid, size)
1614 struct ed_softc *sc = device_get_softc(dev);
1615 struct resource *res;
1617 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1618 0ul, ~0ul, size, RF_ACTIVE);
1622 sc->port_used = size;
1630 * Allocate a memory resource with the given resource id.
1633 ed_alloc_memory(dev, rid, size)
1638 struct ed_softc *sc = device_get_softc(dev);
1639 struct resource *res;
1641 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1642 0ul, ~0ul, size, RF_ACTIVE);
1646 sc->mem_used = size;
1654 * Allocate an irq resource with the given resource id.
1657 ed_alloc_irq(dev, rid, flags)
1662 struct ed_softc *sc = device_get_softc(dev);
1663 struct resource *res;
1665 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1666 (RF_ACTIVE | flags));
1677 * Release all resources
1680 ed_release_resources(dev)
1683 struct ed_softc *sc = device_get_softc(dev);
1686 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1687 sc->port_rid, sc->port_res);
1688 bus_release_resource(dev, SYS_RES_IOPORT,
1689 sc->port_rid, sc->port_res);
1693 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1694 sc->mem_rid, sc->mem_res);
1695 bus_release_resource(dev, SYS_RES_MEMORY,
1696 sc->mem_rid, sc->mem_res);
1700 bus_deactivate_resource(dev, SYS_RES_IRQ,
1701 sc->irq_rid, sc->irq_res);
1702 bus_release_resource(dev, SYS_RES_IRQ,
1703 sc->irq_rid, sc->irq_res);
1709 * Install interface into kernel networking data structures
1712 ed_attach(device_t dev)
1714 struct ed_softc *sc = device_get_softc(dev);
1715 struct ifnet *ifp = &sc->arpcom.ac_if;
1717 callout_init(&sc->ed_timer);
1719 * Set interface to stopped condition (reset)
1724 * Initialize ifnet structure
1727 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1728 ifp->if_mtu = ETHERMTU;
1729 ifp->if_start = ed_start;
1730 ifp->if_ioctl = ed_ioctl;
1731 ifp->if_watchdog = ed_watchdog;
1732 ifp->if_init = ed_init;
1733 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1734 ifq_set_ready(&ifp->if_snd);
1735 ifp->if_linkmib = &sc->mibdata;
1736 ifp->if_linkmiblen = sizeof sc->mibdata;
1737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1739 * XXX - should do a better job.
1741 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1742 sc->mibdata.dot3StatsEtherChipSet =
1743 DOT3CHIPSET(dot3VendorWesternDigital,
1744 dot3ChipSetWesternDigital83C790);
1746 sc->mibdata.dot3StatsEtherChipSet =
1747 DOT3CHIPSET(dot3VendorNational,
1748 dot3ChipSetNational8390);
1749 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1752 * Set default state for ALTPHYS flag (used to disable the
1753 * tranceiver for AUI operation), based on compile-time
1756 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1757 ifp->if_flags |= IFF_ALTPHYS;
1760 * Attach the interface
1762 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1764 /* device attach does transition from UNCONFIGURED to IDLE state */
1766 if (sc->type_str && (*sc->type_str != 0))
1767 printf("type %s ", sc->type_str);
1769 printf("type unknown (0x%x) ", sc->type);
1771 if (sc->vendor == ED_VENDOR_HP)
1772 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1773 "16-bit" : "32-bit",
1774 sc->hpp_mem_start ? "memory mapped" : "regular");
1776 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1778 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1779 (sc->vendor == ED_VENDOR_HP)) &&
1780 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1792 struct ed_softc *sc = ifp->if_softc;
1802 * Stop interface and re-initialize.
1811 * Take interface offline.
1815 struct ed_softc *sc;
1819 #ifndef ED_NO_MIIBUS
1820 callout_stop(&sc->ed_timer);
1825 * Stop everything on the interface, and select page 0 registers.
1827 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1830 * Wait for interface to enter stopped state, but limit # of checks to
1831 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1832 * just in case it's an old one.
1834 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1835 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1839 * Device timeout/watchdog routine. Entered if the device neglects to
1840 * generate an interrupt after a transmit has been started on it.
1846 struct ed_softc *sc = ifp->if_softc;
1850 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1856 #ifndef ED_NO_MIIBUS
1861 struct ed_softc *sc = arg;
1862 struct mii_data *mii;
1871 if (sc->miibus != NULL) {
1872 mii = device_get_softc(sc->miibus);
1876 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1883 * Initialize device.
1889 struct ed_softc *sc = xsc;
1890 struct ifnet *ifp = &sc->arpcom.ac_if;
1900 /* address not known */
1901 if (TAILQ_EMPTY(&ifp->if_addrhead)) { /* unlikely? XXX */
1907 * Initialize the NIC in the exact order outlined in the NS manual.
1908 * This init procedure is "mandatory"...don't change what or when
1912 /* reset transmitter flags */
1918 sc->txb_next_tx = 0;
1920 /* This variable is used below - don't move this assignment */
1921 sc->next_packet = sc->rec_page_start + 1;
1924 * Set interface for page 0, Remote DMA complete, Stopped
1926 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1931 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1932 * order=80x86, word-wide DMA xfers,
1934 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1938 * Same as above, but byte-wide DMA xfers
1940 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1944 * Clear Remote Byte Count Registers
1946 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1947 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1950 * For the moment, don't store incoming packets in memory.
1952 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1955 * Place NIC in internal loopback mode
1957 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1960 * Initialize transmit/receive (ring-buffer) Page Start
1962 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1963 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1964 /* Set lower bits of byte addressable framing to 0 */
1965 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1966 ed_nic_outb(sc, 0x09, 0);
1969 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1971 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1972 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1975 * Clear all interrupts. A '1' in each bit position clears the
1976 * corresponding flag.
1978 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1981 * Enable the following interrupts: receive/transmit complete,
1982 * receive/transmit error, and Receiver OverWrite.
1984 * Counter overflow and Remote DMA complete are *not* enabled.
1986 ed_nic_outb(sc, ED_P0_IMR,
1987 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1990 * Program Command Register for page 1
1992 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1995 * Copy out our station address
1997 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1998 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
2001 * Set Current Page pointer to next_packet (initialized above)
2003 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
2006 * Program Receiver Configuration Register and multicast filter. CR is
2007 * set to page 0 on return.
2012 * Take interface out of loopback
2014 ed_nic_outb(sc, ED_P0_TCR, 0);
2017 * If this is a 3Com board, the tranceiver must be software enabled
2018 * (there is no settable hardware default).
2020 if (sc->vendor == ED_VENDOR_3COM) {
2021 if (ifp->if_flags & IFF_ALTPHYS) {
2022 ed_asic_outb(sc, ED_3COM_CR, 0);
2024 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2028 #ifndef ED_NO_MIIBUS
2029 if (sc->miibus != NULL) {
2030 struct mii_data *mii;
2031 mii = device_get_softc(sc->miibus);
2036 * Set 'running' flag, and clear output active flag.
2038 ifp->if_flags |= IFF_RUNNING;
2039 ifp->if_flags &= ~IFF_OACTIVE;
2042 * ...and attempt to start output
2046 #ifndef ED_NO_MIIBUS
2047 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
2054 * This routine actually starts the transmission on the interface
2056 static __inline void
2058 struct ed_softc *sc;
2060 struct ifnet *ifp = (struct ifnet *)sc;
2065 len = sc->txb_len[sc->txb_next_tx];
2068 * Set NIC for page 0 register access
2070 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2073 * Set TX buffer start page
2075 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2076 sc->txb_next_tx * ED_TXBUF_SIZE);
2081 ed_nic_outb(sc, ED_P0_TBCR0, len);
2082 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2085 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2087 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2091 * Point to next transmit buffer slot and wrap if necessary.
2094 if (sc->txb_next_tx == sc->txb_cnt)
2095 sc->txb_next_tx = 0;
2098 * Set a timer just in case we never hear from the board again
2104 * Start output on interface.
2105 * We make two assumptions here:
2106 * 1) that the current priority is set to splimp _before_ this code
2107 * is called *and* is returned to the appropriate priority after
2109 * 2) that the IFF_OACTIVE flag is checked before this code is called
2110 * (i.e. that the output part of the interface is idle)
2116 struct ed_softc *sc = ifp->if_softc;
2117 struct mbuf *m0, *m;
2122 printf("ed_start(%p) GONE\n",ifp);
2128 * First, see if there are buffered packets and an idle transmitter -
2129 * should never happen at this point.
2131 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2132 printf("ed: packets buffered, but transmitter idle\n");
2137 * See if there is room to put another packet in the buffer.
2139 if (sc->txb_inuse == sc->txb_cnt) {
2142 * No room. Indicate this to the outside world and exit.
2144 ifp->if_flags |= IFF_OACTIVE;
2147 m = ifq_dequeue(&ifp->if_snd);
2151 * We are using the !OACTIVE flag to indicate to the outside
2152 * world that we can accept an additional packet rather than
2153 * that the transmitter is _actually_ active. Indeed, the
2154 * transmitter may be active, but if we haven't filled all the
2155 * buffers with data then we still want to accept more.
2157 ifp->if_flags &= ~IFF_OACTIVE;
2162 * Copy the mbuf chain into the transmit buffer
2167 /* txb_new points to next open buffer slot */
2168 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2170 if (sc->mem_shared) {
2173 * Special case setup for 16 bit boards...
2176 switch (sc->vendor) {
2179 * For 16bit 3Com boards (which have 16k of
2180 * memory), we have the xmit buffers in a
2181 * different page of memory ('page 0') - so
2184 case ED_VENDOR_3COM:
2185 ed_asic_outb(sc, ED_3COM_GACFR,
2186 ED_3COM_GACFR_RSEL);
2190 * Enable 16bit access to shared memory on
2193 case ED_VENDOR_WD_SMC:
2194 ed_asic_outb(sc, ED_WD_LAAR,
2195 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2196 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2197 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2202 for (len = 0; m != 0; m = m->m_next) {
2203 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2209 * Restore previous shared memory access
2212 switch (sc->vendor) {
2213 case ED_VENDOR_3COM:
2214 ed_asic_outb(sc, ED_3COM_GACFR,
2215 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2217 case ED_VENDOR_WD_SMC:
2218 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2219 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2221 ed_asic_outb(sc, ED_WD_LAAR,
2222 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2227 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2234 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2239 * Point to next buffer slot and wrap if necessary.
2242 if (sc->txb_new == sc->txb_cnt)
2245 if (sc->xmit_busy == 0)
2253 * Loop back to the top to possibly buffer more packets
2259 * Ethernet interface receiver interrupt.
2261 static __inline void
2263 struct ed_softc *sc;
2265 struct ifnet *ifp = &sc->arpcom.ac_if;
2268 struct ed_ring packet_hdr;
2275 * Set NIC to page 1 registers to get 'current' pointer
2277 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2280 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2281 * i.e. it points to where new data has been buffered. The 'CURR'
2282 * (current) register points to the logical end of the ring-buffer -
2283 * i.e. it points to where additional new data will be added. We loop
2284 * here until the logical beginning equals the logical end (or in
2285 * other words, until the ring-buffer is empty).
2287 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2289 /* get pointer to this buffer's header structure */
2290 packet_ptr = sc->mem_ring +
2291 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2294 * The byte count includes a 4 byte header that was added by
2298 packet_hdr = *(struct ed_ring *) packet_ptr;
2300 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2301 sizeof(packet_hdr));
2302 len = packet_hdr.count;
2303 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2304 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2306 * Length is a wild value. There's a good chance that
2307 * this was caused by the NIC being old and buggy.
2308 * The bug is that the length low byte is duplicated in
2309 * the high byte. Try to recalculate the length based on
2310 * the pointer to the next packet.
2313 * NOTE: sc->next_packet is pointing at the current packet.
2315 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2316 if (packet_hdr.next_packet >= sc->next_packet) {
2317 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2319 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2320 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2323 * because buffers are aligned on 256-byte boundary,
2324 * the length computed above is off by 256 in almost
2325 * all cases. Fix it...
2329 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2330 + sizeof(struct ed_ring)))
2331 sc->mibdata.dot3StatsFrameTooLongs++;
2334 * Be fairly liberal about what we allow as a "reasonable" length
2335 * so that a [crufty] packet will make it to BPF (and can thus
2336 * be analyzed). Note that all that is really important is that
2337 * we have a length that will fit into one mbuf cluster or less;
2338 * the upper layer protocols can then figure out the length from
2339 * their own length field(s).
2340 * But make sure that we have at least a full ethernet header
2341 * or we would be unable to call ether_input() later.
2343 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2344 (len <= MCLBYTES) &&
2345 (packet_hdr.next_packet >= sc->rec_page_start) &&
2346 (packet_hdr.next_packet < sc->rec_page_stop)) {
2350 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2351 len - sizeof(struct ed_ring));
2355 * Really BAD. The ring pointers are corrupted.
2358 "%s: NIC memory corrupt - invalid packet length %d\n",
2359 ifp->if_xname, len);
2366 * Update next packet pointer
2368 sc->next_packet = packet_hdr.next_packet;
2371 * Update NIC boundry pointer - being careful to keep it one
2372 * buffer behind. (as recommended by NS databook)
2374 boundry = sc->next_packet - 1;
2375 if (boundry < sc->rec_page_start)
2376 boundry = sc->rec_page_stop - 1;
2379 * Set NIC to page 0 registers to update boundry register
2381 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2383 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2386 * Set NIC to page 1 registers before looping to top (prepare
2387 * to get 'CURR' current pointer)
2389 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2394 * Ethernet interface interrupt processor
2400 struct ed_softc *sc = (struct ed_softc*) arg;
2401 struct ifnet *ifp = (struct ifnet *)sc;
2408 * Set NIC to page 0 registers
2410 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2413 * loop until there are no more new interrupts. When the card
2414 * goes away, the hardware will read back 0xff. Looking at
2415 * the interrupts, it would appear that 0xff is impossible,
2416 * or at least extremely unlikely.
2418 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2421 * reset all the bits that we are 'acknowledging' by writing a
2422 * '1' to each bit position that was set (writing a '1'
2425 ed_nic_outb(sc, ED_P0_ISR, isr);
2428 * XXX workaround for AX88190
2429 * We limit this to 5000 iterations. At 1us per inb/outb,
2430 * this translates to about 15ms, which should be plenty
2431 * of time, and also gives protection in the card eject
2434 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2435 count = 5000; /* 15ms */
2436 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2437 ed_nic_outb(sc, ED_P0_ISR,0);
2438 ed_nic_outb(sc, ED_P0_ISR,isr);
2445 * Handle transmitter interrupts. Handle these first because
2446 * the receiver will reset the board under some conditions.
2448 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2449 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2452 * Check for transmit error. If a TX completed with an
2453 * error, we end up throwing the packet away. Really
2454 * the only error that is possible is excessive
2455 * collisions, and in this case it is best to allow
2456 * the automatic mechanisms of TCP to backoff the
2457 * flow. Of course, with UDP we're screwed, but this
2458 * is expected when a network is heavily loaded.
2460 (void) ed_nic_inb(sc, ED_P0_TSR);
2461 if (isr & ED_ISR_TXE) {
2465 * Excessive collisions (16)
2467 tsr = ed_nic_inb(sc, ED_P0_TSR);
2468 if ((tsr & ED_TSR_ABT)
2469 && (collisions == 0)) {
2472 * When collisions total 16, the
2473 * P0_NCR will indicate 0, and the
2477 sc->mibdata.dot3StatsExcessiveCollisions++;
2478 sc->mibdata.dot3StatsCollFrequencies[15]++;
2480 if (tsr & ED_TSR_OWC)
2481 sc->mibdata.dot3StatsLateCollisions++;
2482 if (tsr & ED_TSR_CDH)
2483 sc->mibdata.dot3StatsSQETestErrors++;
2484 if (tsr & ED_TSR_CRS)
2485 sc->mibdata.dot3StatsCarrierSenseErrors++;
2486 if (tsr & ED_TSR_FU)
2487 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2490 * update output errors counter
2496 * Update total number of successfully
2497 * transmitted packets.
2503 * reset tx busy and output active flags
2506 ifp->if_flags &= ~IFF_OACTIVE;
2509 * clear watchdog timer
2514 * Add in total number of collisions on last
2517 ifp->if_collisions += collisions;
2518 switch(collisions) {
2523 sc->mibdata.dot3StatsSingleCollisionFrames++;
2524 sc->mibdata.dot3StatsCollFrequencies[0]++;
2527 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2529 dot3StatsCollFrequencies[collisions-1]
2535 * Decrement buffer in-use count if not zero (can only
2536 * be zero if a transmitter interrupt occured while
2537 * not actually transmitting). If data is ready to
2538 * transmit, start it transmitting, otherwise defer
2539 * until after handling receiver
2541 if (sc->txb_inuse && --sc->txb_inuse)
2546 * Handle receiver interrupts
2548 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2551 * Overwrite warning. In order to make sure that a
2552 * lockup of the local DMA hasn't occurred, we reset
2553 * and re-init the NIC. The NSC manual suggests only a
2554 * partial reset/re-init is necessary - but some chips
2555 * seem to want more. The DMA lockup has been seen
2556 * only with early rev chips - Methinks this bug was
2557 * fixed in later revs. -DG
2559 if (isr & ED_ISR_OVW) {
2563 "%s: warning - receiver ring buffer overrun\n",
2568 * Stop/reset/re-init NIC
2574 * Receiver Error. One or more of: CRC error,
2575 * frame alignment error FIFO overrun, or
2578 if (isr & ED_ISR_RXE) {
2580 rsr = ed_nic_inb(sc, ED_P0_RSR);
2581 if (rsr & ED_RSR_CRC)
2582 sc->mibdata.dot3StatsFCSErrors++;
2583 if (rsr & ED_RSR_FAE)
2584 sc->mibdata.dot3StatsAlignmentErrors++;
2585 if (rsr & ED_RSR_FO)
2586 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2589 if_printf("receive error %x\n",
2590 ed_nic_inb(sc, ED_P0_RSR));
2595 * Go get the packet(s) XXX - Doing this on an
2596 * error is dubious because there shouldn't be
2597 * any data to get (we've configured the
2598 * interface to not accept packets with
2603 * Enable 16bit access to shared memory first
2607 (sc->vendor == ED_VENDOR_WD_SMC)) {
2609 ed_asic_outb(sc, ED_WD_LAAR,
2610 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2611 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2612 ed_asic_outb(sc, ED_WD_MSR,
2618 /* disable 16bit access */
2620 (sc->vendor == ED_VENDOR_WD_SMC)) {
2622 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2623 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2625 ed_asic_outb(sc, ED_WD_LAAR,
2626 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2632 * If it looks like the transmitter can take more data,
2633 * attempt to start output on the interface. This is done
2634 * after handling the receiver to give the receiver priority.
2636 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2640 * return NIC CR to standard state: page 0, remote DMA
2641 * complete, start (toggling the TXP bit off, even if was just
2642 * set in the transmit routine, is *okay* - it is 'edge'
2643 * triggered from low to high)
2645 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2648 * If the Network Talley Counters overflow, read them to reset
2649 * them. It appears that old 8390's won't clear the ISR flag
2650 * otherwise - resulting in an infinite loop.
2652 if (isr & ED_ISR_CNT) {
2653 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2654 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2655 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2661 * Process an ioctl request. This code needs some work - it looks
2665 ed_ioctl(ifp, command, data, cr)
2671 struct ed_softc *sc = ifp->if_softc;
2672 #ifndef ED_NO_MIIBUS
2673 struct ifreq *ifr = (struct ifreq *)data;
2674 struct mii_data *mii;
2680 if (sc == NULL || sc->gone) {
2681 ifp->if_flags &= ~IFF_RUNNING;
2690 * If the interface is marked up and stopped, then start it.
2691 * If it is marked down and running, then stop it.
2693 if (ifp->if_flags & IFF_UP) {
2694 if ((ifp->if_flags & IFF_RUNNING) == 0)
2697 if (ifp->if_flags & IFF_RUNNING) {
2699 ifp->if_flags &= ~IFF_RUNNING;
2704 * Promiscuous flag may have changed, so reprogram the RCR.
2709 * An unfortunate hack to provide the (required) software
2710 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2711 * disables the tranceiver if set.
2713 if (sc->vendor == ED_VENDOR_3COM) {
2714 if (ifp->if_flags & IFF_ALTPHYS) {
2715 ed_asic_outb(sc, ED_3COM_CR, 0);
2717 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2719 } else if (sc->vendor == ED_VENDOR_HP)
2720 ed_hpp_set_physical_link(sc);
2726 * Multicast list has changed; set the hardware filter
2733 #ifndef ED_NO_MIIBUS
2736 if (sc->miibus == NULL) {
2740 mii = device_get_softc(sc->miibus);
2741 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2746 error = ether_ioctl(ifp, command, data);
2756 * Given a source and destination address, copy 'amount' of a packet from
2757 * the ring buffer into a linear destination buffer. Takes into account
2760 static __inline char *
2761 ed_ring_copy(sc, src, dst, amount)
2762 struct ed_softc *sc;
2769 /* does copy wrap to lower addr in ring buffer? */
2770 if (src + amount > sc->mem_end) {
2771 tmp_amount = sc->mem_end - src;
2773 /* copy amount up to end of NIC memory */
2775 bcopy(src, dst, tmp_amount);
2777 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2779 amount -= tmp_amount;
2784 bcopy(src, dst, amount);
2786 ed_pio_readmem(sc, (int)src, dst, amount);
2788 return (src + amount);
2792 * Retreive packet from shared memory and send to the next level up via
2796 ed_get_packet(sc, buf, len)
2797 struct ed_softc *sc;
2801 struct ifnet *ifp = &sc->arpcom.ac_if;
2802 struct ether_header *eh;
2806 * Allocate a header mbuf.
2807 * We always put the received packet in a single buffer -
2808 * either with just an mbuf header or in a cluster attached
2809 * to the header. The +2 is to compensate for the alignment
2812 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL);
2815 m->m_pkthdr.rcvif = ifp;
2816 m->m_pkthdr.len = m->m_len = len;
2819 * The +2 is to longword align the start of the real packet.
2820 * This is important for NFS.
2823 eh = mtod(m, struct ether_header *);
2826 * Don't read in the entire packet if we know we're going to drop it
2827 * and no bpf is active.
2829 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
2832 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2833 bif = bridge_in_ptr(ifp, eh) ;
2834 if (bif == BDG_DROP) {
2838 if (len > ETHER_HDR_LEN)
2839 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2840 (char *)(eh + 1), len - ETHER_HDR_LEN);
2843 * Get packet, including link layer address, from interface.
2845 ed_ring_copy(sc, buf, (char *)eh, len);
2847 m->m_pkthdr.len = m->m_len = len;
2849 (*ifp->if_input)(ifp, m);
2853 * Supporting routines
2857 * Given a NIC memory source address and a host memory destination
2858 * address, copy 'amount' from NIC to host using Programmed I/O.
2859 * The 'amount' is rounded up to a word - okay as long as mbufs
2861 * This routine is currently Novell-specific.
2864 ed_pio_readmem(sc, src, dst, amount)
2865 struct ed_softc *sc;
2868 unsigned short amount;
2870 /* HP PC Lan+ cards need special handling */
2871 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2872 ed_hpp_readmem(sc, src, dst, amount);
2876 /* Regular Novell cards */
2877 /* select page 0 registers */
2878 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2880 /* round up to a word */
2884 /* set up DMA byte count */
2885 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2886 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2888 /* set up source address in NIC mem */
2889 ed_nic_outb(sc, ED_P0_RSAR0, src);
2890 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2892 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2895 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2897 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2902 * Stripped down routine for writing a linear buffer to NIC memory.
2903 * Only used in the probe routine to test the memory. 'len' must
2907 ed_pio_writemem(sc, src, dst, len)
2908 struct ed_softc *sc;
2913 int maxwait = 200; /* about 240us */
2915 /* select page 0 registers */
2916 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2918 /* reset remote DMA complete flag */
2919 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2921 /* set up DMA byte count */
2922 ed_nic_outb(sc, ED_P0_RBCR0, len);
2923 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2925 /* set up destination address in NIC mem */
2926 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2927 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2929 /* set remote DMA write */
2930 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2933 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2935 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2939 * Wait for remote DMA complete. This is necessary because on the
2940 * transmit side, data is handled internally by the NIC in bursts and
2941 * we can't start another remote DMA until this one completes. Not
2942 * waiting causes really bad things to happen - like the NIC
2943 * irrecoverably jamming the ISA bus.
2945 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2949 * Write an mbuf chain to the destination NIC memory address using
2953 ed_pio_write_mbufs(sc, m, dst)
2954 struct ed_softc *sc;
2958 struct ifnet *ifp = (struct ifnet *)sc;
2959 unsigned short total_len, dma_len;
2961 int maxwait = 200; /* about 240us */
2963 /* HP PC Lan+ cards need special handling */
2964 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2965 return ed_hpp_write_mbufs(sc, m, dst);
2968 /* Regular Novell cards */
2969 /* First, count up the total number of bytes to copy */
2970 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2971 total_len += mp->m_len;
2973 dma_len = total_len;
2974 if (sc->isa16bit && (dma_len & 1))
2977 /* select page 0 registers */
2978 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2980 /* reset remote DMA complete flag */
2981 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2983 /* set up DMA byte count */
2984 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2985 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2987 /* set up destination address in NIC mem */
2988 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2989 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2991 /* set remote DMA write */
2992 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2995 * Transfer the mbuf chain to the NIC memory.
2996 * 16-bit cards require that data be transferred as words, and only words.
2997 * So that case requires some extra code to patch over odd-length mbufs.
3000 if (!sc->isa16bit) {
3001 /* NE1000s are easy */
3004 ed_asic_outsb(sc, ED_NOVELL_DATA,
3005 m->m_data, m->m_len);
3010 /* NE2000s are a pain */
3011 unsigned char *data;
3013 unsigned char savebyte[2];
3020 data = mtod(m, caddr_t);
3021 /* finish the last word */
3023 savebyte[1] = *data;
3024 ed_asic_outw(sc, ED_NOVELL_DATA,
3025 *(u_short *)savebyte);
3030 /* output contiguous words */
3032 ed_asic_outsw(sc, ED_NOVELL_DATA,
3037 /* save last byte, if necessary */
3039 savebyte[0] = *data;
3045 /* spit last byte */
3047 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
3052 * Wait for remote DMA complete. This is necessary because on the
3053 * transmit side, data is handled internally by the NIC in bursts and
3054 * we can't start another remote DMA until this one completes. Not
3055 * waiting causes really bad things to happen - like the NIC
3056 * irrecoverably jamming the ISA bus.
3058 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3061 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
3070 * Support routines to handle the HP PC Lan+ card.
3074 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3079 ed_hpp_readmem(sc, src, dst, amount)
3080 struct ed_softc *sc;
3083 unsigned short amount;
3086 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3089 /* Program the source address in RAM */
3090 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3093 * The HP PC Lan+ card supports word reads as well as
3094 * a memory mapped i/o port that is aliased to every
3095 * even address on the board.
3098 if (sc->hpp_mem_start) {
3100 /* Enable memory mapped access. */
3101 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3102 ~(ED_HPP_OPTION_MEM_DISABLE |
3103 ED_HPP_OPTION_BOOT_ROM_ENB));
3105 if (use_32bit_access && (amount > 3)) {
3106 u_int32_t *dl = (u_int32_t *) dst;
3107 volatile u_int32_t *const sl =
3108 (u_int32_t *) sc->hpp_mem_start;
3109 u_int32_t *const fence = dl + (amount >> 2);
3111 /* Copy out NIC data. We could probably write this
3112 as a `movsl'. The currently generated code is lousy.
3118 dst += (amount & ~3);
3123 /* Finish off any words left, as a series of short reads */
3125 u_short *d = (u_short *) dst;
3126 volatile u_short *const s =
3127 (u_short *) sc->hpp_mem_start;
3128 u_short *const fence = d + (amount >> 1);
3130 /* Copy out NIC data. */
3135 dst += (amount & ~1);
3140 * read in a byte; however we need to always read 16 bits
3141 * at a time or the hardware gets into a funny state
3145 /* need to read in a short and copy LSB */
3146 volatile u_short *const s =
3147 (volatile u_short *) sc->hpp_mem_start;
3152 /* Restore Boot ROM access. */
3154 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3158 /* Read in data using the I/O port */
3159 if (use_32bit_access && (amount > 3)) {
3160 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3161 dst += (amount & ~3);
3165 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3166 dst += (amount & ~1);
3169 if (amount == 1) { /* read in a short and keep the LSB */
3170 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3176 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3178 * Only used in the probe routine to test the memory. 'len' must
3182 ed_hpp_writemem(sc, src, dst, len)
3183 struct ed_softc *sc;
3188 /* reset remote DMA complete flag */
3189 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3191 /* program the write address in RAM */
3192 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3194 if (sc->hpp_mem_start) {
3195 u_short *s = (u_short *) src;
3196 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3197 u_short *const fence = s + (len >> 1);
3200 * Enable memory mapped access.
3203 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3204 ~(ED_HPP_OPTION_MEM_DISABLE |
3205 ED_HPP_OPTION_BOOT_ROM_ENB));
3208 * Copy to NIC memory.
3215 * Restore Boot ROM access.
3218 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3221 /* write data using I/O writes */
3222 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3227 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3228 * outsw() or via the memory mapped interface to the same register.
3229 * Writes have to be in word units; byte accesses won't work and may cause
3230 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3235 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3238 unsigned short total_len;
3239 unsigned char savebyte[2];
3240 volatile u_short * const d =
3241 (volatile u_short *) sc->hpp_mem_start;
3242 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3244 /* select page 0 registers */
3245 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3247 /* reset remote DMA complete flag */
3248 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3250 /* program the write address in RAM */
3251 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3253 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3254 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3255 ~(ED_HPP_OPTION_MEM_DISABLE |
3256 ED_HPP_OPTION_BOOT_ROM_ENB));
3261 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3263 total_len += (len = m->m_len);
3265 caddr_t data = mtod(m, caddr_t);
3266 /* finish the last word of the previous mbuf */
3268 savebyte[1] = *data;
3269 *d = *((u_short *) savebyte);
3270 data++; len--; wantbyte = 0;
3272 /* output contiguous words */
3273 if ((len > 3) && (use_32bit_accesses)) {
3274 volatile u_int32_t *const dl =
3275 (volatile u_int32_t *) d;
3276 u_int32_t *sl = (u_int32_t *) data;
3277 u_int32_t *fence = sl + (len >> 2);
3285 /* finish off remain 16 bit writes */
3287 u_short *s = (u_short *) data;
3288 u_short *fence = s + (len >> 1);
3296 /* save last byte if needed */
3297 if ((wantbyte = (len == 1)) != 0)
3298 savebyte[0] = *data;
3300 m = m->m_next; /* to next mbuf */
3302 if (wantbyte) /* write last byte */
3303 *d = *((u_short *) savebyte);
3305 /* use programmed I/O */
3307 total_len += (len = m->m_len);
3309 caddr_t data = mtod(m, caddr_t);
3310 /* finish the last word of the previous mbuf */
3312 savebyte[1] = *data;
3313 ed_asic_outw(sc, ED_HPP_PAGE_4,
3314 *((u_short *)savebyte));
3319 /* output contiguous words */
3320 if ((len > 3) && use_32bit_accesses) {
3321 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3326 /* finish off remaining 16 bit accesses */
3328 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3333 if ((wantbyte = (len == 1)) != 0)
3334 savebyte[0] = *data;
3339 if (wantbyte) /* spit last byte */
3340 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3344 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3345 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3350 #ifndef ED_NO_MIIBUS
3352 * MII bus support routines.
3355 ed_miibus_readreg(dev, phy, reg)
3359 struct ed_softc *sc = device_get_softc(dev);
3369 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3370 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3371 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3372 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3373 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3375 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3376 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3377 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3381 return (failed ? 0 : val);
3385 ed_miibus_writereg(dev, phy, reg, data)
3389 struct ed_softc *sc = device_get_softc(dev);
3398 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3399 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3400 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3401 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3402 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3403 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3404 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3405 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3414 struct ed_softc *sc;
3415 struct mii_data *mii;
3418 if (sc->gone || sc->miibus == NULL)
3421 mii = device_get_softc(sc->miibus);
3422 return mii_mediachg(mii);
3426 ed_ifmedia_sts(ifp, ifmr)
3428 struct ifmediareq *ifmr;
3430 struct ed_softc *sc;
3431 struct mii_data *mii;
3434 if (sc->gone || sc->miibus == NULL)
3437 mii = device_get_softc(sc->miibus);
3439 ifmr->ifm_active = mii->mii_media_active;
3440 ifmr->ifm_status = mii->mii_media_status;
3444 ed_child_detached(dev, child)
3448 struct ed_softc *sc;
3450 sc = device_get_softc(dev);
3451 if (child == sc->miibus)
3458 struct ed_softc *sc;
3460 struct ifnet *ifp = (struct ifnet *)sc;
3464 /* Bit 6 in AX88190 RCR register must be set. */
3465 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3470 /* set page 1 registers */
3471 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3473 if (ifp->if_flags & IFF_PROMISC) {
3476 * Reconfigure the multicast filter.
3478 for (i = 0; i < 8; i++)
3479 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3482 * And turn on promiscuous mode. Also enable reception of
3483 * runts and packets with CRC & alignment errors.
3485 /* Set page 0 registers */
3486 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3488 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3489 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3491 /* set up multicast addresses and filter modes */
3492 if (ifp->if_flags & IFF_MULTICAST) {
3495 if (ifp->if_flags & IFF_ALLMULTI) {
3496 mcaf[0] = 0xffffffff;
3497 mcaf[1] = 0xffffffff;
3499 ds_getmcaf(sc, mcaf);
3502 * Set multicast filter on chip.
3504 for (i = 0; i < 8; i++)
3505 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3507 /* Set page 0 registers */
3508 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3510 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3514 * Initialize multicast address hashing registers to
3515 * not accept multicasts.
3517 for (i = 0; i < 8; ++i)
3518 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3520 /* Set page 0 registers */
3521 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3523 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3530 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3534 * Compute crc for ethernet address
3538 const uint8_t *addr;
3540 #define ED_POLYNOMIAL 0x04c11db6
3541 uint32_t crc = 0xffffffff;
3542 int carry, idx, bit;
3545 for (idx = 6; --idx >= 0;) {
3546 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3547 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
3550 crc = (crc ^ ED_POLYNOMIAL) | carry;
3558 * Compute the multicast address filter from the
3559 * list of multicast addresses we need to listen to.
3562 ds_getmcaf(sc, mcaf)
3563 struct ed_softc *sc;
3567 u_char *af = (u_char *) mcaf;
3568 struct ifmultiaddr *ifma;
3573 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3574 ifma = ifma->ifma_link.le_next) {
3575 if (ifma->ifma_addr->sa_family != AF_LINK)
3577 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3579 af[index >> 3] |= 1 << (index & 7);