2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/pci/agp_intel.c,v 1.1.2.5 2003/06/02 17:38:19 jhb Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
39 #include <pci/pcivar.h>
40 #include <pci/pcireg.h>
41 #include <pci/agppriv.h>
42 #include <pci/agpreg.h>
45 #include <vm/vm_object.h>
48 #define MAX_APSIZE 0x3f /* 256 MB */
50 struct agp_intel_softc {
52 u_int32_t initial_aperture; /* aperture size at startup */
53 struct agp_gatt *gatt;
58 agp_intel_match(device_t dev)
60 if (pci_get_class(dev) != PCIC_BRIDGE
61 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
64 if (agp_find_caps(dev) == 0)
67 switch (pci_get_devid(dev)) {
68 /* Intel -- vendor 0x8086 */
70 return ("Intel 82443LX (440 LX) host to PCI bridge");
73 return ("Intel 82443BX (440 BX) host to PCI bridge");
76 return ("Intel 82443GX host to PCI bridge");
79 return ("Intel 82443GX host to AGP bridge");
82 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
86 return ("Intel 82820 host to AGP bridge");
89 return ("Intel 82830 host to AGP bridge");
92 return ("Intel 82840 host to AGP bridge");
95 return ("Intel 82845 host to AGP bridge");
98 return ("Intel 82850 host to AGP bridge");
101 return ("Intel 82860 host to AGP bridge");
104 return ("Intel 82865 host to AGP bridge");
107 if (pci_get_vendor(dev) == 0x8086)
108 return ("Intel Generic host to PCI bridge");
114 agp_intel_probe(device_t dev)
118 desc = agp_intel_match(dev);
121 device_set_desc(dev, desc);
129 agp_intel_attach(device_t dev)
131 struct agp_intel_softc *sc = device_get_softc(dev);
132 struct agp_gatt *gatt;
133 u_int32_t type = pci_get_devid(dev);
137 error = agp_generic_attach(dev);
141 /* Determine maximum supported aperture size. */
142 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
143 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
144 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
146 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
147 sc->initial_aperture = AGP_GET_APERTURE(dev);
150 gatt = agp_alloc_gatt(dev);
155 * Probably contigmalloc failure. Try reducing the
156 * aperture so that the gatt size reduces.
158 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
159 agp_generic_detach(dev);
165 /* Install the gatt. */
166 pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
168 /* Enable the GLTB and setup the control register. */
170 case 0x71908086: /* 440LX/EX */
171 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
173 case 0x71808086: /* 440BX */
175 * XXX: Should be 0xa080? Bit 9 is undefined, and
176 * bit 13 being on and bit 15 being clear is illegal.
178 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
181 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
182 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
185 /* Enable things, clear errors etc. */
187 case 0x1a218086: /* i840 */
188 case 0x25308086: /* i850 */
189 case 0x25318086: /* i860 */
190 pci_write_config(dev, AGP_INTEL_MCHCFG,
191 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
195 case 0x25008086: /* i820 */
196 case 0x25018086: /* i820 */
197 pci_write_config(dev, AGP_INTEL_I820_RDCR,
198 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
202 case 0x1a308086: /* i845 */
203 case 0x25708086: /* i865 */
204 pci_write_config(dev, AGP_INTEL_I845_MCHCFG,
205 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
209 default: /* Intel Generic (maybe) */
210 pci_write_config(dev, AGP_INTEL_NBXCFG,
211 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
212 & ~(1 << 10)) | (1 << 9), 4);
216 case 0x1a218086: /* i840 */
217 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
220 case 0x25008086: /* i820 */
221 case 0x25018086: /* i820 */
222 case 0x1a308086: /* i845 */
223 case 0x25308086: /* i850 */
224 case 0x25318086: /* i860 */
225 case 0x25708086: /* i865 */
226 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
229 default: /* Intel Generic (maybe) */
230 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
237 agp_intel_detach(device_t dev)
239 struct agp_intel_softc *sc = device_get_softc(dev);
240 u_int32_t type = pci_get_devid(dev);
243 error = agp_generic_detach(dev);
248 case 0x1a218086: /* i840 */
249 case 0x25308086: /* i850 */
250 case 0x25318086: /* i860 */
251 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
252 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
254 pci_write_config(dev, AGP_INTEL_MCHCFG,
255 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
258 case 0x25008086: /* i820 */
259 case 0x25018086: /* i820 */
260 printf("%s: set RDCR to %x\n", __FUNCTION__, (unsigned)
261 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
263 pci_write_config(dev, AGP_INTEL_I820_RDCR,
264 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
267 case 0x1a308086: /* i845 */
268 case 0x25708086: /* i865 */
269 printf("%s: set MCHCFG to %x\n", __FUNCTION__, (unsigned)
270 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
272 pci_write_config(dev, AGP_INTEL_MCHCFG,
273 (pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
276 default: /* Intel Generic (maybe) */
277 printf("%s: set NBXCFG to %x\n", __FUNCTION__,
278 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
280 pci_write_config(dev, AGP_INTEL_NBXCFG,
281 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
284 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
285 AGP_SET_APERTURE(dev, sc->initial_aperture);
286 agp_free_gatt(sc->gatt);
292 agp_intel_get_aperture(device_t dev)
294 struct agp_intel_softc *sc = device_get_softc(dev);
297 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
300 * The size is determined by the number of low bits of
301 * register APBASE which are forced to zero. The low 22 bits
302 * are always forced to zero and each zero bit in the apsize
303 * field just read forces the corresponding bit in the 27:22
304 * to be zero. We calculate the aperture size accordingly.
306 return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
310 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
312 struct agp_intel_softc *sc = device_get_softc(dev);
316 * Reverse the magic from get_aperture.
318 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
321 * Double check for sanity.
323 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
326 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
332 agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
334 struct agp_intel_softc *sc = device_get_softc(dev);
336 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
339 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
344 agp_intel_unbind_page(device_t dev, int offset)
346 struct agp_intel_softc *sc = device_get_softc(dev);
348 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
351 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
356 agp_intel_flush_tlb(device_t dev)
360 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
361 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 8), 4);
362 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
365 static device_method_t agp_intel_methods[] = {
366 /* Device interface */
367 DEVMETHOD(device_probe, agp_intel_probe),
368 DEVMETHOD(device_attach, agp_intel_attach),
369 DEVMETHOD(device_detach, agp_intel_detach),
370 DEVMETHOD(device_shutdown, bus_generic_shutdown),
371 DEVMETHOD(device_suspend, bus_generic_suspend),
372 DEVMETHOD(device_resume, bus_generic_resume),
375 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
376 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
377 DEVMETHOD(agp_bind_page, agp_intel_bind_page),
378 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
379 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
380 DEVMETHOD(agp_enable, agp_generic_enable),
381 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
382 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
383 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
384 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
389 static driver_t agp_intel_driver = {
392 sizeof(struct agp_intel_softc),
395 static devclass_t agp_devclass;
397 DRIVER_MODULE(agp_intel, pci, agp_intel_driver, agp_devclass, 0, 0);