2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/devicestat.h>
40 #include <sys/sysctl.h>
41 #include <machine/stdarg.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
44 #include <machine/clock.h>
46 #include <machine/md_var.h>
49 #include <pci/pcivar.h>
50 #include <pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
53 /* device structures */
54 struct ata_pci_controller {
55 struct resource *bmio;
62 #define IOMASK 0xfffffffc
63 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
64 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
65 (pci_get_progif(dev) & 0x05) != 0x05)
68 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
73 if (device_get_children(device_get_parent(dev), &children, &nchildren))
76 for (i = 0; i < nchildren; i++) {
77 if (pci_get_devid(children[i]) == devid &&
78 pci_get_revid(children[i]) >= revid) {
79 free(children, M_TEMP);
83 free(children, M_TEMP);
88 ata_via_southbridge_fixup(device_t dev)
93 if (device_get_children(device_get_parent(dev), &children, &nchildren))
96 for (i = 0; i < nchildren; i++) {
97 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
98 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
99 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
100 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
101 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
103 if ((reg76 & 0xf0) != 0xd0) {
105 "Correcting VIA config for southbridge data corruption bug\n");
106 pci_write_config(children[i], 0x75, 0x80, 1);
107 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
112 free(children, M_TEMP);
116 ata_pci_match(device_t dev)
118 if (pci_get_class(dev) != PCIC_STORAGE)
121 switch (pci_get_devid(dev)) {
122 /* supported chipsets */
124 return "Intel PIIX ATA controller";
127 return "Intel PIIX3 ATA controller";
132 return "Intel PIIX4 ATA33 controller";
135 return "Intel ICH0 ATA33 controller";
139 return "Intel ICH ATA66 controller";
143 return "Intel ICH2 ATA100 controller";
147 return "Intel ICH3 ATA100 controller";
150 return "Intel ICH4 ATA100 controller";
153 return "Intel ICH5 ATA100 controller";
156 if (pci_get_revid(dev) >= 0xc4)
157 return "AcerLabs Aladdin ATA100 controller";
158 else if (pci_get_revid(dev) >= 0xc2)
159 return "AcerLabs Aladdin ATA66 controller";
160 else if (pci_get_revid(dev) >= 0x20)
161 return "AcerLabs Aladdin ATA33 controller";
163 return "AcerLabs Aladdin ATA controller";
166 if (ata_find_dev(dev, 0x05861106, 0x02))
167 return "VIA 82C586 ATA33 controller";
168 if (ata_find_dev(dev, 0x05861106, 0))
169 return "VIA 82C586 ATA controller";
170 if (ata_find_dev(dev, 0x05961106, 0x12))
171 return "VIA 82C596 ATA66 controller";
172 if (ata_find_dev(dev, 0x05961106, 0))
173 return "VIA 82C596 ATA33 controller";
174 if (ata_find_dev(dev, 0x06861106, 0x40))
175 return "VIA 82C686 ATA100 controller";
176 if (ata_find_dev(dev, 0x06861106, 0x10))
177 return "VIA 82C686 ATA66 controller";
178 if (ata_find_dev(dev, 0x06861106, 0))
179 return "VIA 82C686 ATA33 controller";
180 if (ata_find_dev(dev, 0x82311106, 0))
181 return "VIA 8231 ATA100 controller";
182 if (ata_find_dev(dev, 0x30741106, 0) ||
183 ata_find_dev(dev, 0x31091106, 0))
184 return "VIA 8233 ATA100 controller";
185 if (ata_find_dev(dev, 0x31471106, 0))
186 return "VIA 8233 ATA133 controller";
187 if (ata_find_dev(dev, 0x31771106, 0))
188 return "VIA 8235 ATA133 controller";
189 return "VIA Apollo ATA controller";
192 if (ata_find_dev(dev, 0x06301039, 0x30) ||
193 ata_find_dev(dev, 0x06331039, 0) ||
194 ata_find_dev(dev, 0x06351039, 0) ||
195 ata_find_dev(dev, 0x06401039, 0) ||
196 ata_find_dev(dev, 0x06451039, 0) ||
197 ata_find_dev(dev, 0x06501039, 0) ||
198 ata_find_dev(dev, 0x07301039, 0) ||
199 ata_find_dev(dev, 0x07331039, 0) ||
200 ata_find_dev(dev, 0x07351039, 0) ||
201 ata_find_dev(dev, 0x07401039, 0) ||
202 ata_find_dev(dev, 0x07451039, 0) ||
203 ata_find_dev(dev, 0x07501039, 0))
204 return "SiS 5591 ATA100 controller";
205 else if (ata_find_dev(dev, 0x05301039, 0) ||
206 ata_find_dev(dev, 0x05401039, 0) ||
207 ata_find_dev(dev, 0x06201039, 0) ||
208 ata_find_dev(dev, 0x06301039, 0))
209 return "SiS 5591 ATA66 controller";
211 return "SiS 5591 ATA33 controller";
214 return "SiI 0680 ATA133 controller";
217 return "CMD 649 ATA100 controller";
220 return "CMD 648 ATA66 controller";
223 return "CMD 646 ATA controller";
226 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
227 return "Cypress 82C693 ATA controller";
231 return "Cyrix 5530 ATA33 controller";
234 return "AMD 756 ATA66 controller";
237 return "AMD 766 ATA100 controller";
240 return "AMD 768 ATA100 controller";
243 return "nVIDIA nForce ATA100 controller";
246 return "ServerWorks ROSB4 ATA33 controller";
249 if (pci_get_revid(dev) >= 0x92)
250 return "ServerWorks CSB5 ATA100 controller";
252 return "ServerWorks CSB5 ATA66 controller";
255 return "Promise ATA33 controller";
259 return "Promise ATA66 controller";
263 return "Promise ATA100 controller";
267 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
268 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
269 static long start = 0, end = 0;
271 /* we belive we are on a TX4, now do our (simple) magic */
272 if (pci_get_slot(dev) == 1) {
273 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
274 return "Promise TX4 ATA100 controller (channel 0+1)";
276 else if (pci_get_slot(dev) == 2 && start && end) {
277 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
279 return "Promise TX4 ATA100 controller (channel 2+3)";
284 return "Promise TX2 ATA100 controller";
290 return "Promise TX2 ATA133 controller";
293 switch (pci_get_revid(dev)) {
296 return "HighPoint HPT366 ATA66 controller";
298 return "HighPoint HPT368 ATA66 controller";
301 return "HighPoint HPT370 ATA100 controller";
303 return "HighPoint HPT372 ATA133 controller";
308 switch (pci_get_revid(dev)) {
311 return "HighPoint HPT372 ATA133 controller";
316 switch (pci_get_revid(dev)) {
318 return "HighPoint HPT374 ATA133 controller";
323 return "Cenatek Rocket Drive controller";
325 /* unsupported but known chipsets, generic DMA only */
328 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
331 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
333 /* unknown chipsets, try generic DMA if it seems possible */
335 if (pci_get_class(dev) == PCIC_STORAGE &&
336 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
337 return "Generic PCI ATA controller";
343 ata_pci_probe(device_t dev)
345 const char *desc = ata_pci_match(dev);
348 device_set_desc(dev, desc);
356 ata_pci_add_child(device_t dev, int unit)
360 /* check if this is located at one of the std addresses */
361 if (ATA_MASTERDEV(dev)) {
362 if (!(child = device_add_child(dev, "ata", unit)))
366 if (!(child = device_add_child(dev, "ata", 2)))
373 ata_pci_attach(device_t dev)
375 struct ata_pci_controller *controller = device_get_softc(dev);
376 u_int8_t class, subclass;
380 /* set up vendor-specific stuff */
381 type = pci_get_devid(dev);
382 class = pci_get_class(dev);
383 subclass = pci_get_subclass(dev);
384 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
386 if (!(cmd & PCIM_CMD_PORTEN)) {
387 device_printf(dev, "ATA channel disabled by BIOS\n");
391 /* is busmastering supported ? */
392 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
393 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
395 /* is there a valid port range to connect to ? */
397 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
398 0, ~0, 1, RF_ACTIVE);
399 if (!controller->bmio)
400 device_printf(dev, "Busmastering DMA not configured\n");
403 device_printf(dev, "Busmastering DMA not supported\n");
405 /* do extra chipset specific setups */
407 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
408 pci_write_config(dev, 0x53,
409 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
412 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
415 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
418 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
419 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
422 case 0x00041103: /* HighPoint HPT366/368/370/372 */
423 if (pci_get_revid(dev) < 2) { /* HPT 366 */
424 /* turn off interrupt prediction */
425 pci_write_config(dev, 0x51,
426 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
429 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
430 /* turn off interrupt prediction */
431 pci_write_config(dev, 0x51,
432 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
433 pci_write_config(dev, 0x55,
434 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
436 /* turn on interrupts */
437 pci_write_config(dev, 0x5a,
438 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
441 pci_write_config(dev, 0x5b, 0x22, 1);
446 case 0x00051103: /* HighPoint HPT372 */
447 case 0x00081103: /* HighPoint HPT374 */
448 /* turn off interrupt prediction */
449 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
450 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
452 /* turn on interrupts */
453 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
456 pci_write_config(dev, 0x5b,
457 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
460 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
461 /* prepare for ATA-66 on the 82C686a and 82C596b */
462 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
463 !ata_find_dev(dev, 0x06861106, 0x40)) ||
464 ata_find_dev(dev, 0x05961106, 0x12))
465 pci_write_config(dev, 0x50, 0x030b030b, 4);
467 /* the southbridge might need the data corruption fix */
468 if (ata_find_dev(dev, 0x06861106, 0x40) ||
469 ata_find_dev(dev, 0x82311106, 0x10))
470 ata_via_southbridge_fixup(dev);
473 case 0x74091022: /* AMD 756 default setup */
474 case 0x74111022: /* AMD 766 default setup */
475 case 0x74411022: /* AMD 768 default setup */
476 case 0x01bc10de: /* nVIDIA nForce default setup */
477 /* set prefetch, postwrite */
478 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
480 /* set fifo configuration half'n'half */
481 pci_write_config(dev, 0x43,
482 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
484 /* set status register read retry */
485 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
487 /* set DMA read & end-of-sector fifo flush */
488 pci_write_config(dev, 0x46,
489 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
491 /* set sector size */
492 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
493 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
496 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
497 pci_write_config(dev, 0x64,
498 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
502 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
503 pci_write_config(dev, 0x5a,
504 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
505 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
508 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
509 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
510 pci_write_config(dev, 0x8a,
511 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
512 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
513 device_printf(dev, "SiI 0680 could not set clock\n");
518 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
519 pci_write_config(dev, 0x71, 0x01, 1);
522 case 0x10001042: /* RZ 100? known bad, no DMA */
524 case 0x06401095: /* CMD 640 known bad, no DMA */
525 controller->bmio = NULL;
526 device_printf(dev, "Busmastering DMA disabled\n");
529 if (controller->bmio) {
530 controller->bmaddr = rman_get_start(controller->bmio);
531 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
532 SYS_RES_IOPORT, rid, controller->bmio);
533 controller->bmio = NULL;
537 * the Cypress chip is a mess, it contains two ATA functions, but
538 * both channels are visible on the first one.
539 * simply ignore the second function for now, as the right
540 * solution (ignoring the second channel on the first function)
541 * doesn't work with the crappy ATA interrupt setup on the alpha.
543 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
546 ata_pci_add_child(dev, 0);
548 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
549 ata_pci_add_child(dev, 1);
551 return bus_generic_attach(dev);
555 ata_pci_intr(struct ata_channel *ch)
560 * since we might share the IRQ with another device, and in some
561 * cases with our twin channel, we only want to process interrupts
562 * that we know this channel generated.
564 switch (ch->chiptype) {
565 case 0x00041103: /* HighPoint HPT366/368/370/372 */
566 case 0x00051103: /* HighPoint HPT372 */
567 case 0x00081103: /* HighPoint HPT374 */
568 if (((dmastat = ata_dmastatus(ch)) &
569 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
571 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
575 case 0x06481095: /* CMD 648 */
576 case 0x06491095: /* CMD 649 */
577 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
578 (ch->unit ? 0x08 : 0x04)))
582 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
583 case 0x0d38105a: /* Promise Fasttrak 66 */
584 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
585 case 0x0d30105a: /* Promise OEM ATA100 */
586 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
587 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
588 (ch->unit ? 0x00004000 : 0x00000400)))
592 case 0x4d68105a: /* Promise TX2 ATA100 */
593 case 0x6268105a: /* Promise TX2 ATA100 */
594 case 0x4d69105a: /* Promise TX2 ATA133 */
595 case 0x5275105a: /* Promise TX2 ATA133 */
596 case 0x6269105a: /* Promise TX2 ATA133 */
597 case 0x7275105a: /* Promise TX2 ATA133 */
598 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
599 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
604 if (ch->flags & ATA_DMA_ACTIVE) {
605 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
607 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
614 ata_pci_print_child(device_t dev, device_t child)
616 struct ata_channel *ch = device_get_softc(child);
619 retval += bus_print_child_header(dev, child);
620 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
622 if (ATA_MASTERDEV(dev))
623 retval += printf(" irq %d", 14 + ch->unit);
625 retval += bus_print_child_footer(dev, child);
630 static struct resource *
631 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
632 u_long start, u_long end, u_long count, u_int flags)
634 struct ata_pci_controller *controller = device_get_softc(dev);
635 struct resource *res = NULL;
636 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
639 if (type == SYS_RES_IOPORT) {
642 if (ATA_MASTERDEV(dev)) {
644 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
645 end = start + ATA_IOSIZE - 1;
647 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
648 SYS_RES_IOPORT, &myrid,
649 start, end, count, flags);
652 myrid = 0x10 + 8 * unit;
653 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
654 SYS_RES_IOPORT, &myrid,
655 start, end, count, flags);
659 case ATA_ALTADDR_RID:
660 if (ATA_MASTERDEV(dev)) {
662 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
663 end = start + ATA_ALTIOSIZE - 1;
664 count = ATA_ALTIOSIZE;
665 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
666 SYS_RES_IOPORT, &myrid,
667 start, end, count, flags);
670 myrid = 0x14 + 8 * unit;
671 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
672 SYS_RES_IOPORT, &myrid,
673 start, end, count, flags);
675 start = rman_get_start(res) + 2;
676 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
677 count = ATA_ALTIOSIZE;
678 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
679 SYS_RES_IOPORT, myrid, res);
680 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
681 SYS_RES_IOPORT, &myrid,
682 start, end, count, flags);
688 if (controller->bmaddr) {
691 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
692 end = start + ATA_BMIOSIZE - 1;
693 count = ATA_BMIOSIZE;
694 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
695 SYS_RES_IOPORT, &myrid,
696 start, end, count, flags);
702 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
703 if (ATA_MASTERDEV(dev)) {
705 return alpha_platform_alloc_ide_intr(unit);
707 int irq = (unit == 0 ? 14 : 15);
709 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
710 SYS_RES_IRQ, rid, irq, irq, 1, flags);
714 /* primary and secondary channels share interrupt, keep track */
715 if (!controller->irq)
716 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
718 rid, 0, ~0, 1, flags);
719 controller->irqcnt++;
720 return controller->irq;
727 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
730 struct ata_pci_controller *controller = device_get_softc(dev);
731 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
733 if (type == SYS_RES_IOPORT) {
736 if (ATA_MASTERDEV(dev))
737 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
738 SYS_RES_IOPORT, 0x0, r);
740 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
741 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
744 case ATA_ALTADDR_RID:
745 if (ATA_MASTERDEV(dev))
746 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
747 SYS_RES_IOPORT, 0x0, r);
749 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
750 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
754 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
755 SYS_RES_IOPORT, 0x20, r);
760 if (type == SYS_RES_IRQ) {
761 if (rid != ATA_IRQ_RID)
764 if (ATA_MASTERDEV(dev)) {
766 return alpha_platform_release_ide_intr(unit, r);
768 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
769 SYS_RES_IRQ, rid, r);
773 /* primary and secondary channels share interrupt, keep track */
774 if (--controller->irqcnt)
776 controller->irq = NULL;
777 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
778 SYS_RES_IRQ, rid, r);
785 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
786 int flags, driver_intr_t *intr, void *arg,
789 if (ATA_MASTERDEV(dev)) {
791 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
793 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
794 flags, intr, arg, cookiep);
798 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
799 flags, intr, arg, cookiep);
803 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
806 if (ATA_MASTERDEV(dev)) {
808 return alpha_platform_teardown_ide_intr(irq, cookie);
810 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
814 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
817 static device_method_t ata_pci_methods[] = {
818 /* device interface */
819 DEVMETHOD(device_probe, ata_pci_probe),
820 DEVMETHOD(device_attach, ata_pci_attach),
821 DEVMETHOD(device_shutdown, bus_generic_shutdown),
822 DEVMETHOD(device_suspend, bus_generic_suspend),
823 DEVMETHOD(device_resume, bus_generic_resume),
826 DEVMETHOD(bus_print_child, ata_pci_print_child),
827 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
828 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
829 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
830 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
831 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
832 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
836 static driver_t ata_pci_driver = {
839 sizeof(struct ata_pci_controller),
842 static devclass_t ata_pci_devclass;
844 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
847 ata_pcisub_probe(device_t dev)
849 struct ata_channel *ch = device_get_softc(dev);
853 /* find channel number on this controller */
854 device_get_children(device_get_parent(dev), &children, &count);
855 for (i = 0; i < count; i++) {
856 if (children[i] == dev)
859 free(children, M_TEMP);
860 ch->chiptype = pci_get_devid(device_get_parent(dev));
861 ch->intr_func = ata_pci_intr;
862 return ata_probe(dev);
865 static device_method_t ata_pcisub_methods[] = {
866 /* device interface */
867 DEVMETHOD(device_probe, ata_pcisub_probe),
868 DEVMETHOD(device_attach, ata_attach),
869 DEVMETHOD(device_detach, ata_detach),
870 DEVMETHOD(device_resume, ata_resume),
874 static driver_t ata_pcisub_driver = {
877 sizeof(struct ata_channel),
880 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);