2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
38 * documentation not available, but ask me nicely.
40 * Written by Bill Paul <william.paul@windriver.com>
45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
46 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
48 * are three supported methods for data transfer between host and
49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
50 * Propulsion Technology (tm) DMA. The latter mechanism is a form
51 * of double buffer DMA where the packet data is copied to a
52 * pre-allocated DMA buffer who's physical address has been loaded
53 * into a table at device initialization time. The rationale is that
54 * the virtual to physical address translation needed for normal
55 * scatter/gather DMA is more expensive than the data copy needed
56 * for double buffering. This may be true in Windows NT and the like,
57 * but it isn't true for us, at least on the x86 arch. This driver
58 * uses the scatter/gather I/O method for both TX and RX.
60 * The LXT1001 only supports TCP/IP checksum offload on receive.
61 * Also, the VLAN tagging is done using a 16-entry table which allows
62 * the chip to perform hardware filtering based on VLAN tags. Sadly,
63 * our vlan support doesn't currently play well with this kind of
67 * - Jeff James at Intel, for arranging to have the LXT1001 manual
68 * released (at long last)
69 * - Beny Chen at D-Link, for actually sending it to me
70 * - Brad Short and Keith Alexis at SMC, for sending me sample
71 * SMC9462SX and SMC9462TX adapters for testing
72 * - Paul Saab at Y!, for not killing me (though it remains to be seen
73 * if in fact he did me much of a favor)
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/socket.h>
85 #include <net/if_arp.h>
86 #include <net/ethernet.h>
87 #include <net/if_dl.h>
88 #include <net/if_media.h>
92 #include <vm/vm.h> /* for vtophys */
93 #include <vm/pmap.h> /* for vtophys */
94 #include <machine/clock.h> /* for DELAY */
95 #include <machine/bus_pio.h>
96 #include <machine/bus_memio.h>
97 #include <machine/bus.h>
98 #include <machine/resource.h>
100 #include <sys/rman.h>
102 #include <dev/mii/mii.h>
103 #include <dev/mii/miivar.h>
105 #include <pci/pcireg.h>
106 #include <pci/pcivar.h>
108 #define LGE_USEIOSPACE
110 #include <dev/lge/if_lgereg.h>
112 /* "controller miibus0" required. See GENERIC if you get errors here. */
113 #include "miibus_if.h"
116 static const char rcsid[] =
117 "$FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $";
121 * Various supported device vendors/types and their names.
123 static struct lge_type lge_devs[] = {
124 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
128 static int lge_probe __P((device_t));
129 static int lge_attach __P((device_t));
130 static int lge_detach __P((device_t));
132 static int lge_alloc_jumbo_mem __P((struct lge_softc *));
133 static void lge_free_jumbo_mem __P((struct lge_softc *));
134 static void *lge_jalloc __P((struct lge_softc *));
135 static void lge_jfree __P((caddr_t, u_int));
136 static void lge_jref __P((caddr_t, u_int));
138 static int lge_newbuf __P((struct lge_softc *,
139 struct lge_rx_desc *,
141 static int lge_encap __P((struct lge_softc *,
142 struct mbuf *, u_int32_t *));
143 static void lge_rxeof __P((struct lge_softc *, int));
144 static void lge_rxeoc __P((struct lge_softc *));
145 static void lge_txeof __P((struct lge_softc *));
146 static void lge_intr __P((void *));
147 static void lge_tick __P((void *));
148 static void lge_start __P((struct ifnet *));
149 static int lge_ioctl __P((struct ifnet *, u_long, caddr_t));
150 static void lge_init __P((void *));
151 static void lge_stop __P((struct lge_softc *));
152 static void lge_watchdog __P((struct ifnet *));
153 static void lge_shutdown __P((device_t));
154 static int lge_ifmedia_upd __P((struct ifnet *));
155 static void lge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
157 static void lge_eeprom_getword __P((struct lge_softc *, int, u_int16_t *));
158 static void lge_read_eeprom __P((struct lge_softc *, caddr_t, int,
161 static int lge_miibus_readreg __P((device_t, int, int));
162 static int lge_miibus_writereg __P((device_t, int, int, int));
163 static void lge_miibus_statchg __P((device_t));
165 static void lge_setmulti __P((struct lge_softc *));
166 static u_int32_t lge_crc __P((struct lge_softc *, caddr_t));
167 static void lge_reset __P((struct lge_softc *));
168 static int lge_list_rx_init __P((struct lge_softc *));
169 static int lge_list_tx_init __P((struct lge_softc *));
171 #ifdef LGE_USEIOSPACE
172 #define LGE_RES SYS_RES_IOPORT
173 #define LGE_RID LGE_PCI_LOIO
175 #define LGE_RES SYS_RES_MEMORY
176 #define LGE_RID LGE_PCI_LOMEM
179 static device_method_t lge_methods[] = {
180 /* Device interface */
181 DEVMETHOD(device_probe, lge_probe),
182 DEVMETHOD(device_attach, lge_attach),
183 DEVMETHOD(device_detach, lge_detach),
184 DEVMETHOD(device_shutdown, lge_shutdown),
187 DEVMETHOD(bus_print_child, bus_generic_print_child),
188 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
192 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
193 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
198 static driver_t lge_driver = {
201 sizeof(struct lge_softc)
204 static devclass_t lge_devclass;
206 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
207 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
209 #define LGE_SETBIT(sc, reg, x) \
210 CSR_WRITE_4(sc, reg, \
211 CSR_READ_4(sc, reg) | (x))
213 #define LGE_CLRBIT(sc, reg, x) \
214 CSR_WRITE_4(sc, reg, \
215 CSR_READ_4(sc, reg) & ~(x))
218 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
221 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
224 * Read a word of data stored in the EEPROM at address 'addr.'
226 static void lge_eeprom_getword(sc, addr, dest)
227 struct lge_softc *sc;
234 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
235 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
237 for (i = 0; i < LGE_TIMEOUT; i++)
238 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
241 if (i == LGE_TIMEOUT) {
242 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
246 val = CSR_READ_4(sc, LGE_EEDATA);
249 *dest = (val >> 16) & 0xFFFF;
251 *dest = val & 0xFFFF;
257 * Read a sequence of words from the EEPROM.
259 static void lge_read_eeprom(sc, dest, off, cnt, swap)
260 struct lge_softc *sc;
267 u_int16_t word = 0, *ptr;
269 for (i = 0; i < cnt; i++) {
270 lge_eeprom_getword(sc, off + i, &word);
271 ptr = (u_int16_t *)(dest + (i * 2));
281 static int lge_miibus_readreg(dev, phy, reg)
285 struct lge_softc *sc;
288 sc = device_get_softc(dev);
291 * If we have a non-PCS PHY, pretend that the internal
292 * autoneg stuff at PHY address 0 isn't there so that
293 * the miibus code will find only the GMII PHY.
295 if (sc->lge_pcs == 0 && phy == 0)
298 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
300 for (i = 0; i < LGE_TIMEOUT; i++)
301 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
304 if (i == LGE_TIMEOUT) {
305 printf("lge%d: PHY read timed out\n", sc->lge_unit);
309 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
312 static int lge_miibus_writereg(dev, phy, reg, data)
316 struct lge_softc *sc;
319 sc = device_get_softc(dev);
321 CSR_WRITE_4(sc, LGE_GMIICTL,
322 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
324 for (i = 0; i < LGE_TIMEOUT; i++)
325 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
328 if (i == LGE_TIMEOUT) {
329 printf("lge%d: PHY write timed out\n", sc->lge_unit);
336 static void lge_miibus_statchg(dev)
339 struct lge_softc *sc;
340 struct mii_data *mii;
342 sc = device_get_softc(dev);
343 mii = device_get_softc(sc->lge_miibus);
345 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
346 switch (IFM_SUBTYPE(mii->mii_media_active)) {
349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
352 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
355 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
359 * Choose something, even if it's wrong. Clearing
360 * all the bits will hose autoneg on the internal
363 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
367 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
368 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
370 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
376 static u_int32_t lge_crc(sc, addr)
377 struct lge_softc *sc;
380 u_int32_t crc, carry;
384 /* Compute CRC for the address value. */
385 crc = 0xFFFFFFFF; /* initial value */
387 for (i = 0; i < 6; i++) {
389 for (j = 0; j < 8; j++) {
390 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
394 crc = (crc ^ 0x04c11db6) | carry;
399 * return the filter bit position
401 return((crc >> 26) & 0x0000003F);
404 static void lge_setmulti(sc)
405 struct lge_softc *sc;
408 struct ifmultiaddr *ifma;
409 u_int32_t h = 0, hashes[2] = { 0, 0 };
411 ifp = &sc->arpcom.ac_if;
413 /* Make sure multicast hash table is enabled. */
414 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
416 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
417 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
418 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
422 /* first, zot all the existing hash bits */
423 CSR_WRITE_4(sc, LGE_MAR0, 0);
424 CSR_WRITE_4(sc, LGE_MAR1, 0);
426 /* now program new ones */
427 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
428 ifma = ifma->ifma_link.le_next) {
429 if (ifma->ifma_addr->sa_family != AF_LINK)
431 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
433 hashes[0] |= (1 << h);
435 hashes[1] |= (1 << (h - 32));
438 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
439 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
444 static void lge_reset(sc)
445 struct lge_softc *sc;
449 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
451 for (i = 0; i < LGE_TIMEOUT; i++) {
452 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
456 if (i == LGE_TIMEOUT)
457 printf("lge%d: reset never completed\n", sc->lge_unit);
459 /* Wait a little while for the chip to get its brains in order. */
466 * Probe for a Level 1 chip. Check the PCI vendor and device
467 * IDs against our list and return a device name if we find a match.
469 static int lge_probe(dev)
476 while(t->lge_name != NULL) {
477 if ((pci_get_vendor(dev) == t->lge_vid) &&
478 (pci_get_device(dev) == t->lge_did)) {
479 device_set_desc(dev, t->lge_name);
489 * Attach the interface. Allocate softc structures, do ifmedia
490 * setup and ethernet/BPF attach.
492 static int lge_attach(dev)
496 u_char eaddr[ETHER_ADDR_LEN];
498 struct lge_softc *sc;
500 int unit, error = 0, rid;
504 sc = device_get_softc(dev);
505 unit = device_get_unit(dev);
506 bzero(sc, sizeof(struct lge_softc));
509 * Handle power management nonsense.
511 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
512 if (command == 0x01) {
514 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
515 if (command & LGE_PSTATE_MASK) {
516 u_int32_t iobase, membase, irq;
518 /* Save important PCI config data. */
519 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
520 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
521 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
523 /* Reset the power state. */
524 printf("lge%d: chip is in D%d power mode "
525 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
526 command &= 0xFFFFFFFC;
527 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
529 /* Restore PCI config data. */
530 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
531 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
532 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
537 * Map control/status registers.
539 command = pci_read_config(dev, PCIR_COMMAND, 4);
540 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
541 pci_write_config(dev, PCIR_COMMAND, command, 4);
542 command = pci_read_config(dev, PCIR_COMMAND, 4);
544 #ifdef LGE_USEIOSPACE
545 if (!(command & PCIM_CMD_PORTEN)) {
546 printf("lge%d: failed to enable I/O ports!\n", unit);
551 if (!(command & PCIM_CMD_MEMEN)) {
552 printf("lge%d: failed to enable memory mapping!\n", unit);
559 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
560 0, ~0, 1, RF_ACTIVE);
562 if (sc->lge_res == NULL) {
563 printf("lge%d: couldn't map ports/memory\n", unit);
568 sc->lge_btag = rman_get_bustag(sc->lge_res);
569 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
571 /* Allocate interrupt */
573 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
574 RF_SHAREABLE | RF_ACTIVE);
576 if (sc->lge_irq == NULL) {
577 printf("lge%d: couldn't map interrupt\n", unit);
578 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
583 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
584 lge_intr, sc, &sc->lge_intrhand);
587 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
588 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
589 printf("lge%d: couldn't set up irq\n", unit);
593 /* Reset the adapter. */
597 * Get station address from the EEPROM.
599 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
600 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
601 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
604 * A Level 1 chip was detected. Inform the world.
606 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":");
609 callout_handle_init(&sc->lge_stat_ch);
610 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
612 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
613 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
615 if (sc->lge_ldata == NULL) {
616 printf("lge%d: no memory for list buffers!\n", unit);
617 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
618 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
619 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
623 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
625 /* Try to allocate memory for jumbo buffers. */
626 if (lge_alloc_jumbo_mem(sc)) {
627 printf("lge%d: jumbo buffer allocation failed\n",
629 contigfree(sc->lge_ldata,
630 sizeof(struct lge_list_data), M_DEVBUF);
631 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
632 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
633 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
638 ifp = &sc->arpcom.ac_if;
641 ifp->if_name = "lge";
642 ifp->if_mtu = ETHERMTU;
643 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
644 ifp->if_ioctl = lge_ioctl;
645 ifp->if_output = ether_output;
646 ifp->if_start = lge_start;
647 ifp->if_watchdog = lge_watchdog;
648 ifp->if_init = lge_init;
649 ifp->if_baudrate = 1000000000;
650 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1;
651 ifp->if_capabilities = IFCAP_RXCSUM;
652 ifp->if_capenable = ifp->if_capabilities;
654 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
662 if (mii_phy_probe(dev, &sc->lge_miibus,
663 lge_ifmedia_upd, lge_ifmedia_sts)) {
664 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
665 contigfree(sc->lge_ldata,
666 sizeof(struct lge_list_data), M_DEVBUF);
667 lge_free_jumbo_mem(sc);
668 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
669 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
670 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
676 * Call MI attach routine.
678 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
679 callout_handle_init(&sc->lge_stat_ch);
686 static int lge_detach(dev)
689 struct lge_softc *sc;
695 sc = device_get_softc(dev);
696 ifp = &sc->arpcom.ac_if;
700 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
702 bus_generic_detach(dev);
703 device_delete_child(dev, sc->lge_miibus);
705 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
706 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
707 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
709 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
710 lge_free_jumbo_mem(sc);
718 * Initialize the transmit descriptors.
720 static int lge_list_tx_init(sc)
721 struct lge_softc *sc;
723 struct lge_list_data *ld;
724 struct lge_ring_data *cd;
729 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
730 ld->lge_tx_list[i].lge_mbuf = NULL;
731 ld->lge_tx_list[i].lge_ctl = 0;
734 cd->lge_tx_prod = cd->lge_tx_cons = 0;
741 * Initialize the RX descriptors and allocate mbufs for them. Note that
742 * we arralge the descriptors in a closed ring, so that the last descriptor
743 * points back to the first.
745 static int lge_list_rx_init(sc)
746 struct lge_softc *sc;
748 struct lge_list_data *ld;
749 struct lge_ring_data *cd;
755 cd->lge_rx_prod = cd->lge_rx_cons = 0;
757 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
759 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
760 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
762 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
766 /* Clear possible 'rx command queue empty' interrupt. */
767 CSR_READ_4(sc, LGE_ISR);
773 * Initialize an RX descriptor and attach an MBUF cluster.
775 static int lge_newbuf(sc, c, m)
776 struct lge_softc *sc;
777 struct lge_rx_desc *c;
780 struct mbuf *m_new = NULL;
784 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
786 printf("lge%d: no memory for rx list "
787 "-- packet dropped!\n", sc->lge_unit);
791 /* Allocate the jumbo buffer */
792 buf = lge_jalloc(sc);
795 printf("lge%d: jumbo allocation failed "
796 "-- packet dropped!\n", sc->lge_unit);
801 /* Attach the buffer to the mbuf */
802 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
803 m_new->m_flags |= M_EXT;
804 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
805 m_new->m_len = LGE_MCLBYTES;
806 m_new->m_ext.ext_free = lge_jfree;
807 m_new->m_ext.ext_ref = lge_jref;
810 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
811 m_new->m_data = m_new->m_ext.ext_buf;
815 * Adjust alignment so packet payload begins on a
816 * longword boundary. Mandatory for Alpha, useful on
819 m_adj(m_new, ETHER_ALIGN);
822 c->lge_fragptr_hi = 0;
823 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
824 c->lge_fraglen = m_new->m_len;
825 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
829 * Put this buffer in the RX command FIFO. To do this,
830 * we just write the physical address of the descriptor
831 * into the RX descriptor address registers. Note that
832 * there are two registers, one high DWORD and one low
833 * DWORD, which lets us specify a 64-bit address if
834 * desired. We only use a 32-bit address for now.
835 * Writing to the low DWORD register is what actually
836 * causes the command to be issued, so we do that
839 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
840 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
845 static int lge_alloc_jumbo_mem(sc)
846 struct lge_softc *sc;
850 struct lge_jpool_entry *entry;
852 /* Grab a big chunk o' storage. */
853 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
854 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
856 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
857 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
861 SLIST_INIT(&sc->lge_jfree_listhead);
862 SLIST_INIT(&sc->lge_jinuse_listhead);
865 * Now divide it up into 9K pieces and save the addresses
868 ptr = sc->lge_cdata.lge_jumbo_buf;
869 for (i = 0; i < LGE_JSLOTS; i++) {
871 aptr = (u_int64_t **)ptr;
872 aptr[0] = (u_int64_t *)sc;
873 ptr += sizeof(u_int64_t);
874 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
875 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
877 entry = malloc(sizeof(struct lge_jpool_entry),
880 printf("lge%d: no memory for jumbo "
881 "buffer queue!\n", sc->lge_unit);
885 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
886 entry, jpool_entries);
892 static void lge_free_jumbo_mem(sc)
893 struct lge_softc *sc;
896 struct lge_jpool_entry *entry;
898 for (i = 0; i < LGE_JSLOTS; i++) {
899 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
900 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
901 free(entry, M_DEVBUF);
904 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
910 * Allocate a jumbo buffer.
912 static void *lge_jalloc(sc)
913 struct lge_softc *sc;
915 struct lge_jpool_entry *entry;
917 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
921 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
926 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
927 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
928 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
929 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
933 * Adjust usage count on a jumbo buffer. In general this doesn't
934 * get used much because our jumbo buffers don't get passed around
935 * a lot, but it's implemented for correctness.
937 static void lge_jref(buf, size)
941 struct lge_softc *sc;
945 /* Extract the softc struct pointer. */
946 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
947 sc = (struct lge_softc *)(aptr[0]);
950 panic("lge_jref: can't find softc pointer!");
952 if (size != LGE_MCLBYTES)
953 panic("lge_jref: adjusting refcount of buf of wrong size!");
955 /* calculate the slot this buffer belongs to */
957 i = ((vm_offset_t)aptr
958 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
960 if ((i < 0) || (i >= LGE_JSLOTS))
961 panic("lge_jref: asked to reference buffer "
962 "that we don't manage!");
963 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
964 panic("lge_jref: buffer already free!");
966 sc->lge_cdata.lge_jslots[i].lge_inuse++;
972 * Release a jumbo buffer.
974 static void lge_jfree(buf, size)
978 struct lge_softc *sc;
981 struct lge_jpool_entry *entry;
983 /* Extract the softc struct pointer. */
984 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
985 sc = (struct lge_softc *)(aptr[0]);
988 panic("lge_jfree: can't find softc pointer!");
990 if (size != LGE_MCLBYTES)
991 panic("lge_jfree: freeing buffer of wrong size!");
993 /* calculate the slot this buffer belongs to */
994 i = ((vm_offset_t)aptr
995 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
997 if ((i < 0) || (i >= LGE_JSLOTS))
998 panic("lge_jfree: asked to free buffer that we don't manage!");
999 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
1000 panic("lge_jfree: buffer already free!");
1002 sc->lge_cdata.lge_jslots[i].lge_inuse--;
1003 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
1004 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
1006 panic("lge_jfree: buffer not in use!");
1008 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
1010 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
1011 entry, jpool_entries);
1019 * A frame has been uploaded: pass the resulting mbuf chain up to
1020 * the higher level protocols.
1022 static void lge_rxeof(sc, cnt)
1023 struct lge_softc *sc;
1026 struct ether_header *eh;
1029 struct lge_rx_desc *cur_rx;
1030 int c, i, total_len = 0;
1031 u_int32_t rxsts, rxctl;
1033 ifp = &sc->arpcom.ac_if;
1035 /* Find out how many frames were processed. */
1037 i = sc->lge_cdata.lge_rx_cons;
1041 struct mbuf *m0 = NULL;
1043 cur_rx = &sc->lge_ldata->lge_rx_list[i];
1044 rxctl = cur_rx->lge_ctl;
1045 rxsts = cur_rx->lge_sts;
1046 m = cur_rx->lge_mbuf;
1047 cur_rx->lge_mbuf = NULL;
1048 total_len = LGE_RXBYTES(cur_rx);
1049 LGE_INC(i, LGE_RX_LIST_CNT);
1053 * If an error occurs, update stats, clear the
1054 * status word and leave the mbuf cluster in place:
1055 * it should simply get re-used next time this descriptor
1056 * comes up in the ring.
1058 if (rxctl & LGE_RXCTL_ERRMASK) {
1060 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1064 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1065 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1066 total_len + ETHER_ALIGN, 0, ifp, NULL);
1067 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1069 printf("lge%d: no receive buffers "
1070 "available -- packet dropped!\n",
1075 m_adj(m0, ETHER_ALIGN);
1078 m->m_pkthdr.rcvif = ifp;
1079 m->m_pkthdr.len = m->m_len = total_len;
1083 eh = mtod(m, struct ether_header *);
1085 /* Remove header from mbuf and pass it on. */
1086 m_adj(m, sizeof(struct ether_header));
1088 /* Do IP checksum checking. */
1089 if (rxsts & LGE_RXSTS_ISIP)
1090 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1091 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1092 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1093 if ((rxsts & LGE_RXSTS_ISTCP &&
1094 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1095 (rxsts & LGE_RXSTS_ISUDP &&
1096 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1097 m->m_pkthdr.csum_flags |=
1098 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1099 m->m_pkthdr.csum_data = 0xffff;
1102 ether_input(ifp, eh, m);
1105 sc->lge_cdata.lge_rx_cons = i;
1111 struct lge_softc *sc;
1115 ifp = &sc->arpcom.ac_if;
1116 ifp->if_flags &= ~IFF_RUNNING;
1122 * A frame was downloaded to the chip. It's safe for us to clean up
1126 static void lge_txeof(sc)
1127 struct lge_softc *sc;
1129 struct lge_tx_desc *cur_tx = NULL;
1131 u_int32_t idx, txdone;
1133 ifp = &sc->arpcom.ac_if;
1135 /* Clear the timeout timer. */
1139 * Go through our tx list and free mbufs for those
1140 * frames that have been transmitted.
1142 idx = sc->lge_cdata.lge_tx_cons;
1143 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1145 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1146 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1149 if (cur_tx->lge_mbuf != NULL) {
1150 m_freem(cur_tx->lge_mbuf);
1151 cur_tx->lge_mbuf = NULL;
1153 cur_tx->lge_ctl = 0;
1156 LGE_INC(idx, LGE_TX_LIST_CNT);
1160 sc->lge_cdata.lge_tx_cons = idx;
1163 ifp->if_flags &= ~IFF_OACTIVE;
1168 static void lge_tick(xsc)
1171 struct lge_softc *sc;
1172 struct mii_data *mii;
1179 ifp = &sc->arpcom.ac_if;
1181 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1182 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1183 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1184 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1186 if (!sc->lge_link) {
1187 mii = device_get_softc(sc->lge_miibus);
1190 if (mii->mii_media_status & IFM_ACTIVE &&
1191 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1193 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1194 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX)
1195 printf("lge%d: gigabit link up\n",
1197 if (ifp->if_snd.ifq_head != NULL)
1202 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1209 static void lge_intr(arg)
1212 struct lge_softc *sc;
1217 ifp = &sc->arpcom.ac_if;
1219 /* Supress unwanted interrupts */
1220 if (!(ifp->if_flags & IFF_UP)) {
1227 * Reading the ISR register clears all interrupts, and
1228 * clears the 'interrupts enabled' bit in the IMR
1231 status = CSR_READ_4(sc, LGE_ISR);
1233 if ((status & LGE_INTRS) == 0)
1236 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1239 if (status & LGE_ISR_RXDMA_DONE)
1240 lge_rxeof(sc, LGE_RX_DMACNT(status));
1242 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1245 if (status & LGE_ISR_PHY_INTR) {
1247 untimeout(lge_tick, sc, sc->lge_stat_ch);
1252 /* Re-enable interrupts. */
1253 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1255 if (ifp->if_snd.ifq_head != NULL)
1262 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1263 * pointers to the fragment pointers.
1265 static int lge_encap(sc, m_head, txidx)
1266 struct lge_softc *sc;
1267 struct mbuf *m_head;
1270 struct lge_frag *f = NULL;
1271 struct lge_tx_desc *cur_tx;
1273 int frag = 0, tot_len = 0;
1276 * Start packing the mbufs in this chain into
1277 * the fragment pointers. Stop when we run out
1278 * of fragments or hit the end of the mbuf chain.
1281 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1284 for (m = m_head; m != NULL; m = m->m_next) {
1285 if (m->m_len != 0) {
1286 tot_len += m->m_len;
1287 f = &cur_tx->lge_frags[frag];
1288 f->lge_fraglen = m->m_len;
1289 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1290 f->lge_fragptr_hi = 0;
1298 cur_tx->lge_mbuf = m_head;
1299 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1300 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1302 /* Queue for transmit */
1303 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1309 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1310 * to the mbuf data regions directly in the transmit lists. We also save a
1311 * copy of the pointers since the transmit list fragment pointers are
1312 * physical addresses.
1315 static void lge_start(ifp)
1318 struct lge_softc *sc;
1319 struct mbuf *m_head = NULL;
1327 idx = sc->lge_cdata.lge_tx_prod;
1329 if (ifp->if_flags & IFF_OACTIVE)
1332 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1333 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1336 IF_DEQUEUE(&ifp->if_snd, m_head);
1340 if (lge_encap(sc, m_head, &idx)) {
1341 IF_PREPEND(&ifp->if_snd, m_head);
1342 ifp->if_flags |= IFF_OACTIVE;
1347 * If there's a BPF listener, bounce a copy of this frame
1351 bpf_mtap(ifp, m_head);
1354 sc->lge_cdata.lge_tx_prod = idx;
1357 * Set a timeout in case the chip goes out to lunch.
1364 static void lge_init(xsc)
1367 struct lge_softc *sc = xsc;
1368 struct ifnet *ifp = &sc->arpcom.ac_if;
1369 struct mii_data *mii;
1372 if (ifp->if_flags & IFF_RUNNING)
1378 * Cancel pending I/O and free all RX/TX buffers.
1383 mii = device_get_softc(sc->lge_miibus);
1385 /* Set MAC address */
1386 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1387 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1389 /* Init circular RX list. */
1390 if (lge_list_rx_init(sc) == ENOBUFS) {
1391 printf("lge%d: initialization failed: no "
1392 "memory for rx buffers\n", sc->lge_unit);
1399 * Init tx descriptors.
1401 lge_list_tx_init(sc);
1403 /* Set initial value for MODE1 register. */
1404 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1405 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1406 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1407 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1409 /* If we want promiscuous mode, set the allframes bit. */
1410 if (ifp->if_flags & IFF_PROMISC) {
1411 CSR_WRITE_4(sc, LGE_MODE1,
1412 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1414 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1418 * Set the capture broadcast bit to capture broadcast frames.
1420 if (ifp->if_flags & IFF_BROADCAST) {
1421 CSR_WRITE_4(sc, LGE_MODE1,
1422 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1424 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1427 /* Packet padding workaround? */
1428 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1430 /* No error frames */
1431 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1433 /* Receive large frames */
1434 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1436 /* Workaround: disable RX/TX flow control */
1437 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1438 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1440 /* Make sure to strip CRC from received frames */
1441 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1443 /* Turn off magic packet mode */
1444 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1446 /* Turn off all VLAN stuff */
1447 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1448 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1450 /* Workarond: FIFO overflow */
1451 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1452 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1455 * Load the multicast filter.
1460 * Enable hardware checksum validation for all received IPv4
1461 * packets, do not reject packets with bad checksums.
1463 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1464 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1465 LGE_MODE2_RX_ERRCSUM);
1468 * Enable the delivery of PHY interrupts based on
1469 * link/speed/duplex status chalges.
1471 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1473 /* Enable receiver and transmitter. */
1474 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1475 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1477 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1478 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1481 * Enable interrupts.
1483 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1484 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1486 lge_ifmedia_upd(ifp);
1488 ifp->if_flags |= IFF_RUNNING;
1489 ifp->if_flags &= ~IFF_OACTIVE;
1493 sc->lge_stat_ch = timeout(lge_tick, sc, hz);
1499 * Set media options.
1501 static int lge_ifmedia_upd(ifp)
1504 struct lge_softc *sc;
1505 struct mii_data *mii;
1509 mii = device_get_softc(sc->lge_miibus);
1511 if (mii->mii_instance) {
1512 struct mii_softc *miisc;
1513 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1514 miisc = LIST_NEXT(miisc, mii_list))
1515 mii_phy_reset(miisc);
1523 * Report current media status.
1525 static void lge_ifmedia_sts(ifp, ifmr)
1527 struct ifmediareq *ifmr;
1529 struct lge_softc *sc;
1530 struct mii_data *mii;
1534 mii = device_get_softc(sc->lge_miibus);
1536 ifmr->ifm_active = mii->mii_media_active;
1537 ifmr->ifm_status = mii->mii_media_status;
1542 static int lge_ioctl(ifp, command, data)
1547 struct lge_softc *sc = ifp->if_softc;
1548 struct ifreq *ifr = (struct ifreq *) data;
1549 struct mii_data *mii;
1557 error = ether_ioctl(ifp, command, data);
1560 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1563 ifp->if_mtu = ifr->ifr_mtu;
1566 if (ifp->if_flags & IFF_UP) {
1567 if (ifp->if_flags & IFF_RUNNING &&
1568 ifp->if_flags & IFF_PROMISC &&
1569 !(sc->lge_if_flags & IFF_PROMISC)) {
1570 CSR_WRITE_4(sc, LGE_MODE1,
1571 LGE_MODE1_SETRST_CTL1|
1572 LGE_MODE1_RX_PROMISC);
1573 } else if (ifp->if_flags & IFF_RUNNING &&
1574 !(ifp->if_flags & IFF_PROMISC) &&
1575 sc->lge_if_flags & IFF_PROMISC) {
1576 CSR_WRITE_4(sc, LGE_MODE1,
1577 LGE_MODE1_RX_PROMISC);
1579 ifp->if_flags &= ~IFF_RUNNING;
1583 if (ifp->if_flags & IFF_RUNNING)
1586 sc->lge_if_flags = ifp->if_flags;
1596 mii = device_get_softc(sc->lge_miibus);
1597 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1609 static void lge_watchdog(ifp)
1612 struct lge_softc *sc;
1617 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1621 ifp->if_flags &= ~IFF_RUNNING;
1624 if (ifp->if_snd.ifq_head != NULL)
1631 * Stop the adapter and free any mbufs allocated to the
1634 static void lge_stop(sc)
1635 struct lge_softc *sc;
1640 ifp = &sc->arpcom.ac_if;
1642 untimeout(lge_tick, sc, sc->lge_stat_ch);
1643 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1645 /* Disable receiver and transmitter. */
1646 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1650 * Free data in the RX lists.
1652 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1653 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1654 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1655 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1658 bzero((char *)&sc->lge_ldata->lge_rx_list,
1659 sizeof(sc->lge_ldata->lge_rx_list));
1662 * Free the TX list buffers.
1664 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1665 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1666 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1667 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1671 bzero((char *)&sc->lge_ldata->lge_tx_list,
1672 sizeof(sc->lge_ldata->lge_tx_list));
1674 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1680 * Stop all chip I/O so that the kernel's probe routines don't
1681 * get confused by errant DMAs when rebooting.
1683 static void lge_shutdown(dev)
1686 struct lge_softc *sc;
1688 sc = device_get_softc(dev);