1 /* $FreeBSD: src/sys/dev/snc/dp83932subr.c,v 1.2.2.2 2003/06/01 04:24:50 nyan Exp $ */
2 /* $NecBSD: dp83932subr.c,v 1.5.6.2 1999/10/09 05:47:23 kmatsuda Exp $ */
6 * Copyright (c) 1997, 1998, 1999
7 * Kouichi Matsuda. All rights reserved.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Kouichi Matsuda for
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Routines of NEC PC-9801-83, 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R
37 * Ethernet interface for NetBSD/pc98, ported by Kouichi Matsuda.
39 * These cards use National Semiconductor DP83934AVQB as Ethernet Controller
40 * and National Semiconductor NS46C46 as (64 * 16 bits) Microwire Serial EEPROM.
44 * Modified for FreeBSD(98) 4.0 from NetBSD/pc98 1.4.2 by Motomichi Matsuzaki.
47 #include <sys/param.h>
48 #include <sys/systm.h>
50 #include <sys/protosw.h>
51 #include <sys/socket.h>
52 #include <sys/syslog.h>
53 #include <sys/errno.h>
55 #include <net/ethernet.h>
57 #include <net/if_arp.h>
58 #include <net/if_dl.h>
59 #include <net/if_types.h>
60 #include <net/if_media.h>
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #include <netinet/if_inarp.h>
73 #include <machine/clock.h>
74 #include <machine/cpu.h>
75 #include <machine/bus_pio.h>
76 #include <machine/bus_memio.h>
77 #include <machine/bus.h>
79 #include <dev/snc/dp83932reg.h>
80 #include <dev/snc/dp83932var.h>
81 #include <dev/snc/if_sncreg.h>
82 #include <dev/snc/dp83932subr.h>
84 integrate u_int16_t snc_nec16_select_bank
85 __P((struct snc_softc *, u_int32_t, u_int32_t));
88 * Interface exists: make available by filling in network interface
89 * record. System will initialize the interface when it is ready
102 * Put the pup in reset mode (sncinit() will fix it later),
103 * stop the timer, disable all interrupts and clear any interrupts.
105 NIC_PUT(sc, SNCR_CR, CR_STP);
107 NIC_PUT(sc, SNCR_CR, CR_RST);
109 NIC_PUT(sc, SNCR_IMR, 0);
111 NIC_PUT(sc, SNCR_ISR, ISR_ALL);
115 * because the SONIC is basically 16bit device it 'concatenates'
116 * a higher buffer address to a 16 bit offset--this will cause wrap
117 * around problems near the end of 64k !!
121 for (i = 0; i < NRRA; i++) {
122 sc->v_rra[i] = SONIC_GETDMA(p);
123 p += RXRSRC_SIZE(sc);
125 sc->v_rea = SONIC_GETDMA(p);
129 sc->v_cda = SONIC_GETDMA(p);
134 for (i = 0; i < NTDA; i++) {
135 struct mtd *mtdp = &sc->mtda[i];
136 mtdp->mtd_vtxp = SONIC_GETDMA(p);
142 if ((p - pp) > NBPG) {
143 device_printf (sc->sc_dev, "sizeof RRA (%ld) + CDA (%ld) +"
144 "TDA (%ld) > NBPG (%d). Punt!\n",
145 (ulong)sc->v_cda - (ulong)sc->v_rra[0],
146 (ulong)sc->mtda[0].mtd_vtxp - (ulong)sc->v_cda,
147 (ulong)p - (ulong)sc->mtda[0].mtd_vtxp,
155 sc->sc_nrda = NBPG / RXPKT_SIZE(sc);
156 sc->v_rda = SONIC_GETDMA(p);
160 for (i = 0; i < NRBA; i++) {
167 for (i = 0; i < NTDA; i++) {
168 struct mtd *mtdp = &sc->mtda[i];
170 mtdp->mtd_vbuf = SONIC_GETDMA(p);
185 * miscellaneous NEC/SONIC detect functions.
189 * check if a specified irq is acceptable.
192 snc_nec16_validate_irq(irq)
195 const u_int8_t encoded_irq[16] = {
196 -1, -1, -1, 0, -1, 1, 2, -1, -1, 3, 4, -1, 5, 6, -1, -1
199 return encoded_irq[irq];
203 * specify irq to board.
206 snc_nec16_register_irq(sc, irq)
207 struct snc_softc *sc;
210 bus_space_tag_t iot = sc->sc_iot;
211 bus_space_handle_t ioh = sc->sc_ioh;
212 u_int8_t encoded_irq;
214 encoded_irq = snc_nec16_validate_irq(irq);
215 if (encoded_irq == (u_int8_t) -1) {
216 printf("snc_nec16_register_irq: unsupported irq (%d)\n", irq);
220 /* select SNECR_IRQSEL register */
221 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IRQSEL);
222 /* write encoded irq value */
223 bus_space_write_1(iot, ioh, SNEC_CTRLB, encoded_irq);
229 * check if a specified memory base address is acceptable.
232 snc_nec16_validate_mem(maddr)
236 /* Check on Normal mode with max range, only */
237 if ((maddr & ~0x1E000) != 0xC0000) {
238 printf("snc_nec16_validate_mem: "
239 "unsupported window base (0x%x)\n", maddr);
247 * specify memory base address to board and map to first bank.
250 snc_nec16_register_mem(sc, maddr)
251 struct snc_softc *sc;
254 bus_space_tag_t iot = sc->sc_iot;
255 bus_space_handle_t ioh = sc->sc_ioh;
257 if (snc_nec16_validate_mem(maddr) == 0)
260 /* select SNECR_MEMSEL register */
261 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMSEL);
262 /* write encoded memory base select value */
263 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_MEMSEL_PHYS2EN(maddr));
266 * set current bank to 0 (bottom) and map
268 /* select SNECR_MEMBS register */
269 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
270 /* select new bank */
271 bus_space_write_1(iot, ioh, SNEC_CTRLB,
272 SNECR_MEMBS_B2EB(0) | SNECR_MEMBS_BSEN);
273 /* set current bank to 0 */
280 snc_nec16_check_memory(iot, ioh, memt, memh)
282 bus_space_handle_t ioh;
283 bus_space_tag_t memt;
284 bus_space_handle_t memh;
290 for (i = 0; i < SNEC_NBANK; i++) {
291 /* select new bank */
292 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
293 bus_space_write_1(iot, ioh, SNEC_CTRLB,
294 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
296 /* write test pattern */
297 for (j = 0; j < SNEC_NMEMS / 2; j++) {
298 bus_space_write_2(memt, memh, j * 2, val + j);
304 for (i = 0; i < SNEC_NBANK; i++) {
305 /* select new bank */
306 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
307 bus_space_write_1(iot, ioh, SNEC_CTRLB,
308 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
310 /* read test pattern */
311 for (j = 0; j < SNEC_NMEMS / 2; j++) {
312 if (bus_space_read_2(memt, memh, j * 2) != val + j)
316 if (j < SNEC_NMEMS / 2) {
317 printf("snc_nec16_check_memory: "
318 "memory check failed at 0x%04x%04x"
319 "val 0x%04x != expected 0x%04x\n", i, j,
320 bus_space_read_2(memt, memh, j * 2),
328 for (i = 0; i < SNEC_NBANK; i++) {
329 /* select new bank */
330 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
331 bus_space_write_1(iot, ioh, SNEC_CTRLB,
332 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
334 bus_space_set_region_4(memt, memh, 0, 0, SNEC_NMEMS >> 2);
337 /* again read test if these are 0 */
338 for (i = 0; i < SNEC_NBANK; i++) {
339 /* select new bank */
340 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
341 bus_space_write_1(iot, ioh, SNEC_CTRLB,
342 SNECR_MEMBS_B2EB(i) | SNECR_MEMBS_BSEN);
344 /* check if cleared */
345 for (j = 0; j < SNEC_NMEMS; j += 2) {
346 if (bus_space_read_2(memt, memh, j) != 0)
350 if (j != SNEC_NMEMS) {
351 printf("snc_nec16_check_memory: "
352 "memory zero clear failed at 0x%04x%04x\n", i, j);
361 snc_nec16_detectsubr(iot, ioh, memt, memh, irq, maddr, type)
363 bus_space_handle_t ioh;
364 bus_space_tag_t memt;
365 bus_space_handle_t memh;
374 if (snc_nec16_validate_irq(irq) == (u_int8_t) -1)
376 /* XXX: maddr already checked */
377 if (snc_nec16_validate_mem(maddr) == 0)
380 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_IDENT);
381 ident = bus_space_read_1(iot, ioh, SNEC_CTRLB);
382 if (ident == 0xff || ident == 0x00) {
388 case SNEC_TYPE_LEGACY:
389 rv = (ident == SNECR_IDENT_LEGACY_CBUS);
392 rv = ((ident == SNECR_IDENT_PNP_CBUS) ||
393 (ident == SNECR_IDENT_PNP_PCMCIABUS));
400 printf("snc_nec16_detectsubr: parent bus mismatch\n");
404 /* select SONIC register SNCR_CR */
405 bus_space_write_1(iot, ioh, SNEC_ADDR, SNCR_CR);
406 bus_space_write_2(iot, ioh, SNEC_CTRL, CR_RXDIS | CR_STP | CR_RST);
409 cr = bus_space_read_2(iot, ioh, SNEC_CTRL);
410 if (cr != (CR_RXDIS | CR_STP | CR_RST)) {
412 printf("snc_nec16_detectsubr: card reset failed, cr = 0x%04x\n",
418 if (snc_nec16_check_memory(iot, ioh, memt, memh) == 0)
425 #define SNC_VENDOR_NEC 0x00004c
426 #define SNC_NEC_SERIES_LEGACY_CBUS 0xa5
427 #define SNC_NEC_SERIES_PNP_PCMCIA 0xd5
428 #define SNC_NEC_SERIES_PNP_PCMCIA2 0x6d /* XXX */
429 #define SNC_NEC_SERIES_PNP_CBUS 0x0d
430 #define SNC_NEC_SERIES_PNP_CBUS2 0x3d
433 snc_nec16_detect_type(myea)
436 u_int32_t vendor = (myea[0] << 16) | (myea[1] << 8) | myea[2];
437 u_int8_t series = myea[3];
438 u_int8_t type = myea[4] & 0x80;
444 case SNC_NEC_SERIES_LEGACY_CBUS:
446 typestr = "NEC PC-9801-84";
448 typestr = "NEC PC-9801-83";
450 case SNC_NEC_SERIES_PNP_CBUS:
451 case SNC_NEC_SERIES_PNP_CBUS2:
453 typestr = "NEC PC-9801-104";
455 typestr = "NEC PC-9801-103";
457 case SNC_NEC_SERIES_PNP_PCMCIA:
458 case SNC_NEC_SERIES_PNP_PCMCIA2:
461 typestr = "NEC PC-9801N-J02R";
463 typestr = "NEC PC-9801N-J02";
466 typestr = "NEC unknown (PC-9801N-25?)";
471 typestr = "unknown (3rd vendor?)";
479 snc_nec16_get_enaddr(iot, ioh, myea)
481 bus_space_handle_t ioh;
484 u_int8_t eeprom[SNEC_EEPROM_SIZE];
485 u_int8_t rom_sum, sum = 0x00;
488 snc_nec16_read_eeprom(iot, ioh, eeprom);
490 for (i = SNEC_EEPROM_KEY0; i < SNEC_EEPROM_CKSUM; i++) {
491 sum = sum ^ eeprom[i];
494 rom_sum = eeprom[SNEC_EEPROM_CKSUM];
496 if (sum != rom_sum) {
497 printf("snc_nec16_get_enaddr: "
498 "checksum mismatch; calculated %02x != read %02x",
503 for (i = 0; i < ETHER_ADDR_LEN; i++)
504 myea[i] = eeprom[SNEC_EEPROM_SA0 + i];
510 * read from NEC/SONIC NIC register.
513 snc_nec16_nic_get(sc, reg)
514 struct snc_softc *sc;
519 /* select SONIC register */
520 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
521 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL);
527 * write to NEC/SONIC NIC register.
530 snc_nec16_nic_put(sc, reg, val)
531 struct snc_softc *sc;
536 /* select SONIC register */
537 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SNEC_ADDR, reg);
538 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SNEC_CTRL, val);
543 * select memory bank and map
544 * where exists specified (internal buffer memory) offset.
547 snc_nec16_select_bank(sc, base, offset)
548 struct snc_softc *sc;
552 bus_space_tag_t iot = sc->sc_iot;
553 bus_space_handle_t ioh = sc->sc_ioh;
557 /* bitmode is fixed to 16 bit. */
558 bank = (base + offset * 2) >> 13;
559 noffset = (base + offset * 2) & (SNEC_NMEMS - 1);
563 device_printf(sc->sc_dev, "noffset is odd (0x%04x)\n",
566 #endif /* SNCDEBUG */
568 if (sc->curbank != bank) {
569 /* select SNECR_MEMBS register */
570 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_MEMBS);
571 /* select new bank */
572 bus_space_write_1(iot, ioh, SNEC_CTRLB,
573 SNECR_MEMBS_B2EB(bank) | SNECR_MEMBS_BSEN);
574 /* update current bank */
582 * write to SONIC descriptors.
585 snc_nec16_writetodesc(sc, base, offset, val)
586 struct snc_softc *sc;
591 bus_space_tag_t memt = sc->sc_memt;
592 bus_space_handle_t memh = sc->sc_memh;
595 noffset = snc_nec16_select_bank(sc, base, offset);
597 bus_space_write_2(memt, memh, noffset, val);
601 * read from SONIC descriptors.
604 snc_nec16_readfromdesc(sc, base, offset)
605 struct snc_softc *sc;
609 bus_space_tag_t memt = sc->sc_memt;
610 bus_space_handle_t memh = sc->sc_memh;
613 noffset = snc_nec16_select_bank(sc, base, offset);
615 return bus_space_read_2(memt, memh, noffset);
619 * read from SONIC data buffer.
622 snc_nec16_copyfrombuf(sc, dst, offset, size)
623 struct snc_softc *sc;
628 bus_space_tag_t memt = sc->sc_memt;
629 bus_space_handle_t memh = sc->sc_memh;
631 u_int8_t* bptr = dst;
633 noffset = snc_nec16_select_bank(sc, offset, 0);
635 /* XXX: should check if offset + size < 0x2000. */
637 bus_space_barrier(memt, memh, noffset, size,
638 BUS_SPACE_BARRIER_READ);
642 size_t asize = 4 - (noffset & 3);
644 bus_space_read_region_1(memt, memh, noffset,
650 bus_space_read_region_4(memt, memh, noffset,
651 (u_int32_t *) bptr, size >> 2);
653 noffset += size & ~3;
657 bus_space_read_region_1(memt, memh, noffset, bptr, size);
661 * write to SONIC data buffer.
664 snc_nec16_copytobuf(sc, src, offset, size)
665 struct snc_softc *sc;
670 bus_space_tag_t memt = sc->sc_memt;
671 bus_space_handle_t memh = sc->sc_memh;
672 u_int16_t noffset, onoffset;
674 u_int8_t* bptr = src;
676 noffset = snc_nec16_select_bank(sc, offset, 0);
679 /* XXX: should check if offset + size < 0x2000. */
683 size_t asize = 4 - (noffset & 3);
685 bus_space_write_region_1(memt, memh, noffset,
691 bus_space_write_region_4(memt, memh, noffset,
692 (u_int32_t *)bptr, size >> 2);
694 noffset += size & ~3;
698 bus_space_write_region_1(memt, memh, noffset, bptr, size);
700 bus_space_barrier(memt, memh, onoffset, osize,
701 BUS_SPACE_BARRIER_WRITE);
705 * write (fill) 0 to SONIC data buffer.
708 snc_nec16_zerobuf(sc, offset, size)
709 struct snc_softc *sc;
713 bus_space_tag_t memt = sc->sc_memt;
714 bus_space_handle_t memh = sc->sc_memh;
715 u_int16_t noffset, onoffset;
718 noffset = snc_nec16_select_bank(sc, offset, 0);
721 /* XXX: should check if offset + size < 0x2000. */
725 size_t asize = 4 - (noffset & 3);
727 bus_space_set_region_1(memt, memh, noffset, 0, asize);
731 bus_space_set_region_4(memt, memh, noffset, 0, size >> 2);
732 noffset += size & ~3;
736 bus_space_set_region_1(memt, memh, noffset, 0, size);
738 bus_space_barrier(memt, memh, onoffset, osize,
739 BUS_SPACE_BARRIER_WRITE);
744 * Routines to read bytes sequentially from EEPROM through NEC PC-9801-83,
745 * 84, 103, 104, PC-9801N-25 and PC-9801N-J02, J02R for NetBSD/pc98.
746 * Ported by Kouichi Matsuda.
748 * This algorism is generic to read data sequentially from 4-Wire
749 * Microwire Serial EEPROM.
752 #define SNEC_EEP_DELAY 1000
755 snc_nec16_read_eeprom(iot, ioh, data)
757 bus_space_handle_t ioh;
760 u_int8_t n, val, bit;
762 /* Read bytes from EEPROM; two bytes per an iteration. */
763 for (n = 0; n < SNEC_EEPROM_SIZE / 2; n++) {
764 /* select SNECR_EEP */
765 bus_space_write_1(iot, ioh, SNEC_ADDR, SNECR_EEP);
767 bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
768 delay(SNEC_EEP_DELAY);
770 /* Start EEPROM access. */
771 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
772 delay(SNEC_EEP_DELAY);
774 bus_space_write_1(iot, ioh, SNEC_CTRLB,
775 SNECR_EEP_CS | SNECR_EEP_SK);
776 delay(SNEC_EEP_DELAY);
778 bus_space_write_1(iot, ioh, SNEC_CTRLB,
779 SNECR_EEP_CS | SNECR_EEP_DI);
780 delay(SNEC_EEP_DELAY);
782 bus_space_write_1(iot, ioh, SNEC_CTRLB,
783 SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
784 delay(SNEC_EEP_DELAY);
786 bus_space_write_1(iot, ioh, SNEC_CTRLB,
787 SNECR_EEP_CS | SNECR_EEP_DI);
788 delay(SNEC_EEP_DELAY);
790 bus_space_write_1(iot, ioh, SNEC_CTRLB,
791 SNECR_EEP_CS | SNECR_EEP_SK | SNECR_EEP_DI);
792 delay(SNEC_EEP_DELAY);
794 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
795 delay(SNEC_EEP_DELAY);
797 bus_space_write_1(iot, ioh, SNEC_CTRLB,
798 SNECR_EEP_CS | SNECR_EEP_SK);
799 delay(SNEC_EEP_DELAY);
801 /* Pass the iteration count to the chip. */
802 for (bit = 0x20; bit != 0x00; bit >>= 1) {
803 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS |
804 ((n & bit) ? SNECR_EEP_DI : 0x00));
805 delay(SNEC_EEP_DELAY);
807 bus_space_write_1(iot, ioh, SNEC_CTRLB,
808 SNECR_EEP_CS | SNECR_EEP_SK |
809 ((n & bit) ? SNECR_EEP_DI : 0x00));
810 delay(SNEC_EEP_DELAY);
813 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
814 (void) bus_space_read_1(iot, ioh, SNEC_CTRLB); /* ACK */
815 delay(SNEC_EEP_DELAY);
819 for (bit = 0x80; bit != 0x00; bit >>= 1) {
820 bus_space_write_1(iot, ioh, SNEC_CTRLB,
821 SNECR_EEP_CS | SNECR_EEP_SK);
822 delay(SNEC_EEP_DELAY);
824 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
826 if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
831 /* Read one more byte. */
833 for (bit = 0x80; bit != 0x00; bit >>= 1) {
834 bus_space_write_1(iot, ioh, SNEC_CTRLB,
835 SNECR_EEP_CS | SNECR_EEP_SK);
836 delay(SNEC_EEP_DELAY);
838 bus_space_write_1(iot, ioh, SNEC_CTRLB, SNECR_EEP_CS);
840 if (bus_space_read_1(iot, ioh, SNEC_CTRLB) & SNECR_EEP_DO)
845 bus_space_write_1(iot, ioh, SNEC_CTRLB, 0x00);
846 delay(SNEC_EEP_DELAY);
850 /* Report what we got. */
851 data -= SNEC_EEPROM_SIZE;
852 log(LOG_INFO, "%s: EEPROM:"
853 " %02x%02x%02x%02x %02x%02x%02x%02x -"
854 " %02x%02x%02x%02x %02x%02x%02x%02x -"
855 " %02x%02x%02x%02x %02x%02x%02x%02x -"
856 " %02x%02x%02x%02x %02x%02x%02x%02x\n",
857 "snc_nec16_read_eeprom",
858 data[ 0], data[ 1], data[ 2], data[ 3],
859 data[ 4], data[ 5], data[ 6], data[ 7],
860 data[ 8], data[ 9], data[10], data[11],
861 data[12], data[13], data[14], data[15],
862 data[16], data[17], data[18], data[19],
863 data[20], data[21], data[22], data[23],
864 data[24], data[25], data[26], data[27],
865 data[28], data[29], data[30], data[31]);
871 snc_nec16_dump_reg(iot, ioh)
873 bus_space_handle_t ioh;
878 printf("SONIC registers (word):");
879 for (n = 0; n < SNC_NREGS; n++) {
880 /* select required SONIC register */
881 bus_space_write_1(iot, ioh, SNEC_ADDR, n);
883 val = bus_space_read_2(iot, ioh, SNEC_CTRL);
885 printf("\n%04x ", val);
887 printf("%04x ", val);
891 printf("NEC/SONIC registers (byte):\n");
892 for (n = SNECR_MEMBS; n <= SNECR_IDENT; n += 2) {
893 /* select required SONIC register */
894 bus_space_write_1(iot, ioh, SNEC_ADDR, n);
896 val = (u_int16_t) bus_space_read_1(iot, ioh, SNEC_CTRLB);
897 printf("%04x ", val);
902 #endif /* SNCDEBUG */