2 * Copyright (c) 2000 Katsurajima Naoto <raven@katsurajima.seya.yokohama.jp>
3 * Copyright (c) 2001 Cameron Grant <cg@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
28 #include <dev/sound/pcm/sound.h>
29 #include <dev/sound/pcm/ac97.h>
30 #include <dev/sound/pci/ich.h>
32 #include <pci/pcireg.h>
33 #include <pci/pcivar.h>
35 SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/ich.c,v 1.3.2.12 2003/01/20 03:59:42 orion Exp $");
37 /* -------------------------------------------------------------------- */
39 #define ICH_TIMEOUT 1000 /* semaphore timeout polling count */
40 #define ICH_DTBL_LENGTH 32
41 #define ICH_DEFAULT_BUFSZ 16384
42 #define ICH_MAX_BUFSZ 65536
44 #define SIS7012ID 0x70121039 /* SiS 7012 needs special handling */
45 #define ICH4ID 0x24c58086 /* ICH4 needs special handling too */
47 /* buffer descriptor */
49 volatile u_int32_t buffer;
50 volatile u_int32_t length;
55 /* channel registers */
57 u_int32_t num:8, run:1, run_save:1;
58 u_int32_t blksz, blkcnt, spd;
59 u_int32_t regbase, spdreg;
63 struct snd_dbuf *buffer;
64 struct pcm_channel *channel;
65 struct sc_info *parent;
67 struct ich_desc *dtbl;
70 /* device private data */
73 int hasvra, hasvrm, hasmic;
74 unsigned int chnum, bufsz;
75 int sample_size, swap_reg;
77 struct resource *nambar, *nabmbar, *irq;
78 int nambarid, nabmbarid, irqid;
79 bus_space_tag_t nambart, nabmbart;
80 bus_space_handle_t nambarh, nabmbarh;
85 struct ac97_info *codec;
86 struct sc_chinfo ch[3];
88 struct ich_desc *dtbl;
89 struct intr_config_hook intrhook;
93 /* -------------------------------------------------------------------- */
95 static u_int32_t ich_fmt[] = {
96 AFMT_STEREO | AFMT_S16_LE,
99 static struct pcmchan_caps ich_vrcaps = {8000, 48000, ich_fmt, 0};
100 static struct pcmchan_caps ich_caps = {48000, 48000, ich_fmt, 0};
102 /* -------------------------------------------------------------------- */
105 ich_rd(struct sc_info *sc, int regno, int size)
109 return bus_space_read_1(sc->nabmbart, sc->nabmbarh, regno);
111 return bus_space_read_2(sc->nabmbart, sc->nabmbarh, regno);
113 return bus_space_read_4(sc->nabmbart, sc->nabmbarh, regno);
120 ich_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
124 bus_space_write_1(sc->nabmbart, sc->nabmbarh, regno, data);
127 bus_space_write_2(sc->nabmbart, sc->nabmbarh, regno, data);
130 bus_space_write_4(sc->nabmbart, sc->nabmbarh, regno, data);
137 ich_waitcd(void *devinfo)
141 struct sc_info *sc = (struct sc_info *)devinfo;
143 for (i = 0; i < ICH_TIMEOUT; i++) {
144 data = ich_rd(sc, ICH_REG_ACC_SEMA, 1);
145 if ((data & 0x01) == 0)
148 device_printf(sc->dev, "CODEC semaphore timeout\n");
153 ich_rdcd(kobj_t obj, void *devinfo, int regno)
155 struct sc_info *sc = (struct sc_info *)devinfo;
160 return bus_space_read_2(sc->nambart, sc->nambarh, regno);
164 ich_wrcd(kobj_t obj, void *devinfo, int regno, u_int16_t data)
166 struct sc_info *sc = (struct sc_info *)devinfo;
170 bus_space_write_2(sc->nambart, sc->nambarh, regno, data);
175 static kobj_method_t ich_ac97_methods[] = {
176 KOBJMETHOD(ac97_read, ich_rdcd),
177 KOBJMETHOD(ac97_write, ich_wrcd),
180 AC97_DECLARE(ich_ac97);
182 /* -------------------------------------------------------------------- */
183 /* common routines */
186 ich_filldtbl(struct sc_chinfo *ch)
191 base = vtophys(sndbuf_getbuf(ch->buffer));
192 ch->blkcnt = sndbuf_getsize(ch->buffer) / ch->blksz;
193 if (ch->blkcnt != 2 && ch->blkcnt != 4 && ch->blkcnt != 8 && ch->blkcnt != 16 && ch->blkcnt != 32) {
195 ch->blksz = sndbuf_getsize(ch->buffer) / ch->blkcnt;
198 for (i = 0; i < ICH_DTBL_LENGTH; i++) {
199 ch->dtbl[i].buffer = base + (ch->blksz * (i % ch->blkcnt));
200 ch->dtbl[i].length = ICH_BDC_IOC
201 | (ch->blksz / ch->parent->sample_size);
206 ich_resetchan(struct sc_info *sc, int num)
211 regbase = ICH_REG_PO_BASE;
213 regbase = ICH_REG_PI_BASE;
215 regbase = ICH_REG_MC_BASE;
219 ich_wr(sc, regbase + ICH_REG_X_CR, 0, 1);
221 ich_wr(sc, regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
222 for (i = 0; i < ICH_TIMEOUT; i++) {
223 cr = ich_rd(sc, regbase + ICH_REG_X_CR, 1);
228 device_printf(sc->dev, "cannot reset channel %d\n", num);
232 /* -------------------------------------------------------------------- */
233 /* channel interface */
236 ichchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
238 struct sc_info *sc = devinfo;
239 struct sc_chinfo *ch;
249 ch->dtbl = sc->dtbl + (ch->num * ICH_DTBL_LENGTH);
251 ch->blksz = sc->bufsz / ch->blkcnt;
255 KASSERT(dir == PCMDIR_PLAY, ("wrong direction"));
256 ch->regbase = ICH_REG_PO_BASE;
257 ch->spdreg = sc->hasvra? AC97_REGEXT_FDACRATE : 0;
258 ch->imask = ICH_GLOB_STA_POINT;
262 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
263 ch->regbase = ICH_REG_PI_BASE;
264 ch->spdreg = sc->hasvra? AC97_REGEXT_LADCRATE : 0;
265 ch->imask = ICH_GLOB_STA_PIINT;
269 KASSERT(dir == PCMDIR_REC, ("wrong direction"));
270 ch->regbase = ICH_REG_MC_BASE;
271 ch->spdreg = sc->hasvrm? AC97_REGEXT_MADCRATE : 0;
272 ch->imask = ICH_GLOB_STA_MINT;
279 if (sndbuf_alloc(ch->buffer, sc->dmat, sc->bufsz))
282 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
288 ichchan_setformat(kobj_t obj, void *data, u_int32_t format)
294 ichchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
296 struct sc_chinfo *ch = data;
297 struct sc_info *sc = ch->parent;
301 if (sc->ac97rate <= 32000 || sc->ac97rate >= 64000)
302 sc->ac97rate = 48000;
303 r = (speed * 48000) / sc->ac97rate;
305 * Cast the return value of ac97_setrate() to u_int so that
306 * the math don't overflow into the negative range.
308 ch->spd = ((u_int)ac97_setrate(sc->codec, ch->spdreg, r) *
309 sc->ac97rate) / 48000;
317 ichchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
319 struct sc_chinfo *ch = data;
320 struct sc_info *sc = ch->parent;
322 ch->blksz = blocksize;
324 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, ch->blkcnt - 1, 1);
330 ichchan_trigger(kobj_t obj, void *data, int go)
332 struct sc_chinfo *ch = data;
333 struct sc_info *sc = ch->parent;
338 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
339 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM | ICH_X_CR_LVBIE | ICH_X_CR_IOCE, 1);
343 ich_resetchan(sc, ch->num);
351 ichchan_getptr(kobj_t obj, void *data)
353 struct sc_chinfo *ch = data;
354 struct sc_info *sc = ch->parent;
357 ch->civ = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1) % ch->blkcnt;
359 pos = ch->civ * ch->blksz;
364 static struct pcmchan_caps *
365 ichchan_getcaps(kobj_t obj, void *data)
367 struct sc_chinfo *ch = data;
369 return ch->spdreg? &ich_vrcaps : &ich_caps;
372 static kobj_method_t ichchan_methods[] = {
373 KOBJMETHOD(channel_init, ichchan_init),
374 KOBJMETHOD(channel_setformat, ichchan_setformat),
375 KOBJMETHOD(channel_setspeed, ichchan_setspeed),
376 KOBJMETHOD(channel_setblocksize, ichchan_setblocksize),
377 KOBJMETHOD(channel_trigger, ichchan_trigger),
378 KOBJMETHOD(channel_getptr, ichchan_getptr),
379 KOBJMETHOD(channel_getcaps, ichchan_getcaps),
382 CHANNEL_DECLARE(ichchan);
384 /* -------------------------------------------------------------------- */
385 /* The interrupt handler */
390 struct sc_info *sc = (struct sc_info *)p;
391 struct sc_chinfo *ch;
392 u_int32_t cbi, lbi, lvi, st, gs;
395 gs = ich_rd(sc, ICH_REG_GLOB_STA, 4) & ICH_GLOB_STA_IMASK;
396 if (gs & (ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES)) {
397 /* Clear resume interrupt(s) - nothing doing with them */
398 ich_wr(sc, ICH_REG_GLOB_STA, gs, 4);
400 gs &= ~(ICH_GLOB_STA_PRES | ICH_GLOB_STA_SRES);
402 for (i = 0; i < 3; i++) {
404 if ((ch->imask & gs) == 0)
407 st = ich_rd(sc, ch->regbase +
408 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
410 st &= ICH_X_SR_FIFOE | ICH_X_SR_BCIS | ICH_X_SR_LVBCI;
411 if (st & (ICH_X_SR_BCIS | ICH_X_SR_LVBCI)) {
412 /* block complete - update buffer */
414 chn_intr(ch->channel);
415 lvi = ich_rd(sc, ch->regbase + ICH_REG_X_LVI, 1);
416 cbi = ch->civ % ch->blkcnt;
418 cbi = ch->blkcnt - 1;
421 lbi = lvi % ch->blkcnt;
425 lvi += cbi + ch->blkcnt - lbi;
426 lvi %= ICH_DTBL_LENGTH;
427 ich_wr(sc, ch->regbase + ICH_REG_X_LVI, lvi, 1);
430 /* clear status bit */
431 ich_wr(sc, ch->regbase +
432 (sc->swap_reg ? ICH_REG_X_PICB : ICH_REG_X_SR),
436 device_printf(sc->dev,
437 "Unhandled interrupt, gs_intr = %x\n", gs);
441 /* ------------------------------------------------------------------------- */
442 /* Sysctl to control ac97 speed (some boards overclocked ac97). */
445 ich_initsys(struct sc_info* sc)
448 SYSCTL_ADD_INT(snd_sysctl_tree(sc->dev),
449 SYSCTL_CHILDREN(snd_sysctl_tree_top(sc->dev)),
450 OID_AUTO, "ac97rate", CTLFLAG_RW,
451 &sc->ac97rate, 48000,
452 "AC97 link rate (default = 48000)");
453 #endif /* SND_DYNSYSCTL */
457 /* -------------------------------------------------------------------- */
458 /* Calibrate card (some boards are overclocked and need scaling) */
461 void ich_calibrate(void *arg)
464 struct sc_chinfo *ch;
465 struct timeval t1, t2;
467 u_int32_t wait_us, actual_48k_rate, bytes;
469 sc = (struct sc_info *)arg;
472 if (sc->use_intrhook)
473 config_intrhook_disestablish(&sc->intrhook);
476 * Grab audio from input for fixed interval and compare how
477 * much we actually get with what we expect. Interval needs
478 * to be sufficiently short that no interrupts are
482 KASSERT(ch->regbase == ICH_REG_PI_BASE, ("wrong direction"));
484 bytes = sndbuf_getsize(ch->buffer) / 2;
485 ichchan_setblocksize(0, ch, bytes);
488 * our data format is stereo, 16 bit so each sample is 4 bytes.
489 * assuming we get 48000 samples per second, we get 192000 bytes/sec.
490 * we're going to start recording with interrupts disabled and measure
491 * the time taken for one block to complete. we know the block size,
492 * we know the time in microseconds, we calculate the sample rate:
494 * actual_rate [bps] = bytes / (time [s] * 4)
495 * actual_rate [bps] = (bytes * 1000000) / (time [us] * 4)
496 * actual_rate [Hz] = (bytes * 250000) / time [us]
500 ociv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
502 ich_wr(sc, ch->regbase + ICH_REG_X_BDBAR, (u_int32_t)vtophys(ch->dtbl), 4);
506 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RPBM, 1);
509 while (nciv == ociv) {
511 if (t2.tv_sec - t1.tv_sec > 1)
513 nciv = ich_rd(sc, ch->regbase + ICH_REG_X_CIV, 1);
518 ich_wr(sc, ch->regbase + ICH_REG_X_CR, 0, 1);
522 ich_wr(sc, ch->regbase + ICH_REG_X_CR, ICH_X_CR_RR, 1);
524 /* turn time delta into us */
525 wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec;
528 device_printf(sc->dev, "ac97 link rate calibration timed out after %d us\n", wait_us);
532 actual_48k_rate = (bytes * 250000) / wait_us;
534 if (actual_48k_rate < 47500 || actual_48k_rate > 48500) {
535 sc->ac97rate = actual_48k_rate;
537 sc->ac97rate = 48000;
540 if (bootverbose || sc->ac97rate != 48000) {
541 device_printf(sc->dev, "measured ac97 link rate at %d Hz", actual_48k_rate);
542 if (sc->ac97rate != actual_48k_rate)
543 printf(", will use %d Hz", sc->ac97rate);
549 /* -------------------------------------------------------------------- */
550 /* Probe and attach the card */
553 ich_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
559 ich_init(struct sc_info *sc)
564 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD, 4);
566 stat = ich_rd(sc, ICH_REG_GLOB_STA, 4);
568 if ((stat & ICH_GLOB_STA_PCR) == 0) {
569 /* ICH4 may fail when busmastering is enabled. Continue */
570 if (pci_get_devid(sc->dev) != ICH4ID) {
575 ich_wr(sc, ICH_REG_GLOB_CNT, ICH_GLOB_CTL_COLD | ICH_GLOB_CTL_PRES, 4);
577 if (ich_resetchan(sc, 0) || ich_resetchan(sc, 1))
579 if (sc->hasmic && ich_resetchan(sc, 2))
582 if (bus_dmamem_alloc(sc->dmat, (void **)&sc->dtbl, BUS_DMA_NOWAIT, &sc->dtmap))
585 sz = sizeof(struct ich_desc) * ICH_DTBL_LENGTH * 3;
586 if (bus_dmamap_load(sc->dmat, sc->dtmap, sc->dtbl, sz, ich_setmap, NULL, 0)) {
587 bus_dmamem_free(sc->dmat, (void **)&sc->dtbl, sc->dtmap);
595 ich_pci_probe(device_t dev)
597 switch(pci_get_devid(dev)) {
599 device_set_desc(dev, "Intel 443MX");
603 device_set_desc(dev, "Intel 82801AA (ICH)");
607 device_set_desc(dev, "Intel 82801AB (ICH)");
611 device_set_desc(dev, "Intel 82801BA (ICH2)");
615 device_set_desc(dev, "Intel 82801CA (ICH3)");
619 device_set_desc(dev, "Intel 82801DB (ICH4)");
623 device_set_desc(dev, "SiS 7012");
627 device_set_desc(dev, "Nvidia nForce AC97 controller");
631 device_set_desc(dev, "Nvidia nForce2 AC97 controller");
640 ich_pci_attach(device_t dev)
644 char status[SND_STATUSLEN];
646 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT)) == NULL) {
647 device_printf(dev, "cannot allocate softc\n");
651 bzero(sc, sizeof(*sc));
655 * The SiS 7012 register set isn't quite like the standard ich.
656 * There really should be a general "quirks" mechanism.
658 if (pci_get_devid(dev) == SIS7012ID) {
667 * By default, ich4 has NAMBAR and NABMBAR i/o spaces as
668 * read-only. Need to enable "legacy support", by poking into
669 * pci config space. The driver should use MMBAR and MBBAR,
670 * but doing so will mess things up here. ich4 has enough new
671 * features it warrants it's own driver.
673 if (pci_get_devid(dev) == ICH4ID) {
674 pci_write_config(dev, PCIR_ICH_LEGACY, ICH_LEGACY_ENABLE, 1);
677 pci_enable_io(dev, SYS_RES_IOPORT);
679 * Enable bus master. On ich4 this may prevent the detection of
680 * the primary codec becoming ready in ich_init().
682 pci_enable_busmaster(dev);
684 sc->nambarid = PCIR_NAMBAR;
685 sc->nabmbarid = PCIR_NABMBAR;
686 sc->nambar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nambarid, 0, ~0, 1, RF_ACTIVE);
687 sc->nabmbar = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->nabmbarid, 0, ~0, 1, RF_ACTIVE);
689 if (!sc->nambar || !sc->nabmbar) {
690 device_printf(dev, "unable to map IO port space\n");
694 sc->nambart = rman_get_bustag(sc->nambar);
695 sc->nambarh = rman_get_bushandle(sc->nambar);
696 sc->nabmbart = rman_get_bustag(sc->nabmbar);
697 sc->nabmbarh = rman_get_bushandle(sc->nabmbar);
699 sc->bufsz = pcm_getbuffersize(dev, 4096, ICH_DEFAULT_BUFSZ, ICH_MAX_BUFSZ);
700 if (bus_dma_tag_create(NULL, 8, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
701 NULL, NULL, sc->bufsz, 1, 0x3ffff, 0, &sc->dmat) != 0) {
702 device_printf(dev, "unable to create dma tag\n");
707 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid, 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
708 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ich_intr, sc, &sc->ih)) {
709 device_printf(dev, "unable to map interrupt\n");
714 device_printf(dev, "unable to initialize the card\n");
718 sc->codec = AC97_CREATE(dev, sc, ich_ac97);
719 if (sc->codec == NULL)
721 mixer_init(dev, ac97_getmixerclass(), sc->codec);
723 /* check and set VRA function */
724 extcaps = ac97_getextcaps(sc->codec);
725 sc->hasvra = extcaps & AC97_EXTCAP_VRA;
726 sc->hasvrm = extcaps & AC97_EXTCAP_VRM;
727 sc->hasmic = ac97_getcaps(sc->codec) & AC97_CAP_MICCHANNEL;
728 ac97_setextmode(sc->codec, sc->hasvra | sc->hasvrm);
730 if (pcm_register(dev, sc, 1, sc->hasmic? 2 : 1))
733 pcm_addchan(dev, PCMDIR_PLAY, &ichchan_class, sc); /* play */
734 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record */
736 pcm_addchan(dev, PCMDIR_REC, &ichchan_class, sc); /* record mic */
738 snprintf(status, SND_STATUSLEN, "at io 0x%lx, 0x%lx irq %ld bufsz %u",
739 rman_get_start(sc->nambar), rman_get_start(sc->nabmbar), rman_get_start(sc->irq), sc->bufsz);
741 pcm_setstatus(dev, status);
745 sc->intrhook.ich_func = ich_calibrate;
746 sc->intrhook.ich_arg = sc;
747 sc->use_intrhook = 1;
748 if (config_intrhook_establish(&sc->intrhook) != 0) {
749 device_printf(dev, "Cannot establish calibration hook, will calibrate now\n");
750 sc->use_intrhook = 0;
758 ac97_destroy(sc->codec);
760 bus_teardown_intr(dev, sc->irq, sc->ih);
762 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
764 bus_release_resource(dev, SYS_RES_IOPORT,
765 sc->nambarid, sc->nambar);
767 bus_release_resource(dev, SYS_RES_IOPORT,
768 sc->nabmbarid, sc->nabmbar);
774 ich_pci_detach(device_t dev)
779 r = pcm_unregister(dev);
782 sc = pcm_getdevinfo(dev);
784 bus_teardown_intr(dev, sc->irq, sc->ih);
785 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
786 bus_release_resource(dev, SYS_RES_IOPORT, sc->nambarid, sc->nambar);
787 bus_release_resource(dev, SYS_RES_IOPORT, sc->nabmbarid, sc->nabmbar);
788 bus_dma_tag_destroy(sc->dmat);
794 ich_pci_suspend(device_t dev)
799 sc = pcm_getdevinfo(dev);
800 for (i = 0 ; i < 3; i++) {
801 sc->ch[i].run_save = sc->ch[i].run;
803 ichchan_trigger(0, &sc->ch[i], PCMTRIG_ABORT);
810 ich_pci_resume(device_t dev)
815 sc = pcm_getdevinfo(dev);
817 /* Reinit audio device */
818 if (ich_init(sc) == -1) {
819 device_printf(dev, "unable to reinitialize the card\n");
823 if (mixer_reinit(dev) == -1) {
824 device_printf(dev, "unable to reinitialize the mixer\n");
827 /* Re-start DMA engines */
828 for (i = 0 ; i < 3; i++) {
829 struct sc_chinfo *ch = &sc->ch[i];
830 if (sc->ch[i].run_save) {
831 ichchan_setblocksize(0, ch, ch->blksz);
832 ichchan_setspeed(0, ch, ch->spd);
833 ichchan_trigger(0, ch, PCMTRIG_START);
839 static device_method_t ich_methods[] = {
840 /* Device interface */
841 DEVMETHOD(device_probe, ich_pci_probe),
842 DEVMETHOD(device_attach, ich_pci_attach),
843 DEVMETHOD(device_detach, ich_pci_detach),
844 DEVMETHOD(device_suspend, ich_pci_suspend),
845 DEVMETHOD(device_resume, ich_pci_resume),
849 static driver_t ich_driver = {
855 DRIVER_MODULE(snd_ich, pci, ich_driver, pcm_devclass, 0, 0);
856 MODULE_DEPEND(snd_ich, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
857 MODULE_VERSION(snd_ich, 1);