x86_64: Allow UP kernel to use LAPIC timer and I/O APIC
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
1 /*
2  * Copyright (c) 1991 The Regents of the University of California.
3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
4  * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
5  * All rights reserved.
6  * 
7  * This code is derived from software contributed to The DragonFly Project
8  * by Matthew Dillon <dillon@backplane.com>
9  *
10  * This code is derived from software contributed to Berkeley by
11  * William Jolitz.
12  * 
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  * 3. Neither the name of The DragonFly Project nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific, prior written permission.
26  * 
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41  */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
48 #include <sys/bus.h>
49
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/globaldata.h>
55
56 #include <sys/thread2.h>
57
58 #include <machine_base/icu/icu.h>
59 #include <machine_base/icu/icu_var.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/apic/ioapic_abi.h>
62 #include <machine_base/apic/ioapic_ipl.h>
63 #include <machine_base/apic/apicreg.h>
64
65 extern inthand_t
66         IDTVEC(ioapic_intr0),
67         IDTVEC(ioapic_intr1),
68         IDTVEC(ioapic_intr2),
69         IDTVEC(ioapic_intr3),
70         IDTVEC(ioapic_intr4),
71         IDTVEC(ioapic_intr5),
72         IDTVEC(ioapic_intr6),
73         IDTVEC(ioapic_intr7),
74         IDTVEC(ioapic_intr8),
75         IDTVEC(ioapic_intr9),
76         IDTVEC(ioapic_intr10),
77         IDTVEC(ioapic_intr11),
78         IDTVEC(ioapic_intr12),
79         IDTVEC(ioapic_intr13),
80         IDTVEC(ioapic_intr14),
81         IDTVEC(ioapic_intr15),
82         IDTVEC(ioapic_intr16),
83         IDTVEC(ioapic_intr17),
84         IDTVEC(ioapic_intr18),
85         IDTVEC(ioapic_intr19),
86         IDTVEC(ioapic_intr20),
87         IDTVEC(ioapic_intr21),
88         IDTVEC(ioapic_intr22),
89         IDTVEC(ioapic_intr23),
90         IDTVEC(ioapic_intr24),
91         IDTVEC(ioapic_intr25),
92         IDTVEC(ioapic_intr26),
93         IDTVEC(ioapic_intr27),
94         IDTVEC(ioapic_intr28),
95         IDTVEC(ioapic_intr29),
96         IDTVEC(ioapic_intr30),
97         IDTVEC(ioapic_intr31),
98         IDTVEC(ioapic_intr32),
99         IDTVEC(ioapic_intr33),
100         IDTVEC(ioapic_intr34),
101         IDTVEC(ioapic_intr35),
102         IDTVEC(ioapic_intr36),
103         IDTVEC(ioapic_intr37),
104         IDTVEC(ioapic_intr38),
105         IDTVEC(ioapic_intr39),
106         IDTVEC(ioapic_intr40),
107         IDTVEC(ioapic_intr41),
108         IDTVEC(ioapic_intr42),
109         IDTVEC(ioapic_intr43),
110         IDTVEC(ioapic_intr44),
111         IDTVEC(ioapic_intr45),
112         IDTVEC(ioapic_intr46),
113         IDTVEC(ioapic_intr47),
114         IDTVEC(ioapic_intr48),
115         IDTVEC(ioapic_intr49),
116         IDTVEC(ioapic_intr50),
117         IDTVEC(ioapic_intr51),
118         IDTVEC(ioapic_intr52),
119         IDTVEC(ioapic_intr53),
120         IDTVEC(ioapic_intr54),
121         IDTVEC(ioapic_intr55),
122         IDTVEC(ioapic_intr56),
123         IDTVEC(ioapic_intr57),
124         IDTVEC(ioapic_intr58),
125         IDTVEC(ioapic_intr59),
126         IDTVEC(ioapic_intr60),
127         IDTVEC(ioapic_intr61),
128         IDTVEC(ioapic_intr62),
129         IDTVEC(ioapic_intr63),
130         IDTVEC(ioapic_intr64),
131         IDTVEC(ioapic_intr65),
132         IDTVEC(ioapic_intr66),
133         IDTVEC(ioapic_intr67),
134         IDTVEC(ioapic_intr68),
135         IDTVEC(ioapic_intr69),
136         IDTVEC(ioapic_intr70),
137         IDTVEC(ioapic_intr71),
138         IDTVEC(ioapic_intr72),
139         IDTVEC(ioapic_intr73),
140         IDTVEC(ioapic_intr74),
141         IDTVEC(ioapic_intr75),
142         IDTVEC(ioapic_intr76),
143         IDTVEC(ioapic_intr77),
144         IDTVEC(ioapic_intr78),
145         IDTVEC(ioapic_intr79),
146         IDTVEC(ioapic_intr80),
147         IDTVEC(ioapic_intr81),
148         IDTVEC(ioapic_intr82),
149         IDTVEC(ioapic_intr83),
150         IDTVEC(ioapic_intr84),
151         IDTVEC(ioapic_intr85),
152         IDTVEC(ioapic_intr86),
153         IDTVEC(ioapic_intr87),
154         IDTVEC(ioapic_intr88),
155         IDTVEC(ioapic_intr89),
156         IDTVEC(ioapic_intr90),
157         IDTVEC(ioapic_intr91),
158         IDTVEC(ioapic_intr92),
159         IDTVEC(ioapic_intr93),
160         IDTVEC(ioapic_intr94),
161         IDTVEC(ioapic_intr95),
162         IDTVEC(ioapic_intr96),
163         IDTVEC(ioapic_intr97),
164         IDTVEC(ioapic_intr98),
165         IDTVEC(ioapic_intr99),
166         IDTVEC(ioapic_intr100),
167         IDTVEC(ioapic_intr101),
168         IDTVEC(ioapic_intr102),
169         IDTVEC(ioapic_intr103),
170         IDTVEC(ioapic_intr104),
171         IDTVEC(ioapic_intr105),
172         IDTVEC(ioapic_intr106),
173         IDTVEC(ioapic_intr107),
174         IDTVEC(ioapic_intr108),
175         IDTVEC(ioapic_intr109),
176         IDTVEC(ioapic_intr110),
177         IDTVEC(ioapic_intr111),
178         IDTVEC(ioapic_intr112),
179         IDTVEC(ioapic_intr113),
180         IDTVEC(ioapic_intr114),
181         IDTVEC(ioapic_intr115),
182         IDTVEC(ioapic_intr116),
183         IDTVEC(ioapic_intr117),
184         IDTVEC(ioapic_intr118),
185         IDTVEC(ioapic_intr119),
186         IDTVEC(ioapic_intr120),
187         IDTVEC(ioapic_intr121),
188         IDTVEC(ioapic_intr122),
189         IDTVEC(ioapic_intr123),
190         IDTVEC(ioapic_intr124),
191         IDTVEC(ioapic_intr125),
192         IDTVEC(ioapic_intr126),
193         IDTVEC(ioapic_intr127),
194         IDTVEC(ioapic_intr128),
195         IDTVEC(ioapic_intr129),
196         IDTVEC(ioapic_intr130),
197         IDTVEC(ioapic_intr131),
198         IDTVEC(ioapic_intr132),
199         IDTVEC(ioapic_intr133),
200         IDTVEC(ioapic_intr134),
201         IDTVEC(ioapic_intr135),
202         IDTVEC(ioapic_intr136),
203         IDTVEC(ioapic_intr137),
204         IDTVEC(ioapic_intr138),
205         IDTVEC(ioapic_intr139),
206         IDTVEC(ioapic_intr140),
207         IDTVEC(ioapic_intr141),
208         IDTVEC(ioapic_intr142),
209         IDTVEC(ioapic_intr143),
210         IDTVEC(ioapic_intr144),
211         IDTVEC(ioapic_intr145),
212         IDTVEC(ioapic_intr146),
213         IDTVEC(ioapic_intr147),
214         IDTVEC(ioapic_intr148),
215         IDTVEC(ioapic_intr149),
216         IDTVEC(ioapic_intr150),
217         IDTVEC(ioapic_intr151),
218         IDTVEC(ioapic_intr152),
219         IDTVEC(ioapic_intr153),
220         IDTVEC(ioapic_intr154),
221         IDTVEC(ioapic_intr155),
222         IDTVEC(ioapic_intr156),
223         IDTVEC(ioapic_intr157),
224         IDTVEC(ioapic_intr158),
225         IDTVEC(ioapic_intr159),
226         IDTVEC(ioapic_intr160),
227         IDTVEC(ioapic_intr161),
228         IDTVEC(ioapic_intr162),
229         IDTVEC(ioapic_intr163),
230         IDTVEC(ioapic_intr164),
231         IDTVEC(ioapic_intr165),
232         IDTVEC(ioapic_intr166),
233         IDTVEC(ioapic_intr167),
234         IDTVEC(ioapic_intr168),
235         IDTVEC(ioapic_intr169),
236         IDTVEC(ioapic_intr170),
237         IDTVEC(ioapic_intr171),
238         IDTVEC(ioapic_intr172),
239         IDTVEC(ioapic_intr173),
240         IDTVEC(ioapic_intr174),
241         IDTVEC(ioapic_intr175),
242         IDTVEC(ioapic_intr176),
243         IDTVEC(ioapic_intr177),
244         IDTVEC(ioapic_intr178),
245         IDTVEC(ioapic_intr179),
246         IDTVEC(ioapic_intr180),
247         IDTVEC(ioapic_intr181),
248         IDTVEC(ioapic_intr182),
249         IDTVEC(ioapic_intr183),
250         IDTVEC(ioapic_intr184),
251         IDTVEC(ioapic_intr185),
252         IDTVEC(ioapic_intr186),
253         IDTVEC(ioapic_intr187),
254         IDTVEC(ioapic_intr188),
255         IDTVEC(ioapic_intr189),
256         IDTVEC(ioapic_intr190),
257         IDTVEC(ioapic_intr191);
258
259 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
260         &IDTVEC(ioapic_intr0),
261         &IDTVEC(ioapic_intr1),
262         &IDTVEC(ioapic_intr2),
263         &IDTVEC(ioapic_intr3),
264         &IDTVEC(ioapic_intr4),
265         &IDTVEC(ioapic_intr5),
266         &IDTVEC(ioapic_intr6),
267         &IDTVEC(ioapic_intr7),
268         &IDTVEC(ioapic_intr8),
269         &IDTVEC(ioapic_intr9),
270         &IDTVEC(ioapic_intr10),
271         &IDTVEC(ioapic_intr11),
272         &IDTVEC(ioapic_intr12),
273         &IDTVEC(ioapic_intr13),
274         &IDTVEC(ioapic_intr14),
275         &IDTVEC(ioapic_intr15),
276         &IDTVEC(ioapic_intr16),
277         &IDTVEC(ioapic_intr17),
278         &IDTVEC(ioapic_intr18),
279         &IDTVEC(ioapic_intr19),
280         &IDTVEC(ioapic_intr20),
281         &IDTVEC(ioapic_intr21),
282         &IDTVEC(ioapic_intr22),
283         &IDTVEC(ioapic_intr23),
284         &IDTVEC(ioapic_intr24),
285         &IDTVEC(ioapic_intr25),
286         &IDTVEC(ioapic_intr26),
287         &IDTVEC(ioapic_intr27),
288         &IDTVEC(ioapic_intr28),
289         &IDTVEC(ioapic_intr29),
290         &IDTVEC(ioapic_intr30),
291         &IDTVEC(ioapic_intr31),
292         &IDTVEC(ioapic_intr32),
293         &IDTVEC(ioapic_intr33),
294         &IDTVEC(ioapic_intr34),
295         &IDTVEC(ioapic_intr35),
296         &IDTVEC(ioapic_intr36),
297         &IDTVEC(ioapic_intr37),
298         &IDTVEC(ioapic_intr38),
299         &IDTVEC(ioapic_intr39),
300         &IDTVEC(ioapic_intr40),
301         &IDTVEC(ioapic_intr41),
302         &IDTVEC(ioapic_intr42),
303         &IDTVEC(ioapic_intr43),
304         &IDTVEC(ioapic_intr44),
305         &IDTVEC(ioapic_intr45),
306         &IDTVEC(ioapic_intr46),
307         &IDTVEC(ioapic_intr47),
308         &IDTVEC(ioapic_intr48),
309         &IDTVEC(ioapic_intr49),
310         &IDTVEC(ioapic_intr50),
311         &IDTVEC(ioapic_intr51),
312         &IDTVEC(ioapic_intr52),
313         &IDTVEC(ioapic_intr53),
314         &IDTVEC(ioapic_intr54),
315         &IDTVEC(ioapic_intr55),
316         &IDTVEC(ioapic_intr56),
317         &IDTVEC(ioapic_intr57),
318         &IDTVEC(ioapic_intr58),
319         &IDTVEC(ioapic_intr59),
320         &IDTVEC(ioapic_intr60),
321         &IDTVEC(ioapic_intr61),
322         &IDTVEC(ioapic_intr62),
323         &IDTVEC(ioapic_intr63),
324         &IDTVEC(ioapic_intr64),
325         &IDTVEC(ioapic_intr65),
326         &IDTVEC(ioapic_intr66),
327         &IDTVEC(ioapic_intr67),
328         &IDTVEC(ioapic_intr68),
329         &IDTVEC(ioapic_intr69),
330         &IDTVEC(ioapic_intr70),
331         &IDTVEC(ioapic_intr71),
332         &IDTVEC(ioapic_intr72),
333         &IDTVEC(ioapic_intr73),
334         &IDTVEC(ioapic_intr74),
335         &IDTVEC(ioapic_intr75),
336         &IDTVEC(ioapic_intr76),
337         &IDTVEC(ioapic_intr77),
338         &IDTVEC(ioapic_intr78),
339         &IDTVEC(ioapic_intr79),
340         &IDTVEC(ioapic_intr80),
341         &IDTVEC(ioapic_intr81),
342         &IDTVEC(ioapic_intr82),
343         &IDTVEC(ioapic_intr83),
344         &IDTVEC(ioapic_intr84),
345         &IDTVEC(ioapic_intr85),
346         &IDTVEC(ioapic_intr86),
347         &IDTVEC(ioapic_intr87),
348         &IDTVEC(ioapic_intr88),
349         &IDTVEC(ioapic_intr89),
350         &IDTVEC(ioapic_intr90),
351         &IDTVEC(ioapic_intr91),
352         &IDTVEC(ioapic_intr92),
353         &IDTVEC(ioapic_intr93),
354         &IDTVEC(ioapic_intr94),
355         &IDTVEC(ioapic_intr95),
356         &IDTVEC(ioapic_intr96),
357         &IDTVEC(ioapic_intr97),
358         &IDTVEC(ioapic_intr98),
359         &IDTVEC(ioapic_intr99),
360         &IDTVEC(ioapic_intr100),
361         &IDTVEC(ioapic_intr101),
362         &IDTVEC(ioapic_intr102),
363         &IDTVEC(ioapic_intr103),
364         &IDTVEC(ioapic_intr104),
365         &IDTVEC(ioapic_intr105),
366         &IDTVEC(ioapic_intr106),
367         &IDTVEC(ioapic_intr107),
368         &IDTVEC(ioapic_intr108),
369         &IDTVEC(ioapic_intr109),
370         &IDTVEC(ioapic_intr110),
371         &IDTVEC(ioapic_intr111),
372         &IDTVEC(ioapic_intr112),
373         &IDTVEC(ioapic_intr113),
374         &IDTVEC(ioapic_intr114),
375         &IDTVEC(ioapic_intr115),
376         &IDTVEC(ioapic_intr116),
377         &IDTVEC(ioapic_intr117),
378         &IDTVEC(ioapic_intr118),
379         &IDTVEC(ioapic_intr119),
380         &IDTVEC(ioapic_intr120),
381         &IDTVEC(ioapic_intr121),
382         &IDTVEC(ioapic_intr122),
383         &IDTVEC(ioapic_intr123),
384         &IDTVEC(ioapic_intr124),
385         &IDTVEC(ioapic_intr125),
386         &IDTVEC(ioapic_intr126),
387         &IDTVEC(ioapic_intr127),
388         &IDTVEC(ioapic_intr128),
389         &IDTVEC(ioapic_intr129),
390         &IDTVEC(ioapic_intr130),
391         &IDTVEC(ioapic_intr131),
392         &IDTVEC(ioapic_intr132),
393         &IDTVEC(ioapic_intr133),
394         &IDTVEC(ioapic_intr134),
395         &IDTVEC(ioapic_intr135),
396         &IDTVEC(ioapic_intr136),
397         &IDTVEC(ioapic_intr137),
398         &IDTVEC(ioapic_intr138),
399         &IDTVEC(ioapic_intr139),
400         &IDTVEC(ioapic_intr140),
401         &IDTVEC(ioapic_intr141),
402         &IDTVEC(ioapic_intr142),
403         &IDTVEC(ioapic_intr143),
404         &IDTVEC(ioapic_intr144),
405         &IDTVEC(ioapic_intr145),
406         &IDTVEC(ioapic_intr146),
407         &IDTVEC(ioapic_intr147),
408         &IDTVEC(ioapic_intr148),
409         &IDTVEC(ioapic_intr149),
410         &IDTVEC(ioapic_intr150),
411         &IDTVEC(ioapic_intr151),
412         &IDTVEC(ioapic_intr152),
413         &IDTVEC(ioapic_intr153),
414         &IDTVEC(ioapic_intr154),
415         &IDTVEC(ioapic_intr155),
416         &IDTVEC(ioapic_intr156),
417         &IDTVEC(ioapic_intr157),
418         &IDTVEC(ioapic_intr158),
419         &IDTVEC(ioapic_intr159),
420         &IDTVEC(ioapic_intr160),
421         &IDTVEC(ioapic_intr161),
422         &IDTVEC(ioapic_intr162),
423         &IDTVEC(ioapic_intr163),
424         &IDTVEC(ioapic_intr164),
425         &IDTVEC(ioapic_intr165),
426         &IDTVEC(ioapic_intr166),
427         &IDTVEC(ioapic_intr167),
428         &IDTVEC(ioapic_intr168),
429         &IDTVEC(ioapic_intr169),
430         &IDTVEC(ioapic_intr170),
431         &IDTVEC(ioapic_intr171),
432         &IDTVEC(ioapic_intr172),
433         &IDTVEC(ioapic_intr173),
434         &IDTVEC(ioapic_intr174),
435         &IDTVEC(ioapic_intr175),
436         &IDTVEC(ioapic_intr176),
437         &IDTVEC(ioapic_intr177),
438         &IDTVEC(ioapic_intr178),
439         &IDTVEC(ioapic_intr179),
440         &IDTVEC(ioapic_intr180),
441         &IDTVEC(ioapic_intr181),
442         &IDTVEC(ioapic_intr182),
443         &IDTVEC(ioapic_intr183),
444         &IDTVEC(ioapic_intr184),
445         &IDTVEC(ioapic_intr185),
446         &IDTVEC(ioapic_intr186),
447         &IDTVEC(ioapic_intr187),
448         &IDTVEC(ioapic_intr188),
449         &IDTVEC(ioapic_intr189),
450         &IDTVEC(ioapic_intr190),
451         &IDTVEC(ioapic_intr191)
452 };
453
454 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
455
456 static struct ioapic_irqmap {
457         int                     im_type;        /* IOAPIC_IMT_ */
458         enum intr_trigger       im_trig;
459         enum intr_polarity      im_pola;
460         int                     im_gsi;
461         uint32_t                im_flags;       /* IOAPIC_IMF_ */
462 } ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
463
464 #define IOAPIC_IMT_UNUSED       0
465 #define IOAPIC_IMT_RESERVED     1
466 #define IOAPIC_IMT_LINE         2
467 #define IOAPIC_IMT_SYSCALL      3
468
469 #define IOAPIC_IMF_CONF         0x1
470
471 extern void     IOAPIC_INTREN(int);
472 extern void     IOAPIC_INTRDIS(int);
473
474 extern int      imcr_present;
475
476 static int      ioapic_setvar(int, const void *);
477 static int      ioapic_getvar(int, void *);
478 static int      ioapic_vectorctl(int, int, int);
479 static void     ioapic_finalize(void);
480 static void     ioapic_cleanup(void);
481 static void     ioapic_setdefault(void);
482 static void     ioapic_stabilize(void);
483 static void     ioapic_initmap(void);
484 static void     ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
485 static void     ioapic_abi_intren(int);
486 static void     ioapic_abi_intrdis(int);
487
488 struct machintr_abi MachIntrABI_IOAPIC = {
489         MACHINTR_IOAPIC,
490         .intrdis        = ioapic_abi_intrdis,
491         .intren         = ioapic_abi_intren,
492         .vectorctl      = ioapic_vectorctl,
493         .setvar         = ioapic_setvar,
494         .getvar         = ioapic_getvar,
495         .finalize       = ioapic_finalize,
496         .cleanup        = ioapic_cleanup,
497         .setdefault     = ioapic_setdefault,
498         .stabilize      = ioapic_stabilize,
499         .initmap        = ioapic_initmap,
500         .intr_config    = ioapic_intr_config
501 };
502
503 static int      ioapic_abi_extint_irq = -1;
504
505 struct apic_intmapinfo  int_to_apicintpin[APIC_INTMAPSIZE];
506
507 static void
508 ioapic_abi_intren(int irq)
509 {
510         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
511                 kprintf("ioapic_abi_intren invalid irq %d\n", irq);
512                 return;
513         }
514         IOAPIC_INTREN(irq);
515 }
516
517 static void
518 ioapic_abi_intrdis(int irq)
519 {
520         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
521                 kprintf("ioapic_abi_intrdis invalid irq %d\n", irq);
522                 return;
523         }
524         IOAPIC_INTRDIS(irq);
525 }
526
527 static int
528 ioapic_setvar(int varid, const void *buf)
529 {
530         return ENOENT;
531 }
532
533 static int
534 ioapic_getvar(int varid, void *buf)
535 {
536         return ENOENT;
537 }
538
539 static void
540 ioapic_finalize(void)
541 {
542         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
543         KKASSERT(ioapic_enable);
544
545         /*
546          * If an IMCR is present, program bit 0 to disconnect the 8259
547          * from the BSP.
548          */
549         if (imcr_present) {
550                 outb(0x22, 0x70);       /* select IMCR */
551                 outb(0x23, 0x01);       /* disconnect 8259 */
552         }
553 }
554
555 /*
556  * This routine is called after physical interrupts are enabled but before
557  * the critical section is released.  We need to clean out any interrupts
558  * that had already been posted to the cpu.
559  */
560 static void
561 ioapic_cleanup(void)
562 {
563         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
564 }
565
566 /* Must never be called */
567 static void
568 ioapic_stabilize(void)
569 {
570         panic("ioapic_stabilize is called\n");
571 }
572
573 static int
574 ioapic_vectorctl(int op, int intr, int flags)
575 {
576         int error;
577         int vector;
578         int select;
579         uint32_t value;
580         register_t ef;
581
582         if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
583             intr == IOAPIC_HWI_SYSCALL)
584                 return EINVAL;
585
586         ef = read_rflags();
587         cpu_disable_intr();
588         error = 0;
589
590         switch(op) {
591         case MACHINTR_VECTOR_SETUP:
592                 vector = IDT_OFFSET + intr;
593                 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
594
595                 /*
596                  * Now reprogram the vector in the IO APIC.  In order to avoid
597                  * losing an EOI for a level interrupt, which is vector based,
598                  * make sure that the IO APIC is programmed for edge-triggering
599                  * first, then reprogrammed with the new vector.  This should
600                  * clear the IRR bit.
601                  */
602                 if (int_to_apicintpin[intr].ioapic >= 0) {
603                         imen_lock();
604
605                         select = int_to_apicintpin[intr].redirindex;
606                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
607                                             select);
608                         value |= IOART_INTMSET;
609
610                         ioapic_write(int_to_apicintpin[intr].apic_address,
611                                      select, (value & ~APIC_TRIGMOD_MASK));
612                         ioapic_write(int_to_apicintpin[intr].apic_address,
613                                      select, (value & ~IOART_INTVEC) | vector);
614
615                         imen_unlock();
616                 }
617
618                 machintr_intren(intr);
619                 break;
620
621         case MACHINTR_VECTOR_TEARDOWN:
622                 /*
623                  * Teardown an interrupt vector.  The vector should already be
624                  * installed in the cpu's IDT, but make sure.
625                  */
626                 machintr_intrdis(intr);
627
628                 vector = IDT_OFFSET + intr;
629                 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
630
631                 /*
632                  * In order to avoid losing an EOI for a level interrupt, which
633                  * is vector based, make sure that the IO APIC is programmed for
634                  * edge-triggering first, then reprogrammed with the new vector.
635                  * This should clear the IRR bit.
636                  */
637                 if (int_to_apicintpin[intr].ioapic >= 0) {
638                         imen_lock();
639
640                         select = int_to_apicintpin[intr].redirindex;
641                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
642                                             select);
643
644                         ioapic_write(int_to_apicintpin[intr].apic_address,
645                                      select, (value & ~APIC_TRIGMOD_MASK));
646                         ioapic_write(int_to_apicintpin[intr].apic_address,
647                                      select, (value & ~IOART_INTVEC) | vector);
648
649                         imen_unlock();
650                 }
651                 break;
652
653         default:
654                 error = EOPNOTSUPP;
655                 break;
656         }
657
658         write_rflags(ef);
659         return error;
660 }
661
662 static void
663 ioapic_setdefault(void)
664 {
665         int intr;
666
667         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
668                 if (intr == IOAPIC_HWI_SYSCALL)
669                         continue;
670                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
671                        SEL_KPL, 0);
672         }
673 }
674
675 static void
676 ioapic_initmap(void)
677 {
678         int i;
679
680         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
681                 ioapic_irqmaps[i].im_gsi = -1;
682         ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
683 }
684
685 void
686 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
687     enum intr_polarity pola)
688 {
689         struct apic_intmapinfo *info;
690         struct ioapic_irqmap *map;
691         void *ioaddr;
692         int pin;
693
694         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
695         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
696
697         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
698         map = &ioapic_irqmaps[irq];
699
700         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
701         map->im_type = IOAPIC_IMT_LINE;
702
703         map->im_gsi = gsi;
704         map->im_trig = trig;
705         map->im_pola = pola;
706
707         if (bootverbose) {
708                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
709                         irq, map->im_gsi,
710                         intr_str_trigger(map->im_trig),
711                         intr_str_polarity(map->im_pola));
712         }
713
714         pin = ioapic_gsi_pin(map->im_gsi);
715         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
716
717         info = &int_to_apicintpin[irq];
718
719         imen_lock();
720
721         info->ioapic = 0; /* XXX unused */
722         info->int_pin = pin;
723         info->apic_address = ioaddr;
724         info->redirindex = IOAPIC_REDTBL + (2 * pin);
725         info->flags = IOAPIC_IM_FLAG_MASKED;
726         if (map->im_trig == INTR_TRIGGER_LEVEL)
727                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
728
729         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
730             map->im_trig, map->im_pola);
731
732         imen_unlock();
733 }
734
735 void
736 ioapic_abi_fixup_irqmap(void)
737 {
738         int i;
739
740         for (i = 0; i < 16; ++i) {
741                 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
742
743                 if (map->im_type == IOAPIC_IMT_UNUSED) {
744                         map->im_type = IOAPIC_IMT_RESERVED;
745                         if (bootverbose)
746                                 kprintf("IOAPIC: irq %d reserved\n", i);
747                 }
748         }
749 }
750
751 int
752 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
753 {
754         int irq;
755
756         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
757         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
758
759         for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
760                 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
761
762                 if (map->im_gsi == gsi) {
763                         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
764
765                         if (map->im_flags & IOAPIC_IMF_CONF) {
766                                 if (map->im_trig != trig ||
767                                     map->im_pola != pola)
768                                         return -1;
769                         }
770                         return irq;
771                 }
772         }
773         return -1;
774 }
775
776 int
777 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
778 {
779         const struct ioapic_irqmap *map;
780
781         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
782         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
783
784         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
785                 return -1;
786         map = &ioapic_irqmaps[irq];
787
788         if (map->im_type != IOAPIC_IMT_LINE)
789                 return -1;
790
791         if (map->im_flags & IOAPIC_IMF_CONF) {
792                 if (map->im_trig != trig || map->im_pola != pola)
793                         return -1;
794         }
795         return irq;
796 }
797
798 static void
799 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
800 {
801         struct apic_intmapinfo *info;
802         struct ioapic_irqmap *map;
803         void *ioaddr;
804         int pin;
805
806         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
807         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
808
809         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
810         map = &ioapic_irqmaps[irq];
811
812         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
813
814 #ifdef notyet
815         if (map->im_flags & IOAPIC_IMF_CONF) {
816                 if (trig != map->im_trig) {
817                         panic("ioapic_intr_config: trig %s -> %s\n",
818                               intr_str_trigger(map->im_trig),
819                               intr_str_trigger(trig));
820                 }
821                 if (pola != map->im_pola) {
822                         panic("ioapic_intr_config: pola %s -> %s\n",
823                               intr_str_polarity(map->im_pola),
824                               intr_str_polarity(pola));
825                 }
826                 return;
827         }
828 #endif
829         map->im_flags |= IOAPIC_IMF_CONF;
830
831         if (trig == map->im_trig && pola == map->im_pola)
832                 return;
833
834         if (bootverbose) {
835                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
836                         irq, map->im_gsi,
837                         intr_str_trigger(map->im_trig),
838                         intr_str_polarity(map->im_pola),
839                         intr_str_trigger(trig),
840                         intr_str_polarity(pola));
841         }
842         map->im_trig = trig;
843         map->im_pola = pola;
844
845         pin = ioapic_gsi_pin(map->im_gsi);
846         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
847
848         info = &int_to_apicintpin[irq];
849
850         imen_lock();
851
852         info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
853         if (map->im_trig == INTR_TRIGGER_LEVEL)
854                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
855
856         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
857             map->im_trig, map->im_pola);
858
859         imen_unlock();
860 }
861
862 int
863 ioapic_abi_extint_irqmap(int irq)
864 {
865         struct apic_intmapinfo *info;
866         struct ioapic_irqmap *map;
867         void *ioaddr;
868         int pin, error, vec;
869
870         vec = IDT_OFFSET + irq;
871
872         if (ioapic_abi_extint_irq == irq)
873                 return 0;
874         else if (ioapic_abi_extint_irq >= 0)
875                 return EEXIST;
876
877         error = icu_ioapic_extint(irq, vec);
878         if (error)
879                 return error;
880
881         map = &ioapic_irqmaps[irq];
882
883         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
884                  map->im_type == IOAPIC_IMT_LINE);
885         if (map->im_type == IOAPIC_IMT_LINE) {
886                 if (map->im_flags & IOAPIC_IMF_CONF)
887                         return EEXIST;
888         }
889         ioapic_abi_extint_irq = irq;
890
891         map->im_type = IOAPIC_IMT_LINE;
892         map->im_trig = INTR_TRIGGER_EDGE;
893         map->im_pola = INTR_POLARITY_HIGH;
894         map->im_flags = IOAPIC_IMF_CONF;
895
896         map->im_gsi = ioapic_extpin_gsi();
897         KKASSERT(map->im_gsi >= 0);
898
899         if (bootverbose) {
900                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
901                         irq, map->im_gsi,
902                         intr_str_trigger(map->im_trig),
903                         intr_str_polarity(map->im_pola));
904         }
905
906         pin = ioapic_gsi_pin(map->im_gsi);
907         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
908
909         info = &int_to_apicintpin[irq];
910
911         imen_lock();
912
913         info->ioapic = 0; /* XXX unused */
914         info->int_pin = pin;
915         info->apic_address = ioaddr;
916         info->redirindex = IOAPIC_REDTBL + (2 * pin);
917         info->flags = IOAPIC_IM_FLAG_MASKED;
918
919         ioapic_extpin_setup(ioaddr, pin, vec);
920
921         imen_unlock();
922
923         return 0;
924 }