sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 140 static void     igb_add_sysctl(struct igb_softc *);
 141 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 142 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 143
 144 static void     igb_vf_init_stats(struct igb_softc *);
 145 static void     igb_reset(struct igb_softc *);
 146 static void     igb_update_stats_counters(struct igb_softc *);
 147 static void     igb_update_vf_stats_counters(struct igb_softc *);
 148 static void     igb_update_link_status(struct igb_softc *);
 149 static void     igb_init_tx_unit(struct igb_softc *);
 150 static void     igb_init_rx_unit(struct igb_softc *);
 151
 152 static void     igb_set_vlan(struct igb_softc *);
 153 static void     igb_set_multi(struct igb_softc *);
 154 static void     igb_set_promisc(struct igb_softc *);
 155 static void     igb_disable_promisc(struct igb_softc *);
 156
 157 static int      igb_alloc_rings(struct igb_softc *);
 158 static void     igb_free_rings(struct igb_softc *);
 159 static int      igb_create_tx_ring(struct igb_tx_ring *);
 160 static int      igb_create_rx_ring(struct igb_rx_ring *);
 161 static void     igb_free_tx_ring(struct igb_tx_ring *);
 162 static void     igb_free_rx_ring(struct igb_rx_ring *);
 163 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 164 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 165 static void     igb_init_tx_ring(struct igb_tx_ring *);
 166 static int      igb_init_rx_ring(struct igb_rx_ring *);
 167 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 168 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 169
 170 static void     igb_stop(struct igb_softc *);
 171 static void     igb_init(void *);
 172 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 173 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 174 static int      igb_media_change(struct ifnet *);
 175 static void     igb_timer(void *);
 176 static void     igb_watchdog(struct ifnet *);
 177 static void     igb_start(struct ifnet *);
 178 #ifdef DEVICE_POLLING
 179 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 180 #endif
 181 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 182 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 183 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 184 #ifdef INVARIANTS
 185 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 186                     boolean_t);
 187 #endif
 188
 189 static void     igb_intr(void *);
 190 static void     igb_shared_intr(void *);
 191 static void     igb_rxeof(struct igb_rx_ring *, int);
 192 static void     igb_txeof(struct igb_tx_ring *);
 193 static void     igb_set_eitr(struct igb_softc *);
 194 static void     igb_enable_intr(struct igb_softc *);
 195 static void     igb_disable_intr(struct igb_softc *);
 196 static void     igb_init_unshared_intr(struct igb_softc *);
 197 static void     igb_init_intr(struct igb_softc *);
 198 static int      igb_setup_intr(struct igb_softc *);
 199 static void     igb_setup_tx_intr(struct igb_tx_ring *, int *, int);
 200 static void     igb_setup_rx_intr(struct igb_rx_ring *, int *, int);
 201 static void     igb_set_intr_mask(struct igb_softc *);
 202
 203 /* Management and WOL Support */
 204 static void     igb_get_mgmt(struct igb_softc *);
 205 static void     igb_rel_mgmt(struct igb_softc *);
 206 static void     igb_get_hw_control(struct igb_softc *);
 207 static void     igb_rel_hw_control(struct igb_softc *);
 208 static void     igb_enable_wol(device_t);
 209
 210 static device_method_t igb_methods[] = {
 211         /* Device interface */
 212         DEVMETHOD(device_probe,         igb_probe),
 213         DEVMETHOD(device_attach,        igb_attach),
 214         DEVMETHOD(device_detach,        igb_detach),
 215         DEVMETHOD(device_shutdown,      igb_shutdown),
 216         DEVMETHOD(device_suspend,       igb_suspend),
 217         DEVMETHOD(device_resume,        igb_resume),
 218         { 0, 0 }
 219 };
 220
 221 static driver_t igb_driver = {
 222         "igb",
 223         igb_methods,
 224         sizeof(struct igb_softc),
 225 };
 226
 227 static devclass_t igb_devclass;
 228
 229 DECLARE_DUMMY_MODULE(if_igb);
 230 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 231 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 232
 233 static int      igb_rxd = IGB_DEFAULT_RXD;
 234 static int      igb_txd = IGB_DEFAULT_TXD;
 235 static int      igb_rxr = 0;
 236 static int      igb_msi_enable = 1;
 237 static int      igb_msix_enable = 1;
 238 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 239 static int      igb_fc_setting = e1000_fc_full;
 240
 241 /*
 242  * DMA Coalescing, only for i350 - default to off,
 243  * this feature is for power savings
 244  */
 245 static int      igb_dma_coalesce = 0;
 246
 247 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 248 TUNABLE_INT("hw.igb.txd", &igb_txd);
 249 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 250 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 251 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 252 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 253
 254 /* i350 specific */
 255 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 256 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 257
 258 static __inline void
 259 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 260 {
 261         /* Ignore Checksum bit is set */
 262         if (staterr & E1000_RXD_STAT_IXSM)
 263                 return;
 264
 265         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 266             E1000_RXD_STAT_IPCS)
 267                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 268
 269         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 270                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 271                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 272                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 273                         mp->m_pkthdr.csum_data = htons(0xffff);
 274                 }
 275         }
 276 }
 277
 278 static __inline struct pktinfo *
 279 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 280     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 281 {
 282         switch (hashtype) {
 283         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 284                 pi->pi_netisr = NETISR_IP;
 285                 pi->pi_flags = 0;
 286                 pi->pi_l3proto = IPPROTO_TCP;
 287                 break;
 288
 289         case E1000_RXDADV_RSSTYPE_IPV4:
 290                 if (staterr & E1000_RXD_STAT_IXSM)
 291                         return NULL;
 292
 293                 if ((staterr &
 294                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 295                     E1000_RXD_STAT_TCPCS) {
 296                         pi->pi_netisr = NETISR_IP;
 297                         pi->pi_flags = 0;
 298                         pi->pi_l3proto = IPPROTO_UDP;
 299                         break;
 300                 }
 301                 /* FALL THROUGH */
 302         default:
 303                 return NULL;
 304         }
 305
 306         m->m_flags |= M_HASH;
 307         m->m_pkthdr.hash = toeplitz_hash(hash);
 308         return pi;
 309 }
 310
 311 static int
 312 igb_probe(device_t dev)
 313 {
 314         const struct igb_device *d;
 315         uint16_t vid, did;
 316
 317         vid = pci_get_vendor(dev);
 318         did = pci_get_device(dev);
 319
 320         for (d = igb_devices; d->desc != NULL; ++d) {
 321                 if (vid == d->vid && did == d->did) {
 322                         device_set_desc(dev, d->desc);
 323                         return 0;
 324                 }
 325         }
 326         return ENXIO;
 327 }
 328
 329 static int
 330 igb_attach(device_t dev)
 331 {
 332         struct igb_softc *sc = device_get_softc(dev);
 333         uint16_t eeprom_data;
 334         u_int intr_flags;
 335         int error = 0, i, j, ring_max;
 336
 337 #ifdef notyet
 338         /* SYSCTL stuff */
 339         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 340             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 341             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 342             igb_sysctl_nvm_info, "I", "NVM Information");
 343
 344         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 345             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 346             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 347             &igb_enable_aim, 1, "Interrupt Moderation");
 348
 349         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 350             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 351             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 352             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 353 #endif
 354
 355         callout_init_mp(&sc->timer);
 356
 357         sc->dev = sc->osdep.dev = dev;
 358
 359         /*
 360          * Determine hardware and mac type
 361          */
 362         sc->hw.vendor_id = pci_get_vendor(dev);
 363         sc->hw.device_id = pci_get_device(dev);
 364         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 365         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 366         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 367
 368         if (e1000_set_mac_type(&sc->hw))
 369                 return ENXIO;
 370
 371         /* Are we a VF device? */
 372         if (sc->hw.mac.type == e1000_vfadapt ||
 373             sc->hw.mac.type == e1000_vfadapt_i350)
 374                 sc->vf_ifp = 1;
 375         else
 376                 sc->vf_ifp = 0;
 377
 378         /*
 379          * Configure total supported RX/TX ring count
 380          */
 381         switch (sc->hw.mac.type) {
 382         case e1000_82575:
 383                 ring_max = IGB_MAX_RING_82575;
 384                 break;
 385         case e1000_82580:
 386                 ring_max = IGB_MAX_RING_82580;
 387                 break;
 388         case e1000_i350:
 389                 ring_max = IGB_MAX_RING_I350;
 390                 break;
 391         case e1000_82576:
 392                 ring_max = IGB_MAX_RING_82576;
 393                 break;
 394         default:
 395                 ring_max = IGB_MIN_RING;
 396                 break;
 397         }
 398         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 399         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 400 #ifdef IGB_RSS_DEBUG
 401         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 402 #endif
 403         sc->rx_ring_inuse = sc->rx_ring_cnt;
 404         sc->tx_ring_cnt = 1; /* XXX */
 405
 406         /* Enable bus mastering */
 407         pci_enable_busmaster(dev);
 408
 409         /*
 410          * Allocate IO memory
 411          */
 412         sc->mem_rid = PCIR_BAR(0);
 413         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 414             RF_ACTIVE);
 415         if (sc->mem_res == NULL) {
 416                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 417                 error = ENXIO;
 418                 goto failed;
 419         }
 420         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 421         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 422
 423         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 424
 425         /*
 426          * Allocate interrupt
 427          */
 428         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
 429             &sc->intr_rid, &intr_flags);
 430
 431         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
 432             intr_flags);
 433         if (sc->intr_res == NULL) {
 434                 device_printf(dev, "Unable to allocate bus resource: "
 435                     "interrupt\n");
 436                 error = ENXIO;
 437                 goto failed;
 438         }
 439
 440         /* Save PCI command register for Shared Code */
 441         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 442         sc->hw.back = &sc->osdep;
 443
 444         sc->intr_rate = IGB_INTR_RATE;
 445
 446         /* Do Shared Code initialization */
 447         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 448                 device_printf(dev, "Setup of Shared code failed\n");
 449                 error = ENXIO;
 450                 goto failed;
 451         }
 452
 453         e1000_get_bus_info(&sc->hw);
 454
 455         sc->hw.mac.autoneg = DO_AUTO_NEG;
 456         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 457         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 458
 459         /* Copper options */
 460         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 461                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 462                 sc->hw.phy.disable_polarity_correction = FALSE;
 463                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 464         }
 465
 466         /* Set the frame limits assuming  standard ethernet sized frames. */
 467         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 468
 469         /* Allocate RX/TX rings */
 470         error = igb_alloc_rings(sc);
 471         if (error)
 472                 goto failed;
 473
 474         /*
 475          * Setup serializers
 476          */
 477         lwkt_serialize_init(&sc->main_serialize);
 478         i = 0;
 479         sc->serializes[i++] = &sc->main_serialize;
 480
 481         sc->tx_serialize = i;
 482         for (j = 0; j < sc->tx_ring_cnt; ++j)
 483                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 484
 485         sc->rx_serialize = i;
 486         for (j = 0; j < sc->rx_ring_cnt; ++j)
 487                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 488
 489         sc->serialize_cnt = i;
 490         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 491
 492         /* Allocate the appropriate stats memory */
 493         if (sc->vf_ifp) {
 494                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 495                     M_WAITOK | M_ZERO);
 496                 igb_vf_init_stats(sc);
 497         } else {
 498                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 499                     M_WAITOK | M_ZERO);
 500         }
 501
 502         /* Allocate multicast array memory. */
 503         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 504             M_DEVBUF, M_WAITOK);
 505
 506         /* Some adapter-specific advanced features */
 507         if (sc->hw.mac.type >= e1000_i350) {
 508 #ifdef notyet
 509                 igb_set_sysctl_value(adapter, "dma_coalesce",
 510                     "configure dma coalesce",
 511                     &adapter->dma_coalesce, igb_dma_coalesce);
 512                 igb_set_sysctl_value(adapter, "eee_disabled",
 513                     "enable Energy Efficient Ethernet",
 514                     &adapter->hw.dev_spec._82575.eee_disable,
 515                     igb_eee_disabled);
 516 #else
 517                 sc->dma_coalesce = igb_dma_coalesce;
 518                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 519 #endif
 520                 e1000_set_eee_i350(&sc->hw);
 521         }
 522
 523         /*
 524          * Start from a known state, this is important in reading the nvm and
 525          * mac from that.
 526          */
 527         e1000_reset_hw(&sc->hw);
 528
 529         /* Make sure we have a good EEPROM before we read from it */
 530         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 531                 /*
 532                  * Some PCI-E parts fail the first check due to
 533                  * the link being in sleep state, call it again,
 534                  * if it fails a second time its a real issue.
 535                  */
 536                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 537                         device_printf(dev,
 538                             "The EEPROM Checksum Is Not Valid\n");
 539                         error = EIO;
 540                         goto failed;
 541                 }
 542         }
 543
 544         /* Copy the permanent MAC address out of the EEPROM */
 545         if (e1000_read_mac_addr(&sc->hw) < 0) {
 546                 device_printf(dev, "EEPROM read error while reading MAC"
 547                     " address\n");
 548                 error = EIO;
 549                 goto failed;
 550         }
 551         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 552                 device_printf(dev, "Invalid MAC address\n");
 553                 error = EIO;
 554                 goto failed;
 555         }
 556
 557 #ifdef notyet
 558         /*
 559         ** Configure Interrupts
 560         */
 561         if ((adapter->msix > 1) && (igb_enable_msix))
 562                 error = igb_allocate_msix(adapter);
 563         else /* MSI or Legacy */
 564                 error = igb_allocate_legacy(adapter);
 565         if (error)
 566                 goto err_late;
 567 #endif
 568
 569         /* Setup OS specific network interface */
 570         igb_setup_ifp(sc);
 571
 572         /* Add sysctl tree, must after igb_setup_ifp() */
 573         igb_add_sysctl(sc);
 574
 575         /* Now get a good starting state */
 576         igb_reset(sc);
 577
 578         /* Initialize statistics */
 579         igb_update_stats_counters(sc);
 580
 581         sc->hw.mac.get_link_status = 1;
 582         igb_update_link_status(sc);
 583
 584         /* Indicate SOL/IDER usage */
 585         if (e1000_check_reset_block(&sc->hw)) {
 586                 device_printf(dev,
 587                     "PHY reset is blocked due to SOL/IDER session.\n");
 588         }
 589
 590         /* Determine if we have to control management hardware */
 591         if (e1000_enable_mng_pass_thru(&sc->hw))
 592                 sc->flags |= IGB_FLAG_HAS_MGMT;
 593
 594         /*
 595          * Setup Wake-on-Lan
 596          */
 597         /* APME bit in EEPROM is mapped to WUC.APME */
 598         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 599         if (eeprom_data)
 600                 sc->wol = E1000_WUFC_MAG;
 601         /* XXX disable WOL */
 602         sc->wol = 0;
 603
 604 #ifdef notyet
 605         /* Register for VLAN events */
 606         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 607              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 608         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 609              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 610 #endif
 611
 612 #ifdef notyet
 613         igb_add_hw_stats(adapter);
 614 #endif
 615
 616         error = igb_setup_intr(sc);
 617         if (error) {
 618                 ether_ifdetach(&sc->arpcom.ac_if);
 619                 goto failed;
 620         }
 621         return 0;
 622
 623 failed:
 624         igb_detach(dev);
 625         return error;
 626 }
 627
 628 static int
 629 igb_detach(device_t dev)
 630 {
 631         struct igb_softc *sc = device_get_softc(dev);
 632
 633         if (device_is_attached(dev)) {
 634                 struct ifnet *ifp = &sc->arpcom.ac_if;
 635
 636                 ifnet_serialize_all(ifp);
 637
 638                 igb_stop(sc);
 639
 640                 e1000_phy_hw_reset(&sc->hw);
 641
 642                 /* Give control back to firmware */
 643                 igb_rel_mgmt(sc);
 644                 igb_rel_hw_control(sc);
 645
 646                 if (sc->wol) {
 647                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 648                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 649                         igb_enable_wol(dev);
 650                 }
 651
 652                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
 653
 654                 ifnet_deserialize_all(ifp);
 655
 656                 ether_ifdetach(ifp);
 657         } else if (sc->mem_res != NULL) {
 658                 igb_rel_hw_control(sc);
 659         }
 660         bus_generic_detach(dev);
 661
 662         if (sc->intr_res != NULL) {
 663                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
 664                     sc->intr_res);
 665         }
 666         if (sc->intr_type == PCI_INTR_TYPE_MSI)
 667                 pci_release_msi(dev);
 668
 669         if (sc->mem_res != NULL) {
 670                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 671                     sc->mem_res);
 672         }
 673
 674         igb_free_rings(sc);
 675
 676         if (sc->mta != NULL)
 677                 kfree(sc->mta, M_DEVBUF);
 678         if (sc->stats != NULL)
 679                 kfree(sc->stats, M_DEVBUF);
 680
 681         if (sc->sysctl_tree != NULL)
 682                 sysctl_ctx_free(&sc->sysctl_ctx);
 683
 684         return 0;
 685 }
 686
 687 static int
 688 igb_shutdown(device_t dev)
 689 {
 690         return igb_suspend(dev);
 691 }
 692
 693 static int
 694 igb_suspend(device_t dev)
 695 {
 696         struct igb_softc *sc = device_get_softc(dev);
 697         struct ifnet *ifp = &sc->arpcom.ac_if;
 698
 699         ifnet_serialize_all(ifp);
 700
 701         igb_stop(sc);
 702
 703         igb_rel_mgmt(sc);
 704         igb_rel_hw_control(sc);
 705
 706         if (sc->wol) {
 707                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 708                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 709                 igb_enable_wol(dev);
 710         }
 711
 712         ifnet_deserialize_all(ifp);
 713
 714         return bus_generic_suspend(dev);
 715 }
 716
 717 static int
 718 igb_resume(device_t dev)
 719 {
 720         struct igb_softc *sc = device_get_softc(dev);
 721         struct ifnet *ifp = &sc->arpcom.ac_if;
 722
 723         ifnet_serialize_all(ifp);
 724
 725         igb_init(sc);
 726         igb_get_mgmt(sc);
 727
 728         if_devstart(ifp);
 729
 730         ifnet_deserialize_all(ifp);
 731
 732         return bus_generic_resume(dev);
 733 }
 734
 735 static int
 736 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 737 {
 738         struct igb_softc *sc = ifp->if_softc;
 739         struct ifreq *ifr = (struct ifreq *)data;
 740         int max_frame_size, mask, reinit;
 741         int error = 0;
 742
 743         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 744
 745         switch (command) {
 746         case SIOCSIFMTU:
 747                 max_frame_size = 9234;
 748                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 749                     ETHER_CRC_LEN) {
 750                         error = EINVAL;
 751                         break;
 752                 }
 753
 754                 ifp->if_mtu = ifr->ifr_mtu;
 755                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 756                     ETHER_CRC_LEN;
 757
 758                 if (ifp->if_flags & IFF_RUNNING)
 759                         igb_init(sc);
 760                 break;
 761
 762         case SIOCSIFFLAGS:
 763                 if (ifp->if_flags & IFF_UP) {
 764                         if (ifp->if_flags & IFF_RUNNING) {
 765                                 if ((ifp->if_flags ^ sc->if_flags) &
 766                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 767                                         igb_disable_promisc(sc);
 768                                         igb_set_promisc(sc);
 769                                 }
 770                         } else {
 771                                 igb_init(sc);
 772                         }
 773                 } else if (ifp->if_flags & IFF_RUNNING) {
 774                         igb_stop(sc);
 775                 }
 776                 sc->if_flags = ifp->if_flags;
 777                 break;
 778
 779         case SIOCADDMULTI:
 780         case SIOCDELMULTI:
 781                 if (ifp->if_flags & IFF_RUNNING) {
 782                         igb_disable_intr(sc);
 783                         igb_set_multi(sc);
 784 #ifdef DEVICE_POLLING
 785                         if (!(ifp->if_flags & IFF_POLLING))
 786 #endif
 787                                 igb_enable_intr(sc);
 788                 }
 789                 break;
 790
 791         case SIOCSIFMEDIA:
 792                 /*
 793                  * As the speed/duplex settings are being
 794                  * changed, we need toreset the PHY.
 795                  */
 796                 sc->hw.phy.reset_disable = FALSE;
 797
 798                 /* Check SOL/IDER usage */
 799                 if (e1000_check_reset_block(&sc->hw)) {
 800                         if_printf(ifp, "Media change is "
 801                             "blocked due to SOL/IDER session.\n");
 802                         break;
 803                 }
 804                 /* FALL THROUGH */
 805
 806         case SIOCGIFMEDIA:
 807                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 808                 break;
 809
 810         case SIOCSIFCAP:
 811                 reinit = 0;
 812                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 813                 if (mask & IFCAP_HWCSUM) {
 814                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 815                         reinit = 1;
 816                 }
 817                 if (mask & IFCAP_VLAN_HWTAGGING) {
 818                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 819                         reinit = 1;
 820                 }
 821                 if (mask & IFCAP_RSS)
 822                         ifp->if_capenable ^= IFCAP_RSS;
 823                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 824                         igb_init(sc);
 825                 break;
 826
 827         default:
 828                 error = ether_ioctl(ifp, command, data);
 829                 break;
 830         }
 831         return error;
 832 }
 833
 834 static void
 835 igb_init(void *xsc)
 836 {
 837         struct igb_softc *sc = xsc;
 838         struct ifnet *ifp = &sc->arpcom.ac_if;
 839         int i;
 840
 841         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 842
 843         igb_stop(sc);
 844
 845         /* Get the latest mac address, User can use a LAA */
 846         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 847
 848         /* Put the address into the Receive Address Array */
 849         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 850
 851         igb_reset(sc);
 852         igb_update_link_status(sc);
 853
 854         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 855
 856         /* Set hardware offload abilities */
 857         if (ifp->if_capenable & IFCAP_TXCSUM)
 858                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 859         else
 860                 ifp->if_hwassist = 0;
 861
 862         /* Configure for OS presence */
 863         igb_get_mgmt(sc);
 864
 865         if (IGB_ENABLE_HWRSS(sc)) {
 866                 if (sc->intr_type != PCI_INTR_TYPE_MSIX
 867 #ifdef DEVICE_POLLING
 868                     || (ifp->if_flags & IFF_POLLING)
 869 #endif
 870                     ) {
 871                         sc->rx_ring_inuse = IGB_MIN_RING_RSS;
 872                         if (bootverbose) {
 873                                 if_printf(ifp, "RX rings %d/%d\n",
 874                                     sc->rx_ring_inuse, sc->rx_ring_cnt);
 875                         }
 876                 }
 877         }
 878
 879         /* Prepare transmit descriptors and buffers */
 880         for (i = 0; i < sc->tx_ring_cnt; ++i)
 881                 igb_init_tx_ring(&sc->tx_rings[i]);
 882         igb_init_tx_unit(sc);
 883
 884         /* Setup Multicast table */
 885         igb_set_multi(sc);
 886
 887 #if 0
 888         /*
 889          * Figure out the desired mbuf pool
 890          * for doing jumbo/packetsplit
 891          */
 892         if (adapter->max_frame_size <= 2048)
 893                 adapter->rx_mbuf_sz = MCLBYTES;
 894         else if (adapter->max_frame_size <= 4096)
 895                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 896         else
 897                 adapter->rx_mbuf_sz = MJUM9BYTES;
 898 #endif
 899
 900         /* Initialize interrupt */
 901         igb_init_intr(sc);
 902
 903         /* Prepare receive descriptors and buffers */
 904         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 905                 int error;
 906
 907                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 908                 if (error) {
 909                         if_printf(ifp, "Could not setup receive structures\n");
 910                         igb_stop(sc);
 911                         return;
 912                 }
 913         }
 914         igb_init_rx_unit(sc);
 915
 916         /* Enable VLAN support */
 917         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 918                 igb_set_vlan(sc);
 919
 920         /* Don't lose promiscuous settings */
 921         igb_set_promisc(sc);
 922
 923         ifp->if_flags |= IFF_RUNNING;
 924         ifp->if_flags &= ~IFF_OACTIVE;
 925
 926         callout_reset(&sc->timer, hz, igb_timer, sc);
 927         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 928
 929 #if 0
 930         if (adapter->msix > 1) /* Set up queue routing */
 931                 igb_configure_queues(adapter);
 932 #endif
 933
 934         /* this clears any pending interrupts */
 935         E1000_READ_REG(&sc->hw, E1000_ICR);
 936 #ifdef DEVICE_POLLING
 937         /*
 938          * Only enable interrupts if we are not polling, make sure
 939          * they are off otherwise.
 940          */
 941         if (ifp->if_flags & IFF_POLLING)
 942                 igb_disable_intr(sc);
 943         else
 944 #endif /* DEVICE_POLLING */
 945         {
 946                 igb_enable_intr(sc);
 947                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 948         }
 949
 950         /* Set Energy Efficient Ethernet */
 951         e1000_set_eee_i350(&sc->hw);
 952
 953         /* Don't reset the phy next time init gets called */
 954         sc->hw.phy.reset_disable = TRUE;
 955 }
 956
 957 static void
 958 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 959 {
 960         struct igb_softc *sc = ifp->if_softc;
 961         u_char fiber_type = IFM_1000_SX;
 962
 963         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 964
 965         igb_update_link_status(sc);
 966
 967         ifmr->ifm_status = IFM_AVALID;
 968         ifmr->ifm_active = IFM_ETHER;
 969
 970         if (!sc->link_active)
 971                 return;
 972
 973         ifmr->ifm_status |= IFM_ACTIVE;
 974
 975         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 976             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 977                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 978         } else {
 979                 switch (sc->link_speed) {
 980                 case 10:
 981                         ifmr->ifm_active |= IFM_10_T;
 982                         break;
 983
 984                 case 100:
 985                         ifmr->ifm_active |= IFM_100_TX;
 986                         break;
 987
 988                 case 1000:
 989                         ifmr->ifm_active |= IFM_1000_T;
 990                         break;
 991                 }
 992                 if (sc->link_duplex == FULL_DUPLEX)
 993                         ifmr->ifm_active |= IFM_FDX;
 994                 else
 995                         ifmr->ifm_active |= IFM_HDX;
 996         }
 997 }
 998
 999 static int
1000 igb_media_change(struct ifnet *ifp)
1001 {
1002         struct igb_softc *sc = ifp->if_softc;
1003         struct ifmedia *ifm = &sc->media;
1004
1005         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1006
1007         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1008                 return EINVAL;
1009
1010         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1011         case IFM_AUTO:
1012                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1013                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1014                 break;
1015
1016         case IFM_1000_LX:
1017         case IFM_1000_SX:
1018         case IFM_1000_T:
1019                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1020                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1021                 break;
1022
1023         case IFM_100_TX:
1024                 sc->hw.mac.autoneg = FALSE;
1025                 sc->hw.phy.autoneg_advertised = 0;
1026                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1027                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1028                 else
1029                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1030                 break;
1031
1032         case IFM_10_T:
1033                 sc->hw.mac.autoneg = FALSE;
1034                 sc->hw.phy.autoneg_advertised = 0;
1035                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1036                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1037                 else
1038                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1039                 break;
1040
1041         default:
1042                 if_printf(ifp, "Unsupported media type\n");
1043                 break;
1044         }
1045
1046         igb_init(sc);
1047
1048         return 0;
1049 }
1050
1051 static void
1052 igb_set_promisc(struct igb_softc *sc)
1053 {
1054         struct ifnet *ifp = &sc->arpcom.ac_if;
1055         struct e1000_hw *hw = &sc->hw;
1056         uint32_t reg;
1057
1058         if (sc->vf_ifp) {
1059                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1060                 return;
1061         }
1062
1063         reg = E1000_READ_REG(hw, E1000_RCTL);
1064         if (ifp->if_flags & IFF_PROMISC) {
1065                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1066                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1067         } else if (ifp->if_flags & IFF_ALLMULTI) {
1068                 reg |= E1000_RCTL_MPE;
1069                 reg &= ~E1000_RCTL_UPE;
1070                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1071         }
1072 }
1073
1074 static void
1075 igb_disable_promisc(struct igb_softc *sc)
1076 {
1077         struct e1000_hw *hw = &sc->hw;
1078         uint32_t reg;
1079
1080         if (sc->vf_ifp) {
1081                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1082                 return;
1083         }
1084         reg = E1000_READ_REG(hw, E1000_RCTL);
1085         reg &= ~E1000_RCTL_UPE;
1086         reg &= ~E1000_RCTL_MPE;
1087         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1088 }
1089
1090 static void
1091 igb_set_multi(struct igb_softc *sc)
1092 {
1093         struct ifnet *ifp = &sc->arpcom.ac_if;
1094         struct ifmultiaddr *ifma;
1095         uint32_t reg_rctl = 0;
1096         uint8_t *mta;
1097         int mcnt = 0;
1098
1099         mta = sc->mta;
1100         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1101
1102         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1103                 if (ifma->ifma_addr->sa_family != AF_LINK)
1104                         continue;
1105
1106                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1107                         break;
1108
1109                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1110                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1111                 mcnt++;
1112         }
1113
1114         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1115                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1116                 reg_rctl |= E1000_RCTL_MPE;
1117                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1118         } else {
1119                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1120         }
1121 }
1122
1123 static void
1124 igb_timer(void *xsc)
1125 {
1126         struct igb_softc *sc = xsc;
1127
1128         lwkt_serialize_enter(&sc->main_serialize);
1129
1130         igb_update_link_status(sc);
1131         igb_update_stats_counters(sc);
1132
1133         callout_reset(&sc->timer, hz, igb_timer, sc);
1134
1135         lwkt_serialize_exit(&sc->main_serialize);
1136 }
1137
1138 static void
1139 igb_update_link_status(struct igb_softc *sc)
1140 {
1141         struct ifnet *ifp = &sc->arpcom.ac_if;
1142         struct e1000_hw *hw = &sc->hw;
1143         uint32_t link_check, thstat, ctrl;
1144
1145         link_check = thstat = ctrl = 0;
1146
1147         /* Get the cached link value or read for real */
1148         switch (hw->phy.media_type) {
1149         case e1000_media_type_copper:
1150                 if (hw->mac.get_link_status) {
1151                         /* Do the work to read phy */
1152                         e1000_check_for_link(hw);
1153                         link_check = !hw->mac.get_link_status;
1154                 } else {
1155                         link_check = TRUE;
1156                 }
1157                 break;
1158
1159         case e1000_media_type_fiber:
1160                 e1000_check_for_link(hw);
1161                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1162                 break;
1163
1164         case e1000_media_type_internal_serdes:
1165                 e1000_check_for_link(hw);
1166                 link_check = hw->mac.serdes_has_link;
1167                 break;
1168
1169         /* VF device is type_unknown */
1170         case e1000_media_type_unknown:
1171                 e1000_check_for_link(hw);
1172                 link_check = !hw->mac.get_link_status;
1173                 /* Fall thru */
1174         default:
1175                 break;
1176         }
1177
1178         /* Check for thermal downshift or shutdown */
1179         if (hw->mac.type == e1000_i350) {
1180                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1181                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1182         }
1183
1184         /* Now we check if a transition has happened */
1185         if (link_check && sc->link_active == 0) {
1186                 e1000_get_speed_and_duplex(hw,
1187                     &sc->link_speed, &sc->link_duplex);
1188                 if (bootverbose) {
1189                         if_printf(ifp, "Link is up %d Mbps %s\n",
1190                             sc->link_speed,
1191                             sc->link_duplex == FULL_DUPLEX ?
1192                             "Full Duplex" : "Half Duplex");
1193                 }
1194                 sc->link_active = 1;
1195
1196                 ifp->if_baudrate = sc->link_speed * 1000000;
1197                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1198                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1199                         if_printf(ifp, "Link: thermal downshift\n");
1200                 /* This can sleep */
1201                 ifp->if_link_state = LINK_STATE_UP;
1202                 if_link_state_change(ifp);
1203         } else if (!link_check && sc->link_active == 1) {
1204                 ifp->if_baudrate = sc->link_speed = 0;
1205                 sc->link_duplex = 0;
1206                 if (bootverbose)
1207                         if_printf(ifp, "Link is Down\n");
1208                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1209                     (thstat & E1000_THSTAT_PWR_DOWN))
1210                         if_printf(ifp, "Link: thermal shutdown\n");
1211                 sc->link_active = 0;
1212                 /* This can sleep */
1213                 ifp->if_link_state = LINK_STATE_DOWN;
1214                 if_link_state_change(ifp);
1215         }
1216 }
1217
1218 static void
1219 igb_stop(struct igb_softc *sc)
1220 {
1221         struct ifnet *ifp = &sc->arpcom.ac_if;
1222         int i;
1223
1224         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1225
1226         igb_disable_intr(sc);
1227
1228         callout_stop(&sc->timer);
1229
1230         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1231         ifp->if_timer = 0;
1232
1233         e1000_reset_hw(&sc->hw);
1234         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1235
1236         e1000_led_off(&sc->hw);
1237         e1000_cleanup_led(&sc->hw);
1238
1239         for (i = 0; i < sc->tx_ring_cnt; ++i)
1240                 igb_free_tx_ring(&sc->tx_rings[i]);
1241         for (i = 0; i < sc->rx_ring_cnt; ++i)
1242                 igb_free_rx_ring(&sc->rx_rings[i]);
1243 }
1244
1245 static void
1246 igb_reset(struct igb_softc *sc)
1247 {
1248         struct ifnet *ifp = &sc->arpcom.ac_if;
1249         struct e1000_hw *hw = &sc->hw;
1250         struct e1000_fc_info *fc = &hw->fc;
1251         uint32_t pba = 0;
1252         uint16_t hwm;
1253
1254         /* Let the firmware know the OS is in control */
1255         igb_get_hw_control(sc);
1256
1257         /*
1258          * Packet Buffer Allocation (PBA)
1259          * Writing PBA sets the receive portion of the buffer
1260          * the remainder is used for the transmit buffer.
1261          */
1262         switch (hw->mac.type) {
1263         case e1000_82575:
1264                 pba = E1000_PBA_32K;
1265                 break;
1266
1267         case e1000_82576:
1268         case e1000_vfadapt:
1269                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1270                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1271                 break;
1272
1273         case e1000_82580:
1274         case e1000_i350:
1275         case e1000_vfadapt_i350:
1276                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1277                 pba = e1000_rxpbs_adjust_82580(pba);
1278                 break;
1279                 /* XXX pba = E1000_PBA_35K; */
1280
1281         default:
1282                 break;
1283         }
1284
1285         /* Special needs in case of Jumbo frames */
1286         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1287                 uint32_t tx_space, min_tx, min_rx;
1288
1289                 pba = E1000_READ_REG(hw, E1000_PBA);
1290                 tx_space = pba >> 16;
1291                 pba &= 0xffff;
1292
1293                 min_tx = (sc->max_frame_size +
1294                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1295                 min_tx = roundup2(min_tx, 1024);
1296                 min_tx >>= 10;
1297                 min_rx = sc->max_frame_size;
1298                 min_rx = roundup2(min_rx, 1024);
1299                 min_rx >>= 10;
1300                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1301                         pba = pba - (min_tx - tx_space);
1302                         /*
1303                          * if short on rx space, rx wins
1304                          * and must trump tx adjustment
1305                          */
1306                         if (pba < min_rx)
1307                                 pba = min_rx;
1308                 }
1309                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1310         }
1311
1312         /*
1313          * These parameters control the automatic generation (Tx) and
1314          * response (Rx) to Ethernet PAUSE frames.
1315          * - High water mark should allow for at least two frames to be
1316          *   received after sending an XOFF.
1317          * - Low water mark works best when it is very near the high water mark.
1318          *   This allows the receiver to restart by sending XON when it has
1319          *   drained a bit.
1320          */
1321         hwm = min(((pba << 10) * 9 / 10),
1322             ((pba << 10) - 2 * sc->max_frame_size));
1323
1324         if (hw->mac.type < e1000_82576) {
1325                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1326                 fc->low_water = fc->high_water - 8;
1327         } else {
1328                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1329                 fc->low_water = fc->high_water - 16;
1330         }
1331         fc->pause_time = IGB_FC_PAUSE_TIME;
1332         fc->send_xon = TRUE;
1333
1334         /* Issue a global reset */
1335         e1000_reset_hw(hw);
1336         E1000_WRITE_REG(hw, E1000_WUC, 0);
1337
1338         if (e1000_init_hw(hw) < 0)
1339                 if_printf(ifp, "Hardware Initialization Failed\n");
1340
1341         /* Setup DMA Coalescing */
1342         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1343                 uint32_t reg;
1344
1345                 hwm = (pba - 4) << 10;
1346                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1347                     & E1000_DMACR_DMACTHR_MASK;
1348
1349                 /* transition to L0x or L1 if available..*/
1350                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1351
1352                 /* timer = +-1000 usec in 32usec intervals */
1353                 reg |= (1000 >> 5);
1354                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1355
1356                 /* No lower threshold */
1357                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1358
1359                 /* set hwm to PBA -  2 * max frame size */
1360                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1361
1362                 /* Set the interval before transition */
1363                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1364                 reg |= 0x800000FF; /* 255 usec */
1365                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1366
1367                 /* free space in tx packet buffer to wake from DMA coal */
1368                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1369                     (20480 - (2 * sc->max_frame_size)) >> 6);
1370
1371                 /* make low power state decision controlled by DMA coal */
1372                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1373                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1374                     reg | E1000_PCIEMISC_LX_DECISION);
1375                 if_printf(ifp, "DMA Coalescing enabled\n");
1376         }
1377
1378         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1379         e1000_get_phy_info(hw);
1380         e1000_check_for_link(hw);
1381 }
1382
1383 static void
1384 igb_setup_ifp(struct igb_softc *sc)
1385 {
1386         struct ifnet *ifp = &sc->arpcom.ac_if;
1387
1388         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1389         ifp->if_softc = sc;
1390         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1391         ifp->if_init =  igb_init;
1392         ifp->if_ioctl = igb_ioctl;
1393         ifp->if_start = igb_start;
1394         ifp->if_serialize = igb_serialize;
1395         ifp->if_deserialize = igb_deserialize;
1396         ifp->if_tryserialize = igb_tryserialize;
1397 #ifdef INVARIANTS
1398         ifp->if_serialize_assert = igb_serialize_assert;
1399 #endif
1400 #ifdef DEVICE_POLLING
1401         ifp->if_poll = igb_poll;
1402 #endif
1403         ifp->if_watchdog = igb_watchdog;
1404
1405         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1406         ifq_set_ready(&ifp->if_snd);
1407
1408         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1409
1410         ifp->if_capabilities =
1411             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1412         if (IGB_ENABLE_HWRSS(sc))
1413                 ifp->if_capabilities |= IFCAP_RSS;
1414         ifp->if_capenable = ifp->if_capabilities;
1415         ifp->if_hwassist = IGB_CSUM_FEATURES;
1416
1417         /*
1418          * Tell the upper layer(s) we support long frames
1419          */
1420         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1421
1422         /*
1423          * Specify the media types supported by this adapter and register
1424          * callbacks to update media and link information
1425          */
1426         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1427         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1428             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1429                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1430                     0, NULL);
1431                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1432         } else {
1433                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1434                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1435                     0, NULL);
1436                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1437                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1438                     0, NULL);
1439                 if (sc->hw.phy.type != e1000_phy_ife) {
1440                         ifmedia_add(&sc->media,
1441                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1442                         ifmedia_add(&sc->media,
1443                             IFM_ETHER | IFM_1000_T, 0, NULL);
1444                 }
1445         }
1446         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1447         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1448 }
1449
1450 static void
1451 igb_add_sysctl(struct igb_softc *sc)
1452 {
1453 #ifdef IGB_RSS_DEBUG
1454         char rx_pkt[32];
1455         int i;
1456 #endif
1457
1458         sysctl_ctx_init(&sc->sysctl_ctx);
1459         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1460             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1461             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1462         if (sc->sysctl_tree == NULL) {
1463                 device_printf(sc->dev, "can't add sysctl node\n");
1464                 return;
1465         }
1466
1467         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1468             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1469         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1470             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1471             "# of RX rings used");
1472         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1473             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1474             "# of RX descs");
1475         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1476             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1477             "# of TX descs");
1478
1479         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1480             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1481             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1482
1483         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1484             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1485             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1486             "# of segments per TX interrupt");
1487
1488 #ifdef IGB_RSS_DEBUG
1489         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1490             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1491             "RSS debug level");
1492         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1493                 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
1494                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1495                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, rx_pkt,
1496                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1497         }
1498 #endif
1499 }
1500
1501 static int
1502 igb_alloc_rings(struct igb_softc *sc)
1503 {
1504         int error, i;
1505
1506         /*
1507          * Create top level busdma tag
1508          */
1509         error = bus_dma_tag_create(NULL, 1, 0,
1510             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1511             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1512             &sc->parent_tag);
1513         if (error) {
1514                 device_printf(sc->dev, "could not create top level DMA tag\n");
1515                 return error;
1516         }
1517
1518         /*
1519          * Allocate TX descriptor rings and buffers
1520          */
1521         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1522             M_DEVBUF, M_WAITOK | M_ZERO);
1523         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1524                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1525
1526                 /* Set up some basics */
1527                 txr->sc = sc;
1528                 txr->me = i;
1529                 lwkt_serialize_init(&txr->tx_serialize);
1530
1531                 error = igb_create_tx_ring(txr);
1532                 if (error)
1533                         return error;
1534         }
1535
1536         /*
1537          * Allocate RX descriptor rings and buffers
1538          */
1539         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1540             M_DEVBUF, M_WAITOK | M_ZERO);
1541         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1542                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1543
1544                 /* Set up some basics */
1545                 rxr->sc = sc;
1546                 rxr->me = i;
1547                 lwkt_serialize_init(&rxr->rx_serialize);
1548
1549                 error = igb_create_rx_ring(rxr);
1550                 if (error)
1551                         return error;
1552         }
1553
1554         return 0;
1555 }
1556
1557 static void
1558 igb_free_rings(struct igb_softc *sc)
1559 {
1560         int i;
1561
1562         if (sc->tx_rings != NULL) {
1563                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1564                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1565
1566                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1567                 }
1568                 kfree(sc->tx_rings, M_DEVBUF);
1569         }
1570
1571         if (sc->rx_rings != NULL) {
1572                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1573                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1574
1575                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1576                 }
1577                 kfree(sc->rx_rings, M_DEVBUF);
1578         }
1579 }
1580
1581 static int
1582 igb_create_tx_ring(struct igb_tx_ring *txr)
1583 {
1584         int tsize, error, i;
1585
1586         /*
1587          * Validate number of transmit descriptors. It must not exceed
1588          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1589          */
1590         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1591             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1592                 device_printf(txr->sc->dev,
1593                     "Using %d TX descriptors instead of %d!\n",
1594                     IGB_DEFAULT_TXD, igb_txd);
1595                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1596         } else {
1597                 txr->num_tx_desc = igb_txd;
1598         }
1599
1600         /*
1601          * Allocate TX descriptor ring
1602          */
1603         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1604             IGB_DBA_ALIGN);
1605         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1606             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1607             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1608         if (txr->txdma.dma_vaddr == NULL) {
1609                 device_printf(txr->sc->dev,
1610                     "Unable to allocate TX Descriptor memory\n");
1611                 return ENOMEM;
1612         }
1613         txr->tx_base = txr->txdma.dma_vaddr;
1614         bzero(txr->tx_base, tsize);
1615
1616         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1617             M_DEVBUF, M_WAITOK | M_ZERO);
1618
1619         /*
1620          * Allocate TX head write-back buffer
1621          */
1622         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1623             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1624             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1625         if (txr->tx_hdr == NULL) {
1626                 device_printf(txr->sc->dev,
1627                     "Unable to allocate TX head write-back buffer\n");
1628                 return ENOMEM;
1629         }
1630
1631         /*
1632          * Create DMA tag for TX buffers
1633          */
1634         error = bus_dma_tag_create(txr->sc->parent_tag,
1635             1, 0,               /* alignment, bounds */
1636             BUS_SPACE_MAXADDR,  /* lowaddr */
1637             BUS_SPACE_MAXADDR,  /* highaddr */
1638             NULL, NULL,         /* filter, filterarg */
1639             IGB_TSO_SIZE,       /* maxsize */
1640             IGB_MAX_SCATTER,    /* nsegments */
1641             PAGE_SIZE,          /* maxsegsize */
1642             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1643             BUS_DMA_ONEBPAGE,   /* flags */
1644             &txr->tx_tag);
1645         if (error) {
1646                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1647                 kfree(txr->tx_buf, M_DEVBUF);
1648                 txr->tx_buf = NULL;
1649                 return error;
1650         }
1651
1652         /*
1653          * Create DMA maps for TX buffers
1654          */
1655         for (i = 0; i < txr->num_tx_desc; ++i) {
1656                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1657
1658                 error = bus_dmamap_create(txr->tx_tag,
1659                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1660                 if (error) {
1661                         device_printf(txr->sc->dev,
1662                             "Unable to create TX DMA map\n");
1663                         igb_destroy_tx_ring(txr, i);
1664                         return error;
1665                 }
1666         }
1667
1668         /*
1669          * Initialize various watermark
1670          */
1671         txr->spare_desc = IGB_TX_SPARE;
1672         txr->intr_nsegs = txr->num_tx_desc / 16;
1673         txr->oact_hi_desc = txr->num_tx_desc / 2;
1674         txr->oact_lo_desc = txr->num_tx_desc / 8;
1675         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1676                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1677         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1678                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1679
1680         return 0;
1681 }
1682
1683 static void
1684 igb_free_tx_ring(struct igb_tx_ring *txr)
1685 {
1686         int i;
1687
1688         for (i = 0; i < txr->num_tx_desc; ++i) {
1689                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1690
1691                 if (txbuf->m_head != NULL) {
1692                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1693                         m_freem(txbuf->m_head);
1694                         txbuf->m_head = NULL;
1695                 }
1696         }
1697 }
1698
1699 static void
1700 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1701 {
1702         int i;
1703
1704         if (txr->txdma.dma_vaddr != NULL) {
1705                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1706                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1707                     txr->txdma.dma_map);
1708                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1709                 txr->txdma.dma_vaddr = NULL;
1710         }
1711
1712         if (txr->tx_hdr != NULL) {
1713                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1714                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1715                     txr->tx_hdr_dmap);
1716                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1717                 txr->tx_hdr = NULL;
1718         }
1719
1720         if (txr->tx_buf == NULL)
1721                 return;
1722
1723         for (i = 0; i < ndesc; ++i) {
1724                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1725
1726                 KKASSERT(txbuf->m_head == NULL);
1727                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1728         }
1729         bus_dma_tag_destroy(txr->tx_tag);
1730
1731         kfree(txr->tx_buf, M_DEVBUF);
1732         txr->tx_buf = NULL;
1733 }
1734
1735 static void
1736 igb_init_tx_ring(struct igb_tx_ring *txr)
1737 {
1738         /* Clear the old descriptor contents */
1739         bzero(txr->tx_base,
1740             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1741
1742         /* Clear TX head write-back buffer */
1743         *(txr->tx_hdr) = 0;
1744
1745         /* Reset indices */
1746         txr->next_avail_desc = 0;
1747         txr->next_to_clean = 0;
1748         txr->tx_nsegs = 0;
1749
1750         /* Set number of descriptors available */
1751         txr->tx_avail = txr->num_tx_desc;
1752 }
1753
1754 static void
1755 igb_init_tx_unit(struct igb_softc *sc)
1756 {
1757         struct e1000_hw *hw = &sc->hw;
1758         uint32_t tctl;
1759         int i;
1760
1761         /* Setup the Tx Descriptor Rings */
1762         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1763                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1764                 uint64_t bus_addr = txr->txdma.dma_paddr;
1765                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1766                 uint32_t txdctl = 0;
1767                 uint32_t dca_txctrl;
1768
1769                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1770                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1771                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1772                     (uint32_t)(bus_addr >> 32));
1773                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1774                     (uint32_t)bus_addr);
1775
1776                 /* Setup the HW Tx Head and Tail descriptor pointers */
1777                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1778                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1779
1780                 txdctl |= IGB_TX_PTHRESH;
1781                 txdctl |= IGB_TX_HTHRESH << 8;
1782                 txdctl |= IGB_TX_WTHRESH << 16;
1783                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1784                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1785
1786                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1787                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1788                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1789
1790                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1791                     (uint32_t)(hdr_paddr >> 32));
1792                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1793                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1794         }
1795
1796         if (sc->vf_ifp)
1797                 return;
1798
1799         e1000_config_collision_dist(hw);
1800
1801         /* Program the Transmit Control Register */
1802         tctl = E1000_READ_REG(hw, E1000_TCTL);
1803         tctl &= ~E1000_TCTL_CT;
1804         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1805             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1806
1807         /* This write will effectively turn on the transmit unit. */
1808         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1809 }
1810
1811 static boolean_t
1812 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1813 {
1814         struct e1000_adv_tx_context_desc *TXD;
1815         struct igb_tx_buf *txbuf;
1816         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1817         struct ether_vlan_header *eh;
1818         struct ip *ip = NULL;
1819         int ehdrlen, ctxd, ip_hlen = 0;
1820         uint16_t etype, vlantag = 0;
1821         boolean_t offload = TRUE;
1822
1823         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1824                 offload = FALSE;
1825
1826         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1827         ctxd = txr->next_avail_desc;
1828         txbuf = &txr->tx_buf[ctxd];
1829         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1830
1831         /*
1832          * In advanced descriptors the vlan tag must
1833          * be placed into the context descriptor, thus
1834          * we need to be here just for that setup.
1835          */
1836         if (mp->m_flags & M_VLANTAG) {
1837                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1838                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1839         } else if (!offload) {
1840                 return FALSE;
1841         }
1842
1843         /*
1844          * Determine where frame payload starts.
1845          * Jump over vlan headers if already present,
1846          * helpful for QinQ too.
1847          */
1848         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1849             ("igb_txctx_pullup is not called (eh)?\n"));
1850         eh = mtod(mp, struct ether_vlan_header *);
1851         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1852                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1853                     ("igb_txctx_pullup is not called (evh)?\n"));
1854                 etype = ntohs(eh->evl_proto);
1855                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1856         } else {
1857                 etype = ntohs(eh->evl_encap_proto);
1858                 ehdrlen = ETHER_HDR_LEN;
1859         }
1860
1861         /* Set the ether header length */
1862         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1863
1864         switch (etype) {
1865         case ETHERTYPE_IP:
1866                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1867                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1868
1869                 /* NOTE: We could only safely access ip.ip_vhl part */
1870                 ip = (struct ip *)(mp->m_data + ehdrlen);
1871                 ip_hlen = ip->ip_hl << 2;
1872
1873                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1874                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1875                 break;
1876
1877 #ifdef notyet
1878         case ETHERTYPE_IPV6:
1879                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1880                 ip_hlen = sizeof(struct ip6_hdr);
1881                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1882                 break;
1883 #endif
1884
1885         default:
1886                 offload = FALSE;
1887                 break;
1888         }
1889
1890         vlan_macip_lens |= ip_hlen;
1891         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1892
1893         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1894                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1895         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1896                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1897
1898         /* 82575 needs the queue index added */
1899         if (txr->sc->hw.mac.type == e1000_82575)
1900                 mss_l4len_idx = txr->me << 4;
1901
1902         /* Now copy bits into descriptor */
1903         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1904         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1905         TXD->seqnum_seed = htole32(0);
1906         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1907
1908         txbuf->m_head = NULL;
1909
1910         /* We've consumed the first desc, adjust counters */
1911         if (++ctxd == txr->num_tx_desc)
1912                 ctxd = 0;
1913         txr->next_avail_desc = ctxd;
1914         --txr->tx_avail;
1915
1916         return offload;
1917 }
1918
1919 static void
1920 igb_txeof(struct igb_tx_ring *txr)
1921 {
1922         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1923         int first, hdr, avail;
1924
1925         if (txr->tx_avail == txr->num_tx_desc)
1926                 return;
1927
1928         first = txr->next_to_clean;
1929         hdr = *(txr->tx_hdr);
1930
1931         if (first == hdr)
1932                 return;
1933
1934         avail = txr->tx_avail;
1935         while (first != hdr) {
1936                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1937
1938                 ++avail;
1939                 if (txbuf->m_head) {
1940                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1941                         m_freem(txbuf->m_head);
1942                         txbuf->m_head = NULL;
1943                         ++ifp->if_opackets;
1944                 }
1945                 if (++first == txr->num_tx_desc)
1946                         first = 0;
1947         }
1948         txr->next_to_clean = first;
1949         txr->tx_avail = avail;
1950
1951         /*
1952          * If we have a minimum free, clear IFF_OACTIVE
1953          * to tell the stack that it is OK to send packets.
1954          */
1955         if (IGB_IS_NOT_OACTIVE(txr)) {
1956                 ifp->if_flags &= ~IFF_OACTIVE;
1957
1958                 /*
1959                  * We have enough TX descriptors, turn off
1960                  * the watchdog.  We allow small amount of
1961                  * packets (roughly intr_nsegs) pending on
1962                  * the transmit ring.
1963                  */
1964                 ifp->if_timer = 0;
1965         }
1966 }
1967
1968 static int
1969 igb_create_rx_ring(struct igb_rx_ring *rxr)
1970 {
1971         int rsize, i, error;
1972
1973         /*
1974          * Validate number of receive descriptors. It must not exceed
1975          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1976          */
1977         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1978             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1979                 device_printf(rxr->sc->dev,
1980                     "Using %d RX descriptors instead of %d!\n",
1981                     IGB_DEFAULT_RXD, igb_rxd);
1982                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1983         } else {
1984                 rxr->num_rx_desc = igb_rxd;
1985         }
1986
1987         /*
1988          * Allocate RX descriptor ring
1989          */
1990         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1991             IGB_DBA_ALIGN);
1992         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1993             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1994             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1995             &rxr->rxdma.dma_paddr);
1996         if (rxr->rxdma.dma_vaddr == NULL) {
1997                 device_printf(rxr->sc->dev,
1998                     "Unable to allocate RxDescriptor memory\n");
1999                 return ENOMEM;
2000         }
2001         rxr->rx_base = rxr->rxdma.dma_vaddr;
2002         bzero(rxr->rx_base, rsize);
2003
2004         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2005             M_DEVBUF, M_WAITOK | M_ZERO);
2006
2007         /*
2008          * Create DMA tag for RX buffers
2009          */
2010         error = bus_dma_tag_create(rxr->sc->parent_tag,
2011             1, 0,               /* alignment, bounds */
2012             BUS_SPACE_MAXADDR,  /* lowaddr */
2013             BUS_SPACE_MAXADDR,  /* highaddr */
2014             NULL, NULL,         /* filter, filterarg */
2015             MCLBYTES,           /* maxsize */
2016             1,                  /* nsegments */
2017             MCLBYTES,           /* maxsegsize */
2018             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2019             &rxr->rx_tag);
2020         if (error) {
2021                 device_printf(rxr->sc->dev,
2022                     "Unable to create RX payload DMA tag\n");
2023                 kfree(rxr->rx_buf, M_DEVBUF);
2024                 rxr->rx_buf = NULL;
2025                 return error;
2026         }
2027
2028         /*
2029          * Create spare DMA map for RX buffers
2030          */
2031         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2032             &rxr->rx_sparemap);
2033         if (error) {
2034                 device_printf(rxr->sc->dev,
2035                     "Unable to create spare RX DMA maps\n");
2036                 bus_dma_tag_destroy(rxr->rx_tag);
2037                 kfree(rxr->rx_buf, M_DEVBUF);
2038                 rxr->rx_buf = NULL;
2039                 return error;
2040         }
2041
2042         /*
2043          * Create DMA maps for RX buffers
2044          */
2045         for (i = 0; i < rxr->num_rx_desc; i++) {
2046                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2047
2048                 error = bus_dmamap_create(rxr->rx_tag,
2049                     BUS_DMA_WAITOK, &rxbuf->map);
2050                 if (error) {
2051                         device_printf(rxr->sc->dev,
2052                             "Unable to create RX DMA maps\n");
2053                         igb_destroy_rx_ring(rxr, i);
2054                         return error;
2055                 }
2056         }
2057         return 0;
2058 }
2059
2060 static void
2061 igb_free_rx_ring(struct igb_rx_ring *rxr)
2062 {
2063         int i;
2064
2065         for (i = 0; i < rxr->num_rx_desc; ++i) {
2066                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2067
2068                 if (rxbuf->m_head != NULL) {
2069                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2070                         m_freem(rxbuf->m_head);
2071                         rxbuf->m_head = NULL;
2072                 }
2073         }
2074
2075         if (rxr->fmp != NULL)
2076                 m_freem(rxr->fmp);
2077         rxr->fmp = NULL;
2078         rxr->lmp = NULL;
2079 }
2080
2081 static void
2082 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2083 {
2084         int i;
2085
2086         if (rxr->rxdma.dma_vaddr != NULL) {
2087                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2088                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2089                     rxr->rxdma.dma_map);
2090                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2091                 rxr->rxdma.dma_vaddr = NULL;
2092         }
2093
2094         if (rxr->rx_buf == NULL)
2095                 return;
2096
2097         for (i = 0; i < ndesc; ++i) {
2098                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2099
2100                 KKASSERT(rxbuf->m_head == NULL);
2101                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2102         }
2103         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2104         bus_dma_tag_destroy(rxr->rx_tag);
2105
2106         kfree(rxr->rx_buf, M_DEVBUF);
2107         rxr->rx_buf = NULL;
2108 }
2109
2110 static void
2111 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2112 {
2113         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2114         rxd->wb.upper.status_error = 0;
2115 }
2116
2117 static int
2118 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2119 {
2120         struct mbuf *m;
2121         bus_dma_segment_t seg;
2122         bus_dmamap_t map;
2123         struct igb_rx_buf *rxbuf;
2124         int error, nseg;
2125
2126         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2127         if (m == NULL) {
2128                 if (wait) {
2129                         if_printf(&rxr->sc->arpcom.ac_if,
2130                             "Unable to allocate RX mbuf\n");
2131                 }
2132                 return ENOBUFS;
2133         }
2134         m->m_len = m->m_pkthdr.len = MCLBYTES;
2135
2136         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2137                 m_adj(m, ETHER_ALIGN);
2138
2139         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2140             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2141         if (error) {
2142                 m_freem(m);
2143                 if (wait) {
2144                         if_printf(&rxr->sc->arpcom.ac_if,
2145                             "Unable to load RX mbuf\n");
2146                 }
2147                 return error;
2148         }
2149
2150         rxbuf = &rxr->rx_buf[i];
2151         if (rxbuf->m_head != NULL)
2152                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2153
2154         map = rxbuf->map;
2155         rxbuf->map = rxr->rx_sparemap;
2156         rxr->rx_sparemap = map;
2157
2158         rxbuf->m_head = m;
2159         rxbuf->paddr = seg.ds_addr;
2160
2161         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2162         return 0;
2163 }
2164
2165 static int
2166 igb_init_rx_ring(struct igb_rx_ring *rxr)
2167 {
2168         int i;
2169
2170         /* Clear the ring contents */
2171         bzero(rxr->rx_base,
2172             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2173
2174         /* Now replenish the ring mbufs */
2175         for (i = 0; i < rxr->num_rx_desc; ++i) {
2176                 int error;
2177
2178                 error = igb_newbuf(rxr, i, TRUE);
2179                 if (error)
2180                         return error;
2181         }
2182
2183         /* Setup our descriptor indices */
2184         rxr->next_to_check = 0;
2185
2186         rxr->fmp = NULL;
2187         rxr->lmp = NULL;
2188         rxr->discard = FALSE;
2189
2190         return 0;
2191 }
2192
2193 static void
2194 igb_init_rx_unit(struct igb_softc *sc)
2195 {
2196         struct ifnet *ifp = &sc->arpcom.ac_if;
2197         struct e1000_hw *hw = &sc->hw;
2198         uint32_t rctl, rxcsum, srrctl = 0;
2199         int i;
2200
2201         /*
2202          * Make sure receives are disabled while setting
2203          * up the descriptor ring
2204          */
2205         rctl = E1000_READ_REG(hw, E1000_RCTL);
2206         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2207
2208 #if 0
2209         /*
2210         ** Set up for header split
2211         */
2212         if (igb_header_split) {
2213                 /* Use a standard mbuf for the header */
2214                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2215                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2216         } else
2217 #endif
2218                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2219
2220         /*
2221         ** Set up for jumbo frames
2222         */
2223         if (ifp->if_mtu > ETHERMTU) {
2224                 rctl |= E1000_RCTL_LPE;
2225 #if 0
2226                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2227                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2228                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2229                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2230                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2231                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2232                 }
2233                 /* Set maximum packet len */
2234                 psize = adapter->max_frame_size;
2235                 /* are we on a vlan? */
2236                 if (adapter->ifp->if_vlantrunk != NULL)
2237                         psize += VLAN_TAG_SIZE;
2238                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2239 #else
2240                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2241                 rctl |= E1000_RCTL_SZ_2048;
2242 #endif
2243         } else {
2244                 rctl &= ~E1000_RCTL_LPE;
2245                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2246                 rctl |= E1000_RCTL_SZ_2048;
2247         }
2248
2249         /* Setup the Base and Length of the Rx Descriptor Rings */
2250         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2251                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2252                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2253                 uint32_t rxdctl;
2254
2255                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2256                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2257                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2258                     (uint32_t)(bus_addr >> 32));
2259                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2260                     (uint32_t)bus_addr);
2261                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2262                 /* Enable this Queue */
2263                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2264                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2265                 rxdctl &= 0xFFF00000;
2266                 rxdctl |= IGB_RX_PTHRESH;
2267                 rxdctl |= IGB_RX_HTHRESH << 8;
2268                 rxdctl |= IGB_RX_WTHRESH << 16;
2269                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2270         }
2271
2272         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2273         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2274
2275         /*
2276          * Receive Checksum Offload for TCP and UDP
2277          *
2278          * Checksum offloading is also enabled if multiple receive
2279          * queue is to be supported, since we need it to figure out
2280          * fragments.
2281          */
2282         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2283                 /*
2284                  * NOTE:
2285                  * PCSD must be enabled to enable multiple
2286                  * receive queues.
2287                  */
2288                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2289                     E1000_RXCSUM_PCSD;
2290         } else {
2291                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2292                     E1000_RXCSUM_PCSD);
2293         }
2294         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2295
2296         if (IGB_ENABLE_HWRSS(sc)) {
2297                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2298                 uint32_t reta_shift;
2299                 int j, r;
2300
2301                 /*
2302                  * NOTE:
2303                  * When we reach here, RSS has already been disabled
2304                  * in igb_stop(), so we could safely configure RSS key
2305                  * and redirect table.
2306                  */
2307
2308                 /*
2309                  * Configure RSS key
2310                  */
2311                 toeplitz_get_key(key, sizeof(key));
2312                 for (i = 0; i < IGB_NRSSRK; ++i) {
2313                         uint32_t rssrk;
2314
2315                         rssrk = IGB_RSSRK_VAL(key, i);
2316                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2317
2318                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2319                 }
2320
2321                 /*
2322                  * Configure RSS redirect table in following fashion:
2323                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2324                  */
2325                 reta_shift = IGB_RETA_SHIFT;
2326                 if (hw->mac.type == e1000_82575)
2327                         reta_shift = IGB_RETA_SHIFT_82575;
2328
2329                 r = 0;
2330                 for (j = 0; j < IGB_NRETA; ++j) {
2331                         uint32_t reta = 0;
2332
2333                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2334                                 uint32_t q;
2335
2336                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2337                                 reta |= q << (8 * i);
2338                                 ++r;
2339                         }
2340                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2341                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2342                 }
2343
2344                 /*
2345                  * Enable multiple receive queues.
2346                  * Enable IPv4 RSS standard hash functions.
2347                  * Disable RSS interrupt on 82575
2348                  */
2349                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2350                                 E1000_MRQC_ENABLE_RSS_4Q |
2351                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2352                                 E1000_MRQC_RSS_FIELD_IPV4);
2353         }
2354
2355         /* Setup the Receive Control Register */
2356         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2357         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2358             E1000_RCTL_RDMTS_HALF |
2359             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2360         /* Strip CRC bytes. */
2361         rctl |= E1000_RCTL_SECRC;
2362         /* Make sure VLAN Filters are off */
2363         rctl &= ~E1000_RCTL_VFE;
2364         /* Don't store bad packets */
2365         rctl &= ~E1000_RCTL_SBP;
2366
2367         /* Enable Receives */
2368         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2369
2370         /*
2371          * Setup the HW Rx Head and Tail Descriptor Pointers
2372          *   - needs to be after enable
2373          */
2374         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2375                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2376
2377                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2378                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2379         }
2380 }
2381
2382 static void
2383 igb_rxeof(struct igb_rx_ring *rxr, int count)
2384 {
2385         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2386         union e1000_adv_rx_desc *cur;
2387         uint32_t staterr;
2388         int i;
2389
2390         i = rxr->next_to_check;
2391         cur = &rxr->rx_base[i];
2392         staterr = le32toh(cur->wb.upper.status_error);
2393
2394         if ((staterr & E1000_RXD_STAT_DD) == 0)
2395                 return;
2396
2397         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2398                 struct pktinfo *pi = NULL, pi0;
2399                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2400                 struct mbuf *m = NULL;
2401                 boolean_t eop;
2402
2403                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2404                 if (eop)
2405                         --count;
2406
2407                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2408                     !rxr->discard) {
2409                         struct mbuf *mp = rxbuf->m_head;
2410                         uint32_t hash, hashtype;
2411                         uint16_t vlan;
2412                         int len;
2413
2414                         len = le16toh(cur->wb.upper.length);
2415                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2416                             (staterr & E1000_RXDEXT_STATERR_LB))
2417                                 vlan = be16toh(cur->wb.upper.vlan);
2418                         else
2419                                 vlan = le16toh(cur->wb.upper.vlan);
2420
2421                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2422                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2423                             E1000_RXDADV_RSSTYPE_MASK;
2424
2425                         IGB_RSS_DPRINTF(rxr->sc, 10,
2426                             "ring%d, hash 0x%08x, hashtype %u\n",
2427                             rxr->me, hash, hashtype);
2428
2429                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2430                             BUS_DMASYNC_POSTREAD);
2431
2432                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2433                                 ifp->if_iqdrops++;
2434                                 goto discard;
2435                         }
2436
2437                         mp->m_len = len;
2438                         if (rxr->fmp == NULL) {
2439                                 mp->m_pkthdr.len = len;
2440                                 rxr->fmp = mp;
2441                                 rxr->lmp = mp;
2442                         } else {
2443                                 rxr->lmp->m_next = mp;
2444                                 rxr->lmp = rxr->lmp->m_next;
2445                                 rxr->fmp->m_pkthdr.len += len;
2446                         }
2447
2448                         if (eop) {
2449                                 m = rxr->fmp;
2450                                 rxr->fmp = NULL;
2451                                 rxr->lmp = NULL;
2452
2453                                 m->m_pkthdr.rcvif = ifp;
2454                                 ifp->if_ipackets++;
2455
2456                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2457                                         igb_rxcsum(staterr, m);
2458
2459                                 if (staterr & E1000_RXD_STAT_VP) {
2460                                         m->m_pkthdr.ether_vlantag = vlan;
2461                                         m->m_flags |= M_VLANTAG;
2462                                 }
2463
2464                                 if (ifp->if_capenable & IFCAP_RSS) {
2465                                         pi = igb_rssinfo(m, &pi0,
2466                                             hash, hashtype, staterr);
2467                                 }
2468 #ifdef IGB_RSS_DEBUG
2469                                 rxr->rx_packets++;
2470 #endif
2471                         }
2472                 } else {
2473                         ifp->if_ierrors++;
2474 discard:
2475                         igb_setup_rxdesc(cur, rxbuf);
2476                         if (!eop)
2477                                 rxr->discard = TRUE;
2478                         else
2479                                 rxr->discard = FALSE;
2480                         if (rxr->fmp != NULL) {
2481                                 m_freem(rxr->fmp);
2482                                 rxr->fmp = NULL;
2483                                 rxr->lmp = NULL;
2484                         }
2485                         m = NULL;
2486                 }
2487
2488                 if (m != NULL)
2489                         ether_input_pkt(ifp, m, pi);
2490
2491                 /* Advance our pointers to the next descriptor. */
2492                 if (++i == rxr->num_rx_desc)
2493                         i = 0;
2494
2495                 cur = &rxr->rx_base[i];
2496                 staterr = le32toh(cur->wb.upper.status_error);
2497         }
2498         rxr->next_to_check = i;
2499
2500         if (--i < 0)
2501                 i = rxr->num_rx_desc - 1;
2502         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2503 }
2504
2505
2506 static void
2507 igb_set_vlan(struct igb_softc *sc)
2508 {
2509         struct e1000_hw *hw = &sc->hw;
2510         uint32_t reg;
2511 #if 0
2512         struct ifnet *ifp = sc->arpcom.ac_if;
2513 #endif
2514
2515         if (sc->vf_ifp) {
2516                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2517                 return;
2518         }
2519
2520         reg = E1000_READ_REG(hw, E1000_CTRL);
2521         reg |= E1000_CTRL_VME;
2522         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2523
2524 #if 0
2525         /* Enable the Filter Table */
2526         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2527                 reg = E1000_READ_REG(hw, E1000_RCTL);
2528                 reg &= ~E1000_RCTL_CFIEN;
2529                 reg |= E1000_RCTL_VFE;
2530                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2531         }
2532 #endif
2533
2534         /* Update the frame size */
2535         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2536             sc->max_frame_size + VLAN_TAG_SIZE);
2537
2538 #if 0
2539         /* Don't bother with table if no vlans */
2540         if ((adapter->num_vlans == 0) ||
2541             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2542                 return;
2543         /*
2544         ** A soft reset zero's out the VFTA, so
2545         ** we need to repopulate it now.
2546         */
2547         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2548                 if (adapter->shadow_vfta[i] != 0) {
2549                         if (adapter->vf_ifp)
2550                                 e1000_vfta_set_vf(hw,
2551                                     adapter->shadow_vfta[i], TRUE);
2552                         else
2553                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2554                                  i, adapter->shadow_vfta[i]);
2555                 }
2556 #endif
2557 }
2558
2559 static void
2560 igb_enable_intr(struct igb_softc *sc)
2561 {
2562         lwkt_serialize_handler_enable(&sc->main_serialize);
2563
2564         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2565                 /* XXX MSI-X should use sc->intr_mask */
2566                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2567                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2568                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2569                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2570         } else {
2571                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2572         }
2573         E1000_WRITE_FLUSH(&sc->hw);
2574 }
2575
2576 static void
2577 igb_disable_intr(struct igb_softc *sc)
2578 {
2579         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2580                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2581                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2582         }
2583         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2584         E1000_WRITE_FLUSH(&sc->hw);
2585
2586         lwkt_serialize_handler_disable(&sc->main_serialize);
2587 }
2588
2589 /*
2590  * Bit of a misnomer, what this really means is
2591  * to enable OS management of the system... aka
2592  * to disable special hardware management features
2593  */
2594 static void
2595 igb_get_mgmt(struct igb_softc *sc)
2596 {
2597         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2598                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2599                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2600
2601                 /* disable hardware interception of ARP */
2602                 manc &= ~E1000_MANC_ARP_EN;
2603
2604                 /* enable receiving management packets to the host */
2605                 manc |= E1000_MANC_EN_MNG2HOST;
2606                 manc2h |= 1 << 5; /* Mng Port 623 */
2607                 manc2h |= 1 << 6; /* Mng Port 664 */
2608                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2609                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2610         }
2611 }
2612
2613 /*
2614  * Give control back to hardware management controller
2615  * if there is one.
2616  */
2617 static void
2618 igb_rel_mgmt(struct igb_softc *sc)
2619 {
2620         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2621                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2622
2623                 /* Re-enable hardware interception of ARP */
2624                 manc |= E1000_MANC_ARP_EN;
2625                 manc &= ~E1000_MANC_EN_MNG2HOST;
2626
2627                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2628         }
2629 }
2630
2631 /*
2632  * Sets CTRL_EXT:DRV_LOAD bit.
2633  *
2634  * For ASF and Pass Through versions of f/w this means that
2635  * the driver is loaded.
2636  */
2637 static void
2638 igb_get_hw_control(struct igb_softc *sc)
2639 {
2640         uint32_t ctrl_ext;
2641
2642         if (sc->vf_ifp)
2643                 return;
2644
2645         /* Let firmware know the driver has taken over */
2646         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2647         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2648             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2649 }
2650
2651 /*
2652  * Resets CTRL_EXT:DRV_LOAD bit.
2653  *
2654  * For ASF and Pass Through versions of f/w this means that the
2655  * driver is no longer loaded.
2656  */
2657 static void
2658 igb_rel_hw_control(struct igb_softc *sc)
2659 {
2660         uint32_t ctrl_ext;
2661
2662         if (sc->vf_ifp)
2663                 return;
2664
2665         /* Let firmware taken over control of h/w */
2666         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2667         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2668             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2669 }
2670
2671 static int
2672 igb_is_valid_ether_addr(const uint8_t *addr)
2673 {
2674         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2675
2676         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2677                 return FALSE;
2678         return TRUE;
2679 }
2680
2681 /*
2682  * Enable PCI Wake On Lan capability
2683  */
2684 static void
2685 igb_enable_wol(device_t dev)
2686 {
2687         uint16_t cap, status;
2688         uint8_t id;
2689
2690         /* First find the capabilities pointer*/
2691         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2692
2693         /* Read the PM Capabilities */
2694         id = pci_read_config(dev, cap, 1);
2695         if (id != PCIY_PMG)     /* Something wrong */
2696                 return;
2697
2698         /*
2699          * OK, we have the power capabilities,
2700          * so now get the status register
2701          */
2702         cap += PCIR_POWER_STATUS;
2703         status = pci_read_config(dev, cap, 2);
2704         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2705         pci_write_config(dev, cap, status, 2);
2706 }
2707
2708 static void
2709 igb_update_stats_counters(struct igb_softc *sc)
2710 {
2711         struct e1000_hw *hw = &sc->hw;
2712         struct e1000_hw_stats *stats;
2713         struct ifnet *ifp = &sc->arpcom.ac_if;
2714
2715         /*
2716          * The virtual function adapter has only a
2717          * small controlled set of stats, do only
2718          * those and return.
2719          */
2720         if (sc->vf_ifp) {
2721                 igb_update_vf_stats_counters(sc);
2722                 return;
2723         }
2724         stats = sc->stats;
2725
2726         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2727             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2728                 stats->symerrs +=
2729                     E1000_READ_REG(hw,E1000_SYMERRS);
2730                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2731         }
2732
2733         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2734         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2735         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2736         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2737
2738         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2739         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2740         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2741         stats->dc += E1000_READ_REG(hw, E1000_DC);
2742         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2743         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2744         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2745
2746         /*
2747          * For watchdog management we need to know if we have been
2748          * paused during the last interval, so capture that here.
2749          */
2750         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2751         stats->xoffrxc += sc->pause_frames;
2752         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2753         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2754         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2755         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2756         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2757         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2758         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2759         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2760         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2761         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2762         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2763         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2764
2765         /* For the 64-bit byte counters the low dword must be read first. */
2766         /* Both registers clear on the read of the high dword */
2767
2768         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2769             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2770         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2771             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2772
2773         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2774         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2775         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2776         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2777         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2778
2779         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2780         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2781
2782         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2783         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2784         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2785         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2786         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2787         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2788         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2789         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2790         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2791         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2792
2793         /* Interrupt Counts */
2794
2795         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2796         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2797         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2798         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2799         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2800         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2801         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2802         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2803         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2804
2805         /* Host to Card Statistics */
2806
2807         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2808         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2809         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2810         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2811         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2812         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2813         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2814         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2815             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2816         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2817             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2818         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2819         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2820         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2821
2822         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2823         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2824         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2825         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2826         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2827         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2828
2829         ifp->if_collisions = stats->colc;
2830
2831         /* Rx Errors */
2832         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2833             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2834
2835         /* Tx Errors */
2836         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2837
2838         /* Driver specific counters */
2839         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2840         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2841         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2842         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2843         sc->packet_buf_alloc_tx =
2844             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2845         sc->packet_buf_alloc_rx =
2846             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2847 }
2848
2849 static void
2850 igb_vf_init_stats(struct igb_softc *sc)
2851 {
2852         struct e1000_hw *hw = &sc->hw;
2853         struct e1000_vf_stats *stats;
2854
2855         stats = sc->stats;
2856         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2857         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2858         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2859         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2860         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2861 }
2862
2863 static void
2864 igb_update_vf_stats_counters(struct igb_softc *sc)
2865 {
2866         struct e1000_hw *hw = &sc->hw;
2867         struct e1000_vf_stats *stats;
2868
2869         if (sc->link_speed == 0)
2870                 return;
2871
2872         stats = sc->stats;
2873         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2874         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2875         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2876         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2877         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2878 }
2879
2880 #ifdef DEVICE_POLLING
2881
2882 static void
2883 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2884 {
2885         struct igb_softc *sc = ifp->if_softc;
2886         uint32_t reg_icr;
2887
2888         ASSERT_SERIALIZED(&sc->main_serialize);
2889
2890         switch (cmd) {
2891         case POLL_REGISTER:
2892                 igb_disable_intr(sc);
2893                 break;
2894
2895         case POLL_DEREGISTER:
2896                 igb_enable_intr(sc);
2897                 break;
2898
2899         case POLL_AND_CHECK_STATUS:
2900                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2901                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2902                         sc->hw.mac.get_link_status = 1;
2903                         igb_update_link_status(sc);
2904                 }
2905                 /* FALL THROUGH */
2906         case POLL_ONLY:
2907                 if (ifp->if_flags & IFF_RUNNING) {
2908                         struct igb_tx_ring *txr;
2909                         int i;
2910
2911                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2912                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2913
2914                                 lwkt_serialize_enter(&rxr->rx_serialize);
2915                                 igb_rxeof(rxr, count);
2916                                 lwkt_serialize_exit(&rxr->rx_serialize);
2917                         }
2918
2919                         txr = &sc->tx_rings[0];
2920                         lwkt_serialize_enter(&txr->tx_serialize);
2921                         igb_txeof(txr);
2922                         if (!ifq_is_empty(&ifp->if_snd))
2923                                 if_devstart(ifp);
2924                         lwkt_serialize_exit(&txr->tx_serialize);
2925                 }
2926                 break;
2927         }
2928 }
2929
2930 #endif /* DEVICE_POLLING */
2931
2932 static void
2933 igb_intr(void *xsc)
2934 {
2935         struct igb_softc *sc = xsc;
2936         struct ifnet *ifp = &sc->arpcom.ac_if;
2937         uint32_t eicr;
2938
2939         ASSERT_SERIALIZED(&sc->main_serialize);
2940
2941         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2942
2943         if (eicr == 0)
2944                 return;
2945
2946         if (ifp->if_flags & IFF_RUNNING) {
2947                 struct igb_tx_ring *txr;
2948                 int i;
2949
2950                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2951                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
2952
2953                         if (eicr & rxr->rx_intr_mask) {
2954                                 lwkt_serialize_enter(&rxr->rx_serialize);
2955                                 igb_rxeof(rxr, -1);
2956                                 lwkt_serialize_exit(&rxr->rx_serialize);
2957                         }
2958                 }
2959
2960                 txr = &sc->tx_rings[0];
2961                 if (eicr & txr->tx_intr_mask) {
2962                         lwkt_serialize_enter(&txr->tx_serialize);
2963                         igb_txeof(txr);
2964                         if (!ifq_is_empty(&ifp->if_snd))
2965                                 if_devstart(ifp);
2966                         lwkt_serialize_exit(&txr->tx_serialize);
2967                 }
2968         }
2969
2970         if (eicr & E1000_EICR_OTHER) {
2971                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2972
2973                 /* Link status change */
2974                 if (icr & E1000_ICR_LSC) {
2975                         sc->hw.mac.get_link_status = 1;
2976                         igb_update_link_status(sc);
2977                 }
2978         }
2979
2980         /*
2981          * Reading EICR has the side effect to clear interrupt mask,
2982          * so all interrupts need to be enabled here.
2983          */
2984         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2985 }
2986
2987 static void
2988 igb_shared_intr(void *xsc)
2989 {
2990         struct igb_softc *sc = xsc;
2991         struct ifnet *ifp = &sc->arpcom.ac_if;
2992         uint32_t reg_icr;
2993
2994         ASSERT_SERIALIZED(&sc->main_serialize);
2995
2996         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2997
2998         /* Hot eject?  */
2999         if (reg_icr == 0xffffffff)
3000                 return;
3001
3002         /* Definitely not our interrupt.  */
3003         if (reg_icr == 0x0)
3004                 return;
3005
3006         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3007                 return;
3008
3009         if (ifp->if_flags & IFF_RUNNING) {
3010                 if (reg_icr &
3011                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3012                         int i;
3013
3014                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3015                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3016
3017                                 lwkt_serialize_enter(&rxr->rx_serialize);
3018                                 igb_rxeof(rxr, -1);
3019                                 lwkt_serialize_exit(&rxr->rx_serialize);
3020                         }
3021                 }
3022
3023                 if (reg_icr & E1000_ICR_TXDW) {
3024                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3025
3026                         lwkt_serialize_enter(&txr->tx_serialize);
3027                         igb_txeof(txr);
3028                         if (!ifq_is_empty(&ifp->if_snd))
3029                                 if_devstart(ifp);
3030                         lwkt_serialize_exit(&txr->tx_serialize);
3031                 }
3032         }
3033
3034         /* Link status change */
3035         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3036                 sc->hw.mac.get_link_status = 1;
3037                 igb_update_link_status(sc);
3038         }
3039
3040         if (reg_icr & E1000_ICR_RXO)
3041                 sc->rx_overruns++;
3042 }
3043
3044 static int
3045 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3046 {
3047         struct mbuf *m = *m0;
3048         struct ether_header *eh;
3049         int len;
3050
3051         txr->ctx_try_pullup++;
3052
3053         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3054
3055         if (__predict_false(!M_WRITABLE(m))) {
3056                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3057                         txr->ctx_drop1++;
3058                         m_freem(m);
3059                         *m0 = NULL;
3060                         return ENOBUFS;
3061                 }
3062                 eh = mtod(m, struct ether_header *);
3063
3064                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3065                         len += EVL_ENCAPLEN;
3066
3067                 if (m->m_len < len) {
3068                         txr->ctx_drop2++;
3069                         m_freem(m);
3070                         *m0 = NULL;
3071                         return ENOBUFS;
3072                 }
3073                 return 0;
3074         }
3075
3076         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3077                 txr->ctx_pullup1++;
3078                 m = m_pullup(m, ETHER_HDR_LEN);
3079                 if (m == NULL) {
3080                         txr->ctx_pullup1_failed++;
3081                         *m0 = NULL;
3082                         return ENOBUFS;
3083                 }
3084                 *m0 = m;
3085         }
3086         eh = mtod(m, struct ether_header *);
3087
3088         if (eh->ether_type == htons(ETHERTYPE_VLAN))
3089                 len += EVL_ENCAPLEN;
3090
3091         if (m->m_len < len) {
3092                 txr->ctx_pullup2++;
3093                 m = m_pullup(m, len);
3094                 if (m == NULL) {
3095                         txr->ctx_pullup2_failed++;
3096                         *m0 = NULL;
3097                         return ENOBUFS;
3098                 }
3099                 *m0 = m;
3100         }
3101         return 0;
3102 }
3103
3104 static int
3105 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3106 {
3107         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3108         bus_dmamap_t map;
3109         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3110         union e1000_adv_tx_desc *txd = NULL;
3111         struct mbuf *m_head = *m_headp;
3112         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3113         int maxsegs, nsegs, i, j, error, last = 0;
3114         uint32_t hdrlen = 0;
3115
3116         if (m_head->m_len < IGB_TXCSUM_MINHL &&
3117             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3118              (m_head->m_flags & M_VLANTAG))) {
3119                 /*
3120                  * Make sure that ethernet header and ip.ip_hl are in
3121                  * contiguous memory, since if TXCSUM or VLANTAG is
3122                  * enabled, later TX context descriptor's setup need
3123                  * to access ip.ip_hl.
3124                  */
3125                 error = igb_txctx_pullup(txr, m_headp);
3126                 if (error) {
3127                         KKASSERT(*m_headp == NULL);
3128                         return error;
3129                 }
3130                 m_head = *m_headp;
3131         }
3132
3133         /* Set basic descriptor constants */
3134         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3135         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3136         if (m_head->m_flags & M_VLANTAG)
3137                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3138
3139         /*
3140          * Map the packet for DMA.
3141          */
3142         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3143         tx_buf_mapped = tx_buf;
3144         map = tx_buf->map;
3145
3146         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3147         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3148         if (maxsegs > IGB_MAX_SCATTER)
3149                 maxsegs = IGB_MAX_SCATTER;
3150
3151         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3152             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3153         if (error) {
3154                 if (error == ENOBUFS)
3155                         txr->sc->mbuf_defrag_failed++;
3156                 else
3157                         txr->sc->no_tx_dma_setup++;
3158
3159                 m_freem(*m_headp);
3160                 *m_headp = NULL;
3161                 return error;
3162         }
3163         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3164
3165         m_head = *m_headp;
3166
3167 #if 0
3168         /*
3169          * Set up the context descriptor:
3170          * used when any hardware offload is done.
3171          * This includes CSUM, VLAN, and TSO. It
3172          * will use the first descriptor.
3173          */
3174         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3175                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3176                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3177                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3178                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3179                 } else
3180                         return (ENXIO);
3181         } else if (igb_tx_ctx_setup(txr, m_head))
3182                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3183 #else
3184         if (igb_txctx(txr, m_head)) {
3185                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3186                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3187                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3188                 txr->tx_nsegs++;
3189         }
3190 #endif
3191
3192         txr->tx_nsegs += nsegs;
3193         if (txr->tx_nsegs >= txr->intr_nsegs) {
3194                 /*
3195                  * Report Status (RS) is turned on every intr_nsegs
3196                  * descriptors (roughly).
3197                  */
3198                 txr->tx_nsegs = 0;
3199                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3200         }
3201
3202         /* Calculate payload length */
3203         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3204             << E1000_ADVTXD_PAYLEN_SHIFT);
3205
3206         /* 82575 needs the queue index added */
3207         if (txr->sc->hw.mac.type == e1000_82575)
3208                 olinfo_status |= txr->me << 4;
3209
3210         /* Set up our transmit descriptors */
3211         i = txr->next_avail_desc;
3212         for (j = 0; j < nsegs; j++) {
3213                 bus_size_t seg_len;
3214                 bus_addr_t seg_addr;
3215
3216                 tx_buf = &txr->tx_buf[i];
3217                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3218                 seg_addr = segs[j].ds_addr;
3219                 seg_len = segs[j].ds_len;
3220
3221                 txd->read.buffer_addr = htole64(seg_addr);
3222                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3223                 txd->read.olinfo_status = htole32(olinfo_status);
3224                 last = i;
3225                 if (++i == txr->num_tx_desc)
3226                         i = 0;
3227                 tx_buf->m_head = NULL;
3228         }
3229
3230         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3231         txr->next_avail_desc = i;
3232         txr->tx_avail -= nsegs;
3233
3234         tx_buf->m_head = m_head;
3235         tx_buf_mapped->map = tx_buf->map;
3236         tx_buf->map = map;
3237
3238         /*
3239          * Last Descriptor of Packet needs End Of Packet (EOP)
3240          */
3241         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3242
3243         /*
3244          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3245          * that this frame is available to transmit.
3246          */
3247         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3248         ++txr->tx_packets;
3249
3250         return 0;
3251 }
3252
3253 static void
3254 igb_start(struct ifnet *ifp)
3255 {
3256         struct igb_softc *sc = ifp->if_softc;
3257         struct igb_tx_ring *txr = &sc->tx_rings[0];
3258         struct mbuf *m_head;
3259
3260         ASSERT_SERIALIZED(&txr->tx_serialize);
3261
3262         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3263                 return;
3264
3265         if (!sc->link_active) {
3266                 ifq_purge(&ifp->if_snd);
3267                 return;
3268         }
3269
3270         if (!IGB_IS_NOT_OACTIVE(txr))
3271                 igb_txeof(txr);
3272
3273         while (!ifq_is_empty(&ifp->if_snd)) {
3274                 if (IGB_IS_OACTIVE(txr)) {
3275                         ifp->if_flags |= IFF_OACTIVE;
3276                         /* Set watchdog on */
3277                         ifp->if_timer = 5;
3278                         break;
3279                 }
3280
3281                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3282                 if (m_head == NULL)
3283                         break;
3284
3285                 if (igb_encap(txr, &m_head)) {
3286                         ifp->if_oerrors++;
3287                         continue;
3288                 }
3289
3290                 /* Send a copy of the frame to the BPF listener */
3291                 ETHER_BPF_MTAP(ifp, m_head);
3292         }
3293 }
3294
3295 static void
3296 igb_watchdog(struct ifnet *ifp)
3297 {
3298         struct igb_softc *sc = ifp->if_softc;
3299         struct igb_tx_ring *txr = &sc->tx_rings[0];
3300
3301         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3302
3303         /*
3304          * If flow control has paused us since last checking
3305          * it invalidates the watchdog timing, so dont run it.
3306          */
3307         if (sc->pause_frames) {
3308                 sc->pause_frames = 0;
3309                 ifp->if_timer = 5;
3310                 return;
3311         }
3312
3313         if_printf(ifp, "Watchdog timeout -- resetting\n");
3314         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3315             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3316             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3317         if_printf(ifp, "TX(%d) desc avail = %d, "
3318             "Next TX to Clean = %d\n",
3319             txr->me, txr->tx_avail, txr->next_to_clean);
3320
3321         ifp->if_oerrors++;
3322         sc->watchdog_events++;
3323
3324         igb_init(sc);
3325         if (!ifq_is_empty(&ifp->if_snd))
3326                 if_devstart(ifp);
3327 }
3328
3329 static void
3330 igb_set_eitr(struct igb_softc *sc)
3331 {
3332         uint32_t itr = 0;
3333
3334         if (sc->intr_rate > 0) {
3335                 if (sc->hw.mac.type == e1000_82575) {
3336                         itr = 1000000000 / 256 / sc->intr_rate;
3337                         /*
3338                          * NOTE:
3339                          * Document is wrong on the 2 bits left shift
3340                          */
3341                 } else {
3342                         itr = 1000000 / sc->intr_rate;
3343                         itr <<= 2;
3344                 }
3345                 itr &= 0x7FFC;
3346         }
3347         if (sc->hw.mac.type == e1000_82575)
3348                 itr |= itr << 16;
3349         else
3350                 itr |= E1000_EITR_CNT_IGNR;
3351         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3352 }
3353
3354 static int
3355 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3356 {
3357         struct igb_softc *sc = (void *)arg1;
3358         struct ifnet *ifp = &sc->arpcom.ac_if;
3359         int error, intr_rate;
3360
3361         intr_rate = sc->intr_rate;
3362         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3363         if (error || req->newptr == NULL)
3364                 return error;
3365         if (intr_rate < 0)
3366                 return EINVAL;
3367
3368         ifnet_serialize_all(ifp);
3369
3370         sc->intr_rate = intr_rate;
3371         if (ifp->if_flags & IFF_RUNNING)
3372                 igb_set_eitr(sc);
3373
3374         ifnet_deserialize_all(ifp);
3375
3376         if (bootverbose)
3377                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3378         return 0;
3379 }
3380
3381 static int
3382 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3383 {
3384         struct igb_softc *sc = (void *)arg1;
3385         struct ifnet *ifp = &sc->arpcom.ac_if;
3386         struct igb_tx_ring *txr = &sc->tx_rings[0];
3387         int error, nsegs;
3388
3389         nsegs = txr->intr_nsegs;
3390         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3391         if (error || req->newptr == NULL)
3392                 return error;
3393         if (nsegs <= 0)
3394                 return EINVAL;
3395
3396         ifnet_serialize_all(ifp);
3397
3398         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3399             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3400                 error = EINVAL;
3401         } else {
3402                 error = 0;
3403                 txr->intr_nsegs = nsegs;
3404         }
3405
3406         ifnet_deserialize_all(ifp);
3407
3408         return error;
3409 }
3410
3411 static void
3412 igb_init_intr(struct igb_softc *sc)
3413 {
3414         igb_set_intr_mask(sc);
3415         if (sc->flags & IGB_FLAG_SHARED_INTR)
3416                 igb_set_eitr(sc);
3417         else
3418                 igb_init_unshared_intr(sc);
3419 }
3420
3421 static void
3422 igb_init_unshared_intr(struct igb_softc *sc)
3423 {
3424         struct e1000_hw *hw = &sc->hw;
3425         const struct igb_rx_ring *rxr;
3426         const struct igb_tx_ring *txr;
3427         uint32_t ivar, index;
3428         int i;
3429
3430         /*
3431          * Enable extended mode
3432          */
3433         if (sc->hw.mac.type != e1000_82575) {
3434                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3435         } else {
3436                 uint32_t tmp;
3437
3438                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3439                 tmp |= E1000_CTRL_EXT_IRCA;
3440                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3441         }
3442
3443         /*
3444          * Map TX/RX interrupts to EICR
3445          */
3446         switch (sc->hw.mac.type) {
3447         case e1000_82580:
3448         case e1000_i350:
3449         case e1000_vfadapt:
3450         case e1000_vfadapt_i350:
3451                 /* RX entries */
3452                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3453                         rxr = &sc->rx_rings[i];
3454
3455                         index = i >> 1;
3456                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3457
3458                         if (i & 1) {
3459                                 ivar &= 0xff00ffff;
3460                                 ivar |=
3461                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3462                         } else {
3463                                 ivar &= 0xffffff00;
3464                                 ivar |=
3465                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3466                         }
3467                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3468                 }
3469                 /* TX entries */
3470                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3471                         txr = &sc->tx_rings[i];
3472
3473                         index = i >> 1;
3474                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3475
3476                         if (i & 1) {
3477                                 ivar &= 0x00ffffff;
3478                                 ivar |=
3479                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3480                         } else {
3481                                 ivar &= 0xffff00ff;
3482                                 ivar |=
3483                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3484                         }
3485                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3486                 }
3487                 /* Clear unused IVAR_MISC */
3488                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3489                 break;
3490
3491         case e1000_82576:
3492                 /* RX entries */
3493                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3494                         rxr = &sc->rx_rings[i];
3495
3496                         index = i & 0x7; /* Each IVAR has two entries */
3497                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3498
3499                         if (i < 8) {
3500                                 ivar &= 0xffffff00;
3501                                 ivar |=
3502                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3503                         } else {
3504                                 ivar &= 0xff00ffff;
3505                                 ivar |=
3506                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3507                         }
3508                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3509                 }
3510                 /* TX entries */
3511                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3512                         txr = &sc->tx_rings[i];
3513
3514                         index = i & 0x7; /* Each IVAR has two entries */
3515                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3516
3517                         if (i < 8) {
3518                                 ivar &= 0xffff00ff;
3519                                 ivar |=
3520                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3521                         } else {
3522                                 ivar &= 0x00ffffff;
3523                                 ivar |=
3524                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3525                         }
3526                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3527                 }
3528                 /* Clear unused IVAR_MISC */
3529                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3530                 break;
3531
3532         case e1000_82575:
3533                 /*
3534                  * Enable necessary interrupt bits.
3535                  *
3536                  * The name of the register is confusing; in addition to
3537                  * configuring the first vector of MSI-X, it also configures
3538                  * which bits of EICR could be set by the hardware even when
3539                  * MSI or line interrupt is used; it thus controls interrupt
3540                  * generation.  It MUST be configured explicitly; the default
3541                  * value mentioned in the datasheet is wrong: RX queue0 and
3542                  * TX queue0 are NOT enabled by default.
3543                  */
3544                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3545                 break;
3546
3547         default:
3548                 break;
3549         }
3550
3551         /*
3552          * Configure interrupt moderation
3553          */
3554         igb_set_eitr(sc);
3555 }
3556
3557 static int
3558 igb_setup_intr(struct igb_softc *sc)
3559 {
3560         struct ifnet *ifp = &sc->arpcom.ac_if;
3561         int error, i, intr_bit, intr_bitmax;
3562
3563         /*
3564          * Setup interrupt mask
3565          */
3566         switch (sc->hw.mac.type) {
3567         case e1000_82575:
3568                 intr_bitmax = IGB_MAX_TXRXINT_82575;
3569                 break;
3570         case e1000_82580:
3571                 intr_bitmax = IGB_MAX_TXRXINT_82580;
3572                 break;
3573         case e1000_i350:
3574                 intr_bitmax = IGB_MAX_TXRXINT_I350;
3575                 break;
3576         case e1000_82576:
3577                 intr_bitmax = IGB_MAX_TXRXINT_82576;
3578                 break;
3579         default:
3580                 intr_bitmax = IGB_MIN_TXRXINT;
3581                 break;
3582         }
3583         intr_bit = 0;
3584         for (i = 0; i < sc->tx_ring_cnt; ++i)
3585                 igb_setup_tx_intr(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3586         for (i = 0; i < sc->rx_ring_cnt; ++i)
3587                 igb_setup_rx_intr(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3588
3589         igb_set_intr_mask(sc);
3590
3591         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3592                 int unshared;
3593
3594                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3595                 if (!unshared) {
3596                         sc->flags |= IGB_FLAG_SHARED_INTR;
3597                         if (bootverbose)
3598                                 device_printf(sc->dev, "IRQ shared\n");
3599                 } else if (bootverbose) {
3600                         device_printf(sc->dev, "IRQ unshared\n");
3601                 }
3602         }
3603
3604         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3605             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3606             sc, &sc->intr_tag, &sc->main_serialize);
3607         if (error) {
3608                 device_printf(sc->dev, "Failed to register interrupt handler");
3609                 return error;
3610         }
3611
3612         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3613         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3614
3615         return 0;
3616 }
3617
3618 static void
3619 igb_setup_tx_intr(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3620 {
3621         if (txr->sc->hw.mac.type == e1000_82575) {
3622                 txr->tx_intr_bit = 0;   /* unused */
3623                 switch (txr->me) {
3624                 case 0:
3625                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3626                         break;
3627                 case 1:
3628                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3629                         break;
3630                 case 2:
3631                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3632                         break;
3633                 case 3:
3634                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3635                         break;
3636                 default:
3637                         panic("unsupported # of TX ring, %d\n", txr->me);
3638                 }
3639         } else {
3640                 int intr_bit = *intr_bit0;
3641
3642                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3643                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3644
3645                 *intr_bit0 = intr_bit + 1;
3646         }
3647 }
3648
3649 static void
3650 igb_setup_rx_intr(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3651 {
3652         if (rxr->sc->hw.mac.type == e1000_82575) {
3653                 rxr->rx_intr_bit = 0;   /* unused */
3654                 switch (rxr->me) {
3655                 case 0:
3656                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3657                         break;
3658                 case 1:
3659                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3660                         break;
3661                 case 2:
3662                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3663                         break;
3664                 case 3:
3665                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3666                         break;
3667                 default:
3668                         panic("unsupported # of RX ring, %d\n", rxr->me);
3669                 }
3670         } else {
3671                 int intr_bit = *intr_bit0;
3672
3673                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3674                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3675
3676                 *intr_bit0 = intr_bit + 1;
3677         }
3678 }
3679
3680 static void
3681 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3682 {
3683         struct igb_softc *sc = ifp->if_softc;
3684
3685         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3686             sc->tx_serialize, sc->rx_serialize, slz);
3687 }
3688
3689 static void
3690 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3691 {
3692         struct igb_softc *sc = ifp->if_softc;
3693
3694         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3695             sc->tx_serialize, sc->rx_serialize, slz);
3696 }
3697
3698 static int
3699 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3700 {
3701         struct igb_softc *sc = ifp->if_softc;
3702
3703         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3704             sc->tx_serialize, sc->rx_serialize, slz);
3705 }
3706
3707 #ifdef INVARIANTS
3708
3709 static void
3710 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3711     boolean_t serialized)
3712 {
3713         struct igb_softc *sc = ifp->if_softc;
3714
3715         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3716             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3717 }
3718
3719 #endif  /* INVARIANTS */
3720
3721 static void
3722 igb_set_intr_mask(struct igb_softc *sc)
3723 {
3724         int i;
3725
3726         sc->intr_mask = E1000_EICR_OTHER;
3727         for (i = 0; i < sc->rx_ring_inuse; ++i)
3728                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3729         for (i = 0; i < sc->tx_ring_cnt; ++i)
3730                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3731         if (bootverbose) {
3732                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3733                     sc->intr_mask);
3734         }
3735 }