2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/ig_hal/e1000_dragonfly.h>
112 #include <dev/netif/emx/if_emx.h>
117 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
119 if (sc->rss_debug >= lvl) \
120 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
122 #else /* !EMX_RSS_DEBUG */
123 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
124 #endif /* EMX_RSS_DEBUG */
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 EMX_DEVICE(PCH_LPT_I217_LM),
166 EMX_DEVICE(PCH_LPT_I217_V),
167 EMX_DEVICE(PCH_LPTLP_I218_LM),
168 EMX_DEVICE(PCH_LPTLP_I218_V),
169 EMX_DEVICE(PCH_I218_LM2),
170 EMX_DEVICE(PCH_I218_V2),
171 EMX_DEVICE(PCH_I218_LM3),
172 EMX_DEVICE(PCH_I218_V3),
174 /* required last entry */
178 static int emx_probe(device_t);
179 static int emx_attach(device_t);
180 static int emx_detach(device_t);
181 static int emx_shutdown(device_t);
182 static int emx_suspend(device_t);
183 static int emx_resume(device_t);
185 static void emx_init(void *);
186 static void emx_stop(struct emx_softc *);
187 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
188 static void emx_start(struct ifnet *, struct ifaltq_subque *);
190 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
191 static void emx_npoll_status(struct ifnet *);
192 static void emx_npoll_tx(struct ifnet *, void *, int);
193 static void emx_npoll_rx(struct ifnet *, void *, int);
195 static void emx_watchdog(struct ifaltq_subque *);
196 static void emx_media_status(struct ifnet *, struct ifmediareq *);
197 static int emx_media_change(struct ifnet *);
198 static void emx_timer(void *);
199 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
200 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
201 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
203 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
207 static void emx_intr(void *);
208 static void emx_intr_mask(void *);
209 static void emx_intr_body(struct emx_softc *, boolean_t);
210 static void emx_rxeof(struct emx_rxdata *, int);
211 static void emx_txeof(struct emx_txdata *);
212 static void emx_tx_collect(struct emx_txdata *);
213 static void emx_tx_purge(struct emx_softc *);
214 static void emx_enable_intr(struct emx_softc *);
215 static void emx_disable_intr(struct emx_softc *);
217 static int emx_dma_alloc(struct emx_softc *);
218 static void emx_dma_free(struct emx_softc *);
219 static void emx_init_tx_ring(struct emx_txdata *);
220 static int emx_init_rx_ring(struct emx_rxdata *);
221 static void emx_free_tx_ring(struct emx_txdata *);
222 static void emx_free_rx_ring(struct emx_rxdata *);
223 static int emx_create_tx_ring(struct emx_txdata *);
224 static int emx_create_rx_ring(struct emx_rxdata *);
225 static void emx_destroy_tx_ring(struct emx_txdata *, int);
226 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
227 static int emx_newbuf(struct emx_rxdata *, int, int);
228 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
229 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
230 uint32_t *, uint32_t *);
231 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
232 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
233 uint32_t *, uint32_t *);
234 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
236 static int emx_is_valid_eaddr(const uint8_t *);
237 static int emx_reset(struct emx_softc *);
238 static void emx_setup_ifp(struct emx_softc *);
239 static void emx_init_tx_unit(struct emx_softc *);
240 static void emx_init_rx_unit(struct emx_softc *);
241 static void emx_update_stats(struct emx_softc *);
242 static void emx_set_promisc(struct emx_softc *);
243 static void emx_disable_promisc(struct emx_softc *);
244 static void emx_set_multi(struct emx_softc *);
245 static void emx_update_link_status(struct emx_softc *);
246 static void emx_smartspeed(struct emx_softc *);
247 static void emx_set_itr(struct emx_softc *, uint32_t);
248 static void emx_disable_aspm(struct emx_softc *);
250 static void emx_print_debug_info(struct emx_softc *);
251 static void emx_print_nvm_info(struct emx_softc *);
252 static void emx_print_hw_stats(struct emx_softc *);
254 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
257 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
258 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
261 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
263 static void emx_add_sysctl(struct emx_softc *);
265 static void emx_serialize_skipmain(struct emx_softc *);
266 static void emx_deserialize_skipmain(struct emx_softc *);
268 /* Management and WOL Support */
269 static void emx_get_mgmt(struct emx_softc *);
270 static void emx_rel_mgmt(struct emx_softc *);
271 static void emx_get_hw_control(struct emx_softc *);
272 static void emx_rel_hw_control(struct emx_softc *);
273 static void emx_enable_wol(device_t);
275 static device_method_t emx_methods[] = {
276 /* Device interface */
277 DEVMETHOD(device_probe, emx_probe),
278 DEVMETHOD(device_attach, emx_attach),
279 DEVMETHOD(device_detach, emx_detach),
280 DEVMETHOD(device_shutdown, emx_shutdown),
281 DEVMETHOD(device_suspend, emx_suspend),
282 DEVMETHOD(device_resume, emx_resume),
286 static driver_t emx_driver = {
289 sizeof(struct emx_softc),
292 static devclass_t emx_devclass;
294 DECLARE_DUMMY_MODULE(if_emx);
295 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
296 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
301 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
302 static int emx_rxd = EMX_DEFAULT_RXD;
303 static int emx_txd = EMX_DEFAULT_TXD;
304 static int emx_smart_pwr_down = 0;
305 static int emx_rxr = 0;
306 static int emx_txr = 1;
308 /* Controls whether promiscuous also shows bad packets */
309 static int emx_debug_sbp = 0;
311 static int emx_82573_workaround = 1;
312 static int emx_msi_enable = 1;
314 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_RXPAUSE;
316 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
317 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
318 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
319 TUNABLE_INT("hw.emx.txd", &emx_txd);
320 TUNABLE_INT("hw.emx.txr", &emx_txr);
321 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
322 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
323 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
324 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
325 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl));
327 /* Global used in WOL setup with multiport cards */
328 static int emx_global_quad_port_a = 0;
330 /* Set this to one to display debug statistics */
331 static int emx_display_debug_stats = 0;
333 #if !defined(KTR_IF_EMX)
334 #define KTR_IF_EMX KTR_ALL
336 KTR_INFO_MASTER(if_emx);
337 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
338 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
339 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
340 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
341 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
342 #define logif(name) KTR_LOG(if_emx_ ## name)
345 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
347 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
348 /* DD bit must be cleared */
349 rxd->rxd_staterr = 0;
353 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
355 /* Ignore Checksum bit is set */
356 if (staterr & E1000_RXD_STAT_IXSM)
359 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
361 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
363 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
364 E1000_RXD_STAT_TCPCS) {
365 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
367 CSUM_FRAG_NOT_CHECKED;
368 mp->m_pkthdr.csum_data = htons(0xffff);
372 static __inline struct pktinfo *
373 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
374 uint32_t mrq, uint32_t hash, uint32_t staterr)
376 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
377 case EMX_RXDMRQ_IPV4_TCP:
378 pi->pi_netisr = NETISR_IP;
380 pi->pi_l3proto = IPPROTO_TCP;
383 case EMX_RXDMRQ_IPV6_TCP:
384 pi->pi_netisr = NETISR_IPV6;
386 pi->pi_l3proto = IPPROTO_TCP;
389 case EMX_RXDMRQ_IPV4:
390 if (staterr & E1000_RXD_STAT_IXSM)
394 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
395 E1000_RXD_STAT_TCPCS) {
396 pi->pi_netisr = NETISR_IP;
398 pi->pi_l3proto = IPPROTO_UDP;
406 m->m_flags |= M_HASH;
407 m->m_pkthdr.hash = toeplitz_hash(hash);
412 emx_probe(device_t dev)
414 const struct emx_device *d;
417 vid = pci_get_vendor(dev);
418 did = pci_get_device(dev);
420 for (d = emx_devices; d->desc != NULL; ++d) {
421 if (vid == d->vid && did == d->did) {
422 device_set_desc(dev, d->desc);
423 device_set_async_attach(dev, TRUE);
431 emx_attach(device_t dev)
433 struct emx_softc *sc = device_get_softc(dev);
434 int error = 0, i, throttle, msi_enable, tx_ring_max;
436 uint16_t eeprom_data, device_id, apme_mask;
437 driver_intr_t *intr_func;
438 char flowctrl[IFM_ETH_FC_STRLEN];
440 int offset, offset_def;
446 for (i = 0; i < EMX_NRX_RING; ++i) {
447 sc->rx_data[i].sc = sc;
448 sc->rx_data[i].idx = i;
454 for (i = 0; i < EMX_NTX_RING; ++i) {
455 sc->tx_data[i].sc = sc;
456 sc->tx_data[i].idx = i;
460 * Initialize serializers
462 lwkt_serialize_init(&sc->main_serialize);
463 for (i = 0; i < EMX_NTX_RING; ++i)
464 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
465 for (i = 0; i < EMX_NRX_RING; ++i)
466 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
469 * Initialize serializer array
473 KKASSERT(i < EMX_NSERIALIZE);
474 sc->serializes[i++] = &sc->main_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
478 KKASSERT(i < EMX_NSERIALIZE);
479 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
481 KKASSERT(i < EMX_NSERIALIZE);
482 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
483 KKASSERT(i < EMX_NSERIALIZE);
484 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
486 KKASSERT(i == EMX_NSERIALIZE);
488 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
489 emx_media_change, emx_media_status);
490 callout_init_mp(&sc->timer);
492 sc->dev = sc->osdep.dev = dev;
495 * Determine hardware and mac type
497 sc->hw.vendor_id = pci_get_vendor(dev);
498 sc->hw.device_id = pci_get_device(dev);
499 sc->hw.revision_id = pci_get_revid(dev);
500 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
501 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
503 if (e1000_set_mac_type(&sc->hw))
506 /* Enable bus mastering */
507 pci_enable_busmaster(dev);
512 sc->memory_rid = EMX_BAR_MEM;
513 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
514 &sc->memory_rid, RF_ACTIVE);
515 if (sc->memory == NULL) {
516 device_printf(dev, "Unable to allocate bus resource: memory\n");
520 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
521 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
523 /* XXX This is quite goofy, it is not actually used */
524 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
527 * Don't enable MSI-X on 82574, see:
528 * 82574 specification update errata #15
530 * Don't enable MSI on 82571/82572, see:
531 * 82571/82572 specification update errata #63
533 msi_enable = emx_msi_enable;
535 (sc->hw.mac.type == e1000_82571 ||
536 sc->hw.mac.type == e1000_82572))
542 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
543 &sc->intr_rid, &intr_flags);
545 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
548 unshared = device_getenv_int(dev, "irq.unshared", 0);
550 sc->flags |= EMX_FLAG_SHARED_INTR;
552 device_printf(dev, "IRQ shared\n");
554 intr_flags &= ~RF_SHAREABLE;
556 device_printf(dev, "IRQ unshared\n");
560 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
562 if (sc->intr_res == NULL) {
563 device_printf(dev, "Unable to allocate bus resource: "
569 /* Save PCI command register for Shared Code */
570 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
571 sc->hw.back = &sc->osdep;
574 * For I217/I218, we need to map the flash memory and this
575 * must happen after the MAC is identified.
577 if (sc->hw.mac.type == e1000_pch_lpt) {
578 sc->flash_rid = EMX_BAR_FLASH;
580 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
581 &sc->flash_rid, RF_ACTIVE);
582 if (sc->flash == NULL) {
583 device_printf(dev, "Mapping of Flash failed\n");
587 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
588 sc->osdep.flash_bus_space_handle =
589 rman_get_bushandle(sc->flash);
592 * This is used in the shared code
593 * XXX this goof is actually not used.
595 sc->hw.flash_address = (uint8_t *)sc->flash;
598 /* Do Shared Code initialization */
599 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
600 device_printf(dev, "Setup of Shared code failed\n");
604 e1000_get_bus_info(&sc->hw);
606 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
607 sc->hw.phy.autoneg_wait_to_complete = FALSE;
608 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
611 * Interrupt throttle rate
613 throttle = device_getenv_int(dev, "int_throttle_ceil",
614 emx_int_throttle_ceil);
616 sc->int_throttle_ceil = 0;
619 throttle = EMX_DEFAULT_ITR;
621 /* Recalculate the tunable value to get the exact frequency. */
622 throttle = 1000000000 / 256 / throttle;
624 /* Upper 16bits of ITR is reserved and should be zero */
625 if (throttle & 0xffff0000)
626 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
628 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
631 e1000_init_script_state_82541(&sc->hw, TRUE);
632 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
635 if (sc->hw.phy.media_type == e1000_media_type_copper) {
636 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
637 sc->hw.phy.disable_polarity_correction = FALSE;
638 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
641 /* Set the frame limits assuming standard ethernet sized frames. */
642 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
644 /* This controls when hardware reports transmit completion status. */
645 sc->hw.mac.report_tx_early = 1;
647 /* Calculate # of RX rings */
648 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
649 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
652 * Calculate # of TX rings
655 * I217/I218 claims to have 2 TX queues
658 * Don't enable multiple TX queues on 82574; it always gives
659 * watchdog timeout on TX queue0, when multiple TCP streams are
660 * received. It was originally suspected that the hardware TX
661 * checksum offloading caused this watchdog timeout, since only
662 * TCP ACKs are sent during TCP receiving tests. However, even
663 * if the hardware TX checksum offloading is disable, TX queue0
664 * still will give watchdog.
667 if (sc->hw.mac.type == e1000_82571 ||
668 sc->hw.mac.type == e1000_82572 ||
669 sc->hw.mac.type == e1000_80003es2lan ||
670 sc->hw.mac.type == e1000_pch_lpt ||
671 sc->hw.mac.type == e1000_82574)
672 tx_ring_max = EMX_NTX_RING;
673 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
674 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
676 /* Allocate RX/TX rings' busdma(9) stuffs */
677 error = emx_dma_alloc(sc);
681 /* Allocate multicast array memory. */
682 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
685 /* Indicate SOL/IDER usage */
686 if (e1000_check_reset_block(&sc->hw)) {
688 "PHY reset is blocked due to SOL/IDER session.\n");
691 /* Disable EEE on I217/I218 */
692 sc->hw.dev_spec.ich8lan.eee_disable = 1;
695 * Start from a known state, this is important in reading the
696 * nvm and mac from that.
698 e1000_reset_hw(&sc->hw);
700 /* Make sure we have a good EEPROM before we read from it */
701 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
703 * Some PCI-E parts fail the first check due to
704 * the link being in sleep state, call it again,
705 * if it fails a second time its a real issue.
707 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
709 "The EEPROM Checksum Is Not Valid\n");
715 /* Copy the permanent MAC address out of the EEPROM */
716 if (e1000_read_mac_addr(&sc->hw) < 0) {
717 device_printf(dev, "EEPROM read error while reading MAC"
722 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
723 device_printf(dev, "Invalid MAC address\n");
728 /* Disable ULP support */
729 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
731 /* Determine if we have to control management hardware */
732 if (e1000_enable_mng_pass_thru(&sc->hw))
733 sc->flags |= EMX_FLAG_HAS_MGMT;
738 apme_mask = EMX_EEPROM_APME;
740 switch (sc->hw.mac.type) {
742 sc->flags |= EMX_FLAG_HAS_AMT;
747 case e1000_80003es2lan:
748 if (sc->hw.bus.func == 1) {
749 e1000_read_nvm(&sc->hw,
750 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
752 e1000_read_nvm(&sc->hw,
753 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
758 e1000_read_nvm(&sc->hw,
759 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
762 if (eeprom_data & apme_mask)
763 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
766 * We have the eeprom settings, now apply the special cases
767 * where the eeprom may be wrong or the board won't support
768 * wake on lan on a particular port
770 device_id = pci_get_device(dev);
772 case E1000_DEV_ID_82571EB_FIBER:
774 * Wake events only supported on port A for dual fiber
775 * regardless of eeprom setting
777 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
782 case E1000_DEV_ID_82571EB_QUAD_COPPER:
783 case E1000_DEV_ID_82571EB_QUAD_FIBER:
784 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
785 /* if quad port sc, disable WoL on all but port A */
786 if (emx_global_quad_port_a != 0)
788 /* Reset for multiple quad port adapters */
789 if (++emx_global_quad_port_a == 4)
790 emx_global_quad_port_a = 0;
794 /* XXX disable wol */
799 * NPOLLING RX CPU offset
801 if (sc->rx_ring_cnt == ncpus2) {
804 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
805 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
806 if (offset >= ncpus2 ||
807 offset % sc->rx_ring_cnt != 0) {
808 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
813 sc->rx_npoll_off = offset;
816 * NPOLLING TX CPU offset
818 if (sc->tx_ring_cnt == ncpus2) {
821 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
822 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
823 if (offset >= ncpus2 ||
824 offset % sc->tx_ring_cnt != 0) {
825 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
830 sc->tx_npoll_off = offset;
832 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
834 /* Setup flow control. */
835 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
837 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
839 /* Setup OS specific network interface */
842 /* Add sysctl tree, must after em_setup_ifp() */
845 /* Reset the hardware */
846 error = emx_reset(sc);
849 * Some 82573 parts fail the first reset, call it again,
850 * if it fails a second time its a real issue.
852 error = emx_reset(sc);
854 device_printf(dev, "Unable to reset the hardware\n");
855 ether_ifdetach(&sc->arpcom.ac_if);
860 /* Initialize statistics */
861 emx_update_stats(sc);
863 sc->hw.mac.get_link_status = 1;
864 emx_update_link_status(sc);
866 /* Non-AMT based hardware can now take control from firmware */
867 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
869 emx_get_hw_control(sc);
872 * Missing Interrupt Following ICR read:
874 * 82571/82572 specification update errata #76
875 * 82573 specification update errata #31
876 * 82574 specification update errata #12
878 intr_func = emx_intr;
879 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
880 (sc->hw.mac.type == e1000_82571 ||
881 sc->hw.mac.type == e1000_82572 ||
882 sc->hw.mac.type == e1000_82573 ||
883 sc->hw.mac.type == e1000_82574))
884 intr_func = emx_intr_mask;
886 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
887 &sc->intr_tag, &sc->main_serialize);
889 device_printf(dev, "Failed to register interrupt handler");
890 ether_ifdetach(&sc->arpcom.ac_if);
900 emx_detach(device_t dev)
902 struct emx_softc *sc = device_get_softc(dev);
904 if (device_is_attached(dev)) {
905 struct ifnet *ifp = &sc->arpcom.ac_if;
907 ifnet_serialize_all(ifp);
911 e1000_phy_hw_reset(&sc->hw);
914 emx_rel_hw_control(sc);
917 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
918 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
922 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
924 ifnet_deserialize_all(ifp);
927 } else if (sc->memory != NULL) {
928 emx_rel_hw_control(sc);
931 ifmedia_removeall(&sc->media);
932 bus_generic_detach(dev);
934 if (sc->intr_res != NULL) {
935 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
939 if (sc->intr_type == PCI_INTR_TYPE_MSI)
940 pci_release_msi(dev);
942 if (sc->memory != NULL) {
943 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
947 if (sc->flash != NULL) {
948 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
955 kfree(sc->mta, M_DEVBUF);
961 emx_shutdown(device_t dev)
963 return emx_suspend(dev);
967 emx_suspend(device_t dev)
969 struct emx_softc *sc = device_get_softc(dev);
970 struct ifnet *ifp = &sc->arpcom.ac_if;
972 ifnet_serialize_all(ifp);
977 emx_rel_hw_control(sc);
980 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
981 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
985 ifnet_deserialize_all(ifp);
987 return bus_generic_suspend(dev);
991 emx_resume(device_t dev)
993 struct emx_softc *sc = device_get_softc(dev);
994 struct ifnet *ifp = &sc->arpcom.ac_if;
997 ifnet_serialize_all(ifp);
1001 for (i = 0; i < sc->tx_ring_inuse; ++i)
1002 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1004 ifnet_deserialize_all(ifp);
1006 return bus_generic_resume(dev);
1010 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1012 struct emx_softc *sc = ifp->if_softc;
1013 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1014 struct mbuf *m_head;
1015 int idx = -1, nsegs = 0;
1017 KKASSERT(tdata->ifsq == ifsq);
1018 ASSERT_SERIALIZED(&tdata->tx_serialize);
1020 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1023 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1028 while (!ifsq_is_empty(ifsq)) {
1029 /* Now do we at least have a minimal? */
1030 if (EMX_IS_OACTIVE(tdata)) {
1031 emx_tx_collect(tdata);
1032 if (EMX_IS_OACTIVE(tdata)) {
1033 ifsq_set_oactive(ifsq);
1039 m_head = ifsq_dequeue(ifsq);
1043 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1044 IFNET_STAT_INC(ifp, oerrors, 1);
1045 emx_tx_collect(tdata);
1050 * TX interrupt are aggressively aggregated, so increasing
1051 * opackets at TX interrupt time will make the opackets
1052 * statistics vastly inaccurate; we do the opackets increment
1055 IFNET_STAT_INC(ifp, opackets, 1);
1057 if (nsegs >= tdata->tx_wreg_nsegs) {
1058 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1063 /* Send a copy of the frame to the BPF listener */
1064 ETHER_BPF_MTAP(ifp, m_head);
1066 /* Set timeout in case hardware has problems transmitting. */
1067 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1070 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1074 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1076 struct emx_softc *sc = ifp->if_softc;
1077 struct ifreq *ifr = (struct ifreq *)data;
1078 uint16_t eeprom_data = 0;
1079 int max_frame_size, mask, reinit;
1082 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1086 switch (sc->hw.mac.type) {
1089 * 82573 only supports jumbo frames
1090 * if ASPM is disabled.
1092 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1094 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1095 max_frame_size = ETHER_MAX_LEN;
1100 /* Limit Jumbo Frame size */
1105 case e1000_80003es2lan:
1106 max_frame_size = 9234;
1110 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1113 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1119 ifp->if_mtu = ifr->ifr_mtu;
1120 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1123 if (ifp->if_flags & IFF_RUNNING)
1128 if (ifp->if_flags & IFF_UP) {
1129 if ((ifp->if_flags & IFF_RUNNING)) {
1130 if ((ifp->if_flags ^ sc->if_flags) &
1131 (IFF_PROMISC | IFF_ALLMULTI)) {
1132 emx_disable_promisc(sc);
1133 emx_set_promisc(sc);
1138 } else if (ifp->if_flags & IFF_RUNNING) {
1141 sc->if_flags = ifp->if_flags;
1146 if (ifp->if_flags & IFF_RUNNING) {
1147 emx_disable_intr(sc);
1149 #ifdef IFPOLL_ENABLE
1150 if (!(ifp->if_flags & IFF_NPOLLING))
1152 emx_enable_intr(sc);
1157 /* Check SOL/IDER usage */
1158 if (e1000_check_reset_block(&sc->hw)) {
1159 device_printf(sc->dev, "Media change is"
1160 " blocked due to SOL/IDER session.\n");
1166 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1171 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1172 if (mask & IFCAP_RXCSUM) {
1173 ifp->if_capenable ^= IFCAP_RXCSUM;
1176 if (mask & IFCAP_VLAN_HWTAGGING) {
1177 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1180 if (mask & IFCAP_TXCSUM) {
1181 ifp->if_capenable ^= IFCAP_TXCSUM;
1182 if (ifp->if_capenable & IFCAP_TXCSUM)
1183 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1185 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1187 if (mask & IFCAP_TSO) {
1188 ifp->if_capenable ^= IFCAP_TSO;
1189 if (ifp->if_capenable & IFCAP_TSO)
1190 ifp->if_hwassist |= CSUM_TSO;
1192 ifp->if_hwassist &= ~CSUM_TSO;
1194 if (mask & IFCAP_RSS)
1195 ifp->if_capenable ^= IFCAP_RSS;
1196 if (reinit && (ifp->if_flags & IFF_RUNNING))
1201 error = ether_ioctl(ifp, command, data);
1208 emx_watchdog(struct ifaltq_subque *ifsq)
1210 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1211 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1212 struct emx_softc *sc = ifp->if_softc;
1215 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1218 * The timer is set to 5 every time start queues a packet.
1219 * Then txeof keeps resetting it as long as it cleans at
1220 * least one descriptor.
1221 * Finally, anytime all descriptors are clean the timer is
1225 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1226 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1228 * If we reach here, all TX jobs are completed and
1229 * the TX engine should have been idled for some time.
1230 * We don't need to call ifsq_devstart_sched() here.
1232 ifsq_clr_oactive(ifsq);
1233 tdata->tx_watchdog.wd_timer = 0;
1238 * If we are in this routine because of pause frames, then
1239 * don't reset the hardware.
1241 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1242 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1246 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1248 IFNET_STAT_INC(ifp, oerrors, 1);
1251 for (i = 0; i < sc->tx_ring_inuse; ++i)
1252 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1258 struct emx_softc *sc = xsc;
1259 struct ifnet *ifp = &sc->arpcom.ac_if;
1260 device_t dev = sc->dev;
1264 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1268 /* Get the latest mac address, User can use a LAA */
1269 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1271 /* Put the address into the Receive Address Array */
1272 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1275 * With the 82571 sc, RAR[0] may be overwritten
1276 * when the other port is reset, we make a duplicate
1277 * in RAR[14] for that eventuality, this assures
1278 * the interface continues to function.
1280 if (sc->hw.mac.type == e1000_82571) {
1281 e1000_set_laa_state_82571(&sc->hw, TRUE);
1282 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1283 E1000_RAR_ENTRIES - 1);
1286 /* Initialize the hardware */
1287 if (emx_reset(sc)) {
1288 device_printf(dev, "Unable to reset the hardware\n");
1289 /* XXX emx_stop()? */
1292 emx_update_link_status(sc);
1294 /* Setup VLAN support, basic and offload if available */
1295 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1297 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1300 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1301 ctrl |= E1000_CTRL_VME;
1302 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1305 /* Configure for OS presence */
1309 #ifdef IFPOLL_ENABLE
1310 if (ifp->if_flags & IFF_NPOLLING)
1313 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1314 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1316 /* Prepare transmit descriptors and buffers */
1317 for (i = 0; i < sc->tx_ring_inuse; ++i)
1318 emx_init_tx_ring(&sc->tx_data[i]);
1319 emx_init_tx_unit(sc);
1321 /* Setup Multicast table */
1324 /* Prepare receive descriptors and buffers */
1325 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1326 if (emx_init_rx_ring(&sc->rx_data[i])) {
1328 "Could not setup receive structures\n");
1333 emx_init_rx_unit(sc);
1335 /* Don't lose promiscuous settings */
1336 emx_set_promisc(sc);
1338 ifp->if_flags |= IFF_RUNNING;
1339 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1340 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1341 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1344 callout_reset(&sc->timer, hz, emx_timer, sc);
1345 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1347 /* MSI/X configuration for 82574 */
1348 if (sc->hw.mac.type == e1000_82574) {
1351 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1352 tmp |= E1000_CTRL_EXT_PBA_CLR;
1353 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1356 * Set the IVAR - interrupt vector routing.
1357 * Each nibble represents a vector, high bit
1358 * is enable, other 3 bits are the MSIX table
1359 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1360 * Link (other) to 2, hence the magic number.
1362 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1366 * Only enable interrupts if we are not polling, make sure
1367 * they are off otherwise.
1370 emx_disable_intr(sc);
1372 emx_enable_intr(sc);
1374 /* AMT based hardware can now take control from firmware */
1375 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1376 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1377 emx_get_hw_control(sc);
1383 emx_intr_body(xsc, TRUE);
1387 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1389 struct ifnet *ifp = &sc->arpcom.ac_if;
1393 ASSERT_SERIALIZED(&sc->main_serialize);
1395 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1397 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1403 * XXX: some laptops trigger several spurious interrupts
1404 * on emx(4) when in the resume cycle. The ICR register
1405 * reports all-ones value in this case. Processing such
1406 * interrupts would lead to a freeze. I don't know why.
1408 if (reg_icr == 0xffffffff) {
1413 if (ifp->if_flags & IFF_RUNNING) {
1415 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1418 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1419 lwkt_serialize_enter(
1420 &sc->rx_data[i].rx_serialize);
1421 emx_rxeof(&sc->rx_data[i], -1);
1422 lwkt_serialize_exit(
1423 &sc->rx_data[i].rx_serialize);
1426 if (reg_icr & E1000_ICR_TXDW) {
1427 struct emx_txdata *tdata = &sc->tx_data[0];
1429 lwkt_serialize_enter(&tdata->tx_serialize);
1431 if (!ifsq_is_empty(tdata->ifsq))
1432 ifsq_devstart(tdata->ifsq);
1433 lwkt_serialize_exit(&tdata->tx_serialize);
1437 /* Link status change */
1438 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1439 emx_serialize_skipmain(sc);
1441 callout_stop(&sc->timer);
1442 sc->hw.mac.get_link_status = 1;
1443 emx_update_link_status(sc);
1445 /* Deal with TX cruft when link lost */
1448 callout_reset(&sc->timer, hz, emx_timer, sc);
1450 emx_deserialize_skipmain(sc);
1453 if (reg_icr & E1000_ICR_RXO)
1460 emx_intr_mask(void *xsc)
1462 struct emx_softc *sc = xsc;
1464 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1467 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1468 * so don't check it.
1470 emx_intr_body(sc, FALSE);
1471 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1475 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1477 struct emx_softc *sc = ifp->if_softc;
1479 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1481 emx_update_link_status(sc);
1483 ifmr->ifm_status = IFM_AVALID;
1484 ifmr->ifm_active = IFM_ETHER;
1486 if (!sc->link_active) {
1487 ifmr->ifm_active |= IFM_NONE;
1491 ifmr->ifm_status |= IFM_ACTIVE;
1492 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1493 ifmr->ifm_active |= IFM_ETH_FORCEPAUSE;
1495 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1496 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1497 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1499 switch (sc->link_speed) {
1501 ifmr->ifm_active |= IFM_10_T;
1504 ifmr->ifm_active |= IFM_100_TX;
1508 ifmr->ifm_active |= IFM_1000_T;
1511 if (sc->link_duplex == FULL_DUPLEX)
1512 ifmr->ifm_active |= IFM_FDX;
1514 ifmr->ifm_active |= IFM_HDX;
1516 if (ifmr->ifm_active & IFM_FDX)
1517 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1521 emx_media_change(struct ifnet *ifp)
1523 struct emx_softc *sc = ifp->if_softc;
1524 struct ifmedia *ifm = &sc->media;
1526 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1528 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1531 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1533 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1534 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1539 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1540 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1544 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1545 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1547 if (IFM_OPTIONS(ifm->ifm_media) &
1548 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1550 if_printf(ifp, "Flow control is not "
1551 "allowed for half-duplex\n");
1555 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1557 sc->hw.mac.autoneg = FALSE;
1558 sc->hw.phy.autoneg_advertised = 0;
1562 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1563 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1565 if (IFM_OPTIONS(ifm->ifm_media) &
1566 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1568 if_printf(ifp, "Flow control is not "
1569 "allowed for half-duplex\n");
1573 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1575 sc->hw.mac.autoneg = FALSE;
1576 sc->hw.phy.autoneg_advertised = 0;
1581 if_printf(ifp, "Unsupported media type %d\n",
1582 IFM_SUBTYPE(ifm->ifm_media));
1586 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1588 if (ifp->if_flags & IFF_RUNNING)
1595 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1596 int *segs_used, int *idx)
1598 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1600 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1601 struct e1000_tx_desc *ctxd = NULL;
1602 struct mbuf *m_head = *m_headp;
1603 uint32_t txd_upper, txd_lower, cmd = 0;
1604 int maxsegs, nsegs, i, j, first, last = 0, error;
1606 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1607 error = emx_tso_pullup(tdata, m_headp);
1613 txd_upper = txd_lower = 0;
1616 * Capture the first descriptor index, this descriptor
1617 * will have the index of the EOP which is the only one
1618 * that now gets a DONE bit writeback.
1620 first = tdata->next_avail_tx_desc;
1621 tx_buffer = &tdata->tx_buf[first];
1622 tx_buffer_mapped = tx_buffer;
1623 map = tx_buffer->map;
1625 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1626 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1627 if (maxsegs > EMX_MAX_SCATTER)
1628 maxsegs = EMX_MAX_SCATTER;
1630 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1631 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1637 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1640 tdata->tx_nsegs += nsegs;
1641 *segs_used += nsegs;
1643 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1644 /* TSO will consume one TX desc */
1645 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1646 tdata->tx_nsegs += i;
1648 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1649 /* TX csum offloading will consume one TX desc */
1650 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1651 tdata->tx_nsegs += i;
1655 /* Handle VLAN tag */
1656 if (m_head->m_flags & M_VLANTAG) {
1657 /* Set the vlan id. */
1658 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1659 /* Tell hardware to add tag */
1660 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1663 i = tdata->next_avail_tx_desc;
1665 /* Set up our transmit descriptors */
1666 for (j = 0; j < nsegs; j++) {
1667 tx_buffer = &tdata->tx_buf[i];
1668 ctxd = &tdata->tx_desc_base[i];
1670 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1671 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1672 txd_lower | segs[j].ds_len);
1673 ctxd->upper.data = htole32(txd_upper);
1676 if (++i == tdata->num_tx_desc)
1680 tdata->next_avail_tx_desc = i;
1682 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1683 tdata->num_tx_desc_avail -= nsegs;
1685 tx_buffer->m_head = m_head;
1686 tx_buffer_mapped->map = tx_buffer->map;
1687 tx_buffer->map = map;
1689 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1690 tdata->tx_nsegs = 0;
1693 * Report Status (RS) is turned on
1694 * every tx_intr_nsegs descriptors.
1696 cmd = E1000_TXD_CMD_RS;
1699 * Keep track of the descriptor, which will
1700 * be written back by hardware.
1702 tdata->tx_dd[tdata->tx_dd_tail] = last;
1703 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1704 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1708 * Last Descriptor of Packet needs End Of Packet (EOP)
1710 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1713 * Defer TDT updating, until enough descriptors are setup
1717 #ifdef EMX_TSS_DEBUG
1725 emx_set_promisc(struct emx_softc *sc)
1727 struct ifnet *ifp = &sc->arpcom.ac_if;
1730 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1732 if (ifp->if_flags & IFF_PROMISC) {
1733 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1734 /* Turn this on if you want to see bad packets */
1736 reg_rctl |= E1000_RCTL_SBP;
1737 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1738 } else if (ifp->if_flags & IFF_ALLMULTI) {
1739 reg_rctl |= E1000_RCTL_MPE;
1740 reg_rctl &= ~E1000_RCTL_UPE;
1741 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1746 emx_disable_promisc(struct emx_softc *sc)
1750 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1752 reg_rctl &= ~E1000_RCTL_UPE;
1753 reg_rctl &= ~E1000_RCTL_MPE;
1754 reg_rctl &= ~E1000_RCTL_SBP;
1755 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1759 emx_set_multi(struct emx_softc *sc)
1761 struct ifnet *ifp = &sc->arpcom.ac_if;
1762 struct ifmultiaddr *ifma;
1763 uint32_t reg_rctl = 0;
1768 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1770 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1771 if (ifma->ifma_addr->sa_family != AF_LINK)
1774 if (mcnt == EMX_MCAST_ADDR_MAX)
1777 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1778 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1782 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1783 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1784 reg_rctl |= E1000_RCTL_MPE;
1785 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1787 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1792 * This routine checks for link status and updates statistics.
1795 emx_timer(void *xsc)
1797 struct emx_softc *sc = xsc;
1798 struct ifnet *ifp = &sc->arpcom.ac_if;
1800 lwkt_serialize_enter(&sc->main_serialize);
1802 emx_update_link_status(sc);
1803 emx_update_stats(sc);
1805 /* Reset LAA into RAR[0] on 82571 */
1806 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1807 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1809 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1810 emx_print_hw_stats(sc);
1814 callout_reset(&sc->timer, hz, emx_timer, sc);
1816 lwkt_serialize_exit(&sc->main_serialize);
1820 emx_update_link_status(struct emx_softc *sc)
1822 struct e1000_hw *hw = &sc->hw;
1823 struct ifnet *ifp = &sc->arpcom.ac_if;
1824 device_t dev = sc->dev;
1825 uint32_t link_check = 0;
1827 /* Get the cached link value or read phy for real */
1828 switch (hw->phy.media_type) {
1829 case e1000_media_type_copper:
1830 if (hw->mac.get_link_status) {
1831 /* Do the work to read phy */
1832 e1000_check_for_link(hw);
1833 link_check = !hw->mac.get_link_status;
1834 if (link_check) /* ESB2 fix */
1835 e1000_cfg_on_link_up(hw);
1841 case e1000_media_type_fiber:
1842 e1000_check_for_link(hw);
1843 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1846 case e1000_media_type_internal_serdes:
1847 e1000_check_for_link(hw);
1848 link_check = sc->hw.mac.serdes_has_link;
1851 case e1000_media_type_unknown:
1856 /* Now check for a transition */
1857 if (link_check && sc->link_active == 0) {
1858 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1862 * Check if we should enable/disable SPEED_MODE bit on
1865 if (sc->link_speed != SPEED_1000 &&
1866 (hw->mac.type == e1000_82571 ||
1867 hw->mac.type == e1000_82572)) {
1870 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1871 tarc0 &= ~EMX_TARC_SPEED_MODE;
1872 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1875 char flowctrl[IFM_ETH_FC_STRLEN];
1877 e1000_fc2str(hw->fc.current_mode, flowctrl,
1879 device_printf(dev, "Link is up %d Mbps %s, "
1880 "Flow control: %s\n",
1882 (sc->link_duplex == FULL_DUPLEX) ?
1883 "Full Duplex" : "Half Duplex",
1886 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1887 e1000_force_flowctrl(hw, sc->ifm_flowctrl);
1888 sc->link_active = 1;
1890 ifp->if_baudrate = sc->link_speed * 1000000;
1891 ifp->if_link_state = LINK_STATE_UP;
1892 if_link_state_change(ifp);
1893 } else if (!link_check && sc->link_active == 1) {
1894 ifp->if_baudrate = sc->link_speed = 0;
1895 sc->link_duplex = 0;
1897 device_printf(dev, "Link is Down\n");
1898 sc->link_active = 0;
1899 ifp->if_link_state = LINK_STATE_DOWN;
1900 if_link_state_change(ifp);
1905 emx_stop(struct emx_softc *sc)
1907 struct ifnet *ifp = &sc->arpcom.ac_if;
1910 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1912 emx_disable_intr(sc);
1914 callout_stop(&sc->timer);
1916 ifp->if_flags &= ~IFF_RUNNING;
1917 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1918 struct emx_txdata *tdata = &sc->tx_data[i];
1920 ifsq_clr_oactive(tdata->ifsq);
1921 ifsq_watchdog_stop(&tdata->tx_watchdog);
1922 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1926 * Disable multiple receive queues.
1929 * We should disable multiple receive queues before
1930 * resetting the hardware.
1932 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1934 e1000_reset_hw(&sc->hw);
1935 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1937 for (i = 0; i < sc->tx_ring_cnt; ++i)
1938 emx_free_tx_ring(&sc->tx_data[i]);
1939 for (i = 0; i < sc->rx_ring_cnt; ++i)
1940 emx_free_rx_ring(&sc->rx_data[i]);
1944 emx_reset(struct emx_softc *sc)
1946 device_t dev = sc->dev;
1947 uint16_t rx_buffer_size;
1950 /* Set up smart power down as default off on newer adapters. */
1951 if (!emx_smart_pwr_down &&
1952 (sc->hw.mac.type == e1000_82571 ||
1953 sc->hw.mac.type == e1000_82572)) {
1954 uint16_t phy_tmp = 0;
1956 /* Speed up time to link by disabling smart power down. */
1957 e1000_read_phy_reg(&sc->hw,
1958 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1959 phy_tmp &= ~IGP02E1000_PM_SPD;
1960 e1000_write_phy_reg(&sc->hw,
1961 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1965 * Packet Buffer Allocation (PBA)
1966 * Writing PBA sets the receive portion of the buffer
1967 * the remainder is used for the transmit buffer.
1969 switch (sc->hw.mac.type) {
1970 /* Total Packet Buffer on these is 48K */
1973 case e1000_80003es2lan:
1974 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1977 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1978 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1982 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1986 pba = E1000_PBA_26K;
1990 /* Devices before 82547 had a Packet Buffer of 64K. */
1991 if (sc->hw.mac.max_frame_size > 8192)
1992 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1994 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1996 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1999 * These parameters control the automatic generation (Tx) and
2000 * response (Rx) to Ethernet PAUSE frames.
2001 * - High water mark should allow for at least two frames to be
2002 * received after sending an XOFF.
2003 * - Low water mark works best when it is very near the high water mark.
2004 * This allows the receiver to restart by sending XON when it has
2005 * drained a bit. Here we use an arbitary value of 1500 which will
2006 * restart after one full frame is pulled from the buffer. There
2007 * could be several smaller frames in the buffer and if so they will
2008 * not trigger the XON until their total number reduces the buffer
2010 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2012 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
2014 sc->hw.fc.high_water = rx_buffer_size -
2015 roundup2(sc->hw.mac.max_frame_size, 1024);
2016 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
2018 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
2019 sc->hw.fc.send_xon = TRUE;
2020 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
2023 * Device specific overrides/settings
2025 if (sc->hw.mac.type == e1000_pch_lpt) {
2026 sc->hw.fc.high_water = 0x5C20;
2027 sc->hw.fc.low_water = 0x5048;
2028 sc->hw.fc.pause_time = 0x0650;
2029 sc->hw.fc.refresh_time = 0x0400;
2030 /* Jumbos need adjusted PBA */
2031 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
2032 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
2034 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
2035 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2036 sc->hw.fc.pause_time = 0xFFFF;
2039 /* Issue a global reset */
2040 e1000_reset_hw(&sc->hw);
2041 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2042 emx_disable_aspm(sc);
2044 if (e1000_init_hw(&sc->hw) < 0) {
2045 device_printf(dev, "Hardware Initialization Failed\n");
2049 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2050 e1000_get_phy_info(&sc->hw);
2051 e1000_check_for_link(&sc->hw);
2057 emx_setup_ifp(struct emx_softc *sc)
2059 struct ifnet *ifp = &sc->arpcom.ac_if;
2062 if_initname(ifp, device_get_name(sc->dev),
2063 device_get_unit(sc->dev));
2065 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2066 ifp->if_init = emx_init;
2067 ifp->if_ioctl = emx_ioctl;
2068 ifp->if_start = emx_start;
2069 #ifdef IFPOLL_ENABLE
2070 ifp->if_npoll = emx_npoll;
2072 ifp->if_serialize = emx_serialize;
2073 ifp->if_deserialize = emx_deserialize;
2074 ifp->if_tryserialize = emx_tryserialize;
2076 ifp->if_serialize_assert = emx_serialize_assert;
2079 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2081 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2082 ifq_set_ready(&ifp->if_snd);
2083 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2085 ifp->if_mapsubq = ifq_mapsubq_mask;
2086 ifq_set_subq_mask(&ifp->if_snd, 0);
2088 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2090 ifp->if_capabilities = IFCAP_HWCSUM |
2091 IFCAP_VLAN_HWTAGGING |
2094 if (sc->rx_ring_cnt > 1)
2095 ifp->if_capabilities |= IFCAP_RSS;
2096 ifp->if_capenable = ifp->if_capabilities;
2097 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2100 * Tell the upper layer(s) we support long frames.
2102 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2104 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2105 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2106 struct emx_txdata *tdata = &sc->tx_data[i];
2108 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2109 ifsq_set_priv(ifsq, tdata);
2110 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2113 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2117 * Specify the media types supported by this sc and register
2118 * callbacks to update media and link information
2120 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2121 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2122 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2125 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2126 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2128 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2129 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2131 if (sc->hw.phy.type != e1000_phy_ife) {
2132 ifmedia_add(&sc->media,
2133 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2136 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2137 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
2141 * Workaround for SmartSpeed on 82541 and 82547 controllers
2144 emx_smartspeed(struct emx_softc *sc)
2148 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2149 sc->hw.mac.autoneg == 0 ||
2150 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2153 if (sc->smartspeed == 0) {
2155 * If Master/Slave config fault is asserted twice,
2156 * we assume back-to-back
2158 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2159 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2161 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2162 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2163 e1000_read_phy_reg(&sc->hw,
2164 PHY_1000T_CTRL, &phy_tmp);
2165 if (phy_tmp & CR_1000T_MS_ENABLE) {
2166 phy_tmp &= ~CR_1000T_MS_ENABLE;
2167 e1000_write_phy_reg(&sc->hw,
2168 PHY_1000T_CTRL, phy_tmp);
2170 if (sc->hw.mac.autoneg &&
2171 !e1000_phy_setup_autoneg(&sc->hw) &&
2172 !e1000_read_phy_reg(&sc->hw,
2173 PHY_CONTROL, &phy_tmp)) {
2174 phy_tmp |= MII_CR_AUTO_NEG_EN |
2175 MII_CR_RESTART_AUTO_NEG;
2176 e1000_write_phy_reg(&sc->hw,
2177 PHY_CONTROL, phy_tmp);
2182 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2183 /* If still no link, perhaps using 2/3 pair cable */
2184 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2185 phy_tmp |= CR_1000T_MS_ENABLE;
2186 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2187 if (sc->hw.mac.autoneg &&
2188 !e1000_phy_setup_autoneg(&sc->hw) &&
2189 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2190 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2191 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2195 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2196 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2201 emx_create_tx_ring(struct emx_txdata *tdata)
2203 device_t dev = tdata->sc->dev;
2204 struct emx_txbuf *tx_buffer;
2205 int error, i, tsize, ntxd;
2208 * Validate number of transmit descriptors. It must not exceed
2209 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2211 ntxd = device_getenv_int(dev, "txd", emx_txd);
2212 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2213 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2214 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2215 EMX_DEFAULT_TXD, ntxd);
2216 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2218 tdata->num_tx_desc = ntxd;
2222 * Allocate Transmit Descriptor ring
2224 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2226 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2227 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2228 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2229 &tdata->tx_desc_paddr);
2230 if (tdata->tx_desc_base == NULL) {
2231 device_printf(dev, "Unable to allocate tx_desc memory\n");
2235 tsize = __VM_CACHELINE_ALIGN(
2236 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2237 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2240 * Create DMA tags for tx buffers
2242 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2243 1, 0, /* alignment, bounds */
2244 BUS_SPACE_MAXADDR, /* lowaddr */
2245 BUS_SPACE_MAXADDR, /* highaddr */
2246 NULL, NULL, /* filter, filterarg */
2247 EMX_TSO_SIZE, /* maxsize */
2248 EMX_MAX_SCATTER, /* nsegments */
2249 EMX_MAX_SEGSIZE, /* maxsegsize */
2250 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2251 BUS_DMA_ONEBPAGE, /* flags */
2254 device_printf(dev, "Unable to allocate TX DMA tag\n");
2255 kfree(tdata->tx_buf, M_DEVBUF);
2256 tdata->tx_buf = NULL;
2261 * Create DMA maps for tx buffers
2263 for (i = 0; i < tdata->num_tx_desc; i++) {
2264 tx_buffer = &tdata->tx_buf[i];
2266 error = bus_dmamap_create(tdata->txtag,
2267 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2270 device_printf(dev, "Unable to create TX DMA map\n");
2271 emx_destroy_tx_ring(tdata, i);
2277 * Setup TX parameters
2279 tdata->spare_tx_desc = EMX_TX_SPARE;
2280 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2283 * Keep following relationship between spare_tx_desc, oact_tx_desc
2284 * and tx_intr_nsegs:
2285 * (spare_tx_desc + EMX_TX_RESERVED) <=
2286 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2288 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2289 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2290 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2291 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2292 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2294 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2295 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2296 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2299 * Pullup extra 4bytes into the first data segment for TSO, see:
2300 * 82571/82572 specification update errata #7
2302 * Same applies to I217 (and maybe I218).
2305 * 4bytes instead of 2bytes, which are mentioned in the errata,
2306 * are pulled; mainly to keep rest of the data properly aligned.
2308 if (tdata->sc->hw.mac.type == e1000_82571 ||
2309 tdata->sc->hw.mac.type == e1000_82572 ||
2310 tdata->sc->hw.mac.type == e1000_pch_lpt)
2311 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2317 emx_init_tx_ring(struct emx_txdata *tdata)
2319 /* Clear the old ring contents */
2320 bzero(tdata->tx_desc_base,
2321 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2324 tdata->next_avail_tx_desc = 0;
2325 tdata->next_tx_to_clean = 0;
2326 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2328 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2329 if (tdata->sc->tx_ring_inuse > 1) {
2330 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2332 if_printf(&tdata->sc->arpcom.ac_if,
2333 "TX %d force ctx setup\n", tdata->idx);
2339 emx_init_tx_unit(struct emx_softc *sc)
2341 uint32_t tctl, tarc, tipg = 0, txdctl;
2344 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2345 struct emx_txdata *tdata = &sc->tx_data[i];
2348 /* Setup the Base and Length of the Tx Descriptor Ring */
2349 bus_addr = tdata->tx_desc_paddr;
2350 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2351 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2352 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2353 (uint32_t)(bus_addr >> 32));
2354 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2355 (uint32_t)bus_addr);
2356 /* Setup the HW Tx Head and Tail descriptor pointers */
2357 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2358 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2361 /* Set the default values for the Tx Inter Packet Gap timer */
2362 switch (sc->hw.mac.type) {
2363 case e1000_80003es2lan:
2364 tipg = DEFAULT_82543_TIPG_IPGR1;
2365 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2366 E1000_TIPG_IPGR2_SHIFT;
2370 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2371 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2372 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2374 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2375 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2376 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2380 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2382 /* NOTE: 0 is not allowed for TIDV */
2383 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2384 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2387 * Errata workaround (obtained from Linux). This is necessary
2388 * to make multiple TX queues work on 82574.
2389 * XXX can't find it in any published errata though.
2391 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2392 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2394 if (sc->hw.mac.type == e1000_82571 ||
2395 sc->hw.mac.type == e1000_82572) {
2396 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2397 tarc |= EMX_TARC_SPEED_MODE;
2398 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2399 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2400 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2402 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2403 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2405 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2408 /* Program the Transmit Control Register */
2409 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2410 tctl &= ~E1000_TCTL_CT;
2411 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2412 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2413 tctl |= E1000_TCTL_MULR;
2415 /* This write will effectively turn on the transmit unit. */
2416 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2418 if (sc->hw.mac.type == e1000_82571 ||
2419 sc->hw.mac.type == e1000_82572 ||
2420 sc->hw.mac.type == e1000_80003es2lan) {
2421 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2422 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2424 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2427 if (sc->tx_ring_inuse > 1) {
2428 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2429 tarc &= ~EMX_TARC_COUNT_MASK;
2431 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2433 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2434 tarc &= ~EMX_TARC_COUNT_MASK;
2436 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2441 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2443 struct emx_txbuf *tx_buffer;
2446 /* Free Transmit Descriptor ring */
2447 if (tdata->tx_desc_base) {
2448 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2449 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2450 tdata->tx_desc_dmap);
2451 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2453 tdata->tx_desc_base = NULL;
2456 if (tdata->tx_buf == NULL)
2459 for (i = 0; i < ndesc; i++) {
2460 tx_buffer = &tdata->tx_buf[i];
2462 KKASSERT(tx_buffer->m_head == NULL);
2463 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2465 bus_dma_tag_destroy(tdata->txtag);
2467 kfree(tdata->tx_buf, M_DEVBUF);
2468 tdata->tx_buf = NULL;
2472 * The offload context needs to be set when we transfer the first
2473 * packet of a particular protocol (TCP/UDP). This routine has been
2474 * enhanced to deal with inserted VLAN headers.
2476 * If the new packet's ether header length, ip header length and
2477 * csum offloading type are same as the previous packet, we should
2478 * avoid allocating a new csum context descriptor; mainly to take
2479 * advantage of the pipeline effect of the TX data read request.
2481 * This function returns number of TX descrptors allocated for
2485 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2486 uint32_t *txd_upper, uint32_t *txd_lower)
2488 struct e1000_context_desc *TXD;
2489 int curr_txd, ehdrlen, csum_flags;
2490 uint32_t cmd, hdr_len, ip_hlen;
2492 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2493 ip_hlen = mp->m_pkthdr.csum_iphlen;
2494 ehdrlen = mp->m_pkthdr.csum_lhlen;
2496 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2497 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2498 tdata->csum_flags == csum_flags) {
2500 * Same csum offload context as the previous packets;
2503 *txd_upper = tdata->csum_txd_upper;
2504 *txd_lower = tdata->csum_txd_lower;
2509 * Setup a new csum offload context.
2512 curr_txd = tdata->next_avail_tx_desc;
2513 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2517 /* Setup of IP header checksum. */
2518 if (csum_flags & CSUM_IP) {
2520 * Start offset for header checksum calculation.
2521 * End offset for header checksum calculation.
2522 * Offset of place to put the checksum.
2524 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2525 TXD->lower_setup.ip_fields.ipcse =
2526 htole16(ehdrlen + ip_hlen - 1);
2527 TXD->lower_setup.ip_fields.ipcso =
2528 ehdrlen + offsetof(struct ip, ip_sum);
2529 cmd |= E1000_TXD_CMD_IP;
2530 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2532 hdr_len = ehdrlen + ip_hlen;
2534 if (csum_flags & CSUM_TCP) {
2536 * Start offset for payload checksum calculation.
2537 * End offset for payload checksum calculation.
2538 * Offset of place to put the checksum.
2540 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2541 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2542 TXD->upper_setup.tcp_fields.tucso =
2543 hdr_len + offsetof(struct tcphdr, th_sum);
2544 cmd |= E1000_TXD_CMD_TCP;
2545 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2546 } else if (csum_flags & CSUM_UDP) {
2548 * Start offset for header checksum calculation.
2549 * End offset for header checksum calculation.
2550 * Offset of place to put the checksum.
2552 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2553 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2554 TXD->upper_setup.tcp_fields.tucso =
2555 hdr_len + offsetof(struct udphdr, uh_sum);
2556 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2559 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2560 E1000_TXD_DTYP_D; /* Data descr */
2562 /* Save the information for this csum offloading context */
2563 tdata->csum_lhlen = ehdrlen;
2564 tdata->csum_iphlen = ip_hlen;
2565 tdata->csum_flags = csum_flags;
2566 tdata->csum_txd_upper = *txd_upper;
2567 tdata->csum_txd_lower = *txd_lower;
2569 TXD->tcp_seg_setup.data = htole32(0);
2570 TXD->cmd_and_length =
2571 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2573 if (++curr_txd == tdata->num_tx_desc)
2576 KKASSERT(tdata->num_tx_desc_avail > 0);
2577 tdata->num_tx_desc_avail--;
2579 tdata->next_avail_tx_desc = curr_txd;
2584 emx_txeof(struct emx_txdata *tdata)
2586 struct emx_txbuf *tx_buffer;
2587 int first, num_avail;
2589 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2592 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2595 num_avail = tdata->num_tx_desc_avail;
2596 first = tdata->next_tx_to_clean;
2598 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2599 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2600 struct e1000_tx_desc *tx_desc;
2602 tx_desc = &tdata->tx_desc_base[dd_idx];
2603 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2604 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2606 if (++dd_idx == tdata->num_tx_desc)
2609 while (first != dd_idx) {
2614 tx_buffer = &tdata->tx_buf[first];
2615 if (tx_buffer->m_head) {
2616 bus_dmamap_unload(tdata->txtag,
2618 m_freem(tx_buffer->m_head);
2619 tx_buffer->m_head = NULL;
2622 if (++first == tdata->num_tx_desc)
2629 tdata->next_tx_to_clean = first;
2630 tdata->num_tx_desc_avail = num_avail;
2632 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2633 tdata->tx_dd_head = 0;
2634 tdata->tx_dd_tail = 0;
2637 if (!EMX_IS_OACTIVE(tdata)) {
2638 ifsq_clr_oactive(tdata->ifsq);
2640 /* All clean, turn off the timer */
2641 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2642 tdata->tx_watchdog.wd_timer = 0;
2647 emx_tx_collect(struct emx_txdata *tdata)
2649 struct emx_txbuf *tx_buffer;
2650 int tdh, first, num_avail, dd_idx = -1;
2652 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2655 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2656 if (tdh == tdata->next_tx_to_clean)
2659 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2660 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2662 num_avail = tdata->num_tx_desc_avail;
2663 first = tdata->next_tx_to_clean;
2665 while (first != tdh) {
2670 tx_buffer = &tdata->tx_buf[first];
2671 if (tx_buffer->m_head) {
2672 bus_dmamap_unload(tdata->txtag,
2674 m_freem(tx_buffer->m_head);
2675 tx_buffer->m_head = NULL;
2678 if (first == dd_idx) {
2679 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2680 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2681 tdata->tx_dd_head = 0;
2682 tdata->tx_dd_tail = 0;
2685 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2689 if (++first == tdata->num_tx_desc)
2692 tdata->next_tx_to_clean = first;
2693 tdata->num_tx_desc_avail = num_avail;
2695 if (!EMX_IS_OACTIVE(tdata)) {
2696 ifsq_clr_oactive(tdata->ifsq);
2698 /* All clean, turn off the timer */
2699 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2700 tdata->tx_watchdog.wd_timer = 0;
2705 * When Link is lost sometimes there is work still in the TX ring
2706 * which will result in a watchdog, rather than allow that do an
2707 * attempted cleanup and then reinit here. Note that this has been
2708 * seens mostly with fiber adapters.
2711 emx_tx_purge(struct emx_softc *sc)
2715 if (sc->link_active)
2718 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2719 struct emx_txdata *tdata = &sc->tx_data[i];
2721 if (tdata->tx_watchdog.wd_timer) {
2722 emx_tx_collect(tdata);
2723 if (tdata->tx_watchdog.wd_timer) {
2724 if_printf(&sc->arpcom.ac_if,
2725 "Link lost, TX pending, reinit\n");
2734 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2737 bus_dma_segment_t seg;
2739 struct emx_rxbuf *rx_buffer;
2742 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2745 if_printf(&rdata->sc->arpcom.ac_if,
2746 "Unable to allocate RX mbuf\n");
2750 m->m_len = m->m_pkthdr.len = MCLBYTES;
2752 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2753 m_adj(m, ETHER_ALIGN);
2755 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2756 rdata->rx_sparemap, m,
2757 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2761 if_printf(&rdata->sc->arpcom.ac_if,
2762 "Unable to load RX mbuf\n");
2767 rx_buffer = &rdata->rx_buf[i];
2768 if (rx_buffer->m_head != NULL)
2769 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2771 map = rx_buffer->map;
2772 rx_buffer->map = rdata->rx_sparemap;
2773 rdata->rx_sparemap = map;
2775 rx_buffer->m_head = m;
2776 rx_buffer->paddr = seg.ds_addr;
2778 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2783 emx_create_rx_ring(struct emx_rxdata *rdata)
2785 device_t dev = rdata->sc->dev;
2786 struct emx_rxbuf *rx_buffer;
2787 int i, error, rsize, nrxd;
2790 * Validate number of receive descriptors. It must not exceed
2791 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2793 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2794 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2795 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2796 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2797 EMX_DEFAULT_RXD, nrxd);
2798 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2800 rdata->num_rx_desc = nrxd;
2804 * Allocate Receive Descriptor ring
2806 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2808 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2809 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2810 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2811 &rdata->rx_desc_paddr);
2812 if (rdata->rx_desc == NULL) {
2813 device_printf(dev, "Unable to allocate rx_desc memory\n");
2817 rsize = __VM_CACHELINE_ALIGN(
2818 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2819 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2822 * Create DMA tag for rx buffers
2824 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2825 1, 0, /* alignment, bounds */
2826 BUS_SPACE_MAXADDR, /* lowaddr */
2827 BUS_SPACE_MAXADDR, /* highaddr */
2828 NULL, NULL, /* filter, filterarg */
2829 MCLBYTES, /* maxsize */
2831 MCLBYTES, /* maxsegsize */
2832 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2835 device_printf(dev, "Unable to allocate RX DMA tag\n");
2836 kfree(rdata->rx_buf, M_DEVBUF);
2837 rdata->rx_buf = NULL;
2842 * Create spare DMA map for rx buffers
2844 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2845 &rdata->rx_sparemap);
2847 device_printf(dev, "Unable to create spare RX DMA map\n");
2848 bus_dma_tag_destroy(rdata->rxtag);
2849 kfree(rdata->rx_buf, M_DEVBUF);
2850 rdata->rx_buf = NULL;
2855 * Create DMA maps for rx buffers
2857 for (i = 0; i < rdata->num_rx_desc; i++) {
2858 rx_buffer = &rdata->rx_buf[i];
2860 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2863 device_printf(dev, "Unable to create RX DMA map\n");
2864 emx_destroy_rx_ring(rdata, i);
2872 emx_free_rx_ring(struct emx_rxdata *rdata)
2876 for (i = 0; i < rdata->num_rx_desc; i++) {
2877 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2879 if (rx_buffer->m_head != NULL) {
2880 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2881 m_freem(rx_buffer->m_head);
2882 rx_buffer->m_head = NULL;
2886 if (rdata->fmp != NULL)
2887 m_freem(rdata->fmp);
2893 emx_free_tx_ring(struct emx_txdata *tdata)
2897 for (i = 0; i < tdata->num_tx_desc; i++) {
2898 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2900 if (tx_buffer->m_head != NULL) {
2901 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2902 m_freem(tx_buffer->m_head);
2903 tx_buffer->m_head = NULL;
2907 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2909 tdata->csum_flags = 0;
2910 tdata->csum_lhlen = 0;
2911 tdata->csum_iphlen = 0;
2912 tdata->csum_thlen = 0;
2913 tdata->csum_mss = 0;
2914 tdata->csum_pktlen = 0;
2916 tdata->tx_dd_head = 0;
2917 tdata->tx_dd_tail = 0;
2918 tdata->tx_nsegs = 0;
2922 emx_init_rx_ring(struct emx_rxdata *rdata)
2926 /* Reset descriptor ring */
2927 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2929 /* Allocate new ones. */
2930 for (i = 0; i < rdata->num_rx_desc; i++) {
2931 error = emx_newbuf(rdata, i, 1);
2936 /* Setup our descriptor pointers */
2937 rdata->next_rx_desc_to_check = 0;
2943 emx_init_rx_unit(struct emx_softc *sc)
2945 struct ifnet *ifp = &sc->arpcom.ac_if;
2947 uint32_t rctl, itr, rfctl;
2951 * Make sure receives are disabled while setting
2952 * up the descriptor ring
2954 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2955 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2958 * Set the interrupt throttling rate. Value is calculated
2959 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2961 if (sc->int_throttle_ceil)
2962 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2965 emx_set_itr(sc, itr);
2967 /* Use extended RX descriptor */
2968 rfctl = E1000_RFCTL_EXTEN;
2970 /* Disable accelerated ackknowledge */
2971 if (sc->hw.mac.type == e1000_82574)
2972 rfctl |= E1000_RFCTL_ACK_DIS;
2974 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2977 * Receive Checksum Offload for TCP and UDP
2979 * Checksum offloading is also enabled if multiple receive
2980 * queue is to be supported, since we need it to figure out
2983 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2984 sc->rx_ring_cnt > 1) {
2987 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2991 * PCSD must be enabled to enable multiple
2994 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2996 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
3000 * Configure multiple receive queue (RSS)
3002 if (sc->rx_ring_cnt > 1) {
3003 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
3006 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
3007 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
3011 * When we reach here, RSS has already been disabled
3012 * in emx_stop(), so we could safely configure RSS key
3013 * and redirect table.
3019 toeplitz_get_key(key, sizeof(key));
3020 for (i = 0; i < EMX_NRSSRK; ++i) {
3023 rssrk = EMX_RSSRK_VAL(key, i);
3024 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
3026 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
3030 * Configure RSS redirect table in following fashion:
3031 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3034 for (i = 0; i < EMX_RETA_SIZE; ++i) {
3037 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
3038 reta |= q << (8 * i);
3040 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
3042 for (i = 0; i < EMX_NRETA; ++i)
3043 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
3046 * Enable multiple receive queues.
3047 * Enable IPv4 RSS standard hash functions.
3048 * Disable RSS interrupt.
3050 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3051 E1000_MRQC_ENABLE_RSS_2Q |
3052 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3053 E1000_MRQC_RSS_FIELD_IPV4);
3057 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3058 * long latencies are observed, like Lenovo X60. This
3059 * change eliminates the problem, but since having positive
3060 * values in RDTR is a known source of problems on other
3061 * platforms another solution is being sought.
3063 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3064 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3065 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3068 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3069 struct emx_rxdata *rdata = &sc->rx_data[i];
3072 * Setup the Base and Length of the Rx Descriptor Ring
3074 bus_addr = rdata->rx_desc_paddr;
3075 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3076 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3077 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3078 (uint32_t)(bus_addr >> 32));
3079 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3080 (uint32_t)bus_addr);
3083 * Setup the HW Rx Head and Tail Descriptor Pointers
3085 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3086 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3087 sc->rx_data[i].num_rx_desc - 1);
3090 if (sc->hw.mac.type >= e1000_pch2lan) {
3091 if (ifp->if_mtu > ETHERMTU)
3092 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3094 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3097 /* Setup the Receive Control Register */
3098 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3099 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3100 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3101 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3103 /* Make sure VLAN Filters are off */
3104 rctl &= ~E1000_RCTL_VFE;
3106 /* Don't store bad paket */
3107 rctl &= ~E1000_RCTL_SBP;
3110 rctl |= E1000_RCTL_SZ_2048;
3112 if (ifp->if_mtu > ETHERMTU)
3113 rctl |= E1000_RCTL_LPE;
3115 rctl &= ~E1000_RCTL_LPE;
3117 /* Enable Receives */
3118 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3122 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3124 struct emx_rxbuf *rx_buffer;
3127 /* Free Receive Descriptor ring */
3128 if (rdata->rx_desc) {
3129 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3130 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3131 rdata->rx_desc_dmap);
3132 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3134 rdata->rx_desc = NULL;
3137 if (rdata->rx_buf == NULL)
3140 for (i = 0; i < ndesc; i++) {
3141 rx_buffer = &rdata->rx_buf[i];
3143 KKASSERT(rx_buffer->m_head == NULL);
3144 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3146 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3147 bus_dma_tag_destroy(rdata->rxtag);
3149 kfree(rdata->rx_buf, M_DEVBUF);
3150 rdata->rx_buf = NULL;
3154 emx_rxeof(struct emx_rxdata *rdata, int count)
3156 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3158 emx_rxdesc_t *current_desc;
3160 int i, cpuid = mycpuid;
3162 i = rdata->next_rx_desc_to_check;
3163 current_desc = &rdata->rx_desc[i];
3164 staterr = le32toh(current_desc->rxd_staterr);
3166 if (!(staterr & E1000_RXD_STAT_DD))
3169 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3170 struct pktinfo *pi = NULL, pi0;
3171 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3172 struct mbuf *m = NULL;
3177 mp = rx_buf->m_head;
3180 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3181 * needs to access the last received byte in the mbuf.
3183 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3184 BUS_DMASYNC_POSTREAD);
3186 len = le16toh(current_desc->rxd_length);
3187 if (staterr & E1000_RXD_STAT_EOP) {
3194 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3196 uint32_t mrq, rss_hash;
3199 * Save several necessary information,
3200 * before emx_newbuf() destroy it.
3202 if ((staterr & E1000_RXD_STAT_VP) && eop)
3203 vlan = le16toh(current_desc->rxd_vlan);
3205 mrq = le32toh(current_desc->rxd_mrq);
3206 rss_hash = le32toh(current_desc->rxd_rss);
3208 EMX_RSS_DPRINTF(rdata->sc, 10,
3209 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3210 rdata->idx, mrq, rss_hash);
3212 if (emx_newbuf(rdata, i, 0) != 0) {
3213 IFNET_STAT_INC(ifp, iqdrops, 1);
3217 /* Assign correct length to the current fragment */
3220 if (rdata->fmp == NULL) {
3221 mp->m_pkthdr.len = len;
3222 rdata->fmp = mp; /* Store the first mbuf */
3226 * Chain mbuf's together
3228 rdata->lmp->m_next = mp;
3229 rdata->lmp = rdata->lmp->m_next;
3230 rdata->fmp->m_pkthdr.len += len;
3234 rdata->fmp->m_pkthdr.rcvif = ifp;
3235 IFNET_STAT_INC(ifp, ipackets, 1);
3237 if (ifp->if_capenable & IFCAP_RXCSUM)
3238 emx_rxcsum(staterr, rdata->fmp);
3240 if (staterr & E1000_RXD_STAT_VP) {
3241 rdata->fmp->m_pkthdr.ether_vlantag =
3243 rdata->fmp->m_flags |= M_VLANTAG;
3249 if (ifp->if_capenable & IFCAP_RSS) {
3250 pi = emx_rssinfo(m, &pi0, mrq,
3253 #ifdef EMX_RSS_DEBUG
3258 IFNET_STAT_INC(ifp, ierrors, 1);
3260 emx_setup_rxdesc(current_desc, rx_buf);
3261 if (rdata->fmp != NULL) {
3262 m_freem(rdata->fmp);
3270 ifp->if_input(ifp, m, pi, cpuid);
3272 /* Advance our pointers to the next descriptor. */
3273 if (++i == rdata->num_rx_desc)
3276 current_desc = &rdata->rx_desc[i];
3277 staterr = le32toh(current_desc->rxd_staterr);
3279 rdata->next_rx_desc_to_check = i;
3281 /* Advance the E1000's Receive Queue "Tail Pointer". */
3283 i = rdata->num_rx_desc - 1;
3284 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3288 emx_enable_intr(struct emx_softc *sc)
3290 uint32_t ims_mask = IMS_ENABLE_MASK;
3292 lwkt_serialize_handler_enable(&sc->main_serialize);
3295 if (sc->hw.mac.type == e1000_82574) {
3296 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3297 ims_mask |= EM_MSIX_MASK;
3300 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3304 emx_disable_intr(struct emx_softc *sc)
3306 if (sc->hw.mac.type == e1000_82574)
3307 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3308 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3310 lwkt_serialize_handler_disable(&sc->main_serialize);
3314 * Bit of a misnomer, what this really means is
3315 * to enable OS management of the system... aka
3316 * to disable special hardware management features
3319 emx_get_mgmt(struct emx_softc *sc)
3321 /* A shared code workaround */
3322 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3323 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3324 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3326 /* disable hardware interception of ARP */
3327 manc &= ~(E1000_MANC_ARP_EN);
3329 /* enable receiving management packets to the host */
3330 manc |= E1000_MANC_EN_MNG2HOST;
3331 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3332 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3333 manc2h |= E1000_MNG2HOST_PORT_623;
3334 manc2h |= E1000_MNG2HOST_PORT_664;
3335 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3337 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3342 * Give control back to hardware management
3343 * controller if there is one.
3346 emx_rel_mgmt(struct emx_softc *sc)
3348 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3349 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3351 /* re-enable hardware interception of ARP */
3352 manc |= E1000_MANC_ARP_EN;
3353 manc &= ~E1000_MANC_EN_MNG2HOST;
3355 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3360 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3361 * For ASF and Pass Through versions of f/w this means that
3362 * the driver is loaded. For AMT version (only with 82573)
3363 * of the f/w this means that the network i/f is open.
3366 emx_get_hw_control(struct emx_softc *sc)
3368 /* Let firmware know the driver has taken over */
3369 if (sc->hw.mac.type == e1000_82573) {
3372 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3373 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3374 swsm | E1000_SWSM_DRV_LOAD);
3378 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3379 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3380 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3382 sc->flags |= EMX_FLAG_HW_CTRL;
3386 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3387 * For ASF and Pass Through versions of f/w this means that the
3388 * driver is no longer loaded. For AMT version (only with 82573)
3389 * of the f/w this means that the network i/f is closed.
3392 emx_rel_hw_control(struct emx_softc *sc)
3394 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3396 sc->flags &= ~EMX_FLAG_HW_CTRL;
3398 /* Let firmware taken over control of h/w */
3399 if (sc->hw.mac.type == e1000_82573) {
3402 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3403 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3404 swsm & ~E1000_SWSM_DRV_LOAD);
3408 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3409 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3410 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3415 emx_is_valid_eaddr(const uint8_t *addr)
3417 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3419 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3426 * Enable PCI Wake On Lan capability
3429 emx_enable_wol(device_t dev)
3431 uint16_t cap, status;
3434 /* First find the capabilities pointer*/
3435 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3437 /* Read the PM Capabilities */
3438 id = pci_read_config(dev, cap, 1);
3439 if (id != PCIY_PMG) /* Something wrong */
3443 * OK, we have the power capabilities,
3444 * so now get the status register
3446 cap += PCIR_POWER_STATUS;
3447 status = pci_read_config(dev, cap, 2);
3448 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3449 pci_write_config(dev, cap, status, 2);
3453 emx_update_stats(struct emx_softc *sc)
3455 struct ifnet *ifp = &sc->arpcom.ac_if;
3457 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3458 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3459 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3460 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3462 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3463 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3464 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3465 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3467 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3468 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3469 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3470 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3471 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3472 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3473 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3474 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3475 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3476 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3477 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3478 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3479 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3480 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3481 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3482 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3483 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3484 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3485 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3486 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3488 /* For the 64-bit byte counters the low dword must be read first. */
3489 /* Both registers clear on the read of the high dword */
3491 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3492 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3494 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3495 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3496 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3497 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3498 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3500 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3501 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3503 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3504 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3505 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3506 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3507 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3508 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3509 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3510 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3511 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3512 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3514 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3515 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3516 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3517 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3518 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3519 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3521 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3524 IFNET_STAT_SET(ifp, ierrors,
3525 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3526 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3529 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3533 emx_print_debug_info(struct emx_softc *sc)
3535 device_t dev = sc->dev;
3536 uint8_t *hw_addr = sc->hw.hw_addr;
3539 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3540 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3541 E1000_READ_REG(&sc->hw, E1000_CTRL),
3542 E1000_READ_REG(&sc->hw, E1000_RCTL));
3543 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3544 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3545 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3546 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3547 sc->hw.fc.high_water, sc->hw.fc.low_water);
3548 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3549 E1000_READ_REG(&sc->hw, E1000_TIDV),
3550 E1000_READ_REG(&sc->hw, E1000_TADV));
3551 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3552 E1000_READ_REG(&sc->hw, E1000_RDTR),
3553 E1000_READ_REG(&sc->hw, E1000_RADV));
3555 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3556 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3557 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3558 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3560 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3561 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3562 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3563 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3566 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3567 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3568 sc->tx_data[i].num_tx_desc_avail);
3569 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3570 sc->tx_data[i].tso_segments);
3571 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3572 sc->tx_data[i].tso_ctx_reused);
3577 emx_print_hw_stats(struct emx_softc *sc)
3579 device_t dev = sc->dev;
3581 device_printf(dev, "Excessive collisions = %lld\n",
3582 (long long)sc->stats.ecol);
3583 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3584 device_printf(dev, "Symbol errors = %lld\n",
3585 (long long)sc->stats.symerrs);
3587 device_printf(dev, "Sequence errors = %lld\n",
3588 (long long)sc->stats.sec);
3589 device_printf(dev, "Defer count = %lld\n",
3590 (long long)sc->stats.dc);
3591 device_printf(dev, "Missed Packets = %lld\n",
3592 (long long)sc->stats.mpc);
3593 device_printf(dev, "Receive No Buffers = %lld\n",
3594 (long long)sc->stats.rnbc);
3595 /* RLEC is inaccurate on some hardware, calculate our own. */
3596 device_printf(dev, "Receive Length Errors = %lld\n",
3597 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3598 device_printf(dev, "Receive errors = %lld\n",
3599 (long long)sc->stats.rxerrc);
3600 device_printf(dev, "Crc errors = %lld\n",
3601 (long long)sc->stats.crcerrs);
3602 device_printf(dev, "Alignment errors = %lld\n",
3603 (long long)sc->stats.algnerrc);
3604 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3605 (long long)sc->stats.cexterr);
3606 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3607 device_printf(dev, "XON Rcvd = %lld\n",
3608 (long long)sc->stats.xonrxc);
3609 device_printf(dev, "XON Xmtd = %lld\n",
3610 (long long)sc->stats.xontxc);
3611 device_printf(dev, "XOFF Rcvd = %lld\n",
3612 (long long)sc->stats.xoffrxc);
3613 device_printf(dev, "XOFF Xmtd = %lld\n",
3614 (long long)sc->stats.xofftxc);
3615 device_printf(dev, "Good Packets Rcvd = %lld\n",
3616 (long long)sc->stats.gprc);
3617 device_printf(dev, "Good Packets Xmtd = %lld\n",
3618 (long long)sc->stats.gptc);
3622 emx_print_nvm_info(struct emx_softc *sc)
3624 uint16_t eeprom_data;
3627 /* Its a bit crude, but it gets the job done */
3628 kprintf("\nInterface EEPROM Dump:\n");
3629 kprintf("Offset\n0x0000 ");
3630 for (i = 0, j = 0; i < 32; i++, j++) {
3631 if (j == 8) { /* Make the offset block */
3633 kprintf("\n0x00%x0 ",row);
3635 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3636 kprintf("%04x ", eeprom_data);
3642 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3644 struct emx_softc *sc;
3649 error = sysctl_handle_int(oidp, &result, 0, req);
3650 if (error || !req->newptr)
3653 sc = (struct emx_softc *)arg1;
3654 ifp = &sc->arpcom.ac_if;
3656 ifnet_serialize_all(ifp);
3659 emx_print_debug_info(sc);
3662 * This value will cause a hex dump of the
3663 * first 32 16-bit words of the EEPROM to
3667 emx_print_nvm_info(sc);
3669 ifnet_deserialize_all(ifp);
3675 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3680 error = sysctl_handle_int(oidp, &result, 0, req);
3681 if (error || !req->newptr)
3685 struct emx_softc *sc = (struct emx_softc *)arg1;
3686 struct ifnet *ifp = &sc->arpcom.ac_if;
3688 ifnet_serialize_all(ifp);
3689 emx_print_hw_stats(sc);
3690 ifnet_deserialize_all(ifp);
3696 emx_add_sysctl(struct emx_softc *sc)
3698 struct sysctl_ctx_list *ctx;
3699 struct sysctl_oid *tree;
3700 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3705 ctx = device_get_sysctl_ctx(sc->dev);
3706 tree = device_get_sysctl_tree(sc->dev);
3707 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3708 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3709 emx_sysctl_debug_info, "I", "Debug Information");
3711 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3712 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3713 emx_sysctl_stats, "I", "Statistics");
3715 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3716 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3718 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3719 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3722 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3723 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3724 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3725 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3726 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3727 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3728 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3729 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3730 emx_sysctl_tx_wreg_nsegs, "I",
3731 "# segments sent before write to hardware register");
3733 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3734 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3736 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3737 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3739 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3740 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3741 "# of TX rings used");
3743 #ifdef IFPOLL_ENABLE
3744 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3745 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3746 sc, 0, emx_sysctl_npoll_rxoff, "I",
3747 "NPOLLING RX cpu offset");
3748 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3749 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3750 sc, 0, emx_sysctl_npoll_txoff, "I",
3751 "NPOLLING TX cpu offset");
3754 #ifdef EMX_RSS_DEBUG
3755 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3756 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3757 0, "RSS debug level");
3758 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3759 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3760 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3761 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3765 #ifdef EMX_TSS_DEBUG
3766 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3767 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3768 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3769 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3776 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3778 struct emx_softc *sc = (void *)arg1;
3779 struct ifnet *ifp = &sc->arpcom.ac_if;
3780 int error, throttle;
3782 throttle = sc->int_throttle_ceil;
3783 error = sysctl_handle_int(oidp, &throttle, 0, req);
3784 if (error || req->newptr == NULL)
3786 if (throttle < 0 || throttle > 1000000000 / 256)
3791 * Set the interrupt throttling rate in 256ns increments,
3792 * recalculate sysctl value assignment to get exact frequency.
3794 throttle = 1000000000 / 256 / throttle;
3796 /* Upper 16bits of ITR is reserved and should be zero */
3797 if (throttle & 0xffff0000)
3801 ifnet_serialize_all(ifp);
3804 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3806 sc->int_throttle_ceil = 0;
3808 if (ifp->if_flags & IFF_RUNNING)
3809 emx_set_itr(sc, throttle);
3811 ifnet_deserialize_all(ifp);
3814 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3815 sc->int_throttle_ceil);
3821 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3823 struct emx_softc *sc = (void *)arg1;
3824 struct ifnet *ifp = &sc->arpcom.ac_if;
3825 struct emx_txdata *tdata = &sc->tx_data[0];
3828 segs = tdata->tx_intr_nsegs;
3829 error = sysctl_handle_int(oidp, &segs, 0, req);
3830 if (error || req->newptr == NULL)
3835 ifnet_serialize_all(ifp);
3838 * Don't allow tx_intr_nsegs to become:
3839 * o Less the oact_tx_desc
3840 * o Too large that no TX desc will cause TX interrupt to
3841 * be generated (OACTIVE will never recover)
3842 * o Too small that will cause tx_dd[] overflow
3844 if (segs < tdata->oact_tx_desc ||
3845 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3846 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3852 for (i = 0; i < sc->tx_ring_cnt; ++i)
3853 sc->tx_data[i].tx_intr_nsegs = segs;
3856 ifnet_deserialize_all(ifp);
3862 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3864 struct emx_softc *sc = (void *)arg1;
3865 struct ifnet *ifp = &sc->arpcom.ac_if;
3866 int error, nsegs, i;
3868 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3869 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3870 if (error || req->newptr == NULL)
3873 ifnet_serialize_all(ifp);
3874 for (i = 0; i < sc->tx_ring_cnt; ++i)
3875 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3876 ifnet_deserialize_all(ifp);
3881 #ifdef IFPOLL_ENABLE
3884 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3886 struct emx_softc *sc = (void *)arg1;
3887 struct ifnet *ifp = &sc->arpcom.ac_if;
3890 off = sc->rx_npoll_off;
3891 error = sysctl_handle_int(oidp, &off, 0, req);
3892 if (error || req->newptr == NULL)
3897 ifnet_serialize_all(ifp);
3898 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3902 sc->rx_npoll_off = off;
3904 ifnet_deserialize_all(ifp);
3910 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3912 struct emx_softc *sc = (void *)arg1;
3913 struct ifnet *ifp = &sc->arpcom.ac_if;
3916 off = sc->tx_npoll_off;
3917 error = sysctl_handle_int(oidp, &off, 0, req);
3918 if (error || req->newptr == NULL)
3923 ifnet_serialize_all(ifp);
3924 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3928 sc->tx_npoll_off = off;
3930 ifnet_deserialize_all(ifp);
3935 #endif /* IFPOLL_ENABLE */
3938 emx_dma_alloc(struct emx_softc *sc)
3943 * Create top level busdma tag
3945 error = bus_dma_tag_create(NULL, 1, 0,
3946 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3948 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3949 0, &sc->parent_dtag);
3951 device_printf(sc->dev, "could not create top level DMA tag\n");
3956 * Allocate transmit descriptors ring and buffers
3958 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3959 error = emx_create_tx_ring(&sc->tx_data[i]);
3961 device_printf(sc->dev,
3962 "Could not setup transmit structures\n");
3968 * Allocate receive descriptors ring and buffers
3970 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3971 error = emx_create_rx_ring(&sc->rx_data[i]);
3973 device_printf(sc->dev,
3974 "Could not setup receive structures\n");
3982 emx_dma_free(struct emx_softc *sc)
3986 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3987 emx_destroy_tx_ring(&sc->tx_data[i],
3988 sc->tx_data[i].num_tx_desc);
3991 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3992 emx_destroy_rx_ring(&sc->rx_data[i],
3993 sc->rx_data[i].num_rx_desc);
3996 /* Free top level busdma tag */
3997 if (sc->parent_dtag != NULL)
3998 bus_dma_tag_destroy(sc->parent_dtag);
4002 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4004 struct emx_softc *sc = ifp->if_softc;
4006 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
4010 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4012 struct emx_softc *sc = ifp->if_softc;
4014 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
4018 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4020 struct emx_softc *sc = ifp->if_softc;
4022 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
4026 emx_serialize_skipmain(struct emx_softc *sc)
4028 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
4032 emx_deserialize_skipmain(struct emx_softc *sc)
4034 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
4040 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4041 boolean_t serialized)
4043 struct emx_softc *sc = ifp->if_softc;
4045 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
4049 #endif /* INVARIANTS */
4051 #ifdef IFPOLL_ENABLE
4054 emx_npoll_status(struct ifnet *ifp)
4056 struct emx_softc *sc = ifp->if_softc;
4059 ASSERT_SERIALIZED(&sc->main_serialize);
4061 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4062 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4063 callout_stop(&sc->timer);
4064 sc->hw.mac.get_link_status = 1;
4065 emx_update_link_status(sc);
4066 callout_reset(&sc->timer, hz, emx_timer, sc);
4071 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4073 struct emx_txdata *tdata = arg;
4075 ASSERT_SERIALIZED(&tdata->tx_serialize);
4078 if (!ifsq_is_empty(tdata->ifsq))
4079 ifsq_devstart(tdata->ifsq);
4083 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4085 struct emx_rxdata *rdata = arg;
4087 ASSERT_SERIALIZED(&rdata->rx_serialize);
4089 emx_rxeof(rdata, cycle);
4093 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4095 struct emx_softc *sc = ifp->if_softc;
4098 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4103 info->ifpi_status.status_func = emx_npoll_status;
4104 info->ifpi_status.serializer = &sc->main_serialize;
4106 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4107 off = sc->tx_npoll_off;
4108 for (i = 0; i < txr_cnt; ++i) {
4109 struct emx_txdata *tdata = &sc->tx_data[i];
4112 KKASSERT(idx < ncpus2);
4113 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4114 info->ifpi_tx[idx].arg = tdata;
4115 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4116 ifsq_set_cpuid(tdata->ifsq, idx);
4119 off = sc->rx_npoll_off;
4120 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4121 struct emx_rxdata *rdata = &sc->rx_data[i];
4124 KKASSERT(idx < ncpus2);
4125 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4126 info->ifpi_rx[idx].arg = rdata;
4127 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4130 if (ifp->if_flags & IFF_RUNNING) {
4131 if (txr_cnt == sc->tx_ring_inuse)
4132 emx_disable_intr(sc);
4137 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4138 struct emx_txdata *tdata = &sc->tx_data[i];
4140 ifsq_set_cpuid(tdata->ifsq,
4141 rman_get_cpuid(sc->intr_res));
4144 if (ifp->if_flags & IFF_RUNNING) {
4145 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4146 if (txr_cnt == sc->tx_ring_inuse)
4147 emx_enable_intr(sc);
4154 #endif /* IFPOLL_ENABLE */
4157 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4159 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4160 if (sc->hw.mac.type == e1000_82574) {
4164 * When using MSIX interrupts we need to
4165 * throttle using the EITR register
4167 for (i = 0; i < 4; ++i)
4168 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4173 * Disable the L0s, 82574L Errata #20
4176 emx_disable_aspm(struct emx_softc *sc)
4178 uint16_t link_cap, link_ctrl, disable;
4179 uint8_t pcie_ptr, reg;
4180 device_t dev = sc->dev;
4182 switch (sc->hw.mac.type) {
4187 * 82573 specification update
4188 * errata #8 disable L0s
4189 * errata #41 disable L1
4191 * 82571/82572 specification update
4192 # errata #13 disable L1
4193 * errata #68 disable L0s
4195 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4200 * 82574 specification update errata #20
4202 * There is no need to disable L1
4204 disable = PCIEM_LNKCTL_ASPM_L0S;
4211 pcie_ptr = pci_get_pciecap_ptr(dev);
4215 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4216 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4220 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4222 reg = pcie_ptr + PCIER_LINKCTRL;
4223 link_ctrl = pci_read_config(dev, reg, 2);
4224 link_ctrl &= ~disable;
4225 pci_write_config(dev, reg, link_ctrl, 2);
4229 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4231 int iphlen, hoff, thoff, ex = 0;
4236 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4238 iphlen = m->m_pkthdr.csum_iphlen;
4239 thoff = m->m_pkthdr.csum_thlen;
4240 hoff = m->m_pkthdr.csum_lhlen;
4242 KASSERT(iphlen > 0, ("invalid ip hlen"));
4243 KASSERT(thoff > 0, ("invalid tcp hlen"));
4244 KASSERT(hoff > 0, ("invalid ether hlen"));
4246 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4249 if (m->m_len < hoff + iphlen + thoff + ex) {
4250 m = m_pullup(m, hoff + iphlen + thoff + ex);
4257 ip = mtodoff(m, struct ip *, hoff);
4264 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4265 uint32_t *txd_upper, uint32_t *txd_lower)
4267 struct e1000_context_desc *TXD;
4268 int hoff, iphlen, thoff, hlen;
4269 int mss, pktlen, curr_txd;
4271 #ifdef EMX_TSO_DEBUG
4272 tdata->tso_segments++;
4275 iphlen = mp->m_pkthdr.csum_iphlen;
4276 thoff = mp->m_pkthdr.csum_thlen;
4277 hoff = mp->m_pkthdr.csum_lhlen;
4278 mss = mp->m_pkthdr.tso_segsz;
4279 pktlen = mp->m_pkthdr.len;
4281 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4282 tdata->csum_flags == CSUM_TSO &&
4283 tdata->csum_iphlen == iphlen &&
4284 tdata->csum_lhlen == hoff &&
4285 tdata->csum_thlen == thoff &&
4286 tdata->csum_mss == mss &&
4287 tdata->csum_pktlen == pktlen) {
4288 *txd_upper = tdata->csum_txd_upper;
4289 *txd_lower = tdata->csum_txd_lower;
4290 #ifdef EMX_TSO_DEBUG
4291 tdata->tso_ctx_reused++;
4295 hlen = hoff + iphlen + thoff;
4298 * Setup a new TSO context.
4301 curr_txd = tdata->next_avail_tx_desc;
4302 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4304 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4305 E1000_TXD_DTYP_D | /* Data descr type */
4306 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4308 /* IP and/or TCP header checksum calculation and insertion. */
4309 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4312 * Start offset for header checksum calculation.
4313 * End offset for header checksum calculation.
4314 * Offset of place put the checksum.
4316 TXD->lower_setup.ip_fields.ipcss = hoff;
4317 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4318 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4321 * Start offset for payload checksum calculation.
4322 * End offset for payload checksum calculation.
4323 * Offset of place to put the checksum.
4325 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4326 TXD->upper_setup.tcp_fields.tucse = 0;
4327 TXD->upper_setup.tcp_fields.tucso =
4328 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4331 * Payload size per packet w/o any headers.
4332 * Length of all headers up to payload.
4334 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4335 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4336 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4337 E1000_TXD_CMD_DEXT | /* Extended descr */
4338 E1000_TXD_CMD_TSE | /* TSE context */
4339 E1000_TXD_CMD_IP | /* Do IP csum */
4340 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4341 (pktlen - hlen)); /* Total len */
4343 /* Save the information for this TSO context */
4344 tdata->csum_flags = CSUM_TSO;
4345 tdata->csum_lhlen = hoff;
4346 tdata->csum_iphlen = iphlen;
4347 tdata->csum_thlen = thoff;
4348 tdata->csum_mss = mss;
4349 tdata->csum_pktlen = pktlen;
4350 tdata->csum_txd_upper = *txd_upper;
4351 tdata->csum_txd_lower = *txd_lower;
4353 if (++curr_txd == tdata->num_tx_desc)
4356 KKASSERT(tdata->num_tx_desc_avail > 0);
4357 tdata->num_tx_desc_avail--;
4359 tdata->next_avail_tx_desc = curr_txd;
4364 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4367 return sc->tx_ring_cnt;